Manufacturing method of semiconductor structure, semiconductor structure and image sensor

Abstract

The invention discloses a manufacturing method of a semiconductor structure, the semiconductor structure and an image sensor, and belongs to the technical field of semiconductors, and the manufacturing method of the semiconductor structure comprises the following steps: providing a substrate; the substrate is etched, a plurality of concave parts are formed on the substrate, and convex parts are formed on the substrate between the adjacent concave parts; forming a barrier layer on the side wall of the convex part; the substrate at the bottom of the concave part and the substrate at the top of the convex part are etched synchronously, a first groove is formed in the position of the concave part, a second groove is formed in the position of the convex part, and the depth of the first groove is larger than that of the second groove; and filling media in the first groove and the second groove to form a first groove isolation structure and a second groove isolation structure. Through the manufacturing method of the semiconductor structure, the semiconductor structure and the image sensor disclosed by the invention, the manufacturing cost can be saved.

Description

Technical Field

[0001] This invention belongs to the field of semiconductor technology, and specifically relates to a method for fabricating a semiconductor structure, a semiconductor structure, and an image sensor. Background Technology

[0002] In some semiconductor manufacturing processes, to meet the requirements of the formed semiconductor devices, it is necessary to form deep trench isolation structures and shallow trench isolation structures of different depths on the substrate. For example, in the formation of a back-illuminated image sensor, deep trench isolation structures and shallow trench isolation structures are formed on the photoelectric sensing area to reflect or refract incident light, thereby improving the light conversion efficiency.

[0003] However, when forming deep trench isolation structures and shallow trench isolation structures, one photomask is used for deep trench isolation structures, while another photomask is required for shallow trench isolation structures. Although this can improve light conversion efficiency, it will significantly increase the manufacturing cost. Summary of the Invention

[0004] The purpose of this invention is to provide a method for fabricating a semiconductor structure, a semiconductor structure, and an image sensor, which can solve the problem of high process costs when forming deep trench isolation structures and shallow trench isolation structures.

[0005] To solve the above-mentioned technical problems, the present invention is achieved through the following technical solution: This invention provides a method for fabricating a semiconductor structure, comprising the following steps: Provide a substrate; A patterned hard mask layer is formed on the substrate, and the substrate is etched to form a plurality of recesses on the substrate, with protrusions formed between adjacent recesses; An oxide layer is deposited on the substrate, the oxide layer covering the recess and the protrusion; Etch a portion of the oxide layer at the bottom of the recess and the oxide layer at the top of the protrusion, while retaining the oxide layer on the sidewall of the protrusion, which forms a barrier layer; Simultaneously etch the substrate at the bottom of the recess and the substrate at the top of the protrusion, form a first trench at the location of the recess, and form a second trench at the location of the protrusion, wherein the depth of the first trench is greater than the depth of the second trench; A medium is filled into the first trench and the second trench to form a first trench isolation structure and a second trench isolation structure.

[0006] In one embodiment of the present invention, the barrier layer covers the sidewall of the protrusion and part of the bottom wall of the recess.

[0007] In one embodiment of the present invention, a tetramethylammonium hydroxide solution is used to simultaneously etch the substrate at the bottom of the recess and the substrate at the top of the protrusion.

[0008] In one embodiment of the present invention, as the depth of the first trench increases, the width of the barrier layer increases, and the spacing between the first trench isolation structure and the second trench isolation structure increases.

[0009] In one embodiment of the present invention, the cross-sections of the first trench and the second trench are inverted triangles.

[0010] In one embodiment of the present invention, the medium filled in the first trench and the second trench is a high dielectric constant material.

[0011] The present invention also provides a semiconductor structure, wherein the semiconductor structure is formed using the method for fabricating a semiconductor structure as described in any one of the above claims, and the semiconductor structure comprises: Substrate; A first trench isolation structure and a second trench isolation structure are disposed in the substrate, wherein the depth of the first trench isolation structure is greater than the depth of the second trench isolation structure.

[0012] The present invention also provides an image sensor, comprising: Circuit wiring layer; A photodiode is disposed on one side of the circuit wiring layer; The semiconductor structure described above is disposed on the side of the photodiode away from the circuit wiring layer; A filter is disposed on the side of the semiconductor structure away from the photodiode; A microlens is disposed on the side of the filter away from the semiconductor structure.

[0013] In one embodiment of the present invention, in the growth direction of the image sensor, the second trench isolation structure in the semiconductor structure is located on the line connecting the microlens and the photodiode.

[0014] In one embodiment of the present invention, for each of the first trench isolation structures, the radial dimension of the first trench isolation structure gradually decreases as the depth of the first trench isolation structure increases; for each of the second trench structures, the radial dimension of the second trench isolation structure gradually decreases as the depth of the second trench isolation structure increases.

[0015] In summary, the semiconductor structure fabrication method, semiconductor structure, and image sensor provided by this invention have the following unexpected effects: When forming the first and second trenches, recesses are first formed on the substrate, and convex portions are formed between the recesses; then, a barrier layer is formed on the sidewalls of the recesses, and using the barrier layer as a mask, the substrate at the bottom of the recesses and the substrate at the top of the convex portions are etched, simultaneously forming the first and second trenches of different depths on the substrate; finally, a dielectric is filled into the first and second trenches to form first and second trench isolation structures of different depths. In this way, a single photomask can be used to form the first and second trench isolation structures of different depths, saving a photomask and significantly reducing process costs. When the formed semiconductor structure is placed on a back-illuminated image sensor, placing the semiconductor structure between the microlens and the photodiode increases the photoelectric conversion efficiency. Simultaneously, by setting the trench isolation structure such that the radial dimension of the trench isolation structure gradually decreases with increasing trench isolation structure depth, light reflection and refraction are further increased, thereby increasing light conversion efficiency and improving the performance of the image sensor.

[0016] Of course, any product implementing this invention does not necessarily need to achieve all of the advantages described above at the same time. Attached Figure Description

[0017] To more clearly illustrate the technical solutions of the embodiments of the present invention, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0018] Figure 1 This is a schematic diagram of the structure in one embodiment forming a pad oxide layer, a pad nitride layer, and a photoresist layer.

[0019] Figure 2 This is a schematic diagram of the structure forming the recess in one embodiment.

[0020] Figure 3 This is a schematic diagram of the structure in which the oxide layer is formed in one embodiment.

[0021] Figure 4 This is a schematic diagram of the structure forming the barrier layer in one embodiment.

[0022] Figure 5 This is a schematic diagram of the structure forming the first and second trenches in one embodiment.

[0023] Figure 6 This is a schematic diagram of the structure of the filling medium formed in the first and second trenches in one embodiment.

[0024] Figure 7This is a schematic diagram of a structure forming a first trench isolation structure and a second trench isolation structure in one embodiment.

[0025] Figure 8 This is a schematic diagram of the structure of an image sensor in one embodiment.

[0026] Label Explanation: 101, Substrate; 1011, Recess; 1012, Protrusion; 102, Hard Mask Layer; 1021, Pad Oxide Layer; 1022, Pad Nitride Layer; 103, Photoresist Layer; 1031, Opening; 104, Oxide Layer; 1041, Barrier Layer; 1051, First Trench; 1052, Second Trench; 106, Dielectric Layer; 1061, First Trench Isolation Structure; 1062, Second Trench Isolation Structure; 201, Circuit Wiring Layer; 202, Photodiode; 203, Filter Layer; 204, Microlens. Detailed Implementation

[0027] The following specific examples illustrate the implementation of the present invention. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention.

[0028] It should be noted that the illustrations provided in this embodiment are only schematic representations of the basic concept of the present invention. Therefore, the drawings only show the components related to the present invention and are not drawn according to the actual number, shape and size of the components in the actual implementation. In the actual implementation, the form, quantity and proportion of each component can be arbitrarily changed, and the layout of the components may also be more complex.

[0029] In this invention, it should be noted that the terms "center," "upper," "lower," "left," "right," "vertical," "horizontal," "inner," and "outer," etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are used only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this application. Furthermore, the terms "first" and "second" are used only for descriptive and distinguishing purposes and should not be construed as indicating or implying relative importance.

[0030] Please combine Figure 8As shown, in a conventional front-illuminated sensor, the microlens 204 and photodiode 202 are positioned on opposite sides of the wiring layer 201. When the front-illuminated sensor is operating, light enters through the microlens 204, passes through the wiring layer 201 between the microlens 204 and the photodiode 202, and reaches the photodiode 202 for photoelectric conversion. However, the light is affected by the wiring layer 201, resulting in light loss and impacting image quality. In a back-illuminated image sensor, the position of the photodiode 202 is changed, placing it between the microlens 204 and the wiring layer 201. Light entering through the microlens 204 directly enters the photodiode 202 for photoelectric conversion, increasing the exposure area of ​​the photodiode 202 and reducing light loss through the wiring layer 201, thereby significantly improving light efficiency and image quality. However, in low-light environments, the photoelectric conversion efficiency of back-illuminated image sensors remains low due to the weak light. This application forms a trench isolation structure of varying depths between the photodiode 202 and the microlens 204 to reflect or refract light, thereby increasing light energy and improving light conversion efficiency.

[0031] Please see Figures 1 to 7 As shown, the present invention provides a method for fabricating a semiconductor structure. First, a patterned hard mask layer 102 is formed on a substrate 101, and the substrate 101 is etched to form a plurality of recesses 1011 on the substrate 101. Protrusions 1012 are formed between adjacent recesses 1011. Next, an oxide layer 104 is formed on the substrate 101, and the oxide layer 104 is etched, leaving the oxide layer 104 on the sidewalls of the protrusions 1012 intact, forming a barrier layer 1041. Then, using the barrier layer 1041 as a mask, the substrate 101 at the bottom 104 of the recesses 1011 and the top of the protrusions 1012 are simultaneously etched, forming a first trench 1051 at the location of the recesses 1011 and a second trench 1052 at the location of the protrusions 1012. Finally, a dielectric is deposited in the first trench 1051 and the second trench 1052 to form a first trench isolation structure 1061 and a second trench isolation structure 1062. The semiconductor structure fabrication method provided in this application uses a photomask to form a first trench isolation structure 1061 and a second trench isolation structure 1062 with different depths.

[0032] For details, please refer to Figure 1 As shown, in one embodiment of the present invention, a substrate 101 is first provided, which is, for example, a silicon substrate forming a semiconductor structure. The material of the substrate 101 can be undoped single-crystal silicon, doped single-crystal silicon, silicon-on-insulator (SOI), silicon-on-insulator stacked (SSOI), silicon-on-insulator stacked (S-SiGeOI), silicon-on-insulator (SiGeOI), and germanium-on-insulator (GeOI), etc. In this embodiment, the substrate 101 is a single-crystal silicon substrate, and specifically, undoped single-crystal silicon.

[0033] Please see Figure 1 and Figure 2 As shown, in one embodiment of the present invention, when forming a semiconductor structure, a patterned hard mask layer 102 is first formed on a substrate 101. In this embodiment, the hard mask layer 102 includes, for example, a pad oxide layer 1021 and a pad nitride layer 1022, wherein the pad oxide layer 1021 is disposed on the substrate 101 and the pad nitride layer 1022 is disposed on the pad oxide layer 1021.

[0034] Please see Figure 1 As shown, in one embodiment of the present invention, when forming the patterned hard mask layer 102, a pad oxide layer 1021 is first formed on the substrate 101. The pad oxide layer 1021 serves as a buffer layer to improve the stress between the substrate 101 and the subsequently formed pad nitride layer 1022. The pad oxide layer 1021 is, for example, a dense silicon oxide material, and the pad oxide layer 1021 can be formed by any one of the following methods: dry oxidation, wet oxidation, or in-situ water vapor growth.

[0035] Please see Figure 1 As shown, in one embodiment of the present invention, after forming the pad oxide layer 1021, a pad nitride layer 1022 is formed on the pad oxide layer 1021. The pad nitride layer 1022 is, for example, a silicon nitride layer, and can be formed, for example, by a method such as low-pressure chemical vapor deposition. During the subsequent formation of the shallow trench isolation structure, the pad nitride layer 1022 serves as a mask to protect the substrate 101 from damage during etching.

[0036] Please see Figure 1 As shown, in one embodiment of the present invention, after forming the pad nitride layer 1022, a patterned photoresist layer 103 is formed on the pad nitride layer 1022. The patterned photoresist layer 103 has a plurality of openings 1031, which are used to define the positions of the recesses 1011 on the substrate 101. Specifically, photoresist can be coated on the pad nitride layer 1022, and the photoresist above the recesses 1011 to be formed can be removed using an alkaline solution wet process or a dry ashing process, thereby patterning the coated photoresist to form the patterned photoresist layer 103.

[0037] Please see Figures 1 to 2 As shown, in one embodiment of the present invention, after forming the patterned photoresist layer 103, the pad nitride layer 1022 and the pad oxide layer 1021 at the bottom of the opening 1031 are etched sequentially to form a patterned mask layer 102. Then, the patterned photoresist layer 103 is removed, and using the pad nitride layer 1022 and the pad oxide layer 1021 as a mask, the substrate 101 is etched to form a plurality of recesses 1011 in the substrate 101.

[0038] Please see Figures 1 to 2As shown, in one embodiment of the present invention, since the materials of the pad nitride layer 1022, the pad oxide layer 1021, and the substrate 101 are different, two or more etching processes are required during etching. In some embodiments, dry etching can be used when etching the pad nitride layer 1022 and the pad oxide layer 1021, using a mixed gas of CF4 and CHF3 to remove the pad nitride layer 1022 and the pad oxide layer 1021 below the opening 1031 in a single etching process. In other embodiments, wet etching can also be used when etching the pad nitride layer 1022 and the pad oxide layer 1021, performed in two stages. For example, the pad nitride layer 1022 can be etched with hot phosphoric acid at a temperature range of 140°C to 200°C, and the pad oxide layer 1021 can be etched with hydrofluoric acid at a concentration of 1% to 10%.

[0039] Please see Figures 1 to 2 As shown, in one embodiment of the present invention, the substrate 101 can be etched using one or more gases selected from SF6, CF4, CF4 / H2, CHF3, CF4 / O2, and HBr for dry etching. For example, HBr and CF4 can be used to etch the substrate 101 to form a recess 1011. After forming the recess 1011, the pad nitride layer 1022 and the pad oxide layer 1021 are removed sequentially.

[0040] Please see Figures 2 to 7 As shown, in one embodiment of the present invention, a plurality of recesses 1011 extend from the surface of the substrate 101 into the substrate 101, and the substrate 101 in two adjacent recesses 1011 forms a protrusion 1012. This application does not limit the shape of the recesses 1011; in this embodiment, the cross-section of the recesses 1011 is rectangular. In other embodiments, the cross-section of the recesses 1011 may also be other shapes, such as trapezoids, or rectangles or trapezoids with rounded corners.

[0041] It is important to note that, in combination Figures 2 to 7As shown, this application does not limit the depth of the recess 1011. The depth of the recess 1011 is linearly related to the depth difference between the ultimately formed first trench isolation structure 1061 and second trench isolation structure 1062. The greater the depth of the recess 1011, the greater the depth difference between the formed first trench isolation structure 1061 and second trench isolation structure 1062; the smaller the depth of the recess 1011, the smaller the depth difference between the formed first trench isolation structure 1061 and second trench isolation structure 1062. In this embodiment, the depth of the recess 1011 is less than 0.5 μm, specifically, for example, 0.4 μm, 0.3 μm, or 0.2 μm. This application does not limit the width of the recess 1011 or the width of the protrusion 1012. The width of the recess 1011 and the width of the protrusion 1012 are related to the width of the ultimately formed first trench isolation structure 1061, the width of the second trench isolation structure 1062, and the spacing between the first trench isolation structure 1061 and the second trench isolation structure 1062. The larger the width of the recess 1011, the larger the sum of the width of the formed first trench isolation structure 1061 and the spacing between the first trench isolation structure 1061 and the second trench isolation structure 1062; the smaller the width of the recess 1011, the smaller the sum of the width of the formed first trench isolation structure 1061 and the spacing between the first trench isolation structure 1061 and the second trench isolation structure 1062. The larger the width of the protrusion 1012, the larger the width of the second trench isolation structure 1062; the smaller the width of the protrusion 1012, the smaller the width of the second trench isolation structure 1062.

[0042] Please see Figures 2 to 4 As shown, in one embodiment of the present invention, after forming the recess 1011, a barrier layer 1041 is formed on the sidewall of the protrusion 1012. In this embodiment, an oxide layer 104 may first be deposited on the substrate 101, covering the recess 1011 and the protrusion 1012 on the surface of the substrate 101. Then, a portion of the oxide layer 104 at the bottom of the recess 1011 and the oxide layer 104 at the top of the protrusion 1012 are etched, leaving the oxide layer 104 on the sidewall of the protrusion 1012 intact, thus forming the barrier layer 1041.

[0043] Please see Figures 2 to 3 As shown, in one embodiment of the present invention, after the recess 1011 is formed, a silicon oxide layer 104 is deposited on the substrate 101 using chemical vapor deposition (CVD) or high-density plasma-chemical vapor deposition (HDP-CVD). The oxide layer 104 fills the recess 1011 and covers the protrusion 1012.

[0044] Please see Figures 3 to 4 As shown, in one embodiment of the present invention, after forming the oxide layer 104, a dry etching method is used to remove a portion of the oxide layer 104 at the bottom of the recess 1011 and the oxide layer 104 at the top of the protrusion 1012, while retaining the oxide layer 104 on the sidewall of the protrusion 1012. The oxide layer 104 on the sidewall of the protrusion 1012 forms a barrier layer 1041. Specifically, fluorine-containing gases such as CHF3, CF4, SF6, C2F6, or C3F4 can be used to etch the oxide layer 104 in the middle portion of the bottom of the recess 1011 and the oxide layer 104 at the top of the protrusion 1012.

[0045] Please see Figure 4 As shown, in one embodiment of the present invention, the formed barrier layer 1041 covers the sidewall of the protrusion 1012 (which is also the sidewall of the recess 1011) and part of the bottom wall of the recess 1011. This application does not limit the size of the formed barrier layer 1041. The width of the barrier layer 1041 on the sidewall of the protrusion 1012 is related to the spacing between the first trench isolation structure 1061 and the second trench isolation structure 1062. The larger the width of the barrier layer 1041 on the sidewall of the protrusion 1012, the larger the spacing between the first trench isolation structure 1061 and the second trench isolation structure 1062; conversely, the smaller the width of the barrier layer 1041 on the sidewall of the protrusion 1012, the smaller the spacing between the first trench isolation structure 1061 and the second trench isolation structure 1062. In this embodiment, the thickness of the barrier layer 1041 on the sidewall of the protrusion 1012 is, for example, 0.15 μm to 0.3 μm, specifically, for example, 0.2 μm. In this embodiment, the thickness of the barrier layer 1041 is perpendicular to the thickness direction of the substrate 101.

[0046] It is important to note that, in combination Figure 4 and Figure 7 As shown, if the layout of the first trench isolation structure 1061 and the second trench isolation structure 1062 changes, the layout of the first trench isolation structure 1061 and the second trench isolation structure 1062 can also be adjusted by changing the position of the barrier layer 1041. For example, the barrier layer 1041 can be disposed in the recess 1011 to form adjacent first trench isolation structures 1061. The barrier layer 1041 can be disposed on the protrusion 1012 to form adjacent second trench isolation structures 1062.

[0047] Please see Figures 4 to 5 As shown, in one embodiment of the present invention, after the barrier layer 1041 is formed, the substrate 101 at the bottom of the recess 1011 and the substrate 101 at the top of the protrusion 1012 are simultaneously etched using the barrier layer 1041 as a mask. A first trench 1051 is formed at the position of the recess 1011, and a second trench 1052 is formed at the position of the protrusion 1012. The depth of the first trench 1051 is greater than the depth of the second trench 1052.

[0048] Please see Figures 4 to 5 As shown, in one embodiment of the present invention, during the formation of the first trench 1051 and the second trench 1052, the substrate 101 is etched using a wet etching method. Specifically, the substrate 101 can be etched using an acidic etching solution or an alkaline etching solution. An acidic etching solution is, for example, a mixture of hydrofluoric acid and nitric acid, while an alkaline solution is, for example, potassium hydroxide solution, ammonium hydroxide solution, or tetramethylammonium hydroxide (TMAH) solution. In this embodiment, tetramethylammonium hydroxide solution is used as the etching solution to etch the substrate 101. Because the wet etching of tetramethylammonium hydroxide solution is anisotropic, it can preferentially etch the material in a specific direction. When wet etching the substrate 101 using tetramethylammonium hydroxide solution, due to the obstruction of the barrier layer 1041, for each first trench 1051, the radial dimension of the first trench 1051 gradually decreases as the depth of the first trench 1051 increases; similarly, for each second trench 1052, the radial dimension of the second trench 1052 gradually decreases as the depth of the second trench 1052 increases.

[0049] Please see Figure 5 As shown, in one embodiment of the present invention, the cross-sections of the formed first groove 1051 and second groove 1052 are inverted triangles. In other embodiments, the cross-sections of the first groove 1051 and second groove 1052 may also be inverted trapezoids.

[0050] Please see Figure 6 and Figure 7 As shown, in one embodiment of the present invention, after forming the first trench 1051 and the second trench 1052, a dielectric layer 106 is formed by filling the first trench 1051 and the second trench 1052 with a dielectric material. The dielectric layer 106 fills the first trench 1051 and the second trench 1052. Subsequently, the dielectric layer 106 and the barrier layer 1041 above the surface of the substrate 101 are ground away by a chemical mechanical polishing (CMP) process. At this time, the dielectric material in the first trench 1051 forms a first trench isolation structure 1061, and the dielectric material in the second trench 1052 forms a second trench isolation structure 1062.

[0051] Please see Figure 6 and Figure 7As shown, in one embodiment of the present invention, the dielectric material filled in the first trench 1051 and the second trench 1052 is a high dielectric constant material, such as alumina (Al2O3) or tantalum pentoxide (Ta2O5). When the trench isolation structure and the second trench isolation structure 1062 formed using high dielectric constant materials are applied in an image sensor, they do not affect light absorption. In other embodiments, when the semiconductor structure provided in this application is applied to other devices, the dielectric material filled in the first trench 1051 and the second trench 1052 may include silicon dioxide, silicon nitride, silicon oxynitride, etc.

[0052] Please see Figure 7 As shown, the semiconductor structure formed by the present invention includes a substrate 101 and a first trench isolation structure 1061 and a second trench isolation structure 1062 disposed in the substrate 101. The depth of the first trench isolation structure 1061 is greater than the depth of the second trench isolation structure 1062. For each first trench isolation structure 1061, the radial dimension of the first trench isolation structure 1061 gradually decreases as the depth of the first trench isolation structure 1061 increases. For each second trench isolation structure 1062, the radial dimension of the second trench isolation structure 1062 gradually decreases as the depth of the second trench isolation structure 1062 increases.

[0053] Please see Figure 8 As shown, in one embodiment of the present invention, when the semiconductor structure formed in this application is disposed in a back-illuminated image sensor, the image sensor includes a circuit wiring layer 201, a photodiode 202 disposed on the circuit wiring layer 201, a semiconductor structure disposed on the photodiode 202, a filter 203 disposed on the semiconductor structure, and a microlens 204 disposed on the filter 203. The semiconductor structure is disposed between the filter 203 and the photodiode 202, and in the growth direction of the image sensor, the second trench isolation structure 1062 in the semiconductor structure is located on the line connecting the microlens 204 and the photodiode 202. When light enters the microlens 204, after reflection and refraction by the second trench isolation structure 1062 and the first trench isolation structure 1061, the spectral absorption range can be broadened, thereby enhancing optical efficiency. To further enhance light reflection and refraction, the first trench isolation structure 1061 and the second trench isolation structure 1062 are configured such that, for each first trench isolation structure 1061, the radial dimension of the first trench isolation structure 1061 gradually decreases as the depth of the first trench isolation structure 1061 increases; and for each second trench isolation structure 1062, the radial dimension of the second trench isolation structure 1062 gradually decreases as the depth of the second trench isolation structure 1062 increases.

[0054] In summary, the present invention provides a method for fabricating a semiconductor structure, a semiconductor structure, and an image sensor. The method for fabricating the semiconductor structure includes: providing a substrate; forming a hard mask layer on the substrate and etching the substrate to form a plurality of recesses on the substrate, wherein the substrate between adjacent recesses forms a convex portion; depositing an oxide layer on the substrate, the oxide layer covering the recesses and convex portions; etching a portion of the oxide layer at the bottom of the recesses and the oxide layer at the top of the convex portions, retaining the oxide layer on the sidewalls of the convex portions, the oxide layer on the sidewalls of the convex portions forming a barrier layer; simultaneously etching the substrate at the bottom of the recesses and the substrate at the top of the convex portions to form a first trench at the location of the recesses and a second trench at the location of the convex portions, the depth of the first trench being greater than the depth of the second trench; filling the first trench and the second trench with a dielectric to form a first trench isolation structure and a second trench isolation structure. This invention provides a method for fabricating a semiconductor structure, the semiconductor structure itself, and an image sensor. An unexpected benefit is that, during the formation of the first and second trenches, recesses are first formed on the substrate, with protrusions formed between the recesses. Then, a barrier layer is formed on the sidewalls of the recesses, and using the barrier layer as a mask, the substrate at the bottom of the recesses and the substrate at the top of the protrusions are etched, simultaneously forming the first and second trenches of different depths on the substrate. Finally, a dielectric is filled into the first and second trenches to form first and second trench isolation structures of different depths. This allows the formation of the first and second trench isolation structures of different depths using a single photomask, saving a photomask and significantly reducing process costs. When the formed semiconductor structure is placed on a back-illuminated image sensor, positioning it between the microlens and the photodiode increases photoelectric conversion efficiency. Furthermore, by setting the trench isolation structure such that its radial dimension gradually decreases with increasing trench isolation structure depth, light reflection and refraction are further increased, thereby increasing light conversion efficiency and improving the performance of the image sensor.

[0055] The embodiments of the present invention disclosed above are merely illustrative of the invention. The embodiments do not exhaustively describe all details, nor do they limit the invention to the specific implementations described. Clearly, many modifications and variations can be made based on the content of this specification. This specification selects and specifically describes these embodiments to better explain the principles and practical applications of the invention, thereby enabling those skilled in the art to better understand and utilize the invention. The invention is limited only by the claims and their full scope and equivalents.

Claims

1. A method for fabricating a semiconductor structure, characterized in that, Includes the following steps: Provide a substrate; A patterned hard mask layer is formed on the substrate, and the substrate is etched to form a plurality of recesses on the substrate, with protrusions formed between adjacent recesses; An oxide layer is deposited on the substrate, the oxide layer covering the recess and the protrusion; Etch a portion of the oxide layer at the bottom of the recess and the oxide layer at the top of the protrusion, while retaining the oxide layer on the sidewall of the protrusion, which forms a barrier layer; Simultaneously etch the substrate at the bottom of the recess and the substrate at the top of the protrusion, form a first trench at the location of the recess, and form a second trench at the location of the protrusion, wherein the depth of the first trench is greater than the depth of the second trench; A medium is filled into the first trench and the second trench to form a first trench isolation structure and a second trench isolation structure.

2. The method for fabricating a semiconductor structure according to claim 1, characterized in that, The barrier layer covers the sidewalls of the protrusion and part of the bottom wall of the recess.

3. The method for fabricating a semiconductor structure according to claim 1, characterized in that, Using a tetramethylammonium hydroxide solution, the substrate at the bottom of the recess and the substrate at the top of the protrusion are simultaneously etched.

4. The method for fabricating a semiconductor structure according to claim 1, characterized in that, The wider the barrier layer, the greater the spacing between the first trench isolation structure and the second trench isolation structure.

5. The method for fabricating a semiconductor structure according to claim 1, characterized in that, The cross-sections of the first groove and the second groove are inverted triangles.

6. The method for fabricating a semiconductor structure according to claim 1, characterized in that, The medium filled in the first trench and the second trench is a high dielectric constant material.

7. A semiconductor structure, characterized in that, The semiconductor structure is formed using a method for fabricating a semiconductor structure as described in any one of claims 1 to 6, and the semiconductor structure comprises: Substrate; A first trench isolation structure and a second trench isolation structure are disposed in the substrate, wherein the depth of the first trench isolation structure is greater than the depth of the second trench isolation structure.

8. An image sensor, characterized in that, include: Circuit wiring layer; A photodiode is disposed on one side of the circuit wiring layer; The semiconductor structure as described in claim 7 is disposed on the side of the photodiode away from the circuit wiring layer; A filter is disposed on the side of the semiconductor structure away from the photodiode; A microlens is disposed on the side of the filter away from the semiconductor structure.

9. The image sensor according to claim 8, characterized in that, In the growth direction of the image sensor, the second trench isolation structure in the semiconductor structure is located on the line connecting the microlens and the photodiode.

10. The image sensor according to claim 8, characterized in that, For each of the first trench isolation structures, as the depth of the first trench isolation structure increases, the radial dimension of the first trench isolation structure gradually decreases; for each of the second trench structures, as the depth of the second trench isolation structure increases, the radial dimension of the second trench isolation structure gradually decreases.

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