Pulse width modulation DC-DC conversion circuit and DC-DC converter

Abstract

The invention discloses a pulse width modulation direct current-direct current conversion circuit and a direct current-direct current converter, and relates to the field of integrated circuits, and the direct current-direct current conversion circuit comprises an output circuit and a detection control circuit. The output circuit is used for receiving an input voltage and outputting an output voltage; the output voltage is higher than the input voltage; the detection control circuit is connected with the output circuit and is used for generating a pulse width modulation driving signal after receiving the output voltage, the reference voltage, the input clock and the external digital control signal; and controlling the charging current of the output circuit to charge the output voltage at the highest allowable current or the current which is positively correlated with the difference value between the preset voltage and the output voltage, and outputting a high voltage establishment completion identification signal when the output voltage reaches the preset value. The circuit is simple in structure, has power-on starting current limitation, and can generate an identification signal after the high voltage is established.

Description

Technical Field

[0001] This application relates to the field of integrated circuits, and in particular to a pulse width modulation DC-DC conversion circuit and a DC-DC converter. Background Technology

[0002] Currently, DC-DC converters have important applications in MEMS gyroscope interface integrated circuits. In particular, boost DC-DC converters provide a sufficiently high bias voltage for MEMS gyroscopes to generate a sufficiently high electrostatic force to achieve closed-loop feedback of the gyroscope drive axis and provide a large C / V conversion sensitivity for the gyroscope detection axis. MEMS gyroscopes operate at their inherent resonant frequencies of the drive axes, typically in the range of 3kHz to 20Hz, and are particularly sensitive to frequency interference. Signals near the resonant frequency should be avoided in the chip to prevent resonance interference. MEMS gyroscopes are often used in multi-axis integration, which limits the power-on startup current of the interface chip, typically with a maximum value of tens of milliamps. MEMS gyroscopes require a high voltage to be fully established before they can start operating; therefore, a high voltage generation circuit is needed to provide an indication signal indicating that the high voltage has been established. A MEMS gyroscope is a complex system with multiple integrated modules, requiring the circuit modules to be as simple as possible while ensuring functionality and performance to save area and power consumption. Furthermore, MEMS gyroscopes may operate in extreme temperature environments, requiring the interface circuit to have strong environmental adaptability.

[0003] DC-DC converters commonly operate in two modes: PFM (Pulse Frequency Modulation) and PWM (Pulse Width Modulation). In PFM mode, the DC-DC converter's operating frequency dynamically changes with the load, causing frequency interference to the gyroscope and reducing its performance. Existing PWM mode DC-DC converters are structurally complex, requiring numerous circuit modules, resulting in higher area and power consumption, limited boost efficiency, fixed ramp signal slope and amplitude, limited environmental adaptability, lack of power-on current limiting, and no high-voltage setup completion indication signal, making it difficult to meet the requirements for on-chip integration in MEMS gyroscopes. Summary of the Invention

[0004] The purpose of this application is to provide a pulse width modulation DC-DC conversion circuit and DC-DC converter with a simple circuit structure, a power-on start-up current limit, and the ability to generate an identification signal after the high voltage is established.

[0005] To achieve the above objectives, this application provides the following solution: In a first aspect, this application provides a pulse width modulation DC-DC converter circuit, comprising: An output circuit is used to receive an input voltage and output an output voltage; the output voltage is higher than the input voltage. A detection control circuit, connected to the output circuit, is used to generate a pulse width modulation drive signal after receiving the output voltage, reference voltage, input clock and external digital control signal, and control the charging current of the output circuit to charge the output voltage at the maximum allowable current or a current positively correlated with the difference between the preset voltage and the output voltage. When the output voltage reaches the preset value, a high voltage establishment completion indicator signal is output.

[0006] Secondly, this application provides a pulse width modulation DC-DC converter, including the aforementioned pulse width modulation DC-DC conversion circuit.

[0007] According to the specific embodiments provided in this application, this application has the following technical effects: This application provides a pulse width modulation (PWM) DC-DC conversion circuit and a DC-DC converter. The circuit controls the charging current of the output circuit by detecting and controlling a PWM drive signal generated by the control circuit, thereby ensuring the output voltage reaches a preset value. The charging current is limited, specifically using a maximum allowable current or a current positively correlated with the difference between the preset voltage and the output voltage. After the output voltage reaches the preset value, the control circuit outputs a high-voltage establishment completion indicator signal to indicate whether the output voltage has been successfully established. Therefore, this application features a simple circuit structure, limits the power-on initiation current, and generates an indicator signal upon high-voltage establishment, making it highly practical. Attached Figure Description

[0008] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0009] Figure 1 A schematic diagram of the circuit structure of a traditional boost DC-DC converter; Figure 2 A modular schematic diagram of a pulse width modulation DC-DC converter circuit provided in an embodiment of this application; Figure 3 This is a schematic diagram of the output circuit and detection control circuit provided in an embodiment of this application; Figure 4 A detailed structural schematic diagram of a detection control circuit provided in an embodiment of this application; Figure 5 This is a waveform diagram of a pulse width modulation DC-DC converter circuit provided in an embodiment of this application. Detailed Implementation

[0010] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0011] To make the above-mentioned objectives, features and advantages of this application more apparent and understandable, the application will be further described in detail below with reference to the accompanying drawings and specific embodiments.

[0012] Currently, traditional pulse-width modulation (PWM) boost DC-DC converters are relatively complex, requiring numerous circuit modules. Their boost efficiency is limited, the ramp signal slope and amplitude are fixed, environmental adaptability is limited, and they lack power-on start-up current limits and high-voltage establishment completion indication signals, making it difficult to meet the operational requirements of MEMS gyroscopes. For example... Figure 1 As shown, a conventional boost DC-DC converter includes an N-type power transistor MN_PW, a power diode D_PW, an inductor L, a resistor divider circuit (composed of resistors R1 and R2), an error amplifier EA, a comparator CMP, a current sensing module ISEN, a ramp signal generator RAMP, a logic controller LOGIC, and a driver for the power transistor MN_PW.

[0013] when Figure 1 When the circuit is working, the voltage divider circuit obtains the voltage V that is equal to the output voltage V. OUT Proportional feedback voltage V FB The difference between the reference voltage and the input clock voltage is amplified by the error amplifier EA to obtain the upper limit voltage of the ramp signal. The ramp signal generator RAMP generates a ramp signal with a certain slope that is consistent with the input clock CLK frequency, and it is superimposed with the output voltage of the current detection module ISEN to generate a composite signal after ramp compensation. The output of the error amplifier EA and the composite ramp signal are input to the comparator CMP for comparison, and a judgment signal is generated and output to the logic control circuit LOGIC. The logic control circuit LOGIC outputs a control pulse, which is driven by the driver to control the conduction time of the N-type power transistor, thereby controlling the charging current of the inductor to obtain the desired output voltage.

[0014] Figure 1Traditional pulse-width modulation (PWM) boost DC-DC converters require inductor current detection to achieve peak current mode loop control. Detecting the inductor current necessitates additional complex detection, amplification, and sampling circuitry, increasing the impedance of the power transistor branch, increasing power loss, and reducing boost efficiency. The synthesis of the ramp signal and the inductor current detection signal requires additional adding circuitry. The ramp signal comparison voltage is output by an error amplifier, but the error amplifier's output range is limited and affected by temperature and manufacturing processes. In extreme temperatures such as -55°C and 125°C used in MEMS gyroscope applications, and under extreme load conditions such as no-load or heavy-load conditions, the ramp comparison voltage can easily exceed the effective output range of the error amplifier, leading to decreased pulse-width modulation accuracy and output voltage performance. Furthermore, traditional PWM boost DC-DC converters lack pulse width limitation, posing a risk of insufficient power supply for multi-axis MEMS gyroscope integration due to excessive boost current. They also fail to provide a high-voltage establishment completion indicator signal, making on-chip combined startup control with MEMS gyroscopes impossible.

[0015] Based on the above problems, and after extensive research, practical testing, and simulation, this application creatively proposes a pulse width modulation DC-DC conversion circuit and a DC-DC converter. The following is a detailed explanation and description of this application.

[0016] In one exemplary embodiment, such as Figure 2 As shown, a pulse width modulation DC-DC converter circuit is provided, including an output circuit 100 and a detection and control circuit 200.

[0017] Output circuit 100 receives input voltage and outputs output voltage; the output voltage is higher than the input voltage. Detection and control circuit 200 is connected to output circuit 100. After receiving output voltage, reference voltage, input clock, and external digital control signals, detection and control circuit 200 generates a pulse width modulation drive signal and controls the charging current of output circuit 100 to charge the output voltage at the maximum allowable current or a current positively correlated with the difference between the preset voltage and the output voltage. It charges the output voltage node, and when the output voltage reaches the preset value, it outputs a high-voltage establishment completion indicator signal.

[0018] In one specific embodiment, such as Figure 3 As shown, the output circuit 100 includes: an inductor L, a power transistor MN_PW, and a power diode D_PW. Figure 3 In the middle, V IN Indicates the input voltage, V OUT Indicates the output voltage, V SW R represents the voltage at the second terminal of inductor L, i.e., the drain voltage of power transistor MN_PW and the anode voltage of power diode D_PW. L and CL These represent the output voltage V. OUT The load resistance and load capacitance.

[0019] The first terminal of the inductor receives the input voltage V. IN The second terminal of the inductor is connected to the drain of the power transistor MN_PW and the anode of the power diode D_PW, respectively; the gate of the power transistor MN_PW is connected to the detection and control circuit 200, and the source of the power transistor MN_PW is grounded; the cathode of the power diode D_PW outputs the output voltage V. OUT .

[0020] In this embodiment, the power transistor MN_PW is turned on by a signal, and the power diode D_PW is forward-biased or reverse-biased by the voltage difference between its anode and cathode to achieve voltage conversion. The power transistor MN_PW and the power diode D_PW cannot be simultaneously turned on and forward-biased, but they can be simultaneously turned off and reverse-biased. That is, when the power transistor MN_PW is turned on, the power diode D_PW is reverse-biased; when the power diode D_PW is forward-biased, the power transistor MN_PW is turned off; or, the power transistor MN_PW and the power diode D_PW can be simultaneously turned off and reverse-biased.

[0021] As a preferred approach, the inductor L can be located outside the chip, while other circuit components can be integrated within the chip. Alternatively, in this embodiment, the output circuit 100 is a boost converter. The pulse-width modulation DC-DC converter circuit described in this embodiment can also be applied to a buck converter structure. In this case, the connection relationships of the inductor L, power transistor MN_PW, and power diode D_PW in the output circuit 100 will be adjusted. The specific connection relationships are prior art and will not be described here.

[0022] In one specific embodiment, such as Figure 3 As shown, the detection control circuit 200 includes: a voltage sampling circuit 210, a voltage-controlled pulse generation module 220, and a drive module 230.

[0023] The voltage sampling circuit 210 is connected to the cathode of the power diode D_PW and is used to receive the output voltage V. OUT and output detection voltage V S .

[0024] The first input terminal of the voltage-controlled pulse generation module 220 receives the reference voltage V. R The second input terminal of the voltage-controlled pulse generation module 220 is connected to the voltage sampling circuit 210 to receive the detected voltage V. SThe third input terminal of the voltage-controlled pulse generation module 220 receives the input clock CLK, and the fourth input terminal of the voltage-controlled pulse generation module 220 receives the external digital control signal D. The first output terminal of the voltage-controlled pulse generation module 220 is connected to the input terminal of the drive module 230; the first output terminal of the voltage-controlled pulse generation module 220 outputs a pulse width adjustment pulse signal PULSE to the input terminal of the drive module 230; the second output terminal of the voltage-controlled pulse generation module 220 outputs a high voltage establishment completion indicator signal RDY.

[0025] The output terminal of the drive module 230 is connected to the gate of the power transistor MN_PW. The output terminal of the drive module 230 outputs a pulse width modulation drive signal S to the gate of the power transistor MN_PW to control the power transistor MN_PW to turn on or off. When the pulse width modulation drive signal S is high, the power transistor MN_PW is turned on, and when the pulse width modulation drive signal S is low, the power transistor MN_PW is turned off.

[0026] The high voltage establishment completion indicator signal RDY represents the output voltage V. OUT Whether the setup is complete, i.e., the output voltage V OUT Has the voltage risen to the preset value? The high voltage establishment completion indicator signal RDY is low, indicating the output voltage V. OUT High voltage establishment not yet complete; the high-level indicator signal RDY indicates that the output voltage V is not yet established. OUT Creation complete.

[0027] When the output voltage V OUT Below the reference voltage V R When multiplied by the first ratio, the output voltage V OUT Not yet established; when the output voltage V OUT Higher than or equal to the reference voltage V R When multiplied by the first ratio, the output voltage V OUT Establishment complete. The first ratio is the ratio of the sum of the resistance values ​​of the first resistor R1 and the second resistor R2 to the resistance value of the second resistor R2.

[0028] In one specific embodiment, such as Figure 3 As shown, the voltage sampling circuit 210 includes a first resistor R1 and a second resistor R2. The first terminal of the first resistor R1 is connected to the cathode of the power diode D_PW, and the first terminal of the first resistor R1 receives the output voltage V. OUT The second end of the first resistor R1 is connected to the first end of the second resistor R2 and the second input end of the voltage-controlled pulse generation module 220, respectively; the second end of the second resistor R2 is grounded.

[0029] The first resistor R1 and the second resistor R2 constitute a voltage sampling circuit 210, which samples the output voltage V. OUTBy performing voltage division, the detection voltage V is obtained. S Detecting voltage V S As the input to the second input terminal of the voltage-controlled pulse generation module 220.

[0030] In one specific embodiment, such as Figure 4 As shown, the voltage-controlled pulse generation module 220 includes: a first transistor M1, a second transistor M2, a third transistor M3, a first capacitor C1, an error amplifier 221, a Schmitt trigger 222, an energy storage capacitor array 223, a comparator 224, and a logic control circuit 225.

[0031] The non-inverting input of error amplifier 221 receives the reference voltage V. R The inverting input of error amplifier 221 is connected to the second terminal of the first resistor R1 to receive the detected voltage V. S The output terminal of error amplifier 221 is connected to the gate of the first transistor M1, the gate of the second transistor M2, and the first terminal of the first capacitor C1, respectively; the output terminal of error amplifier 221 outputs a control voltage V. CTRL The second terminal of the first capacitor C1 is connected to the second terminal of the energy storage capacitor array 223 and the source of the third transistor M3, respectively, and grounded; the source of the first transistor M1 and the source of the second transistor M2 are connected and connected to the power supply.

[0032] The first terminal of the energy storage capacitor array 223 is connected to the second current source I. B2 The non-inverting input of comparator 224, the drain of the second transistor M2, and the drain of the third transistor M3 are connected; the third terminal of the energy storage capacitor array 223 receives the external digital control signal D.

[0033] The inverting input of comparator 224 receives the reference voltage V. R The output of comparator 224 is connected to the second input of logic control circuit 225, and the output of comparator 224 outputs a voltage comparison signal H to the second input of logic control circuit 225.

[0034] The first input terminal of the logic control circuit 225 receives the input clock CLK, the first output terminal of the logic control circuit 225 is connected to the driver module 230, and the first output terminal of the logic control circuit 225 outputs a pulse width modulation pulse signal PULSE; the second output terminal of the logic control circuit 225 is connected to the gate of the third transistor M3, and the second output terminal of the logic control circuit 225 outputs a reset signal RST to the gate of the third transistor M3.

[0035] The input terminals of the Schmitt trigger 222 are connected to the drain of the first transistor M1 and the first current source I, respectively. B1 Connect and receive current status signal V CThe output of the Schmitt trigger 222 outputs a high voltage establishment completion indicator signal RDY.

[0036] In one specific embodiment, such as Figure 4 As shown, the energy storage capacitor array 223 includes: a fourth transistor M4, a fifth transistor M5, a sixth transistor M6, a second capacitor C2, a third capacitor C3, a fourth capacitor C4, and a fifth capacitor C5.

[0037] The first terminal of the second capacitor C2 is connected to the second current source I. B2 The non-inverting input of comparator 224, the drain of the second transistor M2, the drain of the third transistor M3, the drain of the fourth transistor M4, the drain of the fifth transistor M5, and the drain of the sixth transistor M6 are connected. The voltage across the drains of the fourth transistor M4, the fifth transistor M5, and the sixth transistor M6 is V. RAMP .

[0038] The second terminal of the second capacitor C2 is connected to the second terminals of the first capacitor C1, the third capacitor C3, the fourth capacitor C4, and the fifth capacitor C5, respectively.

[0039] The first terminal of the third capacitor C3 is connected to the source of the sixth transistor M6, the first terminal of the fourth capacitor C4 is connected to the source of the fifth transistor M5, and the first terminal of the fifth capacitor C5 is connected to the source of the fourth transistor M4.

[0040] The gate of the fourth transistor M4 receives the first digital control signal D[0] from the external digital control signal D, the gate of the fifth transistor M5 receives the second digital control signal D[1] from the external digital control signal D, and the gate of the sixth transistor M6 receives the third digital control signal D[2] from the external digital control signal D.

[0041] The duration of the low level of the voltage comparison signal H output from the output terminal of comparator 224 is equal to the leakage current of the second transistor M2 and the duration of the low level of the second current source I. B2 Reference voltage V R It is a function of the effective capacitance value of the energy storage capacitor array 223. Where the second current source I... B2 It is a constant current, with a reference voltage V. R The voltage is constant, and the leakage current of the second transistor M2 is determined by the control voltage V. CTRL The effective capacitance value of the energy storage capacitor array 223 is adjusted and controlled by an external digital control signal D. During the high-level period of the input clock CLK, the width (high-level duration) of the pulse width modulation (PWM) pulse signal PULSE is equal to the low-level duration of the voltage comparison signal H. The PWM pulse signal PULSE is used to control the on-time of the power transistor MN_PW, thereby controlling the output voltage V. OUTThe charging current. The width of the pulse width modulation pulse signal PULSE output by the voltage-controlled pulse generation module 220 is also determined by the leakage current of the second transistor M2 and the reference voltage V. R Second current source I B2 The output voltage V is determined by the external digital control signal D, which in turn affects the output voltage V with a corresponding current. OUT Charge.

[0042] Second current source I B2 The base current is provided to charge the energy storage capacitor array 223; the third transistor M3, according to the reset signal RST output by the logic control circuit 225, when RST is high, increases the voltage V on the upper plate of the energy storage capacitor array 223. RAMP (That is, the voltage at the first terminal of the energy storage capacitor array 223) is rapidly discharged to zero. Comparator 224 then discharges the voltage V at the upper plate of the energy storage capacitor array 223 to zero. RAMP and reference voltage V R The voltage comparison signal H is obtained by comparing the voltages on the upper plates of the energy storage capacitor array 223. When the voltage V on the upper plate of the energy storage capacitor array 223... RAMP Less than the reference voltage V R When the voltage comparison signal H is low, the logic control circuit 225 controls the pulse width modulation pulse signal PULSE to output a high level, and the drive module 230 outputs a high-level pulse width modulation drive signal S to control the power transistor MN_PW to turn on. When the voltage V on the upper plate of the energy storage capacitor array 223 is low... RAMP Greater than the reference voltage V R When the voltage comparison signal H is high, the logic control circuit 225 controls the pulse width modulation pulse signal PULSE to output a low level, and the drive module 230 outputs a low-level pulse width modulation drive signal S to control the power transistor MN_PW to turn off.

[0043] In one specific embodiment, such as Figure 4 As shown, the logic control circuit 225 includes: a D flip-flop DFF, a NAND gate ND, and an inverter INV.

[0044] The clock input CK of the D flip-flop (DFF) is connected to the output of comparator 224 to receive the voltage comparison signal H. The data input D of the DFF is connected to the inverting output of the D flip-flop. Connect the inverting output terminal of the D flip-flop. It is also connected to the first input of the NAND gate D, and the inverting reset terminal of the D flip-flop. Both the second input of the NAND gate ND and the second input of the NAND gate ND receive the input clock CLK. The output of the NAND gate ND is connected to the input of the inverter INV, and the output of the NAND gate ND outputs a reset signal RST to the input of the inverter INV. The output of the inverter INV is connected to the input of the driver module 230, and the output of the inverter INV outputs a pulse width modulation pulse signal PULSE to the driver module 230. The driver module 230 is a conventional cascaded inverter group, which is prior art and will not be described in detail here.

[0045] In this embodiment, the logic control circuit 225 receives the input clock CLK and the voltage comparison signal H to determine the operating state of the DC-DC conversion circuit. The logic control module 225 generates the control logic desired by the detection control circuit 200 based on the input clock CLK and the voltage comparison signal H. The reset signal RST is used to control the on and off states of the third transistor M3. Since the gate load capacitance of the power transistor is relatively large, a drive module 230 is designed. The drive module 230 receives the pulse width modulation pulse signal PULSE generated by the logic control circuit 225, enhances its drive current, and generates the gate control signal of the power transistor MN_PW, i.e., the pulse width modulation drive signal S, to control the on and off states of the power transistor MN_PW, thereby controlling the output voltage V. OUT The charging current.

[0046] The working principle of the pulse width modulation DC-DC converter circuit provided in this embodiment is as follows: At the start of the operating cycle of the pulse width modulation DC-DC converter circuit, the input clock CLK is low, the inverted output of the D flip-flop DFF in the logic control circuit 225 is reset to high, that is, the voltage compare and hold signal HR is high, the reset signal RST output of the NAND gate ND is set to high, and the voltage V on the upper plate of the energy storage capacitor array 223... RAMP Rapidly discharge to zero level. The pulse width modulation pulse signal PULSE output from inverter INV is set low, and power transistor MN_PW is turned off. If at this time the anode voltage V of power diode D_PW is... SW Below the cathode voltage V OUT and diode threshold voltage V DTH With the sum of the two, power diode D_PW is turned off, and power diode D_PW does not supply power to the output voltage V. OUT Provides charging current.

[0047] When the input clock CLK is high, the error amplifier 221 amplifies the reference voltage V. R and detection voltage V S The difference when the detection voltage V S Much lower than the reference voltage V R At that time, the control voltage V output by the error amplifier 221CTRL With the power supply voltage as the reference voltage, the first transistor M1 and the second transistor M2 operate in the cutoff region, and the leakage current of both M1 and M2 is 0. The drain voltage V of M1... C By the first current source I B1 Pull to low level, i.e., current status signal V C When the signal is low, the Schmitt trigger 222 receives a low-level current state signal V. C The high voltage establishment completion indicator signal RDY is also low, indicating that the output voltage V... OUT Not yet higher than the reference voltage V R The product of the first ratio. Since the leakage current of the second transistor M2 is 0, only the second current source I... B2 The upper plate of the energy storage capacitor array 223 is charged, and the voltage V of the upper plate of the energy storage capacitor array 223 is... RAMP The voltage gradually increases from zero. When the voltage V on the upper plate of the energy storage capacitor array 223... RAMP Below the reference voltage V R When the voltage comparison signal H output by comparator 224 is low, the voltage comparison holding signal HR output by the inverted output of the D flip-flop DFF in logic control circuit 225 remains high. The reset signal RST output by the NAND gate ND is pulled low by the input clock CLK, the third transistor M3 is turned off, and the pulse width modulation pulse signal PULSE output by the inverter is pulled high. During the period when the pulse width modulation pulse signal PULSE is high, the power transistor MN_PW is turned on, the anode voltage of the power diode D_PW is pulled to zero, and the power diode D_PW is reverse biased and turned off. When the voltage V on the upper plate of the energy storage capacitor array 223... RAMP Gradually rise to above the reference voltage V R When the voltage comparison signal H output by comparator 224 changes from low to high, the voltage comparison hold signal HR output by the inverting output of the D flip-flop DFF becomes low, and the reset signal RST output by the NAND gate ND is pulled high by the voltage comparison hold signal HR, thus turning on the third transistor M3. The voltage V on the upper plate of the energy storage capacitor array 223... RAMP When the circuit is rapidly discharged to zero, the voltage comparison signal H output by comparator 224 is pulled low. Since the D flip-flop (DFF) is triggered on the rising edge of the clock, the output voltage comparison hold signal HR will not change as the voltage comparison signal H goes low. At this time, the pulse width modulation pulse signal PULSE output by inverter INV is pulled low.

[0048] When the second transistor M2 is in the cutoff region, the pulse width modulation pulse signal PULSE remains high for the longest time, approximately: Among them, C TC represents the effective capacitance value of the energy storage capacitor array 223. The on / off state of the fourth transistor M4, fifth transistor M5, and sixth transistor M6 in the energy storage capacitor array 223 is determined by the external digital control signal D; therefore, the capacitance value C of the energy storage capacitor array 223 is... T It is also determined by the external digital control signal D, C T It can be represented as: When D[2] is high, D[2]=1; when D[2] is low, D[2]=0. The cases of D[1] and D[0] are the same and will not be described further. The external digital control signal D is used to adjust the voltage V on the upper plate of the energy storage capacitor array 223. RAMP The rising slope is used to compensate for parameter changes in error amplifier 221, second transistor M2, and second capacitor C2 caused by manufacturing processes, so that V RAMP The upward slope is kept within an appropriate range.

[0049] Second current source I B2 Its function is to limit the boost charging current of the DC-DC converter circuit. This prevents the current from increasing when the detected voltage V... S Much lower than the reference voltage V R When the second transistor M2 is turned off, the voltage V on the upper plate of the energy storage capacitor array 223 decreases. RAMP The inability to raise the voltage level results in the pulse width modulation pulse signal PULSE remaining at a high level for too long, the power transistor MN_PW being on for too long, and the charging current of the inductor L being too large, exceeding the maximum drive current allowed by the power supply of the MEMS gyroscope multi-axis integrated system. This poses a risk of insufficient power supply upon power-up, leading to system startup failure.

[0050] When the detection voltage V S Approximately and slightly below the reference voltage V R At that time, the control voltage V output by the error amplifier 221 CTRL From the reference voltage V R and detection voltage V S The difference determines the voltage V. S and reference voltage V R The larger the difference, the greater the control voltage V. CTRL The higher the potential, the lower the leakage current I of the second transistor M2. M2 The smaller the value, the lower the voltage V on the upper plate of the energy storage capacitor array 223. RAMP Rise to reference voltage V R The longer the required time, the longer the pulse width modulation pulse signal PULSE remains high, the longer the power transistor MN_PW is turned on, and the longer the inductor L outputs voltage V. OUT The higher the charging current, the higher the output voltage V. OUT The faster the rate of increase, the better. (Detection voltage V)S and reference voltage V R The smaller the difference, the lower the control voltage V. CTRL The lower the potential, the lower the leakage current I of the second transistor M2. M2 The larger the voltage V on the upper plate of the energy storage capacitor array 223, the greater the voltage V. RAMP Rise to reference voltage V R The shorter the required time, the shorter the time the pulse width modulation pulse signal PULSE is held high, the shorter the time the power transistor MN_PW is turned on, and the shorter the output voltage V of the inductor L. OUT The smaller the charging current, the lower the output voltage V. OUT The slower the ascent.

[0051] The function of the first capacitor C1 is to filter out the voltage V detected by the sensor. S jitter causes the control voltage V CTRL The generated ripple. When the second transistor M2 is in the saturation region, the pulse width modulation pulse signal PULSE remains high for approximately: When the inductor L outputs voltage V OUT Average charging current and output voltage V OUT When the average load current is equal, the output voltage V OUT The detection voltage V remains constant. Because the error amplifier 221 has a large amplification gain (>40dB), the detection voltage V... S Approximately equal to the reference voltage V R That is, the output voltage V OUT Equal to reference voltage V R The product of the first ratio. The leakage current of the first transistor M1 is a mirror copy of the leakage current of the second transistor M2. By designing the first current source I... B1 The current value is set slightly lower than the output voltage V. OUT The leakage current of the second transistor M2 at maximum load current. When the sensing voltage V... S Approximate reference voltage V R At that time, the leakage current of the first transistor M1 is higher than that of the first current source I. B1 The current, control voltage V C It is pulled high. The function of the Schmitt trigger 222 is to shield the leakage current disturbance of the second transistor M2, so that the high voltage establishment completion indicator signal RDY remains stable, and at the same time, it makes the high voltage establishment completion indicator signal RDY relative to the control voltage V. C After a certain delay, the high voltage establishment indicator signal RDY goes high when the output voltage V is reached. OUT Equal to reference voltage V R After multiplying by the first ratio, the output voltage V is now... OUT It is stable enough.

[0052] During the low-level period of the pulse width modulation pulse signal PULSE, the power transistor MN_PW is turned off. Since the current in the inductor L cannot change instantaneously, the anode voltage of the power diode D_PW is pulled up to be higher than the output voltage V. OUT and diode threshold voltage V DTH The sum of these two forces causes the power diode D_PW to forward bias and conduct, supplying voltage V to the output voltage. OUT Provides charging current. As charge flows to the output voltage V... OUT Transfer, output voltage V OUT As the charging current gradually increases and decreases, the anode voltage V of the power diode D_PW gradually increases. SW Gradually decrease, when V SW Below the output voltage V OUT and diode threshold voltage V DTH When the summation occurs, the power diode D_PW is reverse-biased and turns off, stopping the supply of power to the output voltage V. OUT During charging, the DC-DC conversion circuit completes its operating cycle, and the input clock CLK changes from high to low, entering the next operating cycle.

[0053] like Figure 5 As shown, during the period when the input clock CLK is high, when the output voltage V OUT Much lower than the reference voltage V R When multiplied by the first ratio, the second transistor M2 in the voltage-controlled pulse generation module 220 is turned off, and the second current source I... B2 The upper plate of the energy storage capacitor array 223 is charged with a constant minimum current, and the voltage V of the upper plate of the energy storage capacitor array 223 is... RAMP The boost rate is the slowest and constant, the power transistor MN_PW has the longest conduction time, and the charging current I flowing through the inductor L is the longest. L Maximum, output voltage V OUT The fastest rise time. When the output voltage V... OUT Approximate reference voltage V R When multiplied by the first ratio, the second transistor M2 and the second current source I in the voltage-controlled pulse generation module 220... B2 The upper plates of the energy storage capacitor array 223 are charged together, and the voltage V of the upper plates of the energy storage capacitor array 223 is... RAMP The boost rate is determined by the output voltage V OUT and reference voltage V R The difference between the product of the first ratio and the first proportion determines the output voltage V. OUT and reference voltage V R The smaller the difference between the product of the first ratio and the first ratio (including negative values), the lower the voltage V on the upper plate of the energy storage capacitor array 223. RAMPThe slower the boost rate, the longer the conduction time of the power transistor MN_PW, and the longer the charging current I flowing through the inductor L. L The larger the value, the higher the output voltage V. OUT The faster the ascent rate, the higher the output voltage V. OUT and reference voltage V R The larger the difference between the product of the first ratio and the first ratio (including negative values), the greater the voltage V on the upper plate of the energy storage capacitor array 223. RAMP The faster the boost rate, the shorter the conduction time of the power transistor MN_PW, and the greater the charging current I flowing through the inductor L. L The smaller the value, the lower the output voltage V. OUT The slower the rate of increase, the more significant the increase in the charging current I of inductor L. L When the voltage drops to 0, the power diode D_PW is reverse-biased and cut off until the input clock CLK rises from low to high again, at which point the next duty cycle begins. During this period, the load current affects the output voltage V. OUT Discharge, output voltage V OUT The voltage decreases slowly. When the output voltage V... OUT Below the reference voltage V R When the difference between the product of the first ratio and the first proportion is reached, the leakage current of the first transistor M1 in the voltage-controlled pulse generation module 220 is lower than that of the first current source I. B1 The current and high voltage establishment completion indicator signal RDY is low. When the output voltage V... OUT Approximately equal to the reference voltage V R When the difference is the product of the first ratio, due to the high amplification gain of the error amplifier 221, the inductor L is directed towards the output voltage V. OUT Average charging current I L Equal to output voltage V OUT Average load current I LOAD Output voltage V OUT The average value remains constant. At this time, the leakage current of the first transistor M1 in the voltage-controlled pulse generation module 220 is higher than that of the first current source I. B1 The current and high voltage establishment completion indicator signal RDY is at a high level.

[0054] In summary, the pulse width modulation DC-DC converter circuit provided in this embodiment receives the input voltage in the output circuit 100 and outputs an output voltage higher than the input voltage to the detection and control circuit 200. The detection and control circuit 200 receives the output voltage, reference voltage, input clock, and external digital control signal, and then generates a pulse width modulation drive signal S to control the conduction time of the power transistor MN_PW, thereby controlling the charging current of the inductor L. The output voltage is higher than V. OUT Below the reference voltage V R When multiplied by the first ratio, the entire circuit increases the output voltage V with the maximum permissible charging current. OUTEnsure the charging current is within the system's power supply capacity range. Output voltage V OUT Approximate reference voltage V R When multiplied by the first ratio, the error amplifier 221 amplifies the difference between the two. The output voltage of the error amplifier 221 controls the second transistor M2 to charge the upper plate of the energy storage capacitor array 223, thereby controlling the pulse width of the pulse width modulation pulse signal PULSE and the output voltage V of the inductor L. OUT The charging current. Although the error amplifier 221 also suffers from the limited output range problem encountered in conventional structures, the output of the error amplifier 221 adjusts the voltage rise rate of the energy storage capacitor by controlling the gate voltage of the transistor and thus the leakage current of the transistor. Since the current is proportional to the square of the gate voltage, this control method allows for a wider range of current adjustment, as well as a wider range of adjustment for the capacitor plate voltage rise rate and pulse width. Compared to conventional structures, it can adapt to a wider temperature range and load range. Output voltage V OUT Equal to reference voltage V R When multiplied by the first ratio, the DC-DC converter circuit generates a high-voltage establishment indicator signal RDY, transitioning from a low level to a high level, providing the necessary signal for sensor system control. The DC-DC converter circuit provided in this embodiment has a simple structure, few modules, and advantages such as low power consumption and high boost efficiency. It employs an operational amplifier to control the charging current to achieve pulse width modulation, resulting in stronger environmental and load adaptability. With boost current limiting and a high-voltage establishment completion indicator signal, it facilitates the system integration and control of MEMS inertial sensors, demonstrating high practical value.

[0055] In one exemplary embodiment, a pulse width modulation (PWM) DC-DC converter is provided, which includes the PWM DC-DC conversion circuit described above.

[0056] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0057] This document uses specific examples to illustrate the principles and implementation methods of this application. The descriptions of the above embodiments are only for the purpose of helping to understand the methods and core ideas of this application. Furthermore, those skilled in the art will recognize that, based on the ideas of this application, there will be changes in the specific implementation methods and application scope. Therefore, the content of this specification should not be construed as a limitation of this application.

Claims

1. A pulse width modulated DC-DC conversion circuit, characterized by, The application relates to a high-voltage output circuit. The output circuit receives an input voltage and outputs an output voltage; The output voltage is higher than the input voltage; The detection control circuit is connected with the output circuit, and generates a pulse width modulation driving signal after receiving the output voltage, a reference voltage, an input clock and an external digital control signal, and controls the charging current of the output circuit to charge the output voltage with the highest allowable current or a current positively related to the difference between a preset voltage and the output voltage; when the output voltage reaches the preset value, a high-voltage establishment completion identification signal is output.

2. The pulse width modulated DC-DC conversion circuit according to claim 1, characterized in that, The output circuit comprises an inductor, a power transistor and a power diode; The first end of the inductor receives the input voltage, and the second end of the inductor is connected with the drain of the power transistor and the anode of the power diode respectively; the gate of the power transistor is connected with the detection control circuit, and the source of the power transistor is grounded; and the cathode of the power diode outputs the output voltage.

3. The pulse width modulated DC-DC conversion circuit according to claim 2, characterized in that, The detection control circuit comprises a voltage sampling circuit, a voltage-controlled pulse generation module and a driving module; The voltage sampling circuit is connected with the cathode of the power diode, receives the output voltage and outputs a detection voltage; The first input end of the voltage-controlled pulse generation module receives the reference voltage, the second input end of the voltage-controlled pulse generation module is connected with the voltage sampling circuit and receives the detection voltage, the third input end of the voltage-controlled pulse generation module receives the input clock, and the fourth input end of the voltage-controlled pulse generation module receives the external digital control signal; the first output end of the voltage-controlled pulse generation module is connected with the input end of the driving module; the second output end of the voltage-controlled pulse generation module outputs the high-voltage establishment completion identification signal; and the output end of the driving module is connected with the gate of the power transistor.

4. The pulse width modulated DC-DC conversion circuit according to claim 3, characterized in that, The voltage sampling circuit comprises a first resistor and a second resistor; The first end of the first resistor is connected with the cathode of the power diode, the second end of the first resistor is connected with the first end of the second resistor and the second input end of the voltage-controlled pulse generation module respectively, and the second end of the second resistor is grounded.

5. The pulse width modulated DC-DC conversion circuit according to claim 4, characterized in that, The voltage-controlled pulse generation module comprises a first transistor, a second transistor, a third transistor, a first capacitor, an error amplifier, a Schmitt trigger, an energy storage capacitor array, a comparator and a logic control circuit; The non-inverting input end of the error amplifier receives the reference voltage, the inverting input end of the error amplifier is connected with the second end of the first resistor, the output end of the error amplifier is connected with the gate of the first transistor, the gate of the second transistor and the first end of the first capacitor respectively, the second end of the first capacitor is connected with the second end of the energy storage capacitor array and the source of the third transistor and grounded, and the source of the first transistor and the source of the second transistor are connected and grounded; The first end of the energy storage capacitor array is connected with a second current source, the non-inverting input end of the comparator, the drain of the second transistor and the drain of the third transistor respectively, and the third end of the energy storage capacitor array receives the external digital control signal. An inverting input terminal of the comparator receives the reference voltage, and an output terminal of the comparator is connected with a second input terminal of the logic control circuit; A first input terminal of the logic control circuit receives the input clock, a first output terminal of the logic control circuit is connected with the driving module, and a second output terminal of the logic control circuit is connected with a gate of the third transistor; An input terminal of the Schmitt trigger is connected with a drain of the first transistor and a first current source respectively, and an output terminal of the Schmitt trigger outputs a high-voltage establishment completion identification signal.

6. The pulse width modulated DC-DC conversion circuit according to claim 5, characterized in that, The energy storage capacitor array comprises a fourth transistor, a fifth transistor, a sixth transistor, a second capacitor, a third capacitor, a fourth capacitor and a fifth capacitor; A first terminal of the second capacitor is connected with the second current source, a non-inverting input terminal of the comparator, a drain of the second transistor, a drain of the third transistor, a drain of the fourth transistor, a drain of the fifth transistor and a drain of the sixth transistor respectively; and a second terminal of the second capacitor is connected with a second terminal of the first capacitor, a second terminal of the third capacitor, a second terminal of the fourth capacitor and a second terminal of the fifth capacitor respectively; A first terminal of the third capacitor is connected with a source of the sixth transistor, a first terminal of the fourth capacitor is connected with a source of the fifth transistor, and a first terminal of the fifth capacitor is connected with a source of the fourth transistor; A gate of the fourth transistor receives a first digital control signal in the external digital control signal, a gate of the fifth transistor receives a second digital control signal in the external digital control signal, and a gate of the sixth transistor receives a third digital control signal in the external digital control signal.

7. The pulse width modulated DC-DC conversion circuit according to claim 6, characterized in that, The logic control circuit comprises a D flip-flop, a NAND gate and an inverter; A clock input terminal of the D flip-flop is connected with an output terminal of the comparator, a data input terminal of the D flip-flop is connected with an inverted output terminal of the D flip-flop, the inverted output terminal of the D flip-flop is also connected with a first input terminal of the NAND gate, and an inverted reset terminal of the D flip-flop and a second input terminal of the NAND gate both receive the input clock; an output terminal of the NAND gate is connected with an input terminal of the inverter, and an output terminal of the inverter is connected with an input terminal of the driving module.

8. The pulse width modulated DC-DC conversion circuit according to claim 5, characterized in that, A low-level duration of a voltage comparison signal output by the output terminal of the comparator is a function of a drain current of the second transistor, the second current source, the reference voltage and an effective capacitance value of the energy storage capacitor array.

9. The pulse width modulated DC-DC conversion circuit according to claim 4, characterized in that, The high-voltage establishment completion identification signal is low to represent that the output voltage is not established, and the high-voltage establishment completion identification signal is high to represent that the output voltage is established. When the output voltage is lower than a product of the reference voltage and a first proportion, the output voltage is not established; and when the output voltage is higher than or equal to the product of the reference voltage and the first proportion, the output voltage is established. The first proportion is a ratio of a sum of a resistance value of the first resistor and a resistance value of the second resistor to the resistance value of the second resistor.

10. A pulse width modulated DC-DC converter, characterized by The pulse width modulated DC-DC converter comprises a pulse width modulated DC-DC conversion circuit according to any one of claims 1 to 9.

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