Sine wave generation based on flexible pulse width modulation (PWM) technology

Abstract

The invention relates to sine wave generation based on flexible pulse width modulation (PWM) technology. Apparatus, systems, and methods for sine wave generation based on flexible pulse width modulation (PWM) techniques. An example apparatus may include sine wave generator circuitry and pulse width modulation timer circuitry coupled to the sine wave generator circuitry. The sine wave generator circuitry may include phase accumulator circuitry and phase-to-amplitude conversion circuitry coupled to the phase accumulator circuitry. The phase accumulator circuitry may be configured to receive a digital input value and output a phase value. The phase-to-amplitude conversion circuitry may be configured to receive the phase value and output a digital sinusoidal value. The pulse width modulation timer circuitry may be configured to receive the digital sinusoidal values and output at least one pulse width modulated signal for generating an analog carrier signal. The frequency of the analog carrier signal may be based on the digital input value.

Description

TECHNICAL FIELD

[0001] Example embodiments of the present disclosure relate generally to sine wave generation based on flexible pulse width modulation (PWM) techniques. BACKGROUND

[0002] Resolver sensors can be used to determine the position of an electric motor or motor shaft. For example, in response to an analog sine wave excitation signal input, a resolver sensor can output two modulated feedback signals indicative of the angular position of the electric motor.

[0003] There is a need for new techniques for generating analog sine wave excitation signals. The inventors have found that there are numerous areas of improvement in the existing art and processes, which are the subject of the embodiments described herein. Through tireless effort, ingenuity, and innovation, many of these deficiencies, challenges, and problems have been solved by developing solutions included in embodiments of the present disclosure, some examples of which are described in detail herein. SUMMARY

[0004] Various embodiments described herein relate to sine wave generation based on flexible pulse width modulation (PWM) techniques.

[0005] According to some embodiments of the present disclosure, an example carrier generator is provided. The example carrier generator includes:

[0006] a sine wave generator circuitry, wherein the sine wave generator circuitry includes a phase accumulator circuitry and a phase-to-amplitude conversion circuitry coupled to the phase accumulator circuitry, wherein the phase accumulator circuitry is configured to receive a digital input value and output a set of phase values, and wherein the phase-to-amplitude conversion circuitry is configured to receive the set of phase values and output a set of digital sine values; and a pulse width modulation timer circuitry coupled to the sine wave generator circuitry, wherein the pulse width modulation timer circuitry is configured to receive the set of digital sine values and output at least one pulse width modulation signal for generating an analog carrier signal, wherein a frequency of the analog carrier signal is based at least in part on the digital input value.

[0007] In some embodiments, the phase accumulator circuitry and the phase-to-amplitude conversion circuitry include a digital controlled oscillator circuitry.

[0008] In some embodiments, the phase-to-amplitude conversion circuitry includes a coordinate rotation digital computer circuitry.

[0009] In some embodiments, the phase accumulator circuitry is further configured to receive the digital input value from a user of the carrier generator via a user interface.

[0010] In some embodiments, the pulse width modulation timer circuitry is further configured to receive, via a user interface, a core clock frequency value from a user of the system, and wherein a resolution associated with the pulse width modulation timer circuitry is based at least in part on the core clock frequency value.

[0011] In some embodiments, the at least one pulse width modulation signal includes a first pulse width modulation signal and a second pulse width modulation signal complementary to the first pulse width modulation signal.

[0012] In some such embodiments, the pulse width modulation timer circuitry is coupled to the amplifier and filter circuitry, wherein the amplifier and filter circuitry is configured to receive the at least one pulse width modulation signal and output the analog carrier signal.

[0013] In some embodiments, the digital input value is based at least in part on at least one of: a frequency associated with the analog carrier signal, a second frequency associated with a divide-by clock signal input to the sine wave generator circuitry, or a bit length associated with the phase accumulator circuitry.

[0014] In accordance with some embodiments of the disclosure, an example system is provided. The example system includes:

[0015] a carrier generator including: a sine wave generator circuitry, wherein the sine wave generator circuitry includes a phase accumulator circuitry and a phase-to-amplitude conversion circuitry coupled to the phase accumulator circuitry, wherein the phase accumulator circuitry is configured to receive a digital input value and output a set of phase values, and wherein the phase-to-amplitude conversion circuitry is configured to receive the set of phase values and output a set of digital sine values; and

[0016] a pulse width modulation timer circuitry coupled to the sine wave generator circuitry, wherein the pulse width modulation timer circuitry is configured to receive the set of digital sine values and output at least one pulse width modulation signal; and

[0017] an amplifier and filter circuitry coupled to the carrier generator, wherein the amplifier and filter circuitry is configured to receive the at least one pulse width modulation signal and output an analog carrier signal, wherein a frequency of the analog carrier signal is based at least in part on the digital input value.

[0018] In some embodiments, the phase accumulator circuitry and the phase-to-amplitude conversion circuitry include a digital controlled oscillator circuitry.

[0019] In some embodiments, the phase-to-amplitude conversion circuitry includes a coordinate rotation digital computer circuitry.

[0020] In some embodiments, the phase accumulator circuitry is further configured to receive, via the user interface, a digital input value from a user of the carrier generator.

[0021] In some embodiments, the pulse width modulation timer circuitry is further configured to receive, via the user interface, a core clock frequency value from a user of the system, and wherein a resolution associated with the pulse width modulation timer circuitry is based at least in part on the core clock frequency value.

[0022] In some embodiments, the at least one pulse width modulation signal includes a first pulse width modulation signal and a second pulse width modulation signal complementary to the first pulse width modulation signal.

[0023] In some embodiments, the digital input value is based at least in part on at least one of: a frequency associated with the analog carrier signal, a second frequency associated with a divide-by clock signal input to the sine wave generator circuitry, or a bit length associated with the phase accumulator circuitry.

[0024] According to some embodiments of the disclosure, an example carrier generator is provided. The example carrier generator includes:

[0025] a sine wave generator circuitry, wherein the sine wave generator circuitry includes a phase accumulator circuitry and a phase-to-amplitude conversion circuitry coupled to the phase accumulator circuitry, wherein the phase accumulator circuitry is configured to receive a digital input value and output a set of phase values, and wherein the phase-to-amplitude conversion circuitry is configured to receive the set of phase values and output a set of digital sine values; and a pulse width modulation timer circuitry coupled to the sine wave generator circuitry, wherein the pulse width modulation timer circuitry is configured to receive the set of digital sine values and output at least one pulse width modulation signal for generating an analog carrier signal, wherein a frequency of the analog carrier signal is based at least in part on the digital input value.

[0026] In some embodiments, the phase accumulator circuitry and the phase-to-amplitude conversion circuitry include a digital-to-oscillator circuitry.

[0027] In some embodiments, the phase-to-amplitude conversion circuitry includes a coordinate rotation digital computer circuitry.

[0028] In some embodiments, the phase accumulator circuitry is further configured to receive, via the user interface, a digital input value from a user of the carrier generator.

[0029] In some embodiments, the pulse width modulation timer circuitry is further configured to receive, via the user interface, a core clock frequency value from a user of the system, and wherein a resolution associated with the pulse width modulation timer circuitry is based at least in part on the core clock frequency value.

[0030] In some embodiments, the at least one pulse width modulated signal includes a first pulse width modulated signal and a second pulse width modulated signal complementary to the first pulse width modulated signal.

[0031] In some such embodiments, the pulse width modulator timer circuitry is coupled to the amplifier and filter circuitry, and wherein the amplifier and filter circuitry is configured to receive the at least one pulse width modulated signal and output the analog carrier signal.

[0032] In some embodiments, the digital input value is based at least in part on at least one of: a frequency associated with the analog carrier signal, a second frequency associated with a divided clock signal input to the sine wave generator circuitry, or a bit length associated with the phase accumulator circuitry.

[0033] According to some embodiments of the disclosure, an example method is provided. The example method includes:

[0034] obtaining, at a sine wave generator circuitry, a digital input value, wherein the sine wave generator circuitry includes a phase accumulator circuitry and a phase to amplitude conversion circuitry coupled to the phase accumulator circuitry, wherein the phase accumulator circuitry is configured to output a set of phase values based at least in part on the digital input value, and wherein the phase to amplitude conversion circuitry is configured to receive the set of phase values and output a set of digital sine values; and

[0035] outputting, via a pulse width modulator timer circuitry coupled to the sine wave generator circuitry, at least one pulse width modulated signal, wherein the pulse width modulator timer circuitry is configured to output the at least one pulse width modulated signal based at least in part on the set of digital sine values, and wherein a frequency associated with the at least one pulse width modulated signal is based at least in part on the digital input value.

[0036] In some embodiments, the phase accumulator circuitry and the phase to amplitude conversion circuitry include a digital controlled oscillator circuitry.

[0037] In some embodiments, the phase to amplitude conversion circuitry includes a coordinate rotation digital computer circuitry.

[0038] In some embodiments, the method includes obtaining, at the pulse width modulator timer circuitry, a core clock frequency value, wherein a resolution associated with the pulse width modulator timer circuitry is based at least in part on the core clock frequency value.

[0039] In some embodiments, the at least one pulse width modulated signal includes a first pulse width modulated signal and a second pulse width modulated signal complementary to the first pulse width modulated signal.

[0040] The above summary is provided merely for purposes of summarizing some example embodiments to provide a basic understanding of some aspects of the disclosure. Accordingly, it will be appreciated that the above described embodiments are merely example and should not be construed as limiting the scope or spirit of the disclosure in any way. It will further be appreciated that the scope of the disclosure encompasses many potential embodiments, some of which will be further described hereinafter. BRIEF DESCRIPTION OF DRAWINGS

[0041] Certain example embodiments of the present disclosure are generally described above, reference will now be made to the following drawings, which are not necessarily to scale, and wherein:

[0042] Figure 1 illustrates an exemplary carrier generator configured for sine wave generation based on flexible PWM techniques in accordance with one or more embodiments of the present disclosure;

[0043] Figure 2 illustrates an exemplary plot of a sine wave generated based on flexible PWM techniques in accordance with one or more embodiments of the present disclosure;

[0044] Figure 3 illustrates an exemplary carrier generator configured for sine wave generation based on flexible PWM techniques in accordance with one or more embodiments of the present disclosure;

[0045] Figure 4 illustrates an exemplary carrier generator configured for sine wave generation based on flexible PWM techniques in accordance with one or more embodiments of the present disclosure;

[0046] Figure 5 illustrates an exemplary resolver sensor system configured for sine wave generation based on flexible PWM techniques in accordance with one or more embodiments of the present disclosure;

[0047] Figure 6 illustrates a flowchart of the operation of a carrier generator in accordance with one or more embodiments of the present disclosure; and

[0048] Figure 7 illustrates an exemplary device in accordance with one or more embodiments of the present disclosure. DETAILED DESCRIPTION

[0049] Some embodiments of the disclosure will now be described more fully with reference to the accompanying drawings, in which some embodiments of the disclosure are shown. The disclosure may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein; rather, these embodiments are provided by way of example so that this disclosure will satisfy applicable legal requirements. Throughout the disclosure, like reference numerals are used to refer to like elements throughout.

[0050] As used herein, the term “includes” means includes but not limited to, and should be interpreted in the manner it is typically used in the patent context. The use of the more general term “comprises” or “comprising” should be interpreted to provide support for the more specific term “consisting of” or “consisting essentially of” and “consisting substantially of”.

[0051] The phrases “in various embodiments,” “in one embodiment,” “according to one embodiment,” “in some embodiments,” and the like generally mean that the particular feature, structure, or characteristic following the phrase can be included in at least one embodiment of the present disclosure, and can be included in more than one embodiment of the present disclosure (importantly, such phrases do not necessarily refer to the same embodiment).

[0052] The word “example” or “exemplary” is used herein to mean “serving as an example, instance, or illustration.” Any implementation described herein as “exemplary” is not necessarily to be construed as preferred or advantageous over other implementations.

[0053] If the specification states a component, or feature “may”, “can”, “might” or “could” be included or the specification states a component or feature “should”, “would”, “is likely to”, “is likely”, “is expected to”, “is expected”, “is anticipated”, “is intended” to be included, it is not a requirement that the component or feature be included. The component or feature can be optionally included, or can be excluded.

[0054] Use of the term “circuitry” as a modifier to a given function or set of functions, as used herein, should be understood to encompass both analog and digital circuitry, and / or one or more processors configured with software and / or firmware that carry out the given function or set of functions, unless otherwise indicated. The term “circuitry” should not be interpreted as applying only to fixed logic but can also be realized in firmware or software that executes on a processor, or any combination thereof.

[0055] Overview

[0056] Various embodiments of the present disclosure relate to improved generation of analog sine waves.

[0057] A resolver sensor is a type of position sensor used for electric motor or motor shaft positioning. For example, a resolver sensor can be used to determine a rotational position of an electric motor or motor shaft. A resolver sensor can receive an analog sinusoidal excitation signal as input and, in response, output modulated feedback signals (e.g., two modulated feedback signals). The modulated feedback signals can be indicative of a rotational (e.g., angular) position of the electric motor. In other words, a resolver sensor can use an analog sinusoidal excitation signal (e.g., with a particular resolution) to provide two modulated feedback signals related to a position (e.g., angular) of an electric motor. In some examples, a resolver sensor includes a resolver interface that includes circuitry embedded in a system on chip (SoC), for example, to support a resolver system.

[0058] Conventional methods for generating an analog sinusoidal wave (also referred to herein as a carrier wave) for a resolver sensor can be rigid and result in increased power consumption. For example, some conventional methods for generating an analog sinusoidal wave rely on a local memory approach in which digital values are stored (e.g., pre-stored) in a local memory and scanned in order to provide the digital values of the sinusoidal wave. In such examples, a digital-to-analog converter (DAC) is used to convert the digital values to an analog sinusoidal wave. However, in some cases, the digital values pre-stored in the local memory are fixed (e.g., the number and size of the samples pre-stored in the memory are fixed), which can result in reduced flexibility and / or increased die size. For example, because the number and size of the samples pre-stored in the memory are fixed, the resolution of the sinusoidal wave to be generated is also fixed. To increase the resolution of the sinusoidal wave, a user can increase the number of values stored in the local memory. However, increasing the number of values can require increasing the size of the local memory, thereby increasing the die size.

[0059] Other conventional methods for generating an analog sinusoidal wave can rely on a software approach in which a central processing unit (CPU) is used to generate and calculate the digital values of the sinusoidal wave. In such examples, a DAC is used to convert the digital values to an analog sinusoidal wave. However, in some cases, the software uses an interrupt service routine to call hardware (e.g., to generate an analog sinusoidal wave based on the digital values), which can result in increased processing costs and increased latency. That is, the interrupt service routine can increase data traffic within the SoC (e.g., within the SoC interconnect), thereby increasing power consumption and latency.

[0060] The present disclosure generally relates to improved carrier generators. Among other things, the present disclosure includes improved methods for generating digital values for a sinusoidal wave.

[0061] Various embodiments of the carrier generator of the present disclosure use direct digital synthesis (DDS) techniques and incorporate an internal pulse width modulation (PWM) timer to generate an analog sinusoidal wave. In some embodiments, the carrier generator includes a digital counter with a configurable step size. For example, an input to the digital counter can include a frequency control word (e.g., a digital value) that is a function of a bit length associated with the digital counter, a frequency division clock frequency, and a frequency of an analog sinusoidal wave (e.g., a carrier) output by the carrier generator. Accordingly, a user can use the frequency control word to dynamically adjust a frequency of the carrier. In some embodiments, the user can dynamically adjust the frequency control word, and thus the frequency of the carrier, via a dedicated software register. In some such embodiments, the user can adjust the frequency of the carrier over a relatively wide range (e.g., approximately 10 kHz to approximately 40 kHz) and with a relatively fine resolution. In some examples, by using a digital counter with a configurable step size, the carrier generator can provide increased flexibility.

[0062] In some embodiments, the digital counter is coupled to a phase-to-amplitude converter. For example, the digital counter can be an example of a phase accumulator that can output a set of phase values based on an input frequency control word. In some embodiments, the phase accumulator and the phase-to-amplitude converter can be implemented together in a numerically controlled oscillator (NCO). That is, the carrier generator can include a NCO that includes a phase accumulator and a phase-to-amplitude converter. The set of phase values output from the phase accumulator can be input into the phase-to-amplitude converter. The phase-to-amplitude converter can use the set of phase values (e.g., rotations) to compute a set of digital sinusoidal values. For example, in some embodiments, the phase-to-amplitude converter includes a coordinate rotation digital computer (CORDIC) that performs real-time phase-to-amplitude conversion based on the output of the phase accumulator. In other words, the phase-to-amplitude converter (e.g., CORDIC) can include a hardware-efficient iterative method that uses rotations (e.g., angle values determined from the output of the digital counter) to compute digital sinusoidal values. In some examples, by using the phase-to-amplitude converter to generate digital sinusoidal values in real-time, the carrier generator can provide reduced die size and reduced latency.

[0063] In some embodiments, the phase-to-amplitude converter is coupled to a digital-to-analog converter. For example, the carrier generator can be included in an SoC that also includes an internal digital-to-analog converter. In some examples, the digital-to-analog converter includes a pulse width modulation (PWM) timer, where the width of a pulse output from the PWM timer is a function of the amplitude of the input signal. For example, the period of the digital signal output from the PWM timer is fixed, while the duty cycle of the digital signal varies (e.g., between 0% and 100%) based on the input signal. The duty cycle is the amount of time that the digital PWM signal is on (e.g., in an “active” state) relative to the period of the digital PWM signal. That is, each digital sinusoidal value output from the phase-to-amplitude converter can correspond to (e.g., be encoded with) a duty cycle of the PWM timer. Accordingly, the voltage provided by the digital signal output from the PWM timer is proportional to the duty cycle of the digital signal. In one non-limiting example, a duty cycle of 0% can provide a 0 voltage, while a duty cycle of 100% can provide a peak-to-peak voltage. Thus, the carrier generator can generate an analog sinusoidal wave by using the digital sinusoidal values to vary the duty cycle of the digital signal output from the PWM timer (and, in turn, the voltage) over time. As described herein, flexible PWM techniques refer to PWM techniques in which the period of the PWM timer can be dynamically configured. For example, the SoC can include embedded custom logic for driving the PWM timer. In such examples, the SoC can include a core clock, and the period of the PWM timer can be equal to the period of the core clock. In some embodiments, in accordance with flexible PWM techniques, a user can select the period of the core clock (e.g., can select the core clock frequency) via dedicated software registers. Thus, the present disclosure can provide for dynamically modifying (e.g., configuring) the period of the PWM timer. Moreover, by providing a sinusoidal wave generator (e.g., a sinusoidal duty cycle generator) that generates the duty cycle of the PWM timer in real-time, the present disclosure can provide for a reduced die size of the SoC, and increased flexibility of the carrier generator relative to techniques that can rely on a fixed set of digital values (e.g., a lookup table) stored in local memory.

[0064] Exemplary apparatus, systems, and methods

[0065] Embodiments of the present disclosure herein include systems and apparatuses for sinusoidal wave generation described herein that can be implemented in various embodiments. Exemplary embodiments include a carrier generator configured to generate a sinusoidal wave using sinusoidal wave generator circuitry and digital-to-analog converter circuitry in accordance with one or more embodiments of the present disclosure.

[0066] Figure 1An exemplary carrier generator 100 configured for sine wave generation based on flexible PWM techniques is illustrated in accordance with one or more embodiments of the present disclosure. As depicted, the carrier generator 100 includes sine wave generator circuitry 102 and digital-to-analog converter circuitry 108.

[0067] In some embodiments, the carrier generator 100 is configured to generate a set of digital values of a sine wave using the sine wave generator circuitry 102. For example, as depicted, the sine wave generator circuitry 102 includes phase accumulator circuitry 104 and phase-to-amplitude conversion circuitry 106, where the sine wave generator circuitry 102 is configured to generate the set of digital values of the sine wave using a combination of the phase accumulator circuitry 104 and the phase-to-amplitude conversion circuitry 106. In some embodiments, the phase accumulator circuitry 104 (e.g., with a configurable STEP) is configured to produce a set of angle values. For example, the phase accumulator circuitry 104 can receive a digital value 101 (e.g., a configurable STEP, a frequency control word) and output a set of phase values 103 (e.g., corresponding to the set of angle values) based on the digital value 101.

[0068] As depicted, the phase accumulator circuitry 104 can be coupled to the phase-to-amplitude conversion circuitry 106. Accordingly, the phase-to-amplitude conversion circuitry 106 can receive the set of phase values 103 and output a set of digital sine values 105. In some embodiments, the phase-to-amplitude conversion circuitry 106 can be an example of a CORDIC configured to perform real-time computation of digital sine values based on input angle values (e.g., the set of phase values 103). As described herein, real-time computation refers to a computation that occurs in response to receiving an input (e.g., immediately upon receiving the input, such as within a few milliseconds).

[0069] As depicted, the digital-to-analog converter circuitry 108 can receive the set of digital sine values 105 and output an analog signal 107. That is, the digital-to-analog converter circuitry 108 can be configured to convert the set of digital sine values 105 into an analog sine wave (e.g., a carrier, the analog signal 107). In some examples, the carrier generator 100 is included in a SoC. In some such examples, the digital-to-analog converter circuitry 108 can be configured to convert the set of digital sine values 105 into the analog signal 107 with or without support of one or more components external to the SoC. For example, in some embodiments, the digital-to-analog converter circuitry 108 can include a PWM timer. In such examples, the digital-to-analog converter circuitry 108 can be configured to generate the analog signal 107 (e.g., a sine wave) in accordance with (e.g., based on) flexible PWM techniques.

[0070] Figure 2FIGURE 2A and FIGURE 2B illustrate example graphs 200A and 200B of a sine wave generated based on flexible PWM techniques in accordance with one or more embodiments of the present disclosure.

[0071] Various embodiments of the present disclosure provide for analog sine wave generation using direct digital synthesis (DDS) techniques in conjunction with an internal PWM timer, where embedded custom logic is used to drive the internal PWM timer. The period of a PWM signal (e.g., PWM signal 202A, PWM signal 202B) output from the PWM timer can be fixed, while the corresponding duty cycle of the PWM signal can vary (e.g., between 0% and 100%). For example, the PWM timer is configured with a period (e.g., period 206A, period 206B). The duty cycle of the PWM signal during the period refers to the amount of time the digital signal is on (e.g., an “active” state) relative to the period. Accordingly, as depicted in graph 200A, the duty cycle of PWM signal 202A during period 206A is 75%. Further, as depicted in graph 200B, the duty cycle of PWM signal 202B during period 206B is 50%. The voltage (e.g., average voltage) of the PWM signal output from the PWM timer is proportional to the duty cycle. For example, the voltage of PWM signal 202A during period 206A is 75% of the peak-to-peak voltage associated with the PWM timer. Accordingly, point B in graph 200A corresponds to an amplitude of 75% of the peak amplitude, which occurs at point C (where the duty cycle is 100%, so the voltage is 100% of the peak-to-peak voltage). Further, the voltage of PWM signal 202B during period 206B is 50% of the peak-to-peak voltage associated with the PWM timer. Accordingly, point A in graph 200B corresponds to an amplitude of 50% of the peak amplitude, which occurs at point C (where the duty cycle is 100%, so the voltage is 100% of the peak-to-peak voltage). A carrier generator can use the PWM timer to generate an analog sine wave (e.g., analog sine wave 204A, analog sine wave 204B) by varying the duty cycle of the digital signal output from the PWM timer over time.

[0072] In some embodiments, the duty cycle of the digital signal output from the PWM timer is based on a digital value input into the PWM timer. Accordingly, in such embodiments, each digital value input into the PWM timer corresponds to a respective duty cycle for the PWM timer. In some embodiments, the digital values input to the PWM timer (and, thus, the duty cycle values) are generated internally. For example, the carrier generator can include a sine wave generator configured to generate a set of digital values in real-time. In other words, the sine wave generator (e.g., a sine duty cycle generator) is configured to generate a duty cycle for the PWM timer in real-time, thereby reducing the die size of the SoC and, for example, improving the flexibility of the carrier generator relative to techniques that can rely on a fixed set of digital values (e.g., a lookup table) stored in local memory and reducing latency relative to techniques that can rely on a CPU to generate the duty cycle for the PWM.

[0073] In some embodiments, the frequency of the analog sine wave (e.g., the excitation sine wave) output from the PWM timer can be configured by a user of the carrier generator. For example, the frequency of the analog sine wave 204A (e.g., 10 kHz) and the frequency of the analog sine wave 204B (e.g., 20 kHz) can be programmed by a user via a dedicated software register. In some embodiments, the frequency of the analog sine wave can be programmed over a relatively wide range (e.g., approximately 10 kHz to approximately 40 Hz) and with a relatively fine resolution (e.g., up to a threshold resolution value, such as approximately 9.5 Hz). In some embodiments, the frequency of the analog sine wave can be programmed via a frequency control word (e.g., selected by a user via a dedicated software register). In some such embodiments, the frequency resolution of the analog sine wave (e.g., how finely the resulting frequency of the generated analog sine wave can be changed by changing the frequency control word) can be based on the number of bits associated with the phase accumulator (e.g., the NCO counter bits) that are used to generate the duty cycle for the PWM timer.

[0074] In some embodiments, the resolution of the PWM timer corresponds to the granularity with which the duty cycle can be modulated (e.g., to accurately reproduce a corresponding sinusoidal wave sample, the respective duty cycle of each PWM period can be modulated with more precision, e.g., through successive digital-to-analog conversions). In some embodiments, the resolution of the PWM timer can be based on a ratio between a peripheral clock frequency and a core clock frequency of the sinusoidal wave generator. In some embodiments, the ratio can be denoted as ARR. Accordingly, in some embodiments, the PWM resolution can be configured (e.g., selected) by a user. For example, the core clock period can be defined by a user via a software programmable register (e.g., defined according to a selected core clock frequency generated by a SoC clock controller). The period of the PWM timer corresponds to the duration of the PWM pattern repetition (e.g., a new duty cycle of the PWM signal 202A can begin after the duration of the PWM period 206A, and a new duty cycle of the PWM signal 202B can begin after the duration of the PWM period 206B).

[0075] In some embodiments, the number of PWM samples (e.g., the number of points per period of the generated analog sinusoidal wave) can be based on a ratio between the frequency of the core clock and the frequency of the analog sinusoidal wave to be generated. For example, 8 PWM samples (e.g., 8 duty cycles, which correspond to points A-H in the graph 200A) can be used to generate a period of the analog sinusoidal wave 204A (e.g., an analog sinusoidal wave with a frequency of approximately 10 kHz). Further, 4 PWM samples (e.g., 4 duty cycles, which correspond to points A-G in the graph 200B) can be used to generate a period of the analog sinusoidal wave 204B (e.g., an analog sinusoidal wave with a frequency of approximately 20 kHz).

[0076] Figure 3 FIG. illustrates an exemplary carrier generator 300 configured for sinusoidal wave generation based on flexible PWM techniques, in accordance with one or more embodiments of the present disclosure.

[0077] As depicted, the FCW 302 (e.g., a frequency control word register) can output a digital value 301. In some embodiments, a user can select the digital value 301 via the FCW 302. For example, a user can select the digital value 301 (e.g., a frequency control word) using a user interface, which can be provided to (and stored in) the FCW 302. The digital value 301 corresponds to the frequency of the analog signal 331 output from the carrier generator 300. In other words, the digital value 301 indicates the frequency of the analog signal 331. Accordingly, a user can select a digital value corresponding to a desired frequency for the analog signal 331.

[0078] The phase accumulator circuitry 304 can be configured to output a set of phase values based on the digital value 301. For example, the phase accumulator circuitry 304 can be an example of a digital counter that can count by the digital value 301 (e.g., a step size). In some embodiments, as depicted, the phase accumulator circuitry 304 includes adder circuitry 306 and phase register circuitry 308 configured with a sampling time (T s ). In some such embodiments, the digital value 301 is input to the adder circuitry 306 coupled to the phase register circuitry 308. The phase register circuitry 308 is configured to output a set of phase values (e.g., a sequence of phase values) over the sampling time (T s ), where each phase value in the set of phase values is generated by incrementing (e.g., via the adder circuitry 306) a generated phase value (e.g., a starting phase value or a previously generated phase value) by an amount based on the digital value 301. In some examples, the incrementing the generated phase value is responsive to the divided clock input signal 313A.

[0079] For example, the phase register circuitry 308 can be a digital counter having a quantity of digital states. Accordingly, the phase register circuitry 308 can store a digital state (e.g., a binary value corresponding to a starting phase value or a previously generated phase value) and can increment the digital state of the phase register circuitry 308 responsive to the divided clock input signal 313A (e.g., for each system clock input pulse from the divided clock circuitry 312). The size of the increment is based on the digital value 301. For example, the phase accumulator circuitry 304 can include a binary counter (e.g., having an input step size corresponding to the digital value 301) configured to sweep an angle from 0° to 360° over the sampling time (e.g., based on the digital value 301). In some such examples, the set of binary values output from the phase register circuitry 308 can be converted to a set of radian values (e.g., corresponding to respective angles) via the multiplier circuitry 310. That is, the phase accumulator circuitry 304 includes the multiplier circuitry 310 configured to convert the set of binary values output from the phase register circuitry 308 to a first set of phase values 309 (e.g., radian values), e.g., by multiplying the set of binary values by π (or some other suitable value). In some embodiments, such as embodiments in which the phase accumulator circuitry 304 is a modulo-N digital counter having 2 N digital states, the phase values (e.g., each phase value) of the first set of phase values 309 can be expressible using N bits.

[0080] That is, the phase accumulator circuitry 304 (e.g., the phase register circuitry 308 within the phase accumulator circuitry 304) accumulates phase values within a range that can correspond to an entire cycle of a waveform (e.g., a period of a sine wave), such as 0 to 2p radians (e.g., 0° to 360°). In other words, to sweep through an angle from 0° to 360°, the phase accumulator circuitry 304 accumulates phase values within a range of 0 to 2p radians. In one non-limiting example, for a modulo-N digital counter having 2 N digital states, the phase accumulator circuitry 304 can map the 2 N digital states to 0 to 2p radians, where each phase value corresponds to a particular angle within a cycle of a waveform. Further, the phase accumulator circuitry 304 can start at 0° (or some other suitable phase value) and can increment the phase value (e.g., the digital state) in response to (e.g., at each of) the divided clock input signals 313A. Accordingly, when the phase value (e.g., the digital state of the phase register circuitry 308) becomes greater than 360° (e.g., greater than 2p radians), the phase accumulator circuitry 304 (e.g., the binary counter) can restart counting from 0°. The frequency at which the phase accumulator circuitry 304 sweeps through an angle from 0° to 360° (e.g., completes an entire cycle of a waveform, sweeps 0 to 2p radians) is based on the size of the increment, which can be determined based on the digital value 301. Accordingly, in some embodiments, the digital value 301 (v[n]) can be a function of the bit length (n) of the phase accumulator circuitry 304, the frequency associated with the divided clock circuitry 312 (e.g., the sampling time (T s )) and the desired frequency of the analog signal 331 to be generated. The carrier generator 300 can include a peripheral clock, and the divided clock circuitry 312 can be configured to divide the frequency associated with the peripheral clock such that the divided clock circuitry 312 can output the divided clock input signals 313A (and 313B) according to a frequency (e.g., a lower frequency) that is different from the peripheral clock frequency. In some embodiments, the divided clock circuitry 312 can be referred to as a core clock.

[0081] In some embodiments, the CORDIC circuitry 316 includes an algorithm that outputs an amplitude of a sine wave based on a corresponding phase of the sine wave. In some such embodiments, a number of bits used to drive the CORDIC circuitry 316 (e.g., B bits) can be less than N bits. Accordingly, the carrier generator 300 can include phase truncation circuitry 314 configured to reduce a number of bits output by the phase accumulator circuitry 304 to a number of bits used to drive the CORDIC circuitry 316 (e.g., configured to convert the first set of phase values 309 to the second set of phase values 311, each phase value can be expressed by B bits).

[0082] In some embodiments, the CORDIC circuitry 316 is configured to receive the second set of phase values 311 and output a set of digital sine values 315. In some embodiments, the CORDIC circuitry 316 can be synchronized with the phase accumulator circuitry 304 via the frequency division clock circuitry 312. For example, the CORDIC circuitry 316 can be configured to output the set of digital sine values 315 based on the frequency division clock input signal 313B. In other words, the CORDIC circuitry 316 (e.g., a hardware-efficient iterative method) uses iterative rotations to calculate an amplitude of a sine wave (e.g., a digital value of a sine wave, such as the digital values of points A, B, C, D, E, F, G, and H shown in FIG. 3B) where a rate at which the iterations occur is based on the frequency division clock circuitry 312. Accordingly, the phase accumulator circuitry 304 and the CORDIC circuitry 316 enable the carrier generator to calculate digital values of a sine wave in real-time (e.g., without using local memory). Figure 2

[0083] ​In some embodiments, the carrier generator includes arithmetic circuitry 324 configured to scale the set of digital sine values 315 to a scale associated with the PWM timer circuitry 329 (e.g., to a full scale of the PWM timer circuitry). For example, the arithmetic circuitry 324 includes a first arithmetic circuitry 318 configured to add 1 (or another suitable value) to the set of digital sine values 315 and a second arithmetic circuitry 320 configured to multiply the output of the first arithmetic circuitry 318 by 0.5 (or another suitable value). Further, the PWM timer circuitry 329 can be synchronized (e.g., can generate the PWM signals according to a clock input signal 327 (e.g., a peripheral clock) from the peripheral clock circuitry 328), where a frequency associated with the peripheral clock circuitry 328 can be a peripheral clock frequency. Accordingly, the arithmetic circuitry 324 can also include a third arithmetic circuitry 322 configured to multiply the output of the second arithmetic circuitry 320 by ARR (e.g., a ratio between the peripheral clock frequency and a core clock frequency of the sine wave generator). In some embodiments, ARR can correspond to a clock division factor (e.g., a clock division factor (CDF) value) used to determine a divided clock frequency associated with the divided clock circuitry 312.

[0084] As depicted, the scaled digital sine values 323 output from the arithmetic circuitry 324 are input into the PWM timer circuitry 329, which provides the PWM signal 325A and the PWM signal 325B. The PWM signal 325A and the PWM signal 325B can be Figure 2 shown and described Figure 2 with reference to

[0085] As depicted, the PWM signal 325A and the PWM signal 325B can be input into the amplifier and filter circuitry 330. In some embodiments, the PWM signal 325B is a complementary signal to the PWM signal 325A. For example, in some embodiments, the PWM timer circuitry 329 is configured to provide a PWM signal and a complementary PWM signal to drive an amplifier and filter circuit (e.g., the amplifier and filter circuitry 330). In some examples, the amplifier and filter circuitry 330 is configured to filter the PWM signal 325A (e.g., permanently filter the PWM signal 325A). For example, the PWM signal 325A can include high frequency components and low frequency components (e.g., can be a high frequency signal modulated at a low frequency). Accordingly, the amplifier and filter circuitry 330 can be configured to filter out the high frequency components in the PWM signal 325A (e.g., and amplify the low frequency components) to provide the analog signal 331. The analog signal 331 can be Figure 2 shown and described Figure 2An example of a simulated sinusoidal wave is depicted. In some embodiments, PWM signal 325A and PWM signal 325B (e.g., complementary PWM signals) can be used to drive amplifier and filter circuitry 330 (e.g., external amplifier and filter circuitry). For example, the amplifier can use differential inputs to generate (e.g., properly generate) an output.

[0086] Figure 4 An example of a carrier generator configured for sinusoidal wave generation based on flexible PWM techniques in accordance with one or more embodiments of the present disclosure is depicted. Carrier generator 400 can be an example of carrier generator 300 Figures 1-3 An example of carrier generator 400 is depicted and described with reference to Figures 1-3 An example of a carrier generator is depicted. For example, carrier generator 400 can include sinusoidal wave generator circuitry 402 coupled to PWM timer circuitry 424. In some embodiments, carrier generator 400 can be included in a microcontroller unit (MCU), such as an MCU used for traction inverter applications. In some such embodiments, carrier generator 400 can be included in a resolver interface of the MCU.

[0087] As depicted, carrier generator 400 includes sinusoidal wave generator circuitry 402 and PWM timer circuitry 424. Sinusoidal wave generator circuitry 402 includes phase accumulator circuitry 404 and CORDIC circuitry 414. Phase accumulator circuitry 404 can be an example of a digital counter (e.g., a binary counter) with a configurable step size. Further, CORDIC circuitry 414 can be an example of phase-to-amplitude conversion circuitry. Figures 1-3 An example of phase accumulator circuitry 404 is depicted and described with reference to Figures 1-3 An example of phase accumulator circuitry is depicted. For example, phase accumulator circuitry 404 can be an example of a digital counter (e.g., a binary counter) with a configurable step size. Further, CORDIC circuitry 414 can be an example of phase-to-amplitude conversion circuitry. Figure 3 An example of CORDIC circuitry 414 is depicted and described with reference to Figure 3 An example of CORDIC circuitry is depicted. For example, CORDIC circuitry 414 can be an example of phase-to-amplitude conversion circuitry.

[0088] As depicted, the phase accumulator circuitry 404 can receive a digital input value 401. The digital input value 401 (e.g., a configurable step size) can be a digital word (e.g., a frequency control word). For example, the carrier generator 400 can include an FCW register 410 (frequency control word register) that can store the digital input value 401. In some embodiments, a user can select the digital input value 401 via a user interface. For example, the FCW register 410 can be coupled to an APB interface 406 (advanced peripheral bus interface) through which the FCW register 410 can receive the digital input value 401 selected by the user via the user interface. The phase accumulator circuitry 404 can also receive a divided clock input signal 403. For example, the phase accumulator circuitry 404 can be configured to generate a set of phase values 405 in dependence on the divided clock input signal 403. In this example, the set of phase values 405 can be based on the digital input value 401. For example, the phase accumulator circuitry 404 can be configured to generate the set of phase values 405 by incrementing a phase value (e.g., a starting phase value or a previously generated phase value) in response to the divided clock input signal 403 (e.g., for each divided clock pulse). The size of the increment can be based on the digital input value 401.

[0089] The CORDIC circuitry 414 can be configured to receive the set of phase values 405 and output a set of digital sine values 415. In some examples, a digital sine value in the set of digital sine values 415 can correspond to an amplitude of a waveform (e.g., a sine wave) at a particular phase (e.g., angle) of the waveform within a cycle of the waveform. For example, the digital sine value can set a duty cycle of a period of a PWM timer, and thus, can correspond to an amplitude of the waveform during the period of the PWM timer.

[0090] The PWM timer circuitry 424 coupled to the sine wave generator circuitry 402 can include PWM logic circuitry 420. The PWM logic circuitry 420 is configured to receive the set of digital sine values 415 and output a PWM signal 425A. The PWM signal 425A can be a digital signal. For example, the PWM logic circuitry 420 can be configured to output the PWM signal 425A by setting a duty cycle of a period of a PWM timer based on the set of digital sine values 415. The PWM logic circuitry 420 can be configured to output the PWM signal 425A by setting a duty cycle of a period of a PWM timer based on the set of digital sine values 415. The PWM logic circuitry 420 can be configured to output the PWM signal 425A by setting a duty cycle of a period of a PWM timer based on the set of digital sine values 415. Figures 1-3 shown and described Figures 1-3An example of a PWM signal is described. For example, a period associated with the PWM signal 425A can be fixed, while a duty cycle of the PWM signal 425A can vary (e.g., between 0% and 100%) according to the set of digital sine values 415. In other words, the PWM timer circuitry 424 can use the set of digital sine values 415 to modulate the PWM signal 425A. Accordingly, the PWM signal 425A can include high frequency components and low frequency components (e.g., corresponding to the modulation of the PWM signal 425A). To obtain an analog signal based on the PWM signal 425A, the carrier generator 400 can use a low pass filter to remove the high frequency components of the PWM signal 425A. For example, the carrier generator can input the PWM signal 425A into an amplifier and filter circuitry that is configured to filter (e.g., permanently filter) the PWM signal 425A. In some examples, a complementary signal is used to drive the amplifier and filter circuitry. Accordingly, the PWM timer circuitry 424 can include an inverter 422 (e.g., an operational amplifier inverter) to generate a PWM signal 425B that can be a complementary signal to the PWM signal 425A.

[0091] Figure 5 An exemplary resolver sensor system 500 configured for sine wave generation based on flexible PWM techniques in accordance with one or more embodiments of the present disclosure is illustrated. In some embodiments, the resolver sensor system 500 includes an MCU 502. The MCU 502 can include a CPU 504 coupled to a resolver interface 508 via an APB interface 506. In some such embodiments, the resolver interface 508 includes a carrier generator 510. The carrier generator 510 can be Figures 1-4 shown and described Figures 1-4An example of a carrier generator is described. For example, the carrier generator 510 can include sine wave generator circuitry and PWM timer circuitry configured to generate a sine wave using a flexible PWM technique. In some examples, in accordance with the flexible PWM technique, the carrier generator can receive (e.g., via the APB interface 506) a digital input value and can output a PWM signal 511 A and a PWM signal 511B. In some such examples, the carrier generator 510 can output the PWM signal 511 A and the PWM signal 511B to the amplifier and filter circuitry 512, e.g., to filter out high frequency components in the PWM signal 511 A and amplify low frequency components of the PWM signal 511 A (e.g., an analog signal 513). That is, the amplifier and filter circuitry 512 can receive the PWM signal 511 A and the PWM signal 511B and can output the analog signal 513. As depicted, the analog signal 513 can be an excitation signal for the resolver 514 (e.g., a resolver sensor).

[0092] Figure 6 A flowchart 600 illustrating operation of a carrier generator (e.g., in a resolver system) in accordance with one or more embodiments of the present disclosure is shown. The operations depicted in the flowchart can be implemented by a carrier generator (such as the carrier generator 510) described above. Figures 1-5 shown and described Figures 1-5 above.

[0093] At operation 602, the carrier generator can obtain a digital input value at sine wave generator circuitry included in the carrier generator. In some embodiments, the digital input value can be obtained via a frequency control word register. For example, the carrier generator can include (or otherwise be coupled to) one or more registers, including a frequency control word register, and the one or more registers can be in communication with a CPU via an APB interface. In some embodiments, the frequency control register can be associated with a software register that a user can use (e.g., via a user interface associated with the software register) to select a frequency control word corresponding to a digital value. Phase accumulator circuitry can obtain the digital input value from the frequency control word register. The phase accumulator circuitry can be coupled to phase-to-amplitude conversion circuitry included in the carrier generator. For example, the phase accumulator circuitry can be configured to output a set of phase values based on the digital input value, and the phase-to-amplitude conversion circuitry can be configured to receive the set of phase values and output a set of digital sine values. In some embodiments, the phase accumulator circuitry and the phase-to-amplitude conversion circuitry can be (or be included in) a digital controlled oscillator circuitry. Further, in some embodiments, the phase-to-amplitude conversion circuitry can include (or be included in) CORDIC circuitry.

[0094] At operation 604, the carrier generator can output at least one pulse width modulation signal via (e.g., from) pulse width modulation timer circuitry coupled to the sine wave generator circuitry. For example, the pulse width modulation timer circuitry can be configured to output the at least one pulse width modulation signal based on the set of digital sine values output from the phase-to-amplitude conversion circuitry. In some embodiments, a frequency associated with the at least one pulse width modulation signal can be based on the digital input value. For example, the at least one pulse width modulation signal can be used to generate an analog carrier signal, where a frequency of the analog carrier signal is based on the digital input value. For example, the at least one pulse width modulation signal can include a high frequency component and a low frequency component (e.g., can be a high frequency signal modulated at a low frequency). Accordingly, the carrier generator can pass the at least one pulse width modulation signal through (e.g., can output the at least one pulse width modulation signal to) a low pass filter, which can be configured to filter out the high frequency component in the at least one pulse width modulation signal and output an analog signal 331.

[0095] Figure 7 An example device 700 is illustrated in accordance with one or more embodiments of the present disclosure. The device 700 can be a device for an application, apparatus, and / or system. For example, the device 700 can be a resolver sensor system or a device for another application, or implemented therein, such as described herein. The device 700 can be a system and / or apparatus that includes a processor 702, a memory 704, communication circuitry 706, input / output circuitry 708, a carrier generator 710, and all of these components can be connected through one or more buses 712. It should be appreciated that, in some embodiments, the device 700 can include or otherwise be coupled to one or more other components, such as a power source (e.g., a drive circuit, a traction inverter) and / or a load(s). The power source and / or load(s) can be internal or external to the device 700. For example, the power source can be coupled to at least the carrier generator 710 via a bus or one or more connectors. Additionally, or alternatively, the load(s) can be coupled to at least the carrier generator 710 via a bus or a connector.

[0096] The processor 702, although illustrated as a single block, can be comprised of multiple components and / or processor circuitry. The processor 702 can be implemented as, for instance, various components including one or more microprocessors with accompanying digital signal processors; one or more processors without accompanying digital signal processors; one or more coprocessors; one or more multi-core processors; processing circuitry; and various other processing elements. The processor can include integrated circuitry. In various embodiments, the processor 702 can be configured to execute instructions stored in the processor 702, the memory 704, or otherwise accessible to the processor 702. When executing instructions, the processor 702 can be capable of performing any of the operations and / or functions attributed to any of the disclosed embodiments. Whether configured as hardware or software methods, or combinations thereof, the processor 702 can include entities capable of performing operations in accordance with embodiments of the present disclosure when so configured.

[0097] The memory 704 can include, for example, volatile memory, non-volatile memory, or a combination thereof. Although illustrated as a single block, the memory 704 can comprise multiple memory components. In various embodiments, the memory 704 can include, for example, random access memory, cache memory, flash memory, hard disk, circuitry configured to store information, or a combination thereof. The memory 704 can be configured to write or store data, information, applications, instructions, etc. such that the processor 702 can perform various operations and / or functions in accordance with embodiments of the present disclosure. For example, in at least some embodiments, the memory 704 can be configured to buffer or cache data for processing by the processor 702. Additionally or alternatively, in at least some embodiments, the memory 704 can be configured to store program instructions for execution by the processor 702. The memory 704 can store information in the form of static and / or dynamic information. The stored information can be used and / or stored by the processor 702 when performing operations and / or functions.

[0098] The communication circuitry 706 can be implemented as circuitry, hardware, a computer program product, or a combination thereof, configured to receive and / or transmit data from / to another component or device. The computer program product can include computer-readable program instructions stored on a computer-readable medium (e.g., the memory 704) and executed by the processor 702. In various embodiments, the communication circuitry 706 (as well as the other components discussed herein) can be implemented at least in part as a portion of the processor 702, or otherwise controlled by the processor 702. The communication circuitry 706 can be in communication with the processor 702, for example, through the bus 712. Such a bus 712 can be connected to the processor 702 and can also be connected to one or more other components of the processor 702. The communication circuitry 706 can be composed of, for example, a transmitter, a receiver, a transceiver, a network interface card, and / or supporting hardware and / or firmware / software, and can be used to establish communications with other component(s), device(s), and / or system(s). The communication circuitry 706 can be configured to receive and / or transmit data that can be stored by, for example, the memory 704, through the use of one or more protocols that can be used for communication between components, devices, and / or systems.

[0099] The input / output circuitry 708 can be in communication with the processor 702 to receive instructions entered by an operator and / or to supply audible, visual, mechanical, or other output to the operator. The input / output circuitry 708 can include support devices, such as a keyboard, a mouse, a user interface, a display, a touch screen display, lights (e.g., warning lights), indicators, a speaker, and / or other input / output mechanisms. The input / output circuitry 708 can include one or more interfaces to which the support devices can connect. In various embodiments, aspects of the input / output circuitry 708 can be implemented on a device used by the operator to communicate with the processor 702. The input / output circuitry 708 can be in communication with the memory 704, the communication circuitry 706, and / or any other component, for example, through the bus 712.

[0100] The device 700 can include or otherwise be coupled to a series of registers that can be used to set one or more internal parameters, as well as exchange data with a CPU (e.g., the processor 702). The device 700 can include or otherwise be coupled to one or more interfaces (e.g., input / output circuitry 708) for integration within a microcontroller, including an Advanced Peripheral Bus (APB), a Direct Memory Access (DMA) interface, an interface for a system fault control and collection unit, and / or one or more other specialized interfaces. The device 700 can also include or otherwise be coupled to one or more clocks, including but not limited to a system clock (also referred to as a peripheral clock, which is coupled to the carrier generator 710 and used for sine wave generation), a core clock (used as a synchronization and frequency divided clock signal from the system clock), and a system DMA clock for synchronization in the DMA interface. In some embodiments, the core clock can be referred to as a divided clock.

[0101] The carrier generator 710 can be Figures 1-6 shown and described Figures 1-6 with reference to the example carrier generator described above. For example, the carrier generator 710 can include sine wave generator circuitry 720 and PWM timer circuitry 730. The carrier generator 710 receives an input signal (e.g., an input digital value) and generates an analog sine wave excitation signal based on the input digital value. In some examples, the carrier generator 710 is coupled to a resolver sensor. In some such examples, the carrier generator 710 can output the analog sine wave excitation signal to the resolver sensor, which can provide a modulated feedback signal to the device 700. The device 700 can use the modulated feedback signal to determine (e.g., calculate) a position of an electric motor.

[0102] The device 700 can be implemented in hardware, software, or a combination of hardware and software. In various embodiments, the device 700 can be implemented in an integrated circuit, an MCU (e.g., a virtual machine running in an MCU), and / or the like.

[0103] It should be readily appreciated that embodiments of the systems and apparatuses described herein can be configured in various additional and alternative manners than those expressly stated herein.

[0104] CONCLUSION

[0105] The operations and / or functions of the present disclosure have been described herein, such as in flow diagrams. As will be recognized, computer program instructions can be loaded onto a computer or other programmable apparatus (e.g., hardware) to produce a machine, such that the resulting computer or other programmable apparatus implements the operations and / or functions described in the flow diagrams' blocks. These computer program instructions can also be stored in a computer-readable memory that can direct a computer, processor, or other programmable apparatus to function in a particular manner, such that the instructions stored in the computer-readable memory produce an article of manufacture that, when executed, implements the operations and / or functions described in the flow diagrams' blocks. The computer program instructions can also be loaded onto a computer, processor, or other programmable apparatus to cause a series of operations to be performed on the computer, processor, or other programmable apparatus to produce a computer-implemented process such that the instructions that are executed on the computer, processor, or other programmable apparatus provide operations for implementing the functions and / or operations specified in the flow diagrams' blocks. The flow diagrams' blocks support combinations in means for performing the specified operations and / or functions and combinations of operations and / or functions for performing the specified operations and / or functions. It will be understood that one or more blocks of the flow diagrams, and combinations of blocks in the flow diagrams, can be implemented by special purpose hardware-based computer systems that perform the specified operations and / or functions, or combinations of special purpose hardware and computer instructions.

[0106] While this specification contains many specifics, these should not be construed as limitations on the scope of any disclosures or of any patent claims hereafter taken. Many other specifics can take their place, and not all features and / or objects explained are necessary for a particular embodiment of the present disclosure to achieve its purposes. Certain features and / or objects described in the context of separate embodiments can also be implemented in combination in a single embodiment. Conversely, various features and / or objects described in the context of a single embodiment can also be implemented separately or in any appropriate

[0107] While operations and / or functions are illustrated in the drawings in a particular order, this should not be understood as requiring such order unless otherwise specifically stated. One of ordinary skill in the art will recognize that the operations and / or functions can be performed in any order that is useful, for example, to produce a desired result. In some cases, the actions recited in the claims can be performed in a different order and still achieve desirable results. Thus, although a particular embodiment of the subject matter has been described, other embodiments can also be within the scope of the claims.

[0108] While the present detailed description has set forth various embodiments of the disclosure, the appended claims encompass other embodiments of the disclosure which are not described in detail.

[0109] In the appended claims, unless otherwise indicated the articles "a", "an", and "the" are not intended to be construed in any way as limiting as "one" or "but one". Similarly, unless otherwise indicated the articles "comprising", "containing", "having", "including", "carrying", "compromising", "united" and "in connection with" are not intended to be construed in any way such that they render the claim any less distinctive or restrictive than it would be in the absence of these terms.

Claims

1. A carrier generator, comprising: Sine wave generator circuit system, The sine wave generator circuit system includes a phase accumulator circuit system and a phase-to-amplitude conversion circuit system coupled to the phase accumulator circuit system. The phase accumulator circuit system is configured to receive digital input values ​​and output a set of phase values, and the phase-to-amplitude conversion circuit system is configured to receive the set of phase values ​​and output a set of digital sine values. The pulse width modulation timer circuit system is coupled to the sine wave generator circuit system. The pulse width modulation timer circuit system is configured to receive the set of digital sine values ​​and output at least one pulse width modulation signal to generate an analog carrier signal, wherein the frequency of the analog carrier signal is at least partially based on the digital input values.

2. The carrier generator according to claim 1, wherein, The phase accumulator circuit system and the phase-to-amplitude conversion circuit system include a numerically controlled oscillator circuit system.

3. The carrier generator according to claim 1, wherein, The phase-to-amplitude conversion circuit system includes a coordinate rotation digital computer circuit system.

4. The carrier generator according to claim 1, wherein, The phase accumulator circuitry is also configured to receive the digital input value from a user of the carrier generator via a user interface.

5. The carrier generator according to claim 1, wherein, The pulse width modulation timer circuitry is also configured to receive a kernel clock frequency value from a user of the carrier generator via a user interface, and wherein the resolution associated with the pulse width modulation timer circuitry is at least partially based on the kernel clock frequency value.

6. The carrier generator according to claim 1, wherein, The at least one pulse width modulation signal includes a first pulse width modulation signal and a second pulse width modulation signal that is complementary to the first pulse width modulation signal.

7. The carrier generator according to claim 1, wherein, The pulse width modulation timer circuit system is coupled to an amplifier and filter circuit system, wherein the amplifier and filter circuit system is configured to receive the at least one pulse width modulation signal and output the analog carrier signal.

8. The carrier generator according to claim 1, wherein, The digital input value is based, in part, on at least one of the following: a frequency associated with the analog carrier signal, a second frequency associated with a frequency-divided clock signal input to the sine wave generator circuit system, or a bit length associated with the phase accumulator circuit system.

9. A system comprising: Carrier generator, including: Sine wave generator circuit system, The sine wave generator circuit system includes a phase accumulator circuit system and a phase-to-amplitude conversion circuit system coupled to the phase accumulator circuit system. The phase accumulator circuit system is configured to receive digital input values ​​and output a set of phase values, and the phase-to-amplitude conversion circuit system is configured to receive the set of phase values ​​and output a set of digital sine values. The pulse width modulation timer circuit system is coupled to the sine wave generator circuit system. The pulse width modulation timer circuit system is configured to receive the set of digital sine values ​​and output at least one pulse width modulation signal; and The amplifier and filter circuitry system coupled to the carrier generator The amplifier and filter circuitry is configured to receive the at least one pulse width modulation signal and output an analog carrier signal, wherein the frequency of the analog carrier signal is at least partially based on the digital input value.

10. The system according to claim 9, wherein, The phase accumulator circuit system and the phase-to-amplitude conversion circuit system include a numerically controlled oscillator circuit system.

11. The system according to claim 9, wherein, The phase-to-amplitude conversion circuit system includes a coordinate rotation digital computer circuit system.

12. The system according to claim 9, wherein, The phase accumulator circuitry is also configured to receive the digital input values ​​from the user of the system via a user interface.

13. The system according to claim 9, wherein, The pulse width modulation timer circuitry is also configured to receive a kernel clock frequency value from a user of the system via a user interface, and wherein the resolution associated with the pulse width modulation timer circuitry is at least partially based on the kernel clock frequency value.

14. The system according to claim 9, wherein, The at least one pulse width modulation signal includes a first pulse width modulation signal and a second pulse width modulation signal that is complementary to the first pulse width modulation signal.

15. The system according to claim 9, wherein, The digital input value is based, in part, on at least one of the following: a frequency associated with the analog carrier signal, a second frequency associated with a frequency-divided clock signal input to the sine wave generator circuit system, or a bit length associated with the phase accumulator circuit system.

16. A method comprising: The digital input value is obtained at the sine wave generator circuit system. The sine wave generator circuit system includes a phase accumulator circuit system and a phase-to-amplitude conversion circuit system coupled to the phase accumulator circuit system. The phase accumulator circuit system is configured to output a set of phase values ​​at least partially based on the digital input values, and the phase-to-amplitude conversion circuit system is configured to receive the set of phase values ​​and output a set of digital sine values. At least one pulse width modulation signal is output from the pulse width modulation timer circuit system coupled to the sine wave generator circuit system. The pulse width modulation timer circuit system is configured to output the at least one pulse width modulation signal based at least in part on the set of digital sine values, and wherein the frequency associated with the at least one pulse width modulation signal is based at least in part on the digital input values.

17. The method according to claim 16, wherein, The phase accumulator circuit system and the phase-to-amplitude conversion circuit system include a numerically controlled oscillator circuit system.

18. The method according to claim 16, wherein, The phase-to-amplitude conversion circuit system includes a coordinate rotation digital computer circuit system.

19. The method of claim 16, further comprising: A kernel clock frequency value is obtained at the pulse width modulation timer circuitry, wherein the resolution associated with the pulse width modulation timer circuitry is at least partially based on the kernel clock frequency value.

20. The method of claim 16, wherein, The at least one pulse width modulation signal includes a first pulse width modulation signal and a second pulse width modulation signal that is complementary to the first pulse width modulation signal.

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