Pseudo-differential three-stage ring oscillator and phase-locked loop system

Abstract

The invention belongs to the field of analog integrated circuit design, and particularly relates to a pseudo-differential three-stage ring oscillator and a phase-locked loop system.The pseudo-differential three-stage ring oscillator comprises a pseudo-differential RVCO unit and an output shaping unit, and the pseudo-differential RVCO unit is composed of three stages of delay units; wherein the pseudo-differential RVCO unit is used for realizing self-oscillation through a feedback technology and generating two paths of sine wave signals Vout1 and Vout2; the output shaping unit is used for converting the two paths of sine wave signals into one path of square wave signals and outputting the square wave signals; the pseudo-differential three-stage ring oscillator designed by the invention has the advantages of being simple in circuit structure, low in implementation difficulty and suitable for most processes.

Description

TECHNICAL FIELD

[0001] The application belongs to the field of analog integrated circuit design, and particularly relates to a pseudo-differential three-stage ring oscillator and a phase-locked loop system. BACKGROUND

[0002] A phase-locked loop (PLL) is a closed-loop control circuit widely used in electronic systems, and its core function is to keep the frequency and phase of the system output signal synchronized with the input reference signal through a feedback mechanism. It plays a key role in communication, navigation, measurement, broadcasting, television, digital circuit and other fields.

[0003] A voltage-controlled oscillator (VCO) is a core module in a phase-locked loop system, and its performance directly affects the accuracy and stability of the phase-locked loop system. Voltage-controlled oscillators include LC-VCO and ring VCO (RingVCO). LC-VCO has very low phase noise and has become the mainstream application technology in radio frequency wireless communication systems, but LC-VCO needs to use inductive elements. In the current integrated circuit manufacturing, it is difficult to make inductive elements compatible with standard CMOS manufacturing process, and the chip occupies a large area and has high manufacturing cost. Moreover, the tuning range of LC-VCO is relatively small. Ring VCO can be implemented by CMOS process, has a small size, and also has a wide tuning range and a simpler circuit structure, making it easier to integrate into integrated systems such as phase-locked loop circuits. Therefore, it is widely used in clock generation circuits and data / clock recovery circuits. However, ring VCO has high phase noise, low power efficiency and poor frequency stability. SUMMARY

[0004] To solve the above problems, the application provides a pseudo-differential three-stage ring oscillator and a phase-locked loop system.

[0005] In a first aspect, the application provides a pseudo-differential three-stage ring oscillator, which comprises a pseudo-differential RVCO unit and an output shaping unit, and the pseudo-differential RVCO unit is composed of three-stage delay units; wherein:

[0006] The pseudo-differential RVCO unit is used to generate two sinusoidal signals Vout1 and Vout2 through feedback technology to realize self-oscillation;

[0007] The output shaping unit is used to convert the two sinusoidal signals into a square wave signal output.

[0008] In a second aspect, the application provides a phase-locked loop system using the pseudo-differential three-stage ring oscillator of the first aspect.

[0009] The beneficial effects of the present application are as follows:

[0010] The pseudo-differential three-stage ring oscillator designed in the present application has the advantages of simple circuit structure, low implementation difficulty and suitability for most processes. The output shaping unit can realize full-swing rail-to-rail output, improve driving capability and reduce noise. At the same time, the oscillator designed in the present application has fast lock-in time, wide tuning range and good phase noise. BRIEF DESCRIPTION OF DRAWINGS

[0011] Figure 1 is a conventional pseudo-differential delay unit;

[0012] Figure 2 is a pseudo-differential RVCO unit shown in some embodiments of the present application;

[0013] Figure 3 is a delay unit shown in some embodiments of the present application;

[0014] Figure 4 is an output shaping unit shown in some embodiments of the present application;

[0015] Figure 5 is a phase-locked loop system shown in some embodiments of the present application;

[0016] Figure 6 is a start-up diagram of a pseudo-differential RVCO unit shown in some embodiments of the present application;

[0017] Figure 7 is a frequency tuning gain curve of a pseudo-differential RVCO unit shown in some embodiments of the present application;

[0018] Figure 8 is a waveform diagram of output of an output shaping unit shown in some embodiments of the present application;

[0019] Figure 9 is a phase noise curve of a pseudo-differential RVCO unit shown in some embodiments of the present application;

[0020] Figure 10 is a lock-in diagram of a PLL system shown in some embodiments of the present application. DETAILED DESCRIPTION

[0021] The technical solutions in the embodiments of the present application will be described clearly and completely below with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are only some of the embodiments of the present application, but not all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art without creative work fall within the protection scope of the present application.

[0022] Figure 2is a pseudo-differential RVCO unit shown according to some embodiments of the present application. Figure 3 is a delay unit shown according to some embodiments of the present application. Figure 4 is an output shaping unit shown according to some embodiments of the present application.

[0023] A ring VCO is a high-frequency oscillation circuit based on a ring inverter structure, which adjusts the oscillation frequency through an input control voltage, and is widely used in phase-locked loops (PLLs), frequency synthesizers, clock generation, and other integrated circuits. Among them, the single-ended ring VCO structure is simple, but has weak common-mode noise suppression ability and poor phase noise performance in the power supply, substrate and other application environments. The fully differential ring VCO has good common-mode noise suppression ability and can improve the phase noise to some extent, but the structure is complex and often needs additional bias circuit design, and the power consumption also increases accordingly. The pseudo-differential ring VCO is a voltage-controlled oscillator that combines the advantages of single-ended and fully differential topologies. It has a certain ability to suppress common-mode noise, and its delay circuit structure is simpler than that of the fully differential one and can work at full swing.

[0024] The pseudo-differential delay unit is a core component of the pseudo-differential ring VCO, as shown in Figure 1 The pseudo-differential delay unit is composed of a delay inverter and a latch inverter. The delay inverter determines the charging and discharging current of the pseudo-differential delay unit, and the latch inverter maintains the phase difference between the outputs of the two delay inverters at 180°.

[0025] Theoretically, the pseudo-differential delay unit structure of the second order can oscillate, but the oscillator gain brought by it is large, and the phase noise is high, which is not conducive to design requirements.

[0026] In order to optimize the phase noise and have a wide tuning range while achieving fast locking, the present application provides a pseudo-differential three-stage ring oscillator that satisfies the Barkhausen theorem, which includes a pseudo-differential RVCO unit and an output shaping unit, the pseudo-differential RVCO unit is composed of three delay units; wherein:

[0027] The pseudo-differential RVCO unit is used to generate two sinusoidal signals Vout1 and Vout2 through feedback technology to realize self-oscillation;

[0028] The output shaping unit is used to convert the two sinusoidal signals into a square wave signal output.

[0029] In some embodiments, the pseudo-differential RVCO unit is composed of three series of delay units, wherein the output of the first delay unit is connected to the input of the second delay unit; the output of the second delay unit is connected to the input of the third delay unit; the output of the third delay unit is connected to the input of the fourth delay unit; the output of the fourth delay unit is connected to the input of the first delay unit.

[0030] Each delay unit includes two inputs and two outputs.

[0031] In some embodiments, as shown in FIG. 1, the delay unit includes a main delay inverter N1-N2, one latch inverter composed of inverting units N3-N4, capacitors C1-C4, and switches S1-S2, wherein: Figure 2

[0032] The output of the main delay inverter N1 is connected to one end of the capacitor C1, one end of the switch S1, the input of the inverting unit N3, and the output of the inverting unit N4; the other end of the capacitor C1 is grounded; the other end of the switch S1 is connected to one end of the capacitor C3, and the other end of the capacitor C3 is grounded.

[0033] The output of the main delay inverter N2 is connected to one end of the capacitor C2, one end of the switch S2, the output of the inverting unit N3, and the input of the inverting unit N4; the other end of the capacitor C2 is grounded; the other end of the switch S2 is connected to one end of the capacitor C4, and the other end of the capacitor C4 is grounded.

[0034] The input of the main delay inverter N1 and the input of the main delay inverter N2 serve as the two inputs of the delay unit; the output of the inverting unit N3 and the output of the inverting unit N4 serve as the outputs of the delay unit.

[0035] In some embodiments, as shown in FIG. 2, the main delay inverter N1 includes transistors M3-M4, the main delay inverter N2 includes transistors M5-M6, the inverting unit N3 includes transistors M7-M8, and the inverting unit N4 includes transistors M9-M10; wherein: Figure 3 The gate of the transistor M3 is connected to the gate of the transistor M4, and the connection point serves as the input of the main delay inverter N1; the drain of the transistor M3 is connected to the drain of the transistor M4, and the connection point serves as the output of the main delay inverter N1; the source of the transistor M3 is grounded, and the source of the transistor M4 is connected to a current source.

[0036]

[0037] ​​The gate of the transistor M5 is connected with the gate of the transistor M6, and the connecting point is as the input end of the main delay inverter N2; the drain of the transistor M5 is connected with the drain of the transistor M6, and the connecting point is as the output end of the main delay inverter N2; the source of the transistor M5 is grounded, and the source of the transistor M6 is connected with the current source;

[0038] The gate of the transistor M7 is connected with the gate of the transistor M8, and the connecting point is as the input end of the inverting unit N3; the drain of the transistor M7 is connected with the drain of the transistor M8, and the connecting point is as the output end of the inverting unit N3; the source of the transistor M7 is grounded, and the source of the transistor M8 is connected with the current source;

[0039] The gate of the transistor M9 is connected with the gate of the transistor M10, and the connecting point is as the input end of the inverting unit N4; the drain of the transistor M9 is connected with the drain of the transistor M10, and the connecting point is as the output end of the inverting unit N4; the source of the transistor M9 is grounded, and the source of the transistor M10 is connected with the current source.

[0040] As shown in Figure 3 The current source comprises the transistors M1-M2, and wherein:

[0041] The source of the transistor M1 is connected with the power supply voltage VDD, the gate of the transistor M1 is connected with an external charge pump, the drain of the transistor M1 is connected with the source of the transistor M2, and the connecting point is connected with the external charge pump; the gate of the transistor M2 is connected with a bias voltage Vb, and the drain of the transistor M2 is connected with the sources of the transistors M4, M6, M8 and M10 in the delay unit.

[0042] For example, the transistors M3, M5, M7 and M9 are all NMOS tubes, and the transistors M1, M2, M4, M6, M8 and M10 are all PMOS tubes.

[0043] In the embodiment of the application, the current source composed of the transistors M1-M2 is shared by the three-stage delay unit.

[0044] For example, in order to meet the requirement of the frequency tuning range, all the transistors (M3-M10) in the pseudo-differential RVCO unit adopt 1.3V low-voltage devices to reduce the parasitic capacitance. The power supply voltage of the transistor M1 is 2.5V, and the voltage at the node Vtop (i.e. at the drain of the transistor M2) is not too high through the adjustment of the transistor M2, so that the voltage at the node Vtop is in a safe range, and the device is prevented from being broken down.

[0045] The load capacitors C1~C4 are introduced to reduce the difference in current required by the pseudo-differential RVCO unit at its highest and lowest frequencies, allowing transistor M2 to operate in the saturation region across all frequency bands. This also increases the amplitude of the oscillation signal, which helps reduce phase noise. Furthermore, the switch is introduced to make the capacitance of the pseudo-differential RVCO unit controllable, thereby controlling the output frequency and swing, reducing power supply sensitivity, and lowering phase noise.

[0046] In some embodiments, the size design of the main delay inverter and the latch inverter is a key factor in enabling the pseudo-differential RVCO unit to oscillate. When the aspect ratio of the latch inverter is very small relative to the main delay inverter, the driving capability of the latch inverter is weak, and the phase at the diagonal points is no longer opposite. In this case, the pseudo-differential RVCO unit becomes a single-ended structure with high phase noise. Therefore, the latch inverter needs to have sufficient driving capability to maintain the differential characteristics of the pseudo-differential RVCO unit. When the aspect ratio of the latch inverter is large relative to the main delay inverter, the driving capability of the latch inverter is strong. Due to the positive feedback characteristic of the latch inverter, the voltage at the diagonal points is pulled to the power supply and ground, allowing the pseudo-differential RVCO unit to remain in a steady state and no longer oscillate. Therefore, in the design, the driving capability of the main delay inverter is usually slightly larger than that of the latch inverter to ensure that it can oscillate.

[0047] Based on the above analysis, the oscillation frequency of the pseudo-differential RVCO unit is further derived. Assume the total capacitance of the first-stage delay unit is C, which includes the parasitic capacitance of all transistors. ox and load capacitance C L (Load capacitance C) L (Refers to the sum of capacitors C1 to C4); Let W0 and L0 represent the width and length of a transistor in a main delay inverter, respectively, then the following expression exists:

[0048]

[0049] Let the width and length of each transistor in the current source be W1 and L1, respectively. Then the input control current I... osc Represented as:

[0050]

[0051] Where up represents hole mobility, V DD Indicates the power supply voltage, V con V represents the voltage at the connection point Vcon between the drain of transistor M1 and the source of transistor M2 (i.e., the control voltage generated by the charge pump). TP This indicates the threshold voltage of the PMOS transistor.

[0052] The expression for the oscillation frequency f is:

[0053]

[0054] Where n represents the number of delay units, T d V represents the delay time of a delay unit. top This represents the voltage at the connection point between the drain of transistor M2 and the delay cell.

[0055] It can be seen that the frequency of the pseudo-differential RVCO cell is mainly determined by the size of the MOS device in the delay cell, the size of the load capacitance, and the voltage of node Vcon. The voltage of node Vtop is also determined by the voltage of node Vcon.

[0056] During oscillation, the size of the main delay inverter and the load capacitance primarily determine the oscillation frequency of the oscillator, while the size of the latch determines the switching rate of the oscillation waveform's rise and fall.

[0057] For example, considering the flicker noise of MOS devices, the sizes of both the main delay inverter and the latch inverter are increased. However, the increased parasitic capacitance requires the pseudo-differential RVCO cell to have a larger input current to achieve its original oscillation frequency. To ensure loop stability, the transistors in the current source need to be larger, which leads to enhanced clock feedthrough and affects the control voltage Vosc. Therefore, considering the oscillation conditions, tuning range, and phase noise performance of the pseudo-differential RVCO cell, in this embodiment, the MOS devices in the latch inverter all use smaller channel lengths, such as 60nm, while the aspect ratio of the MOS devices in the main delay inverter is designed to be twice that of the latch inverter. Specifically, the aspect ratios of the transistors can be expressed as M1=M2=M4=M6=1.5M3=1.5M5=2M8=2M10=3M7=3M9.

[0058] Figure 2 The output signal of the pseudo-differential RVCO unit described in the paper is approximately a sine wave. In order to meet the requirement that the output is a square wave signal, the output signals Vout1 and Vout2 need to be processed by a shaping circuit.

[0059] In some embodiments, such as Figure 4 As shown, the output shaping unit includes inverters N5~N8, capacitors C5~C6, and resistors R1~R2, wherein:

[0060] One end of capacitor C5 is connected to the sine wave signal Vout1, and the other end of capacitor C5 is connected to the input terminal of inverter N5; the two ends of resistor R1 are connected to the input terminal and the output terminal of inverter N5, respectively.

[0061] One end of capacitor C6 is connected to the sine wave signal Vout2, and the other end of capacitor C6 is connected to the input terminal of inverter N6; the two ends of resistor R2 are connected to the input terminal and the output terminal of inverter N6, respectively.

[0062] The input end of the inverter N7 is connected with the output end of the inverter N5, and the output end of the inverter N7 is connected with the output end of the inverter N6; the input end of the inverter N8 is connected with the output end of the inverter N6, and the output end of the inverter N8 is connected with the output end of the inverter N5;

[0063] A signal V1 is led out from the output end of the inverter N5, and a signal V2 is led out from the output end of the inverter N6.

[0064] The principle of the output shaping unit is a comparator, which realizes the conversion from a sine wave to a square wave by comparing the amplitude of two sine wave signals.

[0065] The output shaping unit provided in the embodiment of the application isolates a direct current signal by an alternating coupling capacitor and retains an alternating current signal, and by connecting a feedback large resistor (R1, R2) between the input and output of the first stage inverter (N5, N6), the common mode voltage of the input signal can be adjusted to VDD / 2, so that the output duty cycle is very close to 50%. However, at this time, the rising time and the falling time are still relatively long, which will lead to more power noise introduced into the signal, causing the noise and jitter of the signal to increase, and affecting the performance of the chip. Therefore, the latch inverter structure is added in the subsequent stage to make the rising edge and the falling edge of the signal more steep, so as to improve the driving ability and reduce the power noise.

[0066] In some embodiments, the working of the output shaping unit includes:

[0067] When the amplitude of the sine wave signal Vout1 is higher than the amplitude of the sine wave signal Vout2, the signal V1 outputs a low level, and the signal V2 outputs a high level;

[0068] When the amplitude of the sine wave signal Vout1 is not higher than the amplitude of the sine wave signal Vout2, the signal V1 outputs a high level, and the signal V2 outputs a low level.

[0069] The application further provides a phase-locked loop system, as shown in the figure, which comprises a signal input phase frequency detector (PFD), a charge pump (CP), a loop filter (LPF), a frequency divider (DIV), a bandgap reference source (Bangap) for providing a bias voltage, and the pseudo-differential three-stage ring oscillator provided in the application. Figure 5

[0070] ​The input reference clock signal and feedback clock signal are input to the PFD. The PFD detects the phase difference between the input reference clock signal and the feedback clock signal and outputs a pulse signal containing the phase difference information. This pulse signal controls whether the CP switch is on or off. The CP output is a current pulse signal. This current pulse signal is filtered for noise by a loop filter and then converted into a voltage signal for output. This voltage signal serves as the input control signal for the pseudo-differential three-stage ring oscillator, adjusting the oscillation frequency f generated by the pseudo-differential three-stage ring oscillator. vco Typically, the VCO's output signal has a high frequency, so it needs to be divided by a frequency divider before being compared with the input reference clock signal. After this repeated cycle, the PLL is finally locked.

[0071] In some embodiments, simulation experiments are performed on the structure proposed in this invention.

[0072] Figure 6 The diagram shows the start-up of the pseudo-differential RVCO unit of this invention. It can be seen that the pseudo-differential RVCO unit functions normally and completes the start-up within 45ns.

[0073] Figure 7 The frequency tuning gain curve of the pseudo-differential RVCO unit is shown. When the control voltage Vctrl varies from 0.7 V to 1.5 V, the oscillation frequency of the pseudo-differential RVCO unit changes from 0.5 GHz to 9 GHz. The frequency tuning gain K of the pseudo-differential RVCO unit is calculated. VCO =11.25 GHz / V, and the frequency change linearity of the pseudo-differential RVCO unit is high throughout the entire control voltage variation range. When the control voltage Vctrl is 1V, the oscillation waveform of the pseudo-differential RVCO unit is a differential two-way sine wave with an oscillation swing of approximately 570 mV. After passing through the output shaping unit, the differential sine wave is converted into a single-ended square wave signal. The waveform output by the output shaping unit is as follows. Figure 8 As shown, the square wave signal is a full-swing signal with a low level of 0 V and a high level of 1.3 V, which meets the conditions for driving the next stage DIV circuit.

[0074] Figure 9 The figure shows the phase noise curve of the pseudo-differential RVCO unit. It can be seen that under PVT conditions, the phase noise of the VCO at a frequency offset of 1 MHz is about -96.2dBc / Hz, which has good noise performance.

[0075] Figure 10 The diagram shows the locking mechanism of the PLL system, which completes locking within 1µs.

[0076] In the present application, unless otherwise explicitly specified and limited, the terms "mounting", "arrangement", "connection", "fixing", "rotation" and other terms should be understood in a broad sense, for example, can be fixed connection, can also be detachable connection, or integrated; can be mechanical connection, can also be electrical connection; can be directly connected, can also be indirectly connected through an intermediate medium, can be the internal communication of two elements or the interaction relationship of two elements, unless otherwise explicitly limited, the above-mentioned terms in the present application can be understood according to the specific meaning of the above-mentioned terms in the present application by those skilled in the art.

[0077] Although the embodiments of the present application have been shown and described, those skilled in the art can understand that various changes, modifications, replacements and variations can be made to the embodiments without departing from the principles and spirits of the present application, and the scope of the present application is defined by the appended claims and their equivalents.

Claims

1. A pseudo-differential three-stage ring oscillator, characterized by, The pseudo differential RVCO unit and the output shaping unit are included, wherein: The pseudo differential RVCO unit is used to generate two-way sinusoidal wave signals Vout1 and Vout2 by realizing self-excitation oscillation through feedback technology; The output shaping unit is used to convert the two-way sinusoidal wave signals into one-way square wave signal output; The pseudo differential RVCO unit is composed of three-stage delay units, one-stage delay unit includes main delay inverter N1-N2, one latch inverter, capacitors C1-C4, switches S1-S2, the latch inverter is composed of inverting units N3-N4, wherein: The output end of the main delay inverter N1 is connected with one end of the capacitor C1, one end of the switch S1, the input end of the inverting unit N3, and the output end of the inverting unit N4; the other end of the capacitor C1 is grounded; the other end of the switch S1 is connected with one end of the capacitor C3, and the other end of the capacitor C3 is grounded; The output end of the main delay inverter N2 is connected with one end of the capacitor C2, one end of the switch S2, the output end of the inverting unit N3, and the input end of the inverting unit N4; the other end of the capacitor C2 is grounded; the other end of the switch S2 is connected with one end of the capacitor C4, and the other end of the capacitor C4 is grounded; The input end of the main delay inverter N1 and the input end of the main delay inverter N2 serve as the input end of the delay unit; the output end of the inverting unit N3 and the output end of the inverting unit N4 serve as the output end of the delay unit.

2. A pseudo-differential three-stage ring oscillator as claimed in claim 1, characterized in that, The pseudo differential RVCO unit is composed of three-stage delay units connected in series, wherein the output end of the first-stage delay unit is connected with the input end of the second-stage delay unit; the output end of the second-stage delay unit is connected with the input end of the third-stage delay unit; the output end of the third-stage delay unit is connected with the input end of the fourth-stage delay unit; the output end of the fourth-stage delay unit is connected with the input end of the first-stage delay unit.

3. A pseudo-differential three-stage ring oscillator as claimed in claim 1, characterized in that, The main delay inverter N1 includes transistors M3-M4, the main delay inverter N2 includes transistors M5-M6, the inverting unit N3 includes transistors M7-M8, and the inverting unit N4 includes transistors M9-M10; wherein: The gate of the transistor M3 is connected with the gate of the transistor M4, and the connection point serves as the input end of the main delay inverter N1; the drain of the transistor M3 is connected with the drain of the transistor M4, and the connection point serves as the output end of the main delay inverter N1; the source of the transistor M3 is grounded, and the source of the transistor M4 is connected with a current source; The gate of the transistor M5 is connected with the gate of the transistor M6, and the connection point serves as the input end of the main delay inverter N2; the drain of the transistor M5 is connected with the drain of the transistor M6, and the connection point serves as the output end of the main delay inverter N2; the source of the transistor M5 is grounded, and the source of the transistor M6 is connected with a current source; The gate of the transistor M7 is connected with the gate of the transistor M8, and the connection point serves as the input end of the inverting unit N3; the drain of the transistor M7 is connected with the drain of the transistor M8, and the connection point serves as the output end of the inverting unit N3; the source of the transistor M7 is grounded, and the source of the transistor M8 is connected with a current source; The gate of the transistor M9 is connected with the gate of the transistor M10, and the connecting point is the input terminal of the inverting unit N4; the drain of the transistor M9 is connected with the drain of the transistor M10, and the connecting point is the output terminal of the inverting unit N4; the source of the transistor M9 is grounded, and the source of the transistor M10 is connected with the current source.

4. A pseudo-differential three-stage ring oscillator as claimed in claim 3, characterized in that The current source comprises transistors M1-M2, wherein: The source of the transistor M1 is connected with a power supply voltage, the gate of the transistor M1 is connected with an external charge pump, the drain of the transistor M1 is connected with the source of the transistor M2, and the connecting point is connected with the external charge pump; the gate of the transistor M2 is connected with a bias voltage Vb, and the drain of the transistor M2 is connected with the delay unit.

5. A pseudo-differential three-stage ring oscillator as claimed in claim 1, characterized in that, The output shaping unit comprises inverters N5-N8, capacitors C5-C6, and resistors R1-R2, wherein: One end of the capacitor C5 is connected with a sine wave signal Vout1, and the other end of the capacitor C5 is connected with the input terminal of the inverter N5; the two ends of the resistor R1 are respectively connected with the input terminal and the output terminal of the inverter N5; One end of the capacitor C6 is connected with a sine wave signal Vout2, and the other end of the capacitor C6 is connected with the input terminal of the inverter N6; the two ends of the resistor R2 are respectively connected with the input terminal and the output terminal of the inverter N6; The input terminal of the inverter N7 is connected with the output terminal of the inverter N5, and the output terminal of the inverter N7 is connected with the output terminal of the inverter N6; the input terminal of the inverter N8 is connected with the output terminal of the inverter N6, and the output terminal of the inverter N8 is connected with the output terminal of the inverter N5; one signal V1 is led out from the output terminal of the inverter N5, and one signal V2 is led out from the output terminal of the inverter N6.

6. A pseudo-differential three-stage ring oscillator as claimed in claim 1, characterized in that The output shaping unit realizes the conversion from the sine wave to the square wave by comparing the amplitude values of the two sine wave signals, comprising: When the amplitude value of the sine wave signal Vout1 is higher than the amplitude value of the sine wave signal Vout2, the signal V1 is output as a low level, and the signal V2 is output as a high level; When the amplitude value of the sine wave signal Vout1 is not higher than the amplitude value of the sine wave signal Vout2, the signal V1 is output as a high level, and the signal V2 is output as a low level.

7. A phase-locked loop system, characterized by The pseudo-differential three-stage ring oscillator according to any one of claims 1-6.

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