Multi-modulation-system carrier synchronization integrated judging and locking device for satellite-ground data transmission

Abstract

The invention discloses a multi-modulation system carrier synchronization integrated judging and locking device for satellite-to-ground data transmission, and belongs to the field of satellite-to-ground data transmission. The device comprises an AD conversion module, a digital down-conversion module, a low-pass filtering module, a half-band filter bank module, a digital resampling module, a matched filtering module, a carrier phase tracking module, a carrier phase error calculation module, a timing error calculation module and a carrier synchronization judging and locking module. According to the invention, the carrier synchronization integrated locking judgment function of multiple modulation systems in a satellite-ground high-speed data transmission CCM transmission mode and a VCM transmission mode is realized, the adaptability of the device is improved, and the device is convenient to realize and popularize.

Description

Technical Field

[0001] This invention relates to the field of satellite-to-ground data transmission, and in particular to an integrated multi-modulation carrier synchronization detection and locking device for satellite-to-ground data transmission, which can be used for receiving and demodulation applications in the data receiving subsystem of a satellite data ground receiving station. Background Technology

[0002] In current satellite-to-ground data transmission systems, various modulation schemes are widely used to meet different application scenarios and data transmission requirements. Carrier synchronization is a crucial step in the correct reception and demodulation of data, and the process of determining and locking the carrier synchronization status is an important step in verifying that the data transmission signal has correctly achieved carrier synchronization. When carrier synchronization loss is detected, the carrier phase error calculation unit needs to be reset in a timely manner to effectively ensure the carrier synchronization process.

[0003] Traditional carrier-locked devices mainly employ three methods:

[0004] The first method uses a frame synchronization indicator signal to determine carrier synchronization lock. The advantage of this method is that the accuracy of carrier synchronization lock determination is high and it is applicable to all modulation schemes. However, this method requires the use of a frame synchronization indicator signal, and the generation time of the frame synchronization indicator signal is related to the frame length. When the symbol rate of the data transmission signal is low, it takes a long time to complete the carrier synchronization lock determination process. In addition, when the received frame format setting value is inconsistent with the transmitted signal frame format, the frame synchronization indicator signal will always be in a unlocked state. This will cause the carrier synchronization process to be in a cyclic reset state, which will lead to abnormal carrier synchronization.

[0005] The second method involves removing the modulation information of the input signal using a Q-power nonlinear transform and then detecting the residual carrier frequency difference of the current signal using an FFT transform. When the residual frequency difference is small, the carrier synchronization is considered to be locked. The advantage of this method is that only the residual carrier frequency difference is detected during the carrier synchronization locking process, resulting in a shorter detection time and higher detection independence. The disadvantage is that the detection accuracy is lower. To improve the detection accuracy, the amount of data for FFT calculation needs to be increased, which will lead to a longer detection time and an increase in system complexity.

[0006] The third method: This method detects the constellation diagram conformity of the received signal based on the characteristics of the constellation diagram distribution after carrier synchronization, thereby achieving the purpose of carrier synchronization lock determination. The advantage of this method is that the accuracy of carrier synchronization lock determination is high, it is applicable to all modulation schemes, and the lock determination detection is highly independent. However, the disadvantage of this method is that the detection complexity is high, and the signal processing process is different for different modulation schemes. Summary of the Invention

[0007] The purpose of this invention is to overcome the shortcomings of the aforementioned background technology and provide an integrated multi-modulation carrier synchronization and locking device for satellite-to-ground data transmission. This invention features high reliability, high stability, and low implementation complexity.

[0008] The objective of this invention is achieved as follows:

[0009] The multi-modulation carrier synchronization and locking device for satellite-to-ground data transmission includes an AD conversion module 1, a digital down-conversion module 2, a low-pass filter module 3, a half-band filter bank module 4, a digital resampling module 5, a matched filter module 6, a carrier phase tracking module 7, a carrier phase error calculation module 8, a timing error calculation module 9, and a carrier synchronization and locking module 10.

[0010] AD conversion module 1 performs intermediate frequency sampling on the input intermediate frequency analog modulation signal and transmits the intermediate frequency sampled signal to digital downconverter module 2;

[0011] The digital downconversion module 2 performs digital downconversion processing on the input signal to generate two digital baseband signals, I and Q, which are then transmitted to the low-pass filter module 3.

[0012] The low-pass filter module 3 performs low-pass filtering on the input I / Q digital baseband signals and transmits the processed signals to the half-band filter bank module 4.

[0013] The half-band filter bank module 4 performs half-band filtering and downsampling on the input signal and transmits the processed signal to the digital resampling module 5.

[0014] The digital resampling module 5 resamples the input signal to generate two digital baseband signals, I and Q, which are sampled twice, and then transmits them to the matched filter module 6.

[0015] The matched filtering module 6 performs a double-sampled matched filtering process on the input signal and outputs the filtered signal to the carrier phase tracking module 7.

[0016] The carrier phase tracking module 7 receives the signal output by the matched filter module 6, performs carrier phase error compensation on the signal, and generates the final demodulated signal. After being split, it generates three sets of demodulated signals, which are transmitted to the carrier phase error calculation module 8, the timing error calculation module 9, and the carrier synchronization lock detection module 10, respectively.

[0017] The carrier phase error calculation module 8 calculates the carrier phase error of the input demodulated signal and transmits the calculated carrier phase error to the carrier phase tracking module 7.

[0018] The timing error calculation module 9 calculates the timing error of the input demodulated signal and transmits the calculated timing error to the digital resampling module 5.

[0019] The carrier synchronization lock determination module 10 processes the demodulated signal according to the externally input modulation scheme control signal to generate a carrier lock indication signal. The carrier lock indication signal is then split into two carrier lock indication signals. The first carrier lock indication signal is transmitted to the carrier phase error calculation module 8 to control the carrier phase error calculation module 8 to automatically reset in the carrier false lock state. The second carrier lock indication signal is the output of this device to realize the lock determination.

[0020] Furthermore, the carrier synchronization locking module 10 includes a first Q-power operation module 11-1, a second Q-power operation module 11-2, an FFT module 12, a first data modulus calculation module 13-1, a second data modulus calculation module 13-2, a maximum value extraction and decision module 14, a first accumulation and decision module 15-1, a second accumulation and decision module 15-2, a third accumulation and decision module 15-3, a fourth accumulation and decision module 15-4, a phase rotation module 16, a data mapping module 17, a numerical comparison module 18, a weighted locking module 19, an SOF frame header extraction module 20, and an IQ modulus detection module 21.

[0021] The carrier synchronization locking module 10 internally splits the demodulated signal transmitted by the carrier phase tracking module 7 to generate four demodulated signals. The first demodulated signal is transmitted to the first Q-power operation module 11-1, the second demodulated signal is transmitted to the second Q-power operation module 11-2, the third demodulated signal is transmitted to the second data modulus calculation module 13-2, and the fourth demodulated signal is transmitted to the SOF frame header extraction module 20.

[0022] The first Q-power operation module 11-1 performs Q-power operations on the input I / Q digital baseband signals according to the modulation scheme control signal. Specifically, it performs a quadratic operation on the BPSK signal, a quadratic operation on the QPSK signal, an octagonal operation on the 8PSK signal, a twelfth-power operation on the 16APSK signal, a quadratic operation on the 16QAM signal, a sixteenth-power operation on the 32APSK signal, an octagonal operation on the 32QAM signal, a twenty-eighth-power operation on the 64APSK signal, and a quadratic operation on the 64QAM signal. The signal after the Q-power operation is completed is transmitted to the FFT module 12.

[0023] The FFT module 12 groups the input signal, performs FFT transformation on each group of signals, and then outputs the FFT transformed signal of each group.

[0024] The first data modulus calculation module 13-1 receives each set of signals output by the FFT module 12 in sequence, performs modulus calculation on each set of input signals, and then transmits the signal after modulus calculation to the maximum value extraction and decision module 14.

[0025] The maximum value extraction and decision module 14 counts the input modulus signals in a loop, compares the values ​​in each group of signals, and makes a decision on the count value corresponding to the maximum value of each group of modulus signals. When the count value is 1, the output signal value is 1; otherwise, the output signal value is 0.

[0026] The first accumulation and decision module 15-1 receives the decision signal output by the maximum value extraction and decision module 14, and performs accumulation processing on the input signal according to the set accumulation period, and transmits the accumulation result to the weighted decision module 19.

[0027] The second Q-power operation module 11-2 performs Q-power operations on the input I / Q digital baseband signals according to the modulation scheme control signal. Specifically, no operations are performed on BPSK, QPSK, 16QAM, and 64QAM signals. The 8PSK signal is subjected to a quadratic operation, the 16APSK signal is subjected to a tertiary operation, the 32APSK signal is subjected to a quadratic operation, the 32QAM signal is subjected to a quadratic operation, and the 64APSK signal is subjected to a septum operation. The signal after the Q-power operation is completed is transmitted to the phase rotation module 16.

[0028] The phase rotation module 16 performs phase rotation on the input signal according to the modulation scheme control signal. Specifically, no phase rotation is performed on BPSK and 32APSK, while QPSK, 8PSK, 16QAM, 16APSK, 32QAM, 64QAM and 64APSK are rotated by 90 degrees. The phase-rotated signal is then transmitted to the data mapping module 17.

[0029] The data mapping module 17 takes the absolute value of the received I and Q signals respectively, remaps the signal with the larger absolute value to I data, and remaps the signal with the smaller absolute value to Q data, and outputs the mapped data.

[0030] The numerical comparison module 18 receives the I / Q signals output by the data mapping module 17. First, it calculates the magnitude of the input signal. When the magnitude is greater than a preset threshold, it calculates the ratio of the absolute values ​​of the I data and the Q data. When the ratio is greater than 4, the output signal value is 1; otherwise, the output signal value is 0. When the magnitude is less than the preset threshold, there is no output.

[0031] The second accumulation and decision module 15-2 receives the decision signal output by the numerical comparison module 18, accumulates the input signal according to the set accumulation period, and transmits the accumulation result to the weighted decision module 19.

[0032] The second data modulus calculation module 13-2 calculates the modulus of the input signal, and then compares the calculated modulus with a preset threshold value. When the modulus is greater than the threshold, the output signal value is 1; otherwise, the output signal value is 0.

[0033] The third accumulation and decision module 15-3 receives the decision signal output by the second data modulus calculation module 13-2, performs accumulation processing on the input signal according to the set accumulation period, and transmits the accumulation result to the weighted decision module 19.

[0034] SOF frame header extraction module 20 uses the frame header synchronization sequence to complete frame header detection, thereby generating a frame synchronization indication signal, and extracts the frame header IQ signal from the received fourth demodulated signal according to the frame synchronization indication signal, and transmits it to the IQ modulus detection module 21.

[0035] The IQ modulus detection module 21 calculates the modulus values ​​of the input frame header I-channel signal and frame header Q-channel signal respectively. Then, it sums and differs the two modulus values ​​respectively. The difference result is further used to calculate the modulus value. Finally, the summed signal and the differenced and modulo-calculated signal are divided. The division result is transmitted to the fourth accumulation and decision module 15-4.

[0036] The fourth accumulation and decision module 15-4 receives the decision signal output by the IQ modulus detection module 21, accumulates the input signal according to the set accumulation period, and transmits the accumulation result to the weighted decision module 19.

[0037] The weighted locking module 19 receives the accumulation results output by the first accumulation and decision module 15-1, the second accumulation and decision module 15-2, the third accumulation and decision module 15-3, and the fourth accumulation and decision module 15-4, respectively. Based on the preset weighting value, it performs a weighted summation on the received four accumulation results. Then, it compares the summation result with a preset threshold. When the summation result is greater than the threshold, the value of the output carrier lock indication signal is 1, and the carrier synchronization is in a locked state. When the summation result is less than the threshold, the value of the output carrier lock indication signal is 0, and the carrier synchronization is in a unlocked state.

[0038] Compared with the prior art, the present invention has the following advantages:

[0039] 1. Compared with traditional carrier synchronization detection and locking devices, this invention realizes the integrated carrier synchronization detection and locking function for various modulation schemes such as BPSK, QPSK, 8PSK, 16APSK, 16QAM, 32APSK, 32QAM, 64APSK and 64QAM and VCM transmission modes in high-speed satellite-to-ground data transmission (CCM) mode, thereby improving the adaptability of the device.

[0040] 2. Compared with traditional carrier synchronization detection and locking devices, the present invention adopts a method that combines time-domain carrier synchronization detection and locking with frequency-domain carrier synchronization detection and locking, which improves the accuracy of carrier synchronization detection and locking results, thereby improving the effectiveness and adaptability of the device.

[0041] 3. Compared to traditional carrier synchronization locking devices, this invention optimizes the signal processing flow during integrated multi-modulation carrier synchronization locking, organically combining the locking processes of different modulation schemes, thus improving the device's integration and stability. Furthermore, because this device employs a fully digital processing flow and requires relatively small hardware logic resources, its implementation complexity is low, making it easy to implement and promote.

[0042] 4. This invention adopts a mid-frequency sampling all-digital signal processing flow, which has a simple structure and strong portability. Since current mainstream FPGAs integrate comparators, RAM, multipliers and adders, this invention can be implemented through embedded software and has promotional application value. Attached Figure Description

[0043] Figure 1 This is a block diagram illustrating the principle of the present invention.

[0044] Figure 2 This is a block diagram illustrating the principle of the carrier synchronization locking module. Detailed Implementation

[0045] A multi-modulation carrier synchronization integrated detection and locking device for satellite-to-ground data transmission, referencing Figure 1 It includes an AD conversion module 1, a digital down-conversion module 2, a low-pass filter module 3, a half-band filter bank module 4, a digital resampling module 5, a matched filter module 6, a carrier phase tracking module 7, a carrier phase error calculation module 8, a timing error calculation module 9, and a carrier synchronization lock-in module 10.

[0046] First, the AD conversion module 1 performs intermediate frequency (IF) sampling on the input IF analog modulation signal. The sampled IF signal is then transmitted to the digital down-conversion module 2. The digital down-conversion module 2 performs digital down-conversion processing on the input signal, generating I / Q dual-channel digital baseband signals. These I / Q dual-channel digital baseband signals are then transmitted to the low-pass filter module 3. The low-pass filter module 3 performs low-pass filtering on the input I / Q dual-channel digital baseband signals and transmits the processed data to the half-band filter bank module 4. The half-band filter bank module 4 performs half-pass filtering on the input I / Q quadrature baseband signals. After band filtering and downsampling, the processed I / Q digital baseband signals are transmitted to the digital resampling module 5. The digital resampling module 5 resamples the input I / Q digital baseband signals, generating double-sampled I / Q digital baseband signals, which are then transmitted to the matched filtering module 6. The matched filtering module 6 performs double-sampled matched filtering on the input signals and outputs the filtered signals. The carrier phase tracking module 7 receives the signal output from the matched filtering module 6 and performs carrier phase error compensation on the received signal to generate the final solution. The demodulated signal output from the carrier phase tracking module 6 is further split into three sets of demodulated signals. The first set of demodulated signals is transmitted to the carrier phase error calculation module 8, which calculates the carrier phase error of the input demodulated signal and transmits the calculated carrier phase error to the carrier phase tracking module 7. The second set of demodulated signals is transmitted to the timing error calculation module 9, which calculates the timing error of the input demodulated signal and transmits the calculated timing error to the digital resampling module 5. The third set of demodulated signals is transmitted to the carrier synchronization lock detection module 10, which processes the input demodulated signal according to the input modulation scheme control signal and generates a carrier lock indication signal. The carrier lock indication signal output from the carrier synchronization lock detection module 10 is further split into two carrier lock indication signals. The first carrier lock indication signal is transmitted to the carrier phase error calculation module 8 to control the carrier phase error calculation module 8 to automatically reset in the carrier false lock state. The second set of carrier lock indication signals is output by this device and transmitted to the subsequent processing module.

[0047] This device achieves the goal of integrated carrier synchronization and locking across multiple modulation schemes through the above methods.

[0048] In this embodiment, the digital downconversion module 2, low-pass filter module 3, half-band filter bank module 4, digital resampling module 5, matched filter module 6, carrier phase tracking module 7, carrier phase error calculation module 8, timing error calculation module 9, and carrier synchronization lock detection module 10 are all implemented using FPGA.

[0049] Figure 2This is a block diagram illustrating the principle of the carrier synchronization locking module. The implementation example follows... Figure 2The connection line. The carrier synchronization locking module 10 comprises a first Q-power operation module 11-1 and a second Q-power operation module 11-2, an FFT module 12, a first data modulus calculation module 13-1 and a second data modulus calculation module 13-2, a maximum value extraction and decision module 14, a first accumulation and decision module 15-1 to a fourth accumulation and decision module 15-4, a phase rotation module 16, a data mapping module 17, a numerical comparison module 18, a weighted locking module 19, an SOF frame header extraction module 20, and an IQ modulus detection module 21. The demodulated signal transmitted by the carrier phase tracking module 7 is internally split to generate four demodulated signals. The first demodulated signal is transmitted to the first Q-power operation module 11-1. The first Q-power operation module 11-1 performs Q-power operations on the input I / Q digital baseband signals according to the modulation scheme control signal. Specifically, the BPSK signal is subjected to a power operation, the QPSK signal to a power operation, the 8PSK signal to a power operation, the 16APSK signal to a power operation, the 16QAM signal to a power operation, and the 32APSK signal to a power operation. The 32QAM signal undergoes an 8th power operation, the 64APSK signal undergoes a 28th power operation, and the 64QAM signal undergoes a 4th power operation. The resulting Q-power operation signal is transmitted to the FFT module 12. The FFT module 12 groups the input signal and performs an FFT transform on each group, then outputs the transformed signal. The first data modulus calculation module 13-1 sequentially receives the signals output by the FFT module 12, calculates the modulus value for each input group, and then transmits the calculated modulus value signal to the maximum value extraction and decision module 14. The AND-OR decision module 14 sequentially counts the modulo signals of each input group, compares the values ​​within each group, and makes a decision on the count value corresponding to the maximum value of each group's modulo signals. When the count value is 1, the output signal value is 1; otherwise, the output signal value is 0. The first accumulation AND-OR decision module 15-1 receives the decision signal output by the maximum value extraction AND-OR decision module 14, accumulates the input signals according to the set accumulation period, and transmits the accumulation result to the weighted locking module 19. The second demodulated signal is transmitted to the second Q-power operation module 11-2. 11-2 According to the modulation scheme control signal, the input I / Q dual-channel digital baseband signals are subjected to Q-power operations. BPSK, QPSK, 16QAM, and 64QAM signals are not processed; 8PSK signals are processed to the power of 2; 16APSK signals to the power of 3; 32APSK signals to the power of 4; 32QAM signals to the power of 2; and 64APSK signals to the power of 7. The signal after the Q-power operation is completed is transmitted to the phase rotation module 16. The phase rotation module 16 performs phase rotation on the input signal according to the modulation scheme control signal.BPSK and 32APSK do not undergo phase rotation, while QPSK, 8PSK, 16QAM, 16APSK, 32QAM, 64QAM, and 64APSK undergo 90-degree phase rotation. The phase-rotated signals are transmitted to data mapping module 17. Data mapping module 17 takes the absolute values ​​of the received I and Q digital baseband signals, remaps the signal with the larger absolute value to I-channel data, and remaps the signal with the smaller absolute value to Q-channel data, then outputs the mapped data. Value comparison module 18 receives the I and Q digital baseband signals output from data mapping module 17, first calculates the magnitude of the input signal, and when the magnitude exceeds a preset threshold, calculates the ratio of the absolute values ​​of the I-channel data to the absolute values ​​of the Q-channel data. When the ratio is greater than 4, the output signal value is 1; otherwise, the output signal value is 0. When the modulus is less than the set threshold, there is no output. The second accumulation and decision module 15-2 receives the decision signal output by the numerical comparison module 18, accumulates the input signal according to the set accumulation period, and transmits the accumulation result to the weighted locking module 19. The third demodulated signal is transmitted to the second data modulus calculation module 13-2. The second data modulus calculation module 13-2 calculates the modulus of the input signal and then compares the modulus calculation result with the preset threshold value. When the modulus is greater than the threshold, the output signal value is 1; otherwise, the output signal value is 0. The third accumulation and decision module 15-3 receives the decision signal from the second data modulus calculation module 13-2. The output decision signal is processed by accumulating the input signal according to the set accumulation period, and the accumulation result is transmitted to the weighted locking module 19. The fourth demodulated signal is transmitted to the SOF frame header extraction module 20. The SOF frame header extraction module 20 uses the frame header synchronization sequence to complete the frame header detection, and then generates a frame synchronization indication signal. Based on the frame synchronization indication signal, it extracts the frame header IQ signal from the received fourth demodulated signal and transmits the extracted frame header IQ signal to the IQ modulus detection module 21. The IQ modulus detection module 21 calculates the modulus of the input frame header I signal and frame header Q signal respectively, then sums and subtracts the two modulus values ​​respectively, and further calculates the modulus value of the difference result. Finally, the summed signal and the difference and modulus value calculated signal are processed together. The first accumulation and decision module 15-1 receives the decision signal output by the IQ modulus detection module 21, performs accumulation processing on the input signal according to the set accumulation period, and transmits the accumulation result to the weighted locking module 19. The weighted locking module 19 receives the accumulation results transmitted by the first accumulation and decision modules 15-1 to the fourth accumulation and decision modules 15-4 respectively, and performs weighted summation on the four sets of received accumulation results according to the preset weighting value. Then, it compares the summation result with the preset threshold. When the summation result is greater than the threshold, the value of the output carrier lock indication signal is 1, and the carrier synchronization is locked. When the summation result is less than the threshold, ...The output carrier lock indicator signal has a value of 0, indicating that carrier synchronization is lost.

[0050] This invention achieves integrated carrier synchronization locking for various modulation schemes and VCM transmission modes, including BPSK, QPSK, 8PSK, 16APSK, 16QAM, 32APSK, 32QAM, 64APSK, and 64QAM, in high-speed satellite-to-ground data transmission (CCM) mode, improving the device's adaptability. Compared to traditional carrier synchronization locking devices, this invention combines time-domain and frequency-domain carrier synchronization locking methods, improving the accuracy of carrier synchronization locking and thus enhancing the device's effectiveness and adaptability. Furthermore, compared to traditional carrier synchronization locking devices, this invention optimizes the signal processing flow during multi-modulation carrier synchronization locking, organically integrating the locking processes for different modulation schemes, thus improving the device's integration and stability. In addition, this device employs a fully digital processing flow, requiring less hardware logic resources, resulting in lower implementation complexity and facilitating implementation and widespread adoption.

Claims

1. A multi-modulation carrier synchronization integrated detection and locking device for satellite-to-ground data transmission, characterized in that, It includes an AD conversion module (1), a digital down-conversion module (2), a low-pass filter module (3), a half-band filter bank module (4), a digital resampling module (5), a matched filter module (6), a carrier phase tracking module (7), a carrier phase error calculation module (8), a timing error calculation module (9), and a carrier synchronization lock-in module (10). The AD conversion module (1) performs intermediate frequency sampling on the input intermediate frequency analog modulation signal and transmits the intermediate frequency sampled signal to the digital downconversion module (2). The digital downconversion module (2) performs digital downconversion processing on the input signal to generate two digital baseband signals, I and Q, which are then transmitted to the low-pass filter module (3). The low-pass filter module (3) performs low-pass filtering on the input I / Q digital baseband signals and transmits the processed signals to the half-band filter bank module (4). The half-band filter bank module (4) performs half-band filtering and downsampling on the input signal and transmits the processed signal to the digital resampling module (5). The digital resampling module (5) resamples the input signal to generate two digital baseband signals, I and Q, which are sampled twice, and then transmits them to the matched filter module (6). The matched filtering module (6) performs a double-sampled matched filtering on the input signal and outputs the filtered signal to the carrier phase tracking module (7). The carrier phase tracking module (7) receives the signal output by the matched filter module (6), performs carrier phase error compensation on the signal, generates the final demodulated signal, and generates three sets of demodulated signals through a splitter, which are then transmitted to the carrier phase error calculation module (8), the timing error calculation module (9), and the carrier synchronization lock-in module (10), respectively. The carrier phase error calculation module (8) calculates the carrier phase error of the input demodulated signal and transmits the calculated carrier phase error to the carrier phase tracking module (7). The timing error calculation module (9) performs timing error calculation on the input demodulated signal and transmits the calculated timing error to the digital resampling module (5). The carrier synchronization lock determination module (10) processes the demodulated signal according to the externally input modulation system control signal and generates a carrier lock indication signal. The carrier lock indication signal is then split into two carrier lock indication signals. The first carrier lock indication signal is transmitted to the carrier phase error calculation module (8) to control the carrier phase error calculation module (8) to automatically reset in the carrier false lock state. The second carrier lock indication signal is used as the output of this device to realize the lock determination.

2. The integrated multi-modulation carrier synchronization locking device for satellite-to-ground data transmission according to claim 1, characterized in that, The carrier synchronization locking module (10) includes a first Q-power operation module (11-1), a second Q-power operation module (11-2), an FFT module (12), a first data modulus calculation module (13-1), a second data modulus calculation module (13-2), a maximum value extraction and decision module (14), a first accumulation and decision module (15-1), a second accumulation and decision module (15-2), a third accumulation and decision module (15-3), a fourth accumulation and decision module (15-4), a phase rotation module (16), a data mapping module (17), a numerical comparison module (18), a weighted locking module (19), an SOF frame header extraction module (20), and an IQ modulus detection module (21). The carrier synchronization lock-in module (10) internally splits the demodulated signal transmitted by the carrier phase tracking module (7) to generate four demodulated signals. The first demodulated signal is transmitted to the first Q-power operation module (11-1), the second demodulated signal is transmitted to the second Q-power operation module (11-2), the third demodulated signal is transmitted to the second data modulus calculation module (13-2), and the fourth demodulated signal is transmitted to the SOF frame header extraction module (20). The first Q-power operation module (11-1) performs Q-power operations on the input I / Q digital baseband signals according to the modulation scheme control signal. Specifically, it performs a quadratic operation on the BPSK signal, a quadratic operation on the QPSK signal, an octagonal operation on the 8PSK signal, a twelfth-power operation on the 16APSK signal, a quadratic operation on the 16QAM signal, a sixteenth-power operation on the 32APSK signal, an octagonal operation on the 32QAM signal, a twenty-eighth-power operation on the 64APSK signal, and a quadratic operation on the 64QAM signal. The signal after the Q-power operation is completed is transmitted to the FFT module (12). The FFT module (12) groups the input signal, performs FFT transformation on each group of signals, and then outputs the FFT transformed signal of each group. The first data modulus calculation module (13-1) receives each set of signals output by the FFT module (12) in sequence, performs modulus calculation on each set of input signals, and then transmits the signal after modulus calculation to the maximum value extraction and decision module (14). The maximum value extraction and decision module (14) counts the input modulus signals in a loop, compares the values ​​in each signal group, and makes a decision on the count value corresponding to the maximum value of each modulus signal. When the count value is 1, the output signal value is 1; otherwise, the output signal value is 0. The first accumulation and decision module (15-1) receives the decision signal output by the maximum value extraction and decision module (14), and performs accumulation processing on the input signal according to the set accumulation period, and transmits the accumulation result to the weighted decision module (19). The second Q-power operation module (11-2) performs Q-power operations on the input I / Q digital baseband signals according to the modulation scheme control signal. Specifically, no operations are performed on BPSK, QPSK, 16QAM and 64QAM signals. The 8PSK signal is subjected to a quadratic operation, the 16APSK signal is subjected to a tertiary operation, the 32APSK signal is subjected to a quadratic operation, the 32QAM signal is subjected to a quadratic operation, and the 64APSK signal is subjected to a septum operation. The signal after the Q-power operation is completed is transmitted to the phase rotation module (16). The phase rotation module (16) performs phase rotation on the input signal according to the modulation scheme control signal. Specifically, no phase rotation is performed on BPSK and 32APSK, while QPSK, 8PSK, 16QAM, 16APSK, 32QAM, 64QAM and 64APSK are rotated by 90 degrees. The phase-rotated signal is then transmitted to the data mapping module (17). The data mapping module (17) takes the absolute value of the received I and Q signals respectively, and remaps the signal with the larger absolute value to I data and the signal with the smaller absolute value to Q data, and outputs the mapped data. The numerical comparison module (18) receives the I / Q signals output by the data mapping module (17). First, it calculates the magnitude of the input signal. When the magnitude is greater than the preset threshold, it calculates the ratio of the absolute values ​​of the I data and the Q data. When the ratio is greater than 4, the output signal value is 1; otherwise, the output signal value is 0. When the magnitude is less than the preset threshold, there is no output. The second accumulation and decision module (15-2) receives the decision signal output by the numerical comparison module (18), performs accumulation processing on the input signal according to the set accumulation period, and transmits the accumulation result to the weighted decision module (19). The second data modulus calculation module (13-2) performs modulus calculation on the input signal, and then compares the modulus calculation result with a preset threshold value. When the modulus is greater than the threshold, the output signal value is 1; otherwise, the output signal value is 0. The third accumulation and decision module (15-3) receives the decision signal output by the second data modulus calculation module (13-2), performs accumulation processing on the input signal according to the set accumulation period, and transmits the accumulation result to the weighted decision module (19). The SOF frame header extraction module (20) uses the frame header synchronization sequence to complete the frame header detection, thereby generating a frame synchronization indication signal, and extracts the frame header IQ signal from the received fourth demodulated signal according to the frame synchronization indication signal, and transmits it to the IQ modulus detection module (21). The IQ modulus detection module (21) calculates the modulus values ​​of the input frame header I signal and frame header Q signal respectively, then sums and differs the two modulus values ​​respectively, further calculates the modulus value of the difference result, and finally performs a division operation between the summed signal and the signal with the difference and modulus value, and transmits the division result to the fourth accumulation and decision module (15-4). The fourth accumulation and decision module (15-4) receives the decision signal output by the IQ modulus detection module (21), performs accumulation processing on the input signal according to the set accumulation period, and transmits the accumulation result to the weighted decision module (19). The weighted locking module (19) receives the accumulation results output by the first accumulation and decision module (15-1), the second accumulation and decision module (15-2), the third accumulation and decision module (15-3), and the fourth accumulation and decision module (15-4), respectively. Based on the preset weighting value, it performs a weighted summation on the received four accumulation results. Then, it compares the summation result with a preset threshold. When the summation result is greater than the threshold, the value of the output carrier lock indication signal is 1, and the carrier synchronization is in a locked state. When the summation result is less than the threshold, the value of the output carrier lock indication signal is 0, and the carrier synchronization is in a unlocked state.

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