Real-time digital monitoring data processing method and device for dual-frequency modulation signal

Abstract

The invention relates to the technical field of avionics, in particular to a real-time digital monitoring data processing method and device for a dual-frequency modulation signal. Processing a monitoring composite signal of the instrument landing system received by the front end of the receiver to obtain an attenuation processing analog signal; according to an ADC analog-to-digital conversion circuit, performing digital signal conversion on the attenuation processing analog signal to obtain a digital domain sampling signal; performing two-stage DDC orthogonal digital down-conversion processing on the digital domain sampling signal to obtain a baseband signal, a 90Hz component and a 150Hz component; extracting and sampling the baseband signal, the 90Hz component and the 150Hz component to obtain a direct current component sequence, a 90Hz component sequence and a 150Hz component sequence after synchronous downsampling; according to the direct current component sequence, the 90Hz component sequence and the 150Hz component sequence, a modulation degree difference DDM and a modulation degree sum SDM are obtained, and updating of real-time digital monitoring data of the dual-frequency modulation signals is achieved. And the accuracy of signal acquisition and the reliability of subsequent processing are improved.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of avionics, in particular to a real-time digital monitoring data processing method and device for dual-frequency modulation signals. BACKGROUND

[0002] Instrument landing system is the core navigation facility of aviation navigation. It transmits radio navigation signals of specific frequency bands to the air through the heading beacon and the glide beacon, respectively forming the heading path and the glide path, to provide precise horizontal position guidance and vertical glide guidance for the aircraft, and to ensure that the aircraft can safely and accurately complete the approach and landing operation.

[0003] The instrument landing system adopts a unique dual-frequency modulation technology. Two modulation signals (first preset and second preset) are superimposed on the carrier in a specific relationship to form a modulation waveform with special amplitude variation characteristics. After receiving the spatial composite signal, the aircraft accurately analyzes the modulation depth values of the first preset and the second preset signals, and accordingly calculates the spatial position to determine the aircraft's yaw angle and vertical offset in real time. To ensure the correctness of the air signal, the instrument landing system continuously receives the air monitoring signal returned by the synthesis network, and analyzes the power amplitude, modulation degree value, etc. of the path line, path width, clearance, and near field in real time by the receiver. When the monitoring signal is abnormal (such as path deviation and power drop), the system can quickly identify the fault type and respond according to the severity of the fault (turn off the machine, shut down or degrade the use), to prevent the aircraft from deviating from the path due to receiving incorrect signals and causing safety accidents such as collision and crash. Therefore, the accuracy, real-time performance and stability of the receiver signal processing are crucial. In actual application, the amplitude of the radio frequency signal received by the instrument landing system is affected by the multipath effect, electromagnetic interference, noise interference, signal attenuation, etc., and presents amplitude fluctuation characteristics. The dynamic range of the ADC device requires that the front-end signal amplitude be strictly controlled within the optimal quantization interval; the amplitude difference (modulation degree) of the first preset / second preset modulation signal needs to reach a measurement accuracy of 0.1%. Effective front-end processing and subsequent accurate digital signal processing of the signal are needed to improve the signal quality and accurately extract the modulation information.

[0004] Traditional receivers use attenuator jumper combinations, potentiometers, and other methods to adjust and calibrate the input signal amplitude. However, analog devices are significantly affected by temperature drift, with a typical temperature drift coefficient of ±0.5 dB / ℃. This temperature sensitivity makes it impossible for attenuators to achieve step-by-step adjustment of less than 1 dB. Due to insufficient attenuation accuracy, the signal amplitude is easily outside the optimal sampling interval of the ADC (i.e. 30%~70% of the full scale), introducing additional quantization errors and causing ADC sampling distortion, which seriously affects the accuracy of signal acquisition and the reliability of subsequent processing. SUMMARY

[0005] The application aims to provide a real-time digital monitoring data processing method and device for a dual-frequency modulation signal, and solve the problem that due to insufficient attenuation accuracy, the signal amplitude is easy to exceed the optimal sampling interval of an ADC (i.e. 30%~70% of the full scale), additional quantization error is introduced, ADC sampling distortion is caused, and the accuracy of signal collection and the reliability of subsequent processing are seriously affected.

[0006] The application is implemented by the following technical solutions:

[0007] In a first aspect, the application embodiment provides a real-time digital monitoring data processing method for a dual-frequency modulation signal, comprising:

[0008] processing a monitoring composite signal of an instrument landing system received by a receiver front end to obtain an attenuation processing analog signal;

[0009] performing digital signal conversion on the attenuation processing analog signal according to an ADC (analog-to-digital conversion) circuit to obtain a digital domain sampling signal;

[0010] performing two-stage DDC (digital down conversion) orthogonal digital down conversion processing on the digital domain sampling signal to obtain a baseband signal, a 90Hz component and a 150Hz component;

[0011] performing decimation sampling on the baseband signal, the 90Hz component and the 150Hz component to obtain a DC component sequence, a 90Hz component sequence and a 150Hz component sequence after synchronous decimation;

[0012] obtaining a modulation degree difference DDM and a modulation degree sum SDM according to the DC component sequence, the 90Hz component sequence and the 150Hz component sequence, and realizing updating of real-time digital monitoring data of the dual-frequency modulation signal.

[0013] Preferably, the processing of the monitoring composite signal of the instrument landing system received by the receiver front end to obtain the attenuation processing analog signal comprises:

[0014] receiving, by a receiver front end, a monitoring composite signal of an instrument landing system;

[0015] extracting a target frequency band in the monitoring composite signal according to an LC (inductor-capacitor) band pass filter in the receiver front end to obtain a target monitoring composite signal;

[0016] performing attenuation processing on the target monitoring composite signal according to a preset digital control attenuator value and a digital control attenuator to obtain an attenuation processing analog signal.

[0017] Preferably, the attenuation processing on the target monitoring composite signal according to the preset digital control attenuator value and the digital control attenuator to obtain the attenuation processing analog signal comprises:

[0018] Receiving a digital attenuator value sent by a host computer;

[0019] Controlling a digital attenuator to generate an AD value corresponding to the digital attenuator value in real time according to the digital attenuator value;

[0020] If the AD value meets a preset optimal sampling interval, attenuating the target monitoring composite signal according to the digital attenuator value and the digital attenuator to obtain an attenuated analog signal.

[0021] Preferably, the ADC analog-to-digital conversion circuit converts the attenuated analog signal into a digital signal to obtain a digital domain sampling signal, including:

[0022] According to a preset carrier frequency and a sampling frequency, an aliasing frequency is obtained, and the sampling frequency is the number of sample points collected per second when the ADC analog-to-digital conversion circuit samples the analog signal;

[0023] According to the ADC analog-to-digital conversion circuit and the aliasing frequency, the attenuated analog signal is converted into a digital signal to obtain an initial digital domain sampling signal;

[0024] According to the aliasing frequency and the sampling frequency, a digital angular frequency is calculated;

[0025] According to the digital angular frequency, the initial digital domain sampling signal is simplified to obtain a digital domain sampling signal.

[0026] Preferably, the digital domain sampling signal is processed by two-stage DDC quadrature digital down conversion to obtain a baseband signal, a 90Hz component and a 150Hz component, including:

[0027] According to a preset first-stage DDC quadrature digital down conversion, the digital domain sampling signal is down-converted to generate a baseband signal, and the baseband signal includes a direct current component and modulation information;

[0028] According to a preset second-stage DDC quadrature digital down conversion, two independent DDC channels and the baseband signal, a 90Hz component and a 150Hz component are obtained.

[0029] Preferably, the digital domain sampling signal is down-converted according to a preset first-stage DDC quadrature digital down conversion to generate a baseband signal, including:

[0030] According to a carrier frequency and a preset first-stage numerically controlled oscillator, a first-stage I-path local oscillator signal and a first-stage Q-path local oscillator signal are generated;

[0031] The first-stage I-path local oscillator signal is multiplied by the digital domain sampling signal to obtain a first-stage I-path component;

[0032] multiplying the first-stage Q-path local oscillator signal and the digital domain sampling signal to obtain a first-stage Q-path component;

[0033] performing IQ component synthesis on the first-stage I-path component and the first-stage Q-path component to obtain a baseband signal.

[0034] Preferably, the obtaining of the 90Hz component and the 150Hz component according to the preset second-stage DDC quadrature digital down conversion, two independent DDC channels and the baseband signal comprises:

[0035] generating a second-stage 90Hz I-path local oscillator signal and a second-stage 90Hz Q-path local oscillator signal according to a preset 90Hz component numerical control oscillator;

[0036] multiplying the second-stage 90Hz I-path local oscillator signal and the baseband signal to obtain a second-stage 90Hz I-path component;

[0037] multiplying the second-stage 90Hz Q-path local oscillator signal and the baseband signal to obtain a second-stage 90Hz Q-path component;

[0038] performing IQ component synthesis on the second-stage 90Hz I-path component and the second-stage 90Hz Q-path component to obtain a 90Hz component;

[0039] generating a second-stage 150Hz I-path local oscillator signal and a second-stage 150Hz Q-path local oscillator signal according to a preset 150Hz component numerical control oscillator;

[0040] multiplying the second-stage 150Hz I-path local oscillator signal and the baseband signal to obtain a second-stage 150Hz I-path component;

[0041] multiplying the second-stage 150Hz Q-path local oscillator signal and the baseband signal to obtain a second-stage 150Hz Q-path component;

[0042] performing IQ component synthesis on the second-stage 150Hz I-path component and the second-stage 150Hz Q-path component to obtain a 150Hz component.

[0043] Preferably, the decimation sampling of the baseband signal, the 90Hz component and the 150Hz component to obtain a direct current component sequence, a 90Hz component sequence and a 150Hz component sequence after synchronous decimation sampling comprises:

[0044] calculating a decimation factor according to a preset sampling frequency and a target sampling frequency, wherein the target sampling frequency is a sampling frequency output after decimation sampling;

[0045] According to the decimation factor, a first-stage CIC decimation factor, a second-stage CIC decimation factor and a third-stage FIR compensation filter decimation factor in the three-stage decimation filtering are determined;

[0046] According to the first-stage CIC decimation factor, the baseband signal is subjected to first-stage CIC decimation to obtain a decimated baseband signal;

[0047] The decimated baseband signal is subjected to FIR low-pass filtering to obtain a first direct current component;

[0048] According to the second-stage CIC decimation factor, the first direct current component is subjected to second-stage CIC decimation to obtain a second direct current component;

[0049] According to the third-stage FIR compensation filter decimation factor, the second direct current component is subjected to third-stage FIR compensation filter decimation to obtain a direct current component sequence corresponding to the baseband signal;

[0050] According to the first-stage CIC decimation factor, the second-stage CIC decimation factor and the third-stage FIR compensation filter decimation factor, the 90Hz component is sequentially subjected to decimation sampling to obtain a 90Hz component sequence;

[0051] According to the first-stage CIC decimation factor, the second-stage CIC decimation factor and the third-stage FIR compensation filter decimation factor, the 150Hz component is sequentially subjected to decimation sampling to obtain a 150Hz component sequence.

[0052] Preferably, according to the direct current component sequence, the 90Hz component sequence and the 150Hz component sequence, a modulation degree difference DDM and a modulation degree sum SDM are obtained to realize updating of real-time digital monitoring data of a dual-frequency modulation signal, including:

[0053] According to a preset sliding window, the direct current component sequence, the 90Hz component sequence and the 150Hz component sequence are subjected to sliding average respectively to obtain a direct current amplitude average value corresponding to the direct current component sequence, a 90Hz signal amplitude average value corresponding to the 90Hz component sequence and a 150Hz signal amplitude average value corresponding to the 150Hz component sequence;

[0054] According to the direct current amplitude average value, the 90Hz signal amplitude average value and the 150Hz signal amplitude average value, a 90Hz modulation degree and a 150Hz modulation degree are obtained by using a corresponding relationship between modulation degree and amplitude;

[0055] According to the 90Hz modulation degree and the 150Hz modulation degree, a modulation degree difference DDM and a modulation degree sum SDM are obtained.

[0056] In a second aspect, the embodiment of the present application provides a real-time digital monitoring data processing device of a dual-frequency modulation signal, comprising:

[0057] An attenuation module is configured to process a monitoring composite signal of an instrument landing system received by a front end of a receiver to obtain an attenuation processing analog signal;

[0058] A digital signal conversion module is configured to perform digital signal conversion on the attenuation processing analog signal according to an ADC (analog-to-digital conversion) circuit to obtain a digital domain sampling signal;

[0059] A down-conversion module is configured to perform two-stage DDC (digital down conversion) orthogonal digital down-conversion processing on the digital domain sampling signal to obtain a baseband signal, a 90Hz component and a 150Hz component;

[0060] An extraction sampling module is configured to perform extraction sampling on the baseband signal, the 90Hz component and the 150Hz component to obtain a direct current component sequence, a 90Hz component sequence and a 150Hz component sequence after synchronous down-sampling;

[0061] A modulation degree module is configured to obtain a modulation degree difference DDM and a modulation degree sum SDM according to the direct current component sequence, the 90Hz component sequence and the 150Hz component sequence, and to realize updating of real-time digital monitoring data of the dual-frequency modulation signal.

[0062] Compared with the prior art, the present application has the following advantages and beneficial effects:

[0063] By performing digital control attenuation and dynamic adjustment on the input signal, it is ensured that the analog-to-digital converter always works in the best quantization interval, and sampling distortion caused by signal overload or overlow is avoided from the source, and a high-fidelity digital signal source is provided for subsequent processing.

[0064] By using the analog-to-digital conversion based on the under-sampling technology, the requirement for the sampling rate of the ADC device is reduced under the premise of meeting the non-distortion signal acquisition, and the high-frequency radio frequency signal is converted into an intermediate frequency signal which is easy to process in the digital domain, thereby simplifying the front-end design of the system and reducing the hardware cost.

[0065] By performing two-stage orthogonal digital down-conversion processing, the accurate and synchronous separation of the carrier and the two modulation signals is completed in a parallel pipeline manner in the time domain. This method avoids the calculation delay of the traditional FFT algorithm and the precision deficiency of the single-stage down-conversion, and meets the dual requirements of real-time performance and accuracy for aviation-level applications while ensuring high isolation between channels.

[0066] The three signals are synchronously down-sampled by using a multi-stage cascade decimation filter scheme, a CIC filter is used to realize high-efficiency large-factor decimation, and then an FIR filter is used for compensation and anti-aliasing, so that the data rate is reduced from the MHz level to dozens of Hz matching the information update rate. This design greatly reduces the calculation load of the back-end processing unit and ensures the strict synchronization of the DC, 90Hz and 150Hz component sequences, thereby providing time-aligned data basis for instantaneous parameter calculation.

[0067] The measurement noise is effectively suppressed by performing sliding average and parameter calculation on the three synchronous sequences, and the modulation difference and modulation sum are stably output. The entire processing procedure is completed in a closed loop in the digital domain, the influence of the temperature drift and nonlinearity of analog devices is reduced, and the overall precision and long-term stability of the amplitude and modulation measurement are improved, thereby realizing reliable and real-time updating of the navigation monitoring data. BRIEF DESCRIPTION OF DRAWINGS

[0068] In order to more clearly illustrate the technical solutions of the exemplary embodiments of the present application, the drawings needed in the embodiments will be briefly introduced as follows. It should be understood that the following drawings only show some embodiments of the present application, and therefore should not be regarded as a limitation on the scope, and other related drawings can also be obtained by those skilled in the art without creative labor. In the drawings:

[0069] Figure 1 A flowchart of the real-time digital monitoring data processing method of the dual-frequency modulation signal provided in the present embodiment is shown in the figure.

[0070] Figure 2 A front-end attenuation processing flowchart provided in the present embodiment is shown in the figure.

[0071] Figure 3 An ADC under-sampling processing flowchart provided in the present embodiment is shown in the figure.

[0072] Figure 4 A first-stage DDC processing flowchart provided in the present embodiment is shown in the figure.

[0073] Figure 5 A second-stage DDC processing flowchart provided in the present embodiment is shown in the figure.

[0074] Figure 6 A multi-stage decimation filter processing flowchart provided in the present embodiment is shown in the figure.

[0075] Figure 7 A sliding average output processing flowchart provided in the present embodiment is shown in the figure.

[0076] Figure 8 A structure diagram of the real-time digital monitoring data processing device of the dual-frequency modulation signal provided in the present embodiment is shown in the figure. DETAILED DESCRIPTION

[0077] In order to make the objects, technical solutions and advantages of the present application clearer, further detailed description will be given to the present application in combination with embodiments and drawings, the illustrative embodiments of the present application and the description thereof are only used to explain the present application, and do not limit the present application.

[0078] It should be noted that, in this document, the terms such as first and second are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply that there is any such actual relationship or order between these entities or operations. Moreover, the terms “include”, “contain” or any other variants thereof are intended to cover non-exclusive inclusion, so that the process, method, article or device including a series of elements not only includes those elements, but also includes other elements not explicitly listed or inherent to such process, method, article or device. Without more limitations, the elements defined by the statement “include” do not exclude the presence of other identical elements in the process, method, article or device including the elements.

[0079] It should be noted that all actions of acquiring signals, information or data in the present application are carried out in compliance with the corresponding data protection regulations and policies of the place, and with the authorization given by the owner of the corresponding device.

[0080] Embodiment 1

[0081] See Figure 1 The embodiment of the present application provides a real-time digital monitoring data processing method of a dual-frequency modulation signal, which comprises the following steps:

[0082] S1, processing a monitoring composite signal of an instrument landing system received by a receiver front end to obtain an attenuation processing analog signal;

[0083] The invention motive of this step is to solve the problem of insufficient control accuracy and adjustment difficulty caused by temperature drift of traditional analog attenuator. The front-end attenuation link is constructed by using digital attenuator, which is a semiconductor device that can receive instructions through digital interface and accurately adjust the signal attenuation, such as PE43704, with attenuation range of 0 to 31.75dB and step of 0.25dB. The specific implementation process is as follows: the receiver front-end first extracts the target frequency band of the radio frequency signal through the LC band-pass filter, and then the host computer dynamically adjusts the attenuation value of the digital attenuator by sending control word to it based on real-time monitoring of ADC sampling value, so that the input signal amplitude of subsequent ADC is accurately controlled within its optimal quantization interval, thereby generating an attenuated analog signal with moderate amplitude. This process avoids the temperature drift of analog devices through all-digital control, ensuring that the initial conditions of signal acquisition are optimal, laying a foundation for subsequent high-precision digital processing.

[0084] In some embodiments, S1 processes the instrument landing system monitoring composite signal received by the receiver front-end to obtain an attenuated analog signal, including:

[0085] S11, the receiver front-end receives the instrument landing system monitoring composite signal;

[0086] The invention motive of this step is to establish physical connection between the system and external signal source to obtain the original radio frequency signal to be processed. The monitoring composite signal refers to the radio frequency signal containing 90Hz and 150Hz modulation information generated by the ground equipment of the instrument landing system and fed back through the monitoring composite network, which is the data source for parameter monitoring and fault diagnosis of the system. The receiver front-end is usually composed of antenna, low-noise amplifier and transmission link, and its function is to couple the electromagnetic wave signal in space and convert it into an electrical signal for subsequent circuit processing.

[0087] S12, according to the LC band-pass filter in the receiver front-end, the target frequency band in the monitoring composite signal is extracted to obtain a target monitoring composite signal;

[0088] The invention motive of this step is to select the specific navigation frequency band concerned by the system from the wideband received signal to suppress out-of-band noise and interference. The LC band-pass filter is a passive resonant circuit composed of inductor L and capacitor C, and the center frequency and bandwidth determine the frequency range of the passable signal. The specific implementation process is as follows: for different frequency bands of the directional beacon and the glide beacon, corresponding LC filter parameters are designed, for example, for the directional beacon signal with center frequency of 110MHz, the filter passband is set to 108MHz to 112MHz, so that the signal in this frequency band can pass through with low loss, while significantly attenuating irrelevant signals and noise outside this frequency range, obtaining a pure target monitoring composite signal.

[0089] S13, attenuating the target monitoring combined signal according to the preset digital attenuator value and the digital attenuator to obtain an attenuated analog signal.

[0090] The invention motive of this step is to accurately adjust the input signal with a possibly large amplitude dynamic range into the optimal working interval of the analog-to-digital converter, preventing the introduction of quantization error due to signal overload or being too small. The digital attenuator is a semiconductor device whose attenuation can be controlled by a digital code, for example, PE43704, whose attenuation range is 0-31.75 dB, supporting 0.25 dB step adjustment. The specific implementation process is as follows: the host computer or FPGA generates a specific digital attenuator value according to the preset attenuation strategy or real-time feedback ADC sampling value, and sends it to the device through a serial or parallel interface, and the digital attenuator then accurately attenuates the signal amplitude at its radio frequency port according to the digital code. This process directly sets the analog attenuation amount through digital instructions, realizes the programming and automation of attenuation control, avoids the inconvenience and temperature drift of traditional potentiometer adjustment, and ensures that the signal amplitude sent to the ADC is always within the ideal range.

[0091] In some embodiments, S13, attenuating the target monitoring combined signal according to the preset digital attenuator value and the digital attenuator to obtain an attenuated analog signal, comprises:

[0092] S131, receiving the digital attenuator value sent by the host computer;

[0093] In this step, the host computer sends a digital code representing a specific attenuation amount to the FPGA or microcontroller through a standard communication interface such as SPI or I2C.

[0094] S132, controlling the digital attenuator to generate an AD value corresponding to the digital attenuator value in real time according to the digital attenuator value;

[0095] In this step, the FPGA configures the received digital attenuator value to the digital attenuator hardware at the same time, synchronously collects the output of the ADC, and registers or feeds back this output value (i.e. AD value) to the host computer. This process establishes a real-time mapping relationship between the digital attenuator value and the actual sampling effect (AD value). This implementation enables the system to perceive the current attenuation state.

[0096] S133, if the AD value meets the preset optimal sampling interval, attenuating the target monitoring combined signal according to the digital attenuator value and the digital attenuator to obtain an attenuated analog signal.

[0097] The invention motive of this step is to ensure that the analog-to-digital converter always works in the linear region with the minimum nonlinear error, thereby ensuring the accuracy of the sampling data. The optimal sampling interval is a preset numerical range, which can be 30% to 70% of the full scale of the corresponding ADC, and in this interval, the quantization error of the ADC is the smallest and the signal-to-noise ratio is the highest. The specific implementation process is: the system (which can be in the logic of the host computer or FPGA) compares the real-time AD value obtained in step S132 with the upper and lower limits of the preset optimal sampling interval. If the AD value falls within this interval, it is determined that the current numerical control attenuator value is set correctly, and the configuration is maintained. At this time, the numerical control attenuator processes the target monitoring composite signal with this attenuation, and outputs the amplitude-optimized attenuated analog signal to the ADC. This judgment and execution mechanism effectively prevents clipping caused by signal overload or a decrease in quantization signal-to-noise ratio caused by a weak signal, thereby ensuring the quality of signal acquisition from the source.

[0098] Exemplarily, a numerical control attenuator PE43704 is used to receive a heading beacon signal (monitoring composite signal), the carrier frequency is =110MHz, and the sampling frequency =90MHz. The embodiment is described as follows:

[0099] ;

[0100] Among them, is the heading beacon signal, is the coefficient, and is the modulation degree, is the angular frequency corresponding to 90Hz, is the angular frequency corresponding to 150Hz.

[0101] As shown in Figure 2 , S1 includes:

[0102] Step 11: The receiver front end uses an LC bandpass filter to extract the target frequency band (heading 108MHz~112MHz, glide 328MHz~336MHz) as the input of the numerical control attenuator;

[0103] Step 12: The attenuation range of the numerical control attenuator PE43704 is 0~31.75dB, and the attenuation step can be selected (0.25dB, 0.5dB or 1.0dB); the FPGA communicates with the host computer, receives the numerical control attenuator value, controls the numerical control attenuator, and generates the AD value corresponding to the current attenuation value in real time;

[0104] Step 13: When the AD value does not meet the optimal sampling interval, the host computer adjusts the digital attenuation to generate an attenuated analog signal with an appropriate amplitude , wherein, For carrier amplitude, and The frequency of the modulated signal.

[0105] S2. According to the ADC analog-to-digital conversion circuit, the attenuated analog signal is converted into a digital signal to obtain a digital domain sampling signal;

[0106] The motivation behind this invention is to reduce the performance requirements of the ADC device and the speed requirements of subsequent digital processing units while ensuring distortion-free signal acquisition. Undersampling technology is employed, where the ADC samples the analog signal at a sampling frequency less than twice that required by the Nyquist sampling theorem. Specifically, the high-precision ADC analog-to-digital conversion circuit samples the signal at a frequency... For carrier frequency The attenuation processing of the analog signal is sampled when 90MHz and At 110MHz, because it does not meet the requirements The signal spectrum will alias, and its carrier frequency will alias in the digital domain to (Taking k=1), the digital domain sampling signal is obtained. This method converts high-frequency radio frequency signals into easily processed intermediate frequency signals in the digital domain, significantly reducing the system's requirements for ADC sampling rate and subsequent logic processing speed, and optimizing system complexity and cost.

[0107] In some embodiments, S2, according to the ADC analog-to-digital conversion circuit, performs digital signal conversion on the attenuated analog signal to obtain a digital domain sampling signal, including:

[0108] S21. Based on the preset carrier frequency and sampling frequency, the aliasing frequency is obtained, wherein the sampling frequency is the number of sample points collected per second when the ADC analog-to-digital conversion circuit samples the analog signal.

[0109] The motivation behind this invention is to provide a theoretical basis and key parameters for subsequent undersampling processing, ensuring that high-frequency signals can be correctly converted to the digital domain through spectral aliasing. The carrier frequency is the inherent center frequency of the input RF signal, and the sampling frequency is a fixed operating parameter of the ADC. When the sampling frequency does not satisfy the Nyquist sampling theorem, the signal spectrum will undergo periodic shifts. The aliasing frequency refers to the new frequency within the first Nyquist zone that the original carrier frequency maps to after sampling. The specific implementation process is as follows: according to the formula... Perform the calculation, where k is the value that satisfies The integer, by choosing an appropriate value of k (e.g., when =90MHz, When k=1 at 110MHz, the aliasing frequency is calculated. = 20MHz. This step determines the position of the signal in the digital domain by theoretical calculation, and provides an accurate target for the subsequent local oscillator frequency setting.

[0110] S22, digitally converting the attenuated analog signal according to the ADC analog-to-digital conversion circuit and the aliasing frequency, to obtain an initial digital domain sampling signal;

[0111] The invention motive of this step is to perform actual analog-to-digital conversion, to discretize the analog signal with optimized amplitude into a digital sequence, and to reduce the signal center frequency by aliasing effect. The ADC analog-to-digital conversion circuit samples and quantizes the input attenuated analog signal at a fixed sampling frequency. The specific implementation process is: the ADC collects and converts the input voltage into a corresponding digital code once in each clock cycle. Since the sampling frequency is lower than twice the carrier frequency, according to the expectation of step S21, the carrier frequency is After sampling, the signal component with is aliased to , thereby outputting a digital sequence with as the carrier. This process converts the high-frequency radio frequency signal into a lower-frequency intermediate frequency signal in the digital domain, which has the technical effect of reducing the requirement for the sampling rate of the ADC device itself, and relieving the pressure on the subsequent digital logic processing data stream.

[0112] S23, calculating a digital angular frequency according to the aliasing frequency and the sampling frequency;

[0113] In this step, according to the basic relationship of digital signal processing, the formula is used for calculation to normalize the analog frequency of the aliased signal to the sampling frequency. The conversion from physical frequency to the frequency scale inherent in the digital system is realized.

[0114] S24, simplifying the initial digital domain sampling signal according to the digital angular frequency, to obtain a digital domain sampling signal.

[0115] Figure 3 As shown in

[0116] Step 21: the digital domain sampling signal is output in an under-sampling manner to reduce the requirement for ADC speed and subsequent processing. The input signal s(t) is sampled. Since = 90MHz, = 110MHz, , the Nyquist sampling theorem cannot be met, and an aliasing frequency is generated, where k is an integer, so that . Therefore, k = 1 is taken, falling into the first Nyquist zone, to obtain an aliasing frequency = 20MHz, to generate a digital domain sampling signal:

[0117] ,

[0118] wherein the sampling interval , the sampling point ;

[0119] Step 22: calculating the digital angular frequency , and simplifying to obtain the digital domain sampling signal:

[0120] ,

[0121] wherein, .

[0122] S3, performing two-stage DDC quadrature digital down-conversion processing on the digital domain sampling signal to obtain a baseband signal, a 90Hz component and a 150Hz component;

[0123] The invention motive of this step is to separate the carrier, 90Hz and 150Hz modulation signals with high precision and high efficiency, so as to overcome the shortcomings of high complexity of FFT method and insufficient precision of single-stage down-conversion method. The specific implementation process is as follows: the first-stage DDC generates a quadrature local oscillator signal with the same frequency as the aliasing carrier frequency through a numerically controlled oscillator, mixes the digital domain sampling signal with the quadrature local oscillator signal, and after low-pass filtering, obtains a baseband signal containing modulation information, which realizes the separation of the carrier component; the second-stage DDC uses two independent channels, respectively using NCO (Numerically Controlled Oscillator) local oscillator signals with frequencies of 90Hz and 150Hz to perform quadrature down-conversion and low-pass filtering on the baseband signal again, and the cutoff frequency of the low-pass filter is set to only retain the direct current component, so as to demodulate the 90Hz component amplitude and the 150Hz component amplitude proportional to their modulation degrees, respectively. The two-stage structure processes in parallel in the time domain, ensuring the precision of signal separation and the isolation degree between channels, and its pipeline architecture guarantees the real-time performance of data processing.

[0124] In some embodiments, S3, performing two-stage DDC quadrature digital down-conversion processing on the digital domain sampling signal to obtain a baseband signal, a 90Hz component and a 150Hz component, includes:

[0125] S31, performing down-conversion processing on the digital domain sampling signal according to a preset first-stage DDC quadrature digital down-conversion to generate a baseband signal, wherein the baseband signal includes a direct current component and modulation information;

[0126] This step is to remove the high frequency carrier component in the digital domain sampling signal, so as to demodulate the baseband signal containing all information. First, a pair of digital local oscillator signals completely consistent with the carrier frequency in the signal and in phase quadrature, that is, a cosine component and a sine component, are generated. Then, the input digital domain sampling signal is multiplied by the pair of local oscillator signals, and this mixing operation produces a series of new signal components containing sum frequency and difference frequency components. Next, a low-pass filter is used to filter the multiplied signal, and the cutoff frequency is set to be much lower than any sum frequency component, so that all high frequency components generated by mixing are filtered out, and only the difference frequency component is retained. Since the local oscillator frequency is set to be equal to the signal carrier frequency, the difference frequency result is the sum of the direct current component and the original 90Hz and 150Hz modulation information, and this output is the required baseband signal. This step moves the signal spectrum from the carrier frequency to the vicinity of zero frequency through quadrature down-conversion, and the technical effect is to realize carrier separation and prepare conditions for subsequent accurate extraction of individual modulation components.

[0127] S32, obtaining a 90Hz component and a 150Hz component according to the preset second-stage DDC quadrature digital down-conversion, two independent DDC channels and the baseband signal.

[0128] The invention motive of this step is to separate two independent modulation components from the baseband signal containing mixed information without loss. Two parallel digital down-conversion channels with the same structure are set to work independently. The first channel generates a quadrature signal with a local oscillator frequency of 90Hz, and mixes and low-pass filters the baseband signal. The filter is configured to only allow direct current to pass through, so as to output a direct current signal whose amplitude is proportional to the 90Hz modulation degree, that is, a 90Hz component. The second channel uses the same processing logic, but uses a local oscillator signal with a frequency of 150Hz, so as to output a direct current signal whose amplitude is proportional to the 150Hz modulation degree, that is, a 150Hz component. The two channels share the baseband signal as input, but demodulate at their respective frequencies. The technical effect of this parallel processing architecture is to realize the synchronous and high-isolation separation of 90Hz and 150Hz signals, avoiding crosstalk between channels.

[0129] In some embodiments, S31, the digital domain sampling signal is down-converted according to the preset first-stage DDC quadrature digital down-conversion, to generate a baseband signal, including:

[0130] According to the carrier frequency and the preset first-stage numerically controlled oscillator, a first-stage I-path local oscillator signal and a first-stage Q-path local oscillator signal are generated;

[0131] The first-stage I-path local oscillator signal and the digital domain sampling signal are multiplied to obtain a first-stage I-path component;

[0132] multiplying the first-stage I-path component and the first-stage Q-path component to obtain a baseband signal.

[0133] multiplying the first-stage I-path component and the first-stage Q-path component to obtain a baseband signal.

[0134] In the embodiment, first, a first-stage numerically controlled oscillator is configured according to a known carrier frequency, so that the first-stage numerically controlled oscillator generates a pair of digital local oscillator signals with a frequency consistent with the carrier frequency and in phase quadrature, i.e., a first-stage I-path local oscillator signal and a first-stage Q-path local oscillator signal. Subsequently, the input digital-domain sampling signal is subjected to digital multiplication operation with the I-path and Q-path local oscillator signals respectively. The mixing operation utilizes the product-to-sum and difference characteristics of trigonometric functions to generate frequency spectrum components containing the sum and difference of the frequencies of the original signal and the local oscillator signal in the output signal. The first-stage I-path component and the first-stage Q-path component obtained after mixing both contain difference frequency components near the baseband and sum frequency components at high frequencies. To extract useful baseband information, the two signals need to be subjected to IQ component synthesis. The two in-phase real signals are constructed into a complex signal, and the high-frequency sum frequency components generated by mixing are effectively filtered out through a subsequent low-pass filtering link. Finally, the processing step outputs a baseband signal containing only direct current components and 90Hz and 150Hz modulation information, thereby realizing carrier stripping and successfully down-converting the signal to zero intermediate frequency.

[0135] In some embodiments, S32, according to the preset second-stage DDC quadrature digital down-conversion, two independent DDC channels and the baseband signal, obtains 90Hz components and 150Hz components, including:

[0136] generating a second-stage 90Hz I-path local oscillator signal and a second-stage 90Hz Q-path local oscillator signal according to a preset 90Hz component numerically controlled oscillator;

[0137] multiplying the second-stage 90Hz I-path local oscillator signal and the baseband signal to obtain a second-stage 90Hz I-path component;

[0138] multiplying the second-stage 90Hz Q-path local oscillator signal and the baseband signal to obtain a second-stage 90Hz Q-path component;

[0139] performing IQ component synthesis on the second-stage 90Hz I-path component and the second-stage 90Hz Q-path component to obtain 90Hz components;

[0140] generating a second-stage 150Hz I-path local oscillator signal and a second-stage 150Hz Q-path local oscillator signal according to a preset 150Hz component numerically controlled oscillator;

[0141] The second level 150Hz I channel local oscillator signal is multiplied by the baseband signal to obtain a second level 150Hz I channel component;

[0142] The second level 150Hz Q channel local oscillator signal is multiplied by the baseband signal to obtain a second level 150Hz Q channel component;

[0143] The second level 150Hz I channel component and the second level 150Hz Q channel component are subjected to IQ component synthesis to obtain a 150Hz component.

[0144] The embodiment constitutes a second level digital down conversion, and the purpose is to synchronously and independently separate two modulation components of 90Hz and 150Hz from a baseband signal containing mixed modulation information; the specific implementation process is as follows: two independent quadrature down conversion channels are provided in parallel in the system, the first channel generates corresponding quadrature local oscillator signals according to a 90Hz component numerical control oscillator, and the baseband signal is multiplied by the quadrature local oscillator signals respectively, and then the obtained I and Q channel components are synthesized and low-pass filtered, so as to extract a direct current amplitude proportional to the 90Hz modulation depth, that is, the 90Hz component; at the same time, the second channel generates the local oscillator signals according to the 90Hz component numerical control oscillator, and processes the same baseband signal according to the same processing logic, and finally extracts a direct current amplitude proportional to the 150Hz modulation depth, that is, the 150Hz component; the parallel architecture ensures that the two modulation components can be demodulated synchronously and with high isolation, which provides a basis for subsequent accurate calculation of the modulation degree difference and sum.

[0145] Exemplarily, as shown in Figure 4 , the S31 specifically comprises:

[0146] Step 311: generating a first level numerical control oscillator (NCO) local oscillator signal according to a carrier frequency provided by an upper computer , the first level I channel local oscillator is , the first level Q channel local oscillator is (equivalent to a complex signal ), wherein the NCO frequency , the sampling time , and the digital angular frequency ;

[0147] Step 312: dividing the digital domain sampling signal in step 2 into two channels, one of which is multiplied by the first level I channel local oscillator to obtain

[0148] ,

[0149] According to the trigonometric identity cosαcosβ= , a first level I channel component is obtained:

[0150] ;

[0151] Another road and the first level Q road local oscillator, get:

[0152] ,

[0153] According to the identity of the triangle , get the first level Q road component:

[0154] ;

[0155] Step 313: the above first level I road component, Q road component carries high frequency component, digital angle frequency Corresponding analog frequency 40MHz, is not needed frequency component, so use low pass filter (LPF) to retain baseband component and remove 40 MHz high frequency component, the cut-off frequency should be greater than the maximum modulation frequency, only baseband signal is retained. The resulting baseband signal is , to achieve carrier down conversion;

[0156] Further, as Figure 5 , S32 is specifically:

[0157] Step 321: generate 90Hz component NCO local oscillator signal, the second level 90Hz I road local oscillator is , the second level 90Hz Q road local oscillator is (Equivalent to complex signal ), wherein the NCO frequency ;

[0158] Step 322: divide the baseband signal In step 31 into two ways, one way and the second level 90Hz I road local oscillator is multiplied, get:

[0159] ,

[0160] According to the identity of the triangle, get the second level 90Hz I road component:

[0161] ;

[0162] Another road and the second level 90Hz Q road local oscillator, get:

[0163] ,

[0164] According to the identity of the triangle, get the second level 90Hz Q road component:

[0165] ;

[0166] Step 323: low-pass filter and combine the second-stage 90Hz I-path component and the second-stage 90Hz Q-path component signals; the second-stage 90Hz I-path component and the second-stage 90Hz Q-path only need to retain the direct current signal (containing 90Hz information), and the frequency components of 60Hz and above are filtered out by a low-pass filter to obtain , , generate the 90Hz component amplitude ;

[0167] Step 324: generate a 150Hz component NCO local oscillator signal, the second-stage 150Hz I-path local oscillator is , and the second-stage 150Hz Q-path local oscillator is (equivalent to a complex signal ), wherein the NCO frequency ;

[0168] Step 325: divide the baseband signal in step 31 into two paths, one path is multiplied by the second-stage 150Hz I-path local oscillator to obtain:

[0169] ,

[0170] According to the trigonometric identity, the second-stage 150Hz I-path component is obtained:

[0171] ;

[0172] The other path is multiplied by the second-stage 150Hz Q-path local oscillator to obtain:

[0173] ,

[0174] According to the trigonometric identity, the second-stage 150Hz Q-path component is obtained:

[0175] ;

[0176] Step 326: low-pass filter and combine the second-stage 150Hz I-path component and the second-stage 150Hz Q-path component signals; the second-stage 150Hz I-path component and the second-stage 150Hz Q-path only need to retain the direct current signal (containing 150Hz information), and the frequency components of 60Hz and above are filtered out by a low-pass filter to obtain , , generate the 150Hz component amplitude .

[0177] ​S4, performing decimation sampling on the baseband signal, the 90Hz component and the 150Hz component to obtain a sequence of the direct current component, a sequence of the 90Hz component and a sequence of the 150Hz component after synchronous decimation sampling;

[0178] The invention motive of the step is to reduce the signal stream of high sampling rate to low data rate matching the final information update rate, so as to greatly reduce the calculation load and resource occupation of the subsequent processing module. A multi-stage cascaded decimation filtering scheme is adopted. The specific implementation process is as follows: a shared three-stage decimation sequence is designed, wherein the first stage and the second stage adopt a CIC filter with high calculation efficiency to realize a large decimation factor, and the third stage adopts a FIR compensation filter to correct the passband attenuation and complete the final anti-aliasing filtering; for the baseband signal, an FIR low-pass filter is added after the first-stage CIC decimation to separate the pure direct current component, and the 90Hz and 150Hz components are directly decimated by sharing the three-stage pipeline, and finally the direct current component sequence, the 90Hz component sequence and the 150Hz component sequence at the target sampling rate are synchronously output. The multi-stage non-uniform decimation structure reduces the order and logic resource consumption of the single FIR filter to the maximum extent while ensuring the filtering performance, and balances the data processing efficiency and hardware overhead.

[0179] In some embodiments, S4, performing decimation sampling on the baseband signal, the 90Hz component and the 150Hz component to obtain a sequence of the direct current component, a sequence of the 90Hz component and a sequence of the 150Hz component after synchronous decimation sampling, comprises:

[0180] S41, calculating a decimation factor according to a preset sampling frequency and a target sampling frequency, wherein the target sampling frequency is the sampling frequency after decimation sampling;

[0181] The invention motive of the step is to provide a quantitative design target for the subsequent multi-stage decimation filtering to determine the total data rate reduction multiple required. The decimation factor is defined as the ratio of the original sampling frequency to the target sampling frequency, and its value directly reflects the decimation amplitude. The specific implementation process is as follows: the system obtains the original sampling frequency of the ADC operation and the target sampling frequency required for the final parameter update, and calculates the total decimation factor by performing a division operation. For example, when the original sampling frequency is 90MHz and the target sampling frequency is 50Hz, the total decimation factor is calculated to be 1800000. This step establishes the core performance index of the entire decimation process through simple arithmetic operation, and its technical effect is to convert the real-time requirement of the system into a clear and achievable filtering design constraint condition.

[0182] S42, determining a first-stage CIC decimation factor, a second-stage CIC decimation factor and a third-stage FIR compensation filtering decimation factor in the three-stage decimation filtering according to the decimation factor.

[0183] The inventive motivation of this step is to reasonably decompose a large total decimation factor to balance the implementation complexity of each stage filter and the system resource consumption. Multi-stage decimation is a common optimization strategy to reduce the overall computational load by decomposing a single high-order filter into a cascade of multiple low-order filters. The specific implementation process is: according to the size of the total decimation factor, it is decomposed into the product of three sub-decimation factors, that is, the total decimation factor is equal to the product of the first stage CIC decimation factor, the second stage CIC decimation factor and the third stage FIR compensation filter decimation factor. In the decomposition, the first two stages are usually assigned to the CIC filter with high computational efficiency but poor passband characteristics, which is used to realize a large decimation factor; the last stage is assigned to the FIR filter with controllable passband, which is used to compensate for the passband attenuation of the previous stage and complete the precise anti-aliasing. For example, 1800000 is decomposed into the product of 1000, 100 and 18. The technical effect of this decomposition process is to optimize the structure of the filter bank, which significantly reduces the logic resources and computational complexity required for implementation while ensuring the filtering performance.

[0184] S43, performing first stage CIC decimation on the baseband signal according to the first stage CIC decimation factor to obtain a decimated baseband signal;

[0185] The inventive motivation of this step is to perform the first stage of down-sampling, which utilizes the characteristic of CIC filter without multiplier to efficiently realize large data rate compression. CIC is a recursive structure based on integrator and comb filter, which is particularly suitable for high decimation front-end. The specific implementation process is: inputting the baseband signal containing modulation information into the first stage CIC decimation filter, which processes the input data according to the preset first stage CIC decimation factor, for example, 1000, that is, for every 1000 input samples, output 1 sample, thereby reducing the sampling rate of the signal from the original sampling rate to one thousandth. This step realizes a large reduction in data rate through an efficient hardware-friendly structure, and its technical effect is to reduce the data processing pressure of the subsequent stages of filters.

[0186] S44, performing FIR low-pass filter processing on the decimated baseband signal to obtain a first direct current component;

[0187] The inventive motivation of this step is to separate the pure DC component from the baseband signal with reduced sampling rate to remove the modulation information and provide an accurate carrier amplitude reference for subsequent navigation parameter calculation. The FIR low-pass filter is a non-recursive filter with a finite length unit impulse response, whose characteristics are determined by a set of coefficients. The specific implementation process is as follows: the baseband signal after the first-stage CIC decimation is passed through a FIR low-pass filter with extremely low cutoff frequency, and the passband of the filter is designed to allow only the DC component to pass, thereby effectively filtering out the residual 90Hz and 150Hz modulation frequency components in the signal, and outputting a pure first DC component signal representing the carrier amplitude. This step realizes the separation of signal components through accurate frequency selection characteristics and provides an accurate reference amplitude for subsequent calculation.

[0188] S45, performing second-stage CIC decimation on the first DC component according to the second-stage CIC decimation factor to obtain a second DC component;

[0189] The inventive motivation of this step is to further decimate the DC signal after filtering out the modulation information to continue to reduce the data rate. Since the signal is now a pure DC component, there is no need for complex filtering. The specific implementation process is as follows: the first DC component is input to the second-stage CIC decimation filter, which processes the input data according to the pre-set second-stage CIC decimation factor, for example, 100, i.e. for every 100 input samples, 1 sample is output, thereby reducing the sampling rate of the signal again to obtain the second DC component. This step reuses the efficient CIC structure for secondary decimation, further reducing the data throughput while ensuring that the nature of the signal remains unchanged.

[0190] S46, performing third-stage FIR compensation filtering decimation on the second DC component according to the third-stage FIR compensation filtering decimation factor to obtain a DC component sequence corresponding to the baseband signal;

[0191] The inventive motivation of this step is to complete the final decimation and signal quality optimization, and output a DC amplitude sequence that meets the target update rate. The FIR filter has both compensation and anti-aliasing functions of the previous stage. The specific implementation process is as follows: the second DC component is input to the third-stage FIR compensation filter, which performs decimation according to the third-stage FIR compensation filtering decimation factor, for example, 18, while its frequency response is designed to compensate for the passband attenuation introduced by the previous two CIC filters and ensure that aliasing does not occur after the final decimation, thereby outputting a DC component sequence with a sampling rate exactly equal to the target sampling rate and an accurate amplitude. This step finally reduces the data stream to the information update rate required by the system and outputs a high-precision, real-time carrier amplitude data stream.

[0192] S47, sequentially decimating the 90Hz component according to the first-stage CIC decimation factor, the second-stage CIC decimation factor and the third-stage FIR compensation filter decimation factor, to obtain a 90Hz component sequence;

[0193] S48, sequentially decimating the 150Hz component according to the first-stage CIC decimation factor, the second-stage CIC decimation factor and the third-stage FIR compensation filter decimation factor, to obtain a 150Hz component sequence.

[0194] The inventive motivation of steps S47 and S48 is to implement the decimation processing of two modulation components synchronously with the direct current component, to ensure that the three-way data finally used for parameter calculation are aligned in time. The 90Hz component and the 150Hz component are direct current signals representing respective amplitudes after the second-stage DDC output. The specific implementation process is that the two components are directly sent into the third-stage decimation pipeline shared with the direct current component, that is, sequentially passing through the CIC decimation controlled by the same first-stage CIC decimation factor, the CIC decimation controlled by the same second-stage CIC decimation factor, and the FIR decimation filter controlled by the same third-stage FIR compensation filter decimation factor. Since the input signal itself is direct current, it is not necessary to additionally perform the FIR separation filter as the baseband signal. The technical effect of this multiplexing pipeline architecture is to ensure that the direct current, 90Hz and 150Hz three-way signals undergo exactly the same delay and decimation process, thereby guaranteeing the strict synchronization of their final output sequences.

[0195] Exemplarily, as shown in Figure 6 , S4 comprises:

[0196] Step 41: calculating a decimation factor R according to an original sampling rate and a target sampling rate , satisfying . Assuming that the target sampling rate = 50Hz, the above original sampling rate = 90MHz, the decimation factor = 1800000 is obtained. R is very large, to reduce the system overhead, a three-stage decimation filter is adopted, satisfying . Wherein, is the first-stage decimation factor, is the second-stage decimation factor, is the third-stage decimation factor;

[0197] The baseband signal, the 90Hz component and the 150Hz component channel share the same three-stage decimation pipeline architecture. But the baseband signal needs to be additionally pre-filtered, because the baseband signal also contains modulation information. The baseband signal is filtered after the first-stage CIC decimation, to reduce the filter order and save resources, so the first-stage CIC decimation factor =1000, second stage CIC decimation factor =100, third stage FIR compensation filter decimation factor =18, satisfying =1800000;

[0198] Step 42: decimating the baseband signal to generate a 90Hz component sequence at a target sampling rate of ;

[0199] The above baseband signal is subjected to a first stage CIC decimation to output a baseband signal at a sampling rate of =90KHz;

[0200] The above baseband signal at a sampling rate of =90KHz is subjected to a FIR low-pass filter to separate out a DC component ;

[0201] The above DC component is subjected to a second stage CIC decimation to output a DC component at a sampling rate of =900Hz;

[0202] The above DC component is subjected to a third stage FIR compensation filter decimation to output a DC component sequence at a target sampling rate of =50Hz .

[0203] Step 43: decimating the 90Hz component to generate a 90Hz component sequence at a target sampling rate of ;

[0204] Step 44: decimating the 150Hz component to generate a 150Hz component sequence at a target sampling rate of ;

[0205] Further, the specific process of Step 42 is as follows:

[0206] Step 421: first stage CIC decimation, decimation factor , output sampling rate , to generate a baseband signal at a sampling rate of ;

[0207] Step 422: the above baseband signal still contains modulation information, and filtering when reducing the sampling rate can reduce the filter order. The modulation information is filtered out by a FIR low-pass filter, and only the DC component is retained;

[0208] Step 423: second stage CIC decimation, decimation factor , output sampling rate , to generate a DC component at a sampling rate of ;

[0209] Step 424: Third-stage FIR compensated filtering decimation, decimation factor Output sampling frequency ,satisfy , generate target sampling rate DC component sequence;

[0210] Furthermore, the specific process of step 43 is as follows:

[0211] Step 431: Reuse the first-stage CIC extraction from step 421 to extract the aforementioned 90Hz component. Perform the first-stage CIC decimation and output the sampling frequency. =90kHz 90Hz component;

[0212] Step 432: Reuse the second-level CIC decimation from step 423 to perform a second-level CIC decimation on the aforementioned 90Hz component, and output the sampling frequency. =900Hz 90Hz component;

[0213] Step 433: Reuse the third-stage FIR compensated filtering decimation from step 424 to perform third-stage FIR compensated filtering decimation on the 90Hz component, and output the target sampling frequency. =50Hz 90Hz component sequence .

[0214] Furthermore, the specific process of step 44 is as follows:

[0215] Step 441: Reuse the first-stage CIC extraction from step 421 to extract the aforementioned 150Hz component. Perform the first-stage CIC decimation and output the sampling frequency. =150Hz component of 90kHz;

[0216] Step 442: Reuse the second-level CIC decimation from step 423 to perform a second-level CIC decimation on the aforementioned 150Hz component, generating a sampling frequency of... =150Hz component of 900Hz;

[0217] Step 443: Reuse the third-stage FIR compensated filtering decimation from step 424, perform third-stage FIR compensated filtering decimation on the above 150Hz component, and output the target sampling frequency. =50Hz 150Hz component sequence .

[0218] S5, obtaining a modulation depth difference DDM and a modulation depth sum SDM according to the direct current component sequence, the 90Hz component sequence and the 150Hz component sequence, and realizing updating of real-time digital monitoring data of the dual-frequency modulation signal.

[0219] The invention motive of this step is to stably calculate the navigation key parameters from the down-sampled sequences and to meet the system requirements for data output real-time and stability. The specific implementation process is: sliding average processing is applied to the three sequences in parallel, that is, arithmetic average of data is performed in a window with a length of N and the output is slid point by point, so as to obtain the direct current amplitude average value, the 90Hz signal amplitude average value and the 150Hz signal amplitude average value; then, according to the modulation depth definition, the 90Hz modulation depth and the 150Hz modulation depth are calculated respectively; finally, the modulation depth difference and the modulation depth sum are calculated according to the 90Hz modulation depth and the 150Hz modulation depth. The sliding average method effectively suppresses the influence of random fluctuations on amplitude measurement, and the parallel processing architecture guarantees the synchronization of the three data, so that the modulation depth difference DDM and the modulation depth sum SDM can be updated in real time, which provides continuous and reliable monitoring data for the instrument landing system.

[0220] In some embodiments, S5, obtaining a modulation depth difference DDM and a modulation depth sum SDM according to the direct current component sequence, the 90Hz component sequence and the 150Hz component sequence, and realizing updating of real-time digital monitoring data of the dual-frequency modulation signal, includes:

[0221] S51, performing sliding average on the direct current component sequence, the 90Hz component sequence and the 150Hz component sequence according to a preset sliding window, respectively, to obtain a direct current amplitude average value corresponding to the direct current component sequence, a 90Hz signal amplitude average value corresponding to the 90Hz component sequence and a 150Hz signal amplitude average value corresponding to the 150Hz component sequence;

[0222] The invention motive of this step is to suppress random fluctuations and noise in the signal to obtain a stable and reliable amplitude estimation value, providing a basis for subsequent high-precision parameter calculation. Moving average is a time domain digital filtering technique that achieves smoothing by calculating the arithmetic mean value within a fixed-length data window. The specific implementation process is as follows: the system configures three moving averageers with the same structure for the DC, 90Hz and 150Hz component sequences in parallel, and each averageer covers the respective input sequence with a preset length window (e.g. containing 32 data points) in turn; for each group of data covered by the window, calculate its arithmetic mean value and output the result, then slide the window forward by one data point and repeat the process, thus generating three smoothed output sequences, namely the DC amplitude mean value sequence, the 90Hz signal amplitude mean value sequence and the 150Hz signal amplitude mean value sequence. This parallel processing architecture ensures the synchronization of the three channels, effectively filters out the high-frequency fluctuations caused by noise and other factors in amplitude measurement, improves the stability of the data, and at the same time maintains the real-time nature of parameter updating.

[0223] S52, according to the DC amplitude mean value, the 90Hz signal amplitude mean value and the 150Hz signal amplitude mean value, using the corresponding relationship between the modulation degree and the amplitude, obtaining the 90Hz modulation degree and the 150Hz modulation degree;

[0224] The invention motive of this step is to convert the smoothed amplitude information into standard modulation degree parameters, which is the direct basis for navigation parameter calculation. Modulation degree is defined as the ratio of modulation signal amplitude to carrier amplitude, reflecting the modulation depth. The specific implementation process is as follows: the system first obtains the DC amplitude mean value, 90Hz signal amplitude mean value and 150Hz signal amplitude mean value output by step S51 at the same time; then, according to the definition of modulation degree, divide the 90Hz signal amplitude mean value by the DC amplitude mean value, and multiply the result by 100%, to calculate the 90Hz modulation degree at the current time; using the same calculation process, divide the 150Hz signal amplitude mean value by the DC amplitude mean value and multiply by 100% to obtain the 150Hz modulation degree at the current time. This calculation process is based on the linear relationship between amplitude and modulation degree, normalizing the original amplitude measurement value to a dimensionless modulation depth parameter with clear physical meaning.

[0225] S53, according to the 90Hz modulation degree and the 150Hz modulation degree, obtaining the modulation degree difference DDM and the modulation degree sum SDM.

[0226] The inventive motivation of this step is to calculate two final key parameters for spatial positioning guidance in instrument landing system. The modulation difference (DDM) and the modulation sum (SDM) are navigation parameters defined in international standards, which directly drive the display of the aircraft instrument. The specific implementation process is as follows: the system obtains the 90Hz modulation and the 150Hz modulation calculated by step S52; then, a subtraction operation is performed, and the difference between the 150Hz modulation and the 90Hz modulation is the modulation difference DDM; at the same time, an addition operation is performed, and the sum of the 150Hz modulation and the 90Hz modulation is the modulation sum SDM. The core information directly representing the horizontal or vertical position of the aircraft relative to the center line of the runway is output, thereby realizing complete monitoring and data updating of the dual-frequency modulation signal.

[0227] As shown in Figure 7 , S5 includes:

[0228] Step 51: sliding average (window length N) is performed on the above direct current component sequence, assuming that the window length is 32, the update time is 640ms, the sliding average is performed on the above direct current component sequence to generate the direct current amplitude average value DC_avg[k];

[0229] Step 52: reuse the sliding average module in step 51, and sliding average is performed on the above 90Hz component sequence to generate the 90Hz signal amplitude average value A90_avg[k];

[0230] Step 53: reuse the sliding average module in step 51, and sliding average is performed on the above 150Hz component sequence to generate the 150Hz signal amplitude average value A150_avg[k];

[0231] Step 54: using the corresponding relationship between the modulation and the amplitude, the above direct current amplitude average value DC_avg[k], the 90Hz signal amplitude average value A90_avg[k], and the 150Hz signal amplitude average value A150_avg[k] are used to generate the 90Hz modulation , and the 150Hz modulation ;

[0232] Step 55: according to the above 90Hz modulation , 150Hz modulation , further calculation of the modulation difference DDM= , and the modulation sum SDM= is performed to realize the analysis of the modulation signal.

[0233] Embodiment 2

[0234] Please refer to Figure 8The embodiment of the present application provides a real-time digital monitoring data processing device of a double-frequency modulation signal, comprising:

[0235] An attenuation module 801 is used for processing a monitoring composite signal of an instrument landing system received by a front end of a receiver to obtain an attenuation processing analog signal;

[0236] A digital signal conversion module 802 is used for converting the attenuation processing analog signal into a digital signal according to an ADC (analog-to-digital conversion) circuit to obtain a digital domain sampling signal;

[0237] A down-conversion module 803 is used for performing two-stage DDC (digital down conversion) orthogonal digital down-conversion processing on the digital domain sampling signal to obtain a baseband signal, a 90Hz component and a 150Hz component;

[0238] An extraction sampling module 804 is used for extracting and sampling the baseband signal, the 90Hz component and the 150Hz component to obtain a direct current component sequence, a 90Hz component sequence and a 150Hz component sequence after synchronous decimation sampling;

[0239] A modulation degree module 805 is used for obtaining a modulation degree difference DDM and a modulation degree sum SDM according to the direct current component sequence, the 90Hz component sequence and the 150Hz component sequence to realize updating of real-time digital monitoring data of the double-frequency modulation signal.

[0240] It should be noted that the modules and units in the real-time digital monitoring data processing device of the double-frequency modulation signal in the embodiment are one-to-one corresponding to the steps in the real-time digital monitoring data processing method of the double-frequency modulation signal in the foregoing embodiment, and therefore, the specific embodiments of the embodiment can refer to the embodiments of the real-time digital monitoring data processing method of the double-frequency modulation signal, which will not be repeated here.

[0241] The above specific embodiments further specifically describe the purposes, technical solutions and beneficial effects of the present application, and it should be understood that the above description is only the specific embodiments of the present application and is not used to limit the protection scope of the present application, and any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present application should be included in the protection scope of the present application.

Claims

1. A real-time digital monitoring data processing method for a dual frequency modulated signal, characterized in that, The application relates to a method for processing a monitoring composite signal of an instrument landing system received by a receiver front end, and comprises the following steps: processing the monitoring composite signal of the instrument landing system received by the receiver front end to obtain an attenuation processing analog signal; carrying out digital signal conversion on the attenuation processing analog signal by an ADC analog-digital conversion circuit to obtain a digital domain sampling signal; carrying out two-stage DDC quadrature digital down conversion processing on the digital domain sampling signal to obtain a baseband signal, a 90Hz component and a 150Hz component; carrying out decimation sampling on the baseband signal, the 90Hz component and the 150Hz component to obtain a direct current component sequence, a 90Hz component sequence and a 150Hz component sequence after synchronous decimation sampling; obtaining a modulation degree difference DDM and a modulation degree sum SDM according to the direct current component sequence, the 90Hz component sequence and the 150Hz component sequence to realize updating of real-time digital monitoring data of a double-frequency modulation signal.

2. The method of claim 1, wherein, The method for processing the monitoring composite signal of the instrument landing system received by the receiver front end to obtain the attenuation processing analog signal comprises the following steps: receiving the monitoring composite signal of the instrument landing system by the receiver front end; extracting a target frequency band in the monitoring composite signal according to an LC band pass filter in the receiver front end to obtain a target monitoring composite signal; carrying out attenuation processing on the target monitoring composite signal according to a preset numerical control attenuator value and a numerical control attenuator to obtain the attenuation processing analog signal.

3. The method of claim 2, wherein, The method for carrying out attenuation processing on the target monitoring composite signal according to the preset numerical control attenuator value and the numerical control attenuator to obtain the attenuation processing analog signal comprises the following steps: receiving the numerical control attenuator value sent by an upper computer; controlling the numerical control attenuator to generate an AD value corresponding to the numerical control attenuator value in real time according to the numerical control attenuator value; if the AD value meets a preset best sampling interval, carrying out attenuation processing on the target monitoring composite signal according to the numerical control attenuator value and the numerical control attenuator to obtain the attenuation processing analog signal.

4. The method of claim 1, wherein, The method for carrying out digital signal conversion on the attenuation processing analog signal by the ADC analog-digital conversion circuit to obtain the digital domain sampling signal comprises the following steps: obtaining an aliasing frequency according to a preset carrier frequency and a sampling frequency, wherein the sampling frequency is the number of sample points collected per second when the ADC analog-digital conversion circuit samples an analog signal; carrying out digital signal conversion on the attenuation processing analog signal according to the ADC analog-digital conversion circuit and the aliasing frequency to obtain an initial digital domain sampling signal; calculating a digital angular frequency according to the aliasing frequency and the sampling frequency; carrying out simplification processing on the initial digital domain sampling signal according to the digital angular frequency to obtain the digital domain sampling signal.

5. The method of claim 1, wherein, The method for carrying out two-stage DDC quadrature digital down conversion processing on the digital domain sampling signal to obtain the baseband signal, the 90Hz component and the 150Hz component comprises the following steps: carrying out down conversion processing on the digital domain sampling signal according to a preset first-stage DDC quadrature digital down conversion to generate a baseband signal, wherein the baseband signal comprises a direct current component and modulation information; obtaining the 90Hz component and the 150Hz component according to a preset second-stage DDC quadrature digital down conversion, two independent DDC channels and the baseband signal.

6. The method of claim 5, wherein, The first-stage DDC orthogonal digital down-conversion is performed on the digital domain sampling signal according to a preset first-stage DDC, and a baseband signal is generated. The first-stage I-path local oscillator signal and the digital domain sampling signal are multiplied to obtain a first-stage I-path component. The first-stage Q-path local oscillator signal and the digital domain sampling signal are multiplied to obtain a first-stage Q-path component. The first-stage I-path component and the first-stage Q-path component are subjected to IQ component synthesis to obtain the baseband signal. The second-stage DDC orthogonal digital down-conversion is performed on the baseband signal according to a preset second-stage DDC, two independent DDC channels, and the baseband signal, and a 90Hz component and a 150Hz component are generated.

7. The method of claim 5, wherein, The second-stage 90Hz I-path local oscillator signal and the baseband signal are multiplied to obtain a second-stage 90Hz I-path component. The second-stage 90Hz Q-path local oscillator signal and the baseband signal are multiplied to obtain a second-stage 90Hz Q-path component. The second-stage 90Hz I-path component and the second-stage 90Hz Q-path component are subjected to IQ component synthesis to obtain the 90Hz component. The second-stage 150Hz I-path local oscillator signal and the baseband signal are multiplied to obtain a second-stage 150Hz I-path component. The second-stage 150Hz Q-path local oscillator signal and the baseband signal are multiplied to obtain a second-stage 150Hz Q-path component. The second-stage 150Hz I-path component and the second-stage 150Hz Q-path component are subjected to IQ component synthesis to obtain the 150Hz component. The baseband signal, the 90Hz component, and the 150Hz component are subjected to decimation sampling to obtain a direct current component sequence, a 90Hz component sequence, and a 150Hz component sequence after synchronous decimation sampling, including: A decimation factor is calculated according to a preset sampling frequency and a target sampling frequency, wherein the target sampling frequency is a sampling frequency output after decimation sampling. The first-stage CIC decimation factor, the second-stage CIC decimation factor, and the third-stage FIR compensation filter decimation factor in the three-stage decimation filter are determined according to the decimation factor.

8. The method of claim 1, wherein, The first-stage CIC decimation is performed on the baseband signal according to the first-stage CIC decimation factor to obtain a decimated baseband signal. The FIR low-pass filter processing is performed on the decimated baseband signal to obtain a first direct current component. The second-stage CIC decimation is performed on the first direct current component according to the second-stage CIC decimation factor to obtain a second direct current component. The third-stage FIR compensation filter decimation is performed on the second direct current component according to the third-stage FIR compensation filter decimation factor to obtain a direct current component sequence corresponding to the baseband signal. ​ ​ ​ According to the first level CIC decimation factor, the second level CIC decimation factor and the third level FIR compensation filter decimation factor, the 90Hz component is sequentially decimated and sampled to obtain a 90Hz component sequence; According to the first level CIC decimation factor, the second level CIC decimation factor and the third level FIR compensation filter decimation factor, the 150Hz component is sequentially decimated and sampled to obtain a 150Hz component sequence.

9. The method of claim 1, wherein, According to the DC component sequence, the 90Hz component sequence and the 150Hz component sequence, a modulation degree difference DDM and a modulation degree sum SDM are obtained to realize updating of real-time digital monitoring data of a dual-frequency modulation signal, including: According to a preset sliding window, the DC component sequence, the 90Hz component sequence and the 150Hz component sequence are respectively slidingly averaged to obtain a DC amplitude average value corresponding to the DC component sequence, a 90Hz signal amplitude average value corresponding to the 90Hz component sequence and a 150Hz signal amplitude average value corresponding to the 150Hz component sequence; According to the DC amplitude average value, the 90Hz signal amplitude average value and the 150Hz signal amplitude average value, a 90Hz modulation degree and a 150Hz modulation degree are obtained by using a corresponding relationship between a modulation degree and an amplitude; According to the 90Hz modulation degree and the 150Hz modulation degree, a modulation degree difference DDM and a modulation degree sum SDM are obtained.

10. A real-time digital monitoring data processing apparatus for a dual frequency modulated signal, characterized by Including: An attenuation module configured to process a monitoring composite signal of an instrument landing system received by a receiver front end to obtain an attenuation-processed analog signal; A digital signal conversion module configured to perform digital signal conversion on the attenuation-processed analog signal by using an ADC (analog-to-digital conversion) circuit to obtain a digital domain sampling signal; A down-conversion module configured to perform two-stage DDC (digital down-conversion) orthogonal digital down-conversion processing on the digital domain sampling signal to obtain a baseband signal, a 90Hz component and a 150Hz component; An extraction sampling module configured to perform extraction sampling on the baseband signal, the 90Hz component and the 150Hz component to obtain a DC component sequence, a 90Hz component sequence and a 150Hz component sequence after synchronous down-sampling; A modulation degree module configured to obtain a modulation degree difference DDM and a modulation degree sum SDM from the DC component sequence, the 90Hz component sequence and the 150Hz component sequence to realize updating of real-time digital monitoring data of a dual-frequency modulation signal.

Images