Semiconductor device and manufacturing method thereof

Abstract

A semiconductor device is provided. The semiconductor device includes: a bit line extending in a first direction parallel to a substrate; a first channel pattern connected to the bit line and disposed perpendicular to the substrate; a gate insulating pattern disposed on the first channel pattern; a word line disposed on the gate insulating pattern and extending in a second direction parallel to the substrate and perpendicular to the first direction; data storage patterns spaced apart from each other in the first direction and the second direction; storage node contacts, each of which is disposed on a respective one of the data storage patterns; and a molding pattern extending in the second direction and configured to support the first channel pattern. The molding pattern includes a conductive sub-molding pattern.

Description

Cross Reference to Related Applications

[0001] This application claims the benefit of Korean Patent Application No. 10-2024-0073993, filed June 5, 2024, in the Korean Intellectual Property Office, the disclosure of which is incorporated herein in its entirety by reference for all purposes. TECHNICAL FIELD

[0002] Embodiments below relate to a semiconductor device and a method of manufacturing the same. BACKGROUND

[0003] Technologies of manufacturing semiconductor devices have been developed to improve integration density, operating speed, and yield of semiconductor devices. To improve integration density, operating speed, or current driving capability of a transistor, a semiconductor device including a vertical channel transistor (VCT) has been proposed.

[0004] In a semiconductor device including a vertical channel transistor (VCT), a contact portion connecting a channel pattern and a bit line BL can be formed. SUMMARY

[0005] One or more embodiments provide a semiconductor device having enhanced electrical characteristics and reliability.

[0006] According to an aspect, a semiconductor device includes a bit line extending in a first direction parallel to a substrate; a first channel pattern connected to the bit line and disposed perpendicular to the substrate; a gate insulating pattern disposed on the first channel pattern; a word line disposed on the gate insulating pattern and extending in a second direction parallel to the substrate and perpendicular to the first direction; data storage patterns spaced apart from each other in the first and second directions; a storage node contact portion disposed on each of the data storage patterns; and a molding pattern extending in the second direction and configured to support the first channel pattern. The molding pattern includes a conductive molding pattern.

[0007] According to another aspect, a method of manufacturing a semiconductor device includes preparing a storage node contact portion connected to a data storage pattern; forming a molding pattern longitudinally positioned in a first direction, the molding pattern including a conductive molding pattern; forming a first channel pattern on the molding pattern; forming a gate insulating layer on the molding pattern; partially removing a top surface of the first channel pattern and the gate insulating layer disposed on the molding pattern, thereby forming a gate insulating pattern; forming a word line on the gate insulating pattern, the word line extending in a second direction perpendicular to the first direction; forming a second insulating layer and a third insulating layer on the word line; performing planarization, thereby partially removing the second and third insulating layers and exposing the molding pattern and a top surface of the first channel pattern; and forming a bit line by depositing a conductive bit line layer on the first channel pattern.

[0008] According to another aspect, a semiconductor device includes a bit line extending in a first direction parallel to a substrate; a word line extending in a second direction perpendicular to the first direction; a storage node contact connected to the word line; a data storage pattern connected to a lower portion of the storage node contact; a mold pattern extending in the second direction, the mold pattern including a conductive mold pattern; a first channel pattern disposed on the mold pattern; and a gate insulating pattern disposed on the first channel pattern. The bit line is formed of a conductive bit line layer disposed in the first direction.

[0009] Additional aspects of the embodiments will be set forth in part in the description that follows, and in part will be apparent from the description. Other aspects of the present disclosure will be realized and attained by means of the embodiments described in the following description. BRIEF DESCRIPTION OF DRAWINGS

[0010] These and / or other aspects, features, and advantages of the application will become apparent and more readily appreciated from the following description, taken in conjunction with the accompanying drawings, in which:

[0011] Figure 1 is a diagram schematically illustrating a semiconductor device according to an embodiment;

[0012] Figure 2 is a diagram schematically illustrating Figure 1 a perspective view of a memory cell array of the semiconductor device of

[0013] Figure 3 is a cross-sectional view illustrating an example of a semiconductor device according to an embodiment;

[0014] Figures 4-10 , Figure 11A , Figure 11B and Figure 11C are diagrams for describing a method of manufacturing a semiconductor device of Figure 3 ;

[0015] Figure 12 is a cross-sectional view illustrating another example of a semiconductor device according to an embodiment;

[0016] Figure 13 and Figure 14 are diagrams for describing a method of manufacturing a semiconductor device of Figure 12 ;

[0017] Figure 15 is a cross-sectional view illustrating another example of a semiconductor device according to an embodiment;

[0018] Figures 16-20 is a diagram for describing a method of manufacturing a semiconductor device of Figure 15 ;

[0019] Figure 21 is a cross-sectional view showing another example of a semiconductor device according to an embodiment; and

[0020] Figures 22-25 is a diagram for describing a method of manufacturing Figure 21 a semiconductor device. DETAILED DESCRIPTION

[0021] Hereinafter, embodiments will be described in detail with reference to the accompanying drawings. When the embodiments are described with reference to the drawings, like reference numerals refer to like components, and repetitive description thereof can be omitted.

[0022] Figure 1 is a diagram schematically showing a semiconductor device according to an embodiment.

[0023] Figure 1 The semiconductor device 100 can include a memory cell array 1, a row decoder 2, a sense amplifier 3, a column decoder 4, and control logic 5. For example, the semiconductor device 100 can be a semiconductor memory device, and can be implemented as a dynamic random access memory (DRAM) device.

[0024] The memory cell array 1 can include a plurality of memory cells MC arranged two-dimensionally or three-dimensionally. For example, the memory cell array 1 can be provided on one surface of a substrate, and a plane of the memory cell array 1 can be parallel to a plane of the substrate. Each of the memory cells MC can be connected to a word line WL and a bit line BL that intersect each other.

[0025] Each of the memory cells MC can include a selection element TR and a data storage element DS. The selection element TR and the data storage element DS can be electrically connected to each other. The selection element TR can be connected to both the word line WL and the bit line BL. For example, the selection element TR can be provided at a position where the word line WL and the bit line BL intersect each other. The selection element TR can be or include, for example, a field effect transistor (FET).

[0026] The data storage element DS can be or include, for example, a capacitor, a magnetic tunnel junction pattern, or a variable resistor. For example, the data storage element DS can be any type of capacitor (e.g., a ferroelectric capacitor) used in a single transistor single capacitor (1T1C) memory cell, which is a memory that includes one capacitor and one transistor. For example, the data storage element DS can be any type of resistor, including an MTJ (magnetic tunnel junction), a ferroelectric tunnel junction (FTJ), and combinations thereof, used in a single transistor single resistor (1T1R) memory cell, which is a memory that includes one resistor and one transistor. For example, the data storage element DS can be selected from the group consisting of the following data storage structures (patterns): phase change memory (PCM, PRAM, PCRAM, PC-RAM), resistive memory (RRAM), magnetoresistive memory (MRAM), polymer memory (PRAM), molecular memory, ferroelectric memory (FeRAM), ion memory (PMC), memristor memory, spin memory, oxide memory (e.g., ReRAM and OxRAM), conductive bridge random access memory (CBRAM), and combinations thereof.

[0027] For example, the selection element TR can be a transistor, a gate electrode of the transistor can be connected to the word line WL, and a source terminal or a drain terminal of the transistor can be connected to the bit line BL or the data storage element DS. Examples of structures including the word line WL, the bit line BL, the selection element TR, and the data storage element DS of each memory cell MC in the memory cell array 1 will be described below with reference to Figure 2 Examples of structures including the word line WL, the bit line BL, the selection element TR, and the data storage element DS of each memory cell MC in the memory cell array 1 will be described below with reference to

[0028] Figure 2 is a perspective view schematically showing Figure 1 the memory cell array 1 of the semiconductor device 100.

[0029] Referring to Figure 2 , the semiconductor device 100 can include a data storage pattern DSP, a storage node contact BC, word lines WL1 and WL2, and a bit line BL. The bit line BL can extend in a first direction (e.g., a Y-axis direction). The word lines WL1 and WL2 can be provided on the storage node contact BC. The word lines WL1 and WL2 can extend in a second direction (e.g., an X-axis direction) that is perpendicular to the first direction. The first direction and the second direction can be parallel to a plane corresponding to a substrate (not shown in the drawings) or the memory cell array 1. For example, the substrate can have a plate shape that extends along the plane defined by the first direction and the second direction. In an embodiment, a molding structure and a channel pattern can be formed on or over the storage node contact BC.

[0030] Referring to Figure 1 and Figure 2The selection element TR of each of the memory cells MC can be or include a vertical channel transistor (VCT). A longitudinal direction of a channel of the vertical channel transistor (VCT) can be perpendicular to one surface (e.g., a top surface) of the substrate. The data storage element DS of each of the memory cells MC can include or can be a data storage pattern DSP. Details will be described below with reference to Figure 3 Examples of the memory cell MC including a vertical channel transistor (VCT) are described.

[0031] The row decoder 2 can decode an address input from an external circuit or device (e.g., a host device or a memory controller located outside the semiconductor device 100). The row decoder 2 can select one of the word lines WL of the memory cell array 1 based on a result obtained by decoding the address. The result (e.g., the decoded address) obtained by decoding the address in the row decoder 2 can be provided to a row driver (not shown). The row driver can provide a predetermined voltage to the selected word line WL and the unselected word line, respectively, in response to a control of the control circuit.

[0032] The sense amplifier 3 can sense, amplify, and output a voltage difference between the reference bit line and the bit line BL selected based on the address decoded by the column decoder 4.

[0033] The column decoder 4 can provide a data transmission path between the sense amplifier 3 and an external circuit or device (e.g., a memory controller). The column decoder 4 can decode an externally input address to select one of the bit lines BL.

[0034] The control logic 5 can generate a control signal for controlling an operation of writing data to or reading data from a corresponding memory cell in the memory cell array 1.

[0035] For reference, the row decoder 2, the sense amplifier 3, the column decoder 4, and the control logic 5 are shown as being located around the memory cell array 1, however, the present application is not limited thereto. For example, a peripheral circuit including the row decoder 2, the sense amplifier 3, the column decoder 4, and the control logic 5 can be disposed on a plane different from a plane on which the memory cell array 1 is disposed. The peripheral circuit can be disposed above or below the memory cell array 1 such that, for example, the semiconductor device has a coplanar over cell (COP) structure (or scheme). In an example, although not shown in the drawing, the peripheral circuit can be disposed on a substrate, and the memory cell array 1 can be disposed on the peripheral circuit. In another example, the peripheral circuit can be disposed on a first substrate, and the memory cell array 1 can be disposed on a second substrate. In this example, the first substrate and the second substrate can be placed facing each other.

[0036] In Figure 2In the middle, line A-A' is a line in the direction of the bit line BL along the region including the storage node contact BC (e.g., the Y-axis direction), and line B-B' is a line in the direction not including the region of the storage node contact BC. Further, line C-C' is a line in the direction of the word line WL to indicate the region including the molded structure 130 not including the word line WL. The molded structure 130 can extend along the second direction (e.g., the X-axis direction).

[0037] For example, in Figure 2 In the middle, line A-A' is a line in the direction of the bit line BL along the region including the storage node contact BC (e.g., the Y-axis direction), and line B-B' is a line in the direction not including the region of the storage node contact BC. Further, line C-C' is a line in the direction of the word line WL to indicate the region including the molded structure 130 not including the word line WL. The molded structure 130 can extend along the second direction (e.g., the X-axis direction).

[0038] Figure 2 is a perspective view schematically showing Figure 1 the storage unit array 1 of FIG. 1, and shows a state in which the substrate in which the storage node contact BC and the data storage pattern DSP are connected is vertically flipped. To increase the integration density and performance of the semiconductor device, the semiconductor device can be manufactured by a back-end-of-line (BEOL) process of manufacturing the substrate, flipping the substrate, and forming the unit array on the storage node contact BC. For example, the substrate can include a conductive wiring layer and / or pattern to which the storage node contact BC and the data storage pattern DSP can be electrically connected.

[0039] In some embodiments, the storage unit array 1 can include the storage node contact BC and the data storage pattern DSP connected to each other. To increase the integration density and performance of the semiconductor device, a wiring layer and / or wiring pattern can be formed using a back-end-of-line (BEOL) process. Subsequently, the storage unit array 1 can be formed on the wiring layer and / or wiring pattern. In this case, the resulting structure obtained by the BEOL process can be flipped before the storage unit array 1 is formed. The resulting structure obtained by the BEOL process can be disposed on a peripheral circuit provided on the substrate, and the storage unit array 1 can be disposed on the peripheral circuit.

[0040] Referring to Figure 2The semiconductor device 100 can include a data storage pattern DSP, a storage node contact BC, word lines WL1 and WL2, and a bit line BL. The bit line BL can extend in a first direction (e.g., a Y-axis direction). The word lines WL1 and WL2 can be disposed on the storage node contact BC. The word lines WL1 and WL2 can extend in a second direction (e.g., an X-axis direction) perpendicular to the first direction. The first direction and the second direction can be parallel to a plane corresponding to the substrate or the storage cell array 1. For example, the substrate can have a plate shape extending along the plane defined by the first direction and the second direction. In an embodiment, a molding structure and a trench pattern can be formed on or above the storage node contact BC.

[0041] Hereinafter, the semiconductor device 100 according to an embodiment will be mainly described with reference to Figures 3-25 The semiconductor device 100 according to an embodiment will be described in detail, Figures 3-25 is a cross-sectional view illustrating a portion of the semiconductor device 1 shown in Figure 2 is a cross-sectional view illustrating a portion of the semiconductor device 1 shown in

[0042] Figure 3 is a cross-sectional view illustrating an example of a semiconductor device according to an embodiment. Figure 3 illustrates a cross-section obtained by cutting the storage cells of the semiconductor device in a direction perpendicular to the substrate along a line A-A' of Figure 2

[0043] The X-Y plane, the Y-Z plane, and the X-Z plane are formed by the intersection region of one pair of the X-axis, the Y-axis, and the Z-axis in a three-dimensional space. For example, the X-Y plane is the intersection region of the X-axis and the Y-axis, the Y-Z plane is formed by the intersection region of the Y-axis and the Z-axis, and the X-Z plane is formed by the intersection region of the X-axis and the Z-axis.

[0044] In some embodiments, the semiconductor device 100 can include a data storage pattern DSP, a storage node contact BC, a lower insulating layer 110, a first insulating layer 120, a second insulating layer 160, a third insulating layer 170, a molding structure 130, a first trench pattern 140, a gate insulating pattern 150, a second metal layer 190 (BL), and word lines WL1.

[0045] ​The data storage pattern DSP can be disposed on one side (e.g., a lower portion) of the storage node contact BC. The data storage pattern DSP can be electrically connected to the first channel pattern 140 through the storage node contact BC. The data storage pattern DSP can be spaced apart from each other in the first direction and the second direction. The data storage pattern DSP can be arranged in a matrix form (or in a repetitive or regular arrangement), and can be completely overlapped with or partially overlapped with the storage node contact BC in one direction (e.g., a Z-axis direction).

[0046] The data storage pattern DSP can be a capacitor. Although not shown in the drawing, the data storage pattern DSP can include a storage electrode, a plate electrode, and a capacitor dielectric film interposed between the storage electrode and the plate electrode. Here, the storage electrode can be in contact with the storage node contact BC. The storage electrode can have various shapes, such as a circular shape, an elliptical shape, a rectangular shape, a square shape, a diamond shape, or a hexagonal shape.

[0047] The lower insulating layer 110 can be disposed between the data storage patterns DSP. For example, when viewed in a direction perpendicular to the substrate, the lower insulating layer 110 can be disposed in an area defined by the data storage pattern DSP. For example, when viewed from the second metal layer 190 (BL), the data storage pattern DSP can be arranged in a specific pattern. In a plan view (cut along the X-Y plane), the arrangement of the data storage pattern DSP can be in a repetitive or regular form in which the lower insulating layer 110 fills the remaining area.

[0048] The storage node contact BC can be disposed on the data storage pattern DSP. The storage node contact BC can be disposed between the first insulating layer 120. The storage node contact BC can have various shapes, such as a circular shape, an elliptical shape, a rectangular shape, a square shape, a diamond shape, a hexagonal shape, or a polygonal shape having a predetermined thickness. When viewed in a direction perpendicular to the substrate (e.g., a Z-axis direction), the first insulating layer 120 can be disposed in an area defined by the storage node contact BC. For example, when viewed from the second metal layer 190 (BL), the storage node contact BC can be arranged in a specific pattern. In a plan view (e.g., when cut along the X-Y plane), the arrangement of the storage node contact BC can be in the form of a specific pattern within the entire space in which the first insulating layer 120 fills the remaining area.

[0049] The storage node contact BC can include a conductive material. The conductive material can include at least one of, for example, doped polysilicon, a conductive metal nitride, a conductive metal silicon nitride, a metal carbonitride, a conductive metal silicide, a conductive metal oxide, a two-dimensional (2D) material, a metal, or a metal alloy. In some embodiments, although not shown in the drawing, each bonding pad can be disposed on a corresponding one of the storage node contacts BC.

[0050] The first insulating layer 120 can be disposed between the storage node contacts BC. In some embodiments, although not shown in the figures, the first insulating layer 120 can be disposed in an inner region of the storage node contacts BC when viewed in a direction perpendicular to the substrate (e.g., the Z-axis direction). For example, when the storage node contacts BC are formed in a cylindrical or ring shape (e.g., a donut shape), the first insulating layer 120 can be disposed in an inner region of the cylindrical or ring-shaped storage node contacts BC (e.g., the center point of the donut shape). In some embodiments, although not shown in the figures, the first insulating layer 120 can also be disposed between the storage node contacts BC and the landing pads. The first insulating layer 120 can include an insulating material.

[0051] The first channel pattern 140 can be connected to the bit line BL and disposed perpendicular to the substrate. The first channel pattern 140 can be disposed perpendicular to the bit line BL. For example, the first channel pattern 140 can extend in a third direction (e.g., the Z-axis direction) and can be electrically connected to the storage node contacts BC. The first channel pattern 140 can be disposed on a side surface of the molded structure 130.

[0052] The gate insulating pattern 150 can be disposed on the first channel pattern 140. The gate insulating pattern 150 can include an insulating material.

[0053] The word line WL1 can be disposed on the gate insulating pattern 150 and can extend in a second direction (e.g., the X-axis direction).

[0054] According to an embodiment, an upper end portion of the word line WL1 can be disposed at a higher level than a lower end portion of the first metal layer 134.

[0055] The second insulating layer 160 can be disposed on the word line WL1 and an outer side surface of the gate insulating pattern 150, and can be formed of silicon nitride.

[0056] The third insulating layer 170 can be included in a space surrounded by the second insulating layer 160. For example, the third insulating layer 170 can be disposed between two adjacent molded structures 130, and can be formed of silicon oxide.

[0057] The molding structure 130 can protrude in a third direction (e.g., a Z-axis direction) perpendicular to one surface (e.g., a top surface) of the first insulating layer 120. For example, the molding structure 130 can extend from the top surface of the first insulating layer 120 in the third direction (e.g., the Z-axis direction). The molding structure 130 can be positioned longitudinally in the third direction. The third direction can be perpendicular to the first direction and the second direction. The molding structure 130 can be disposed on the first insulating layer 120. For example, the molding structure 130 can be disposed on at least a portion of an area between the storage node contact portions BC. The molding structure 130 can extend in the second direction (e.g., the X-axis direction) and mechanically support the first channel pattern 140.

[0058] The molding structure 130 can be a molding pattern including a first silicon nitride pattern 131, a silicon oxide pattern 132, a second silicon nitride pattern 133, and a first metal layer 134. The silicon oxide pattern 132 can be disposed between the first silicon nitride pattern 131 and the second silicon nitride pattern 133, and the first metal layer 134 can be disposed on the second silicon nitride pattern 133 to form the molding structure 130. For example, the first silicon nitride pattern 131, the silicon oxide pattern 132, the second silicon nitride pattern 133, and the first metal layer 134 can be sequentially disposed from a lower end portion of the molding structure 130. The lower end portion of the first metal layer 134 can be disposed at a lower level than an upper end portion of the word line WL1. For reference, a plurality of molding structures 130 can be arranged in the first direction (e.g., the Y-axis direction). For example, as shown in FIG. 1B, the plurality of molding structures 130 can be spaced apart from each other in the first direction (e.g., the Y-axis direction). Figure 11A

[0059] The first metal layer 134 can be disposed within the molding structure 130. For example, the first metal layer 134 can be a portion of the molding structure 130. The first metal layer 134 can be in contact with the first channel pattern 140. For example, the first metal layer 134 can be in contact with a side surface of the first channel pattern 140. The side surface of the first channel pattern 140 can be parallel to an X-Z plane. The first metal layer 134 can be an electrically conductive molding pattern. The electrically conductive molding pattern 134 can be formed of or include doped polysilicon, metal, electrically conductive metal nitride, electrically conductive metal silicide, electrically conductive metal oxide, or a combination thereof. The electrically conductive molding pattern 134 can be formed of or include doped polysilicon, Al, Cu, Ti, Ta, Ru, W, Mo, Pt, Ni, Co, TiN, TaN, WN, NbN, TiAl, TiAlN, TiSi, TiSiN, TaSi, TaSiN, RuTiN, NiSi, CoSi, IrOx, RuOx, or a combination thereof, but the present application is not limited thereto.

[0060] ​The second metal layer 190 can be disposed on the first metal layer 134, the first channel pattern 140, and the third insulating layer 170. The second metal layer 190 can be a bit line BL. The second metal layer 190 can extend in a first direction parallel to the substrate. The second metal layer 190 can be a conductive bit line layer including or formed of doped polysilicon, metal, conductive metal nitride, conductive metal silicide, conductive metal oxide, or a combination thereof, but the present application is not limited thereto.

[0061] According to an embodiment, the first channel pattern 140 can have a plurality of surfaces, the first metal layer 134 can be in contact with a first surface of the plurality of surfaces, and the second metal layer 190 can be in contact with a second surface of the plurality of surfaces different from the first surface.

[0062] According to an embodiment, the first metal layer 134 and the second metal layer 190 can include the same type or different type of conductive material as each other. For example, the bit line BL can be formed of the second metal layer 190. According to an embodiment, the conductive molding pattern 134 and the bit line 190 can include or be formed of the same conductive material or the same combination of conductive materials as each other. According to another embodiment, the conductive molding pattern 134 and the bit line 190 can include or be formed of different conductive materials or different combinations of conductive materials as each other.

[0063] Each of the first channel patterns 140 and a corresponding one of the conductive molding patterns can be in contact with each other at a contact area, and a height CH of the contact area in a Z-axis direction can exceed a thickness of the first channel pattern 140 in a Y direction.

[0064] According to an embodiment, the bit line BL can be formed of the second metal layer 190 disposed on the first channel pattern 140. For example, the second metal layer 190 can be the bit line BL formed on the first metal layer 134.

[0065] The bit line BL can extend in a first direction parallel to the substrate. The bit line BL can be formed on the first channel pattern 140 in a direction (e.g., the first direction) orthogonal to the word line WL1. For example, the bit line BL can extend across the word line WL.

[0066] Hereinafter, Figures 4-12 is used to describe manufacturing Figure 3FIG. 1 is a diagram of a method of forming a semiconductor device.

[0067] Referring to Figure 4 The storage node contacts BC can be provided with a first insulating layer 120, and the data storage pattern DSP can be provided with an under insulating layer 110.

[0068] For example, the storage node contacts BC and the first insulating layer 120 can be formed such that the first insulating layer 120 is disposed between the storage node contacts BC. The data storage pattern DSP can be formed such that each of the storage node contacts BC is connected to a respective one of the data storage pattern DSP. The under insulating layer 110 can be formed such that it is disposed between the data storage pattern DSP.

[0069] In some embodiments, although not shown in the figures, after the data storage pattern DSP is formed, a wiring layer and / or a wiring pattern can be formed by using a back end of line (BEOL) process on the data storage pattern DSP. Subsequently, the resulting structure, which includes the storage node contacts BC, the data storage pattern DSP, the first insulating layer 120, and the under insulating layer 110, can be flipped such that the storage node contacts BC face upwards. The storage node contacts BC and the first insulating layer 120 can be coated with an insulating film IF.

[0070] Referring to Figure 5The top surface of the first insulating layer 120 can be exposed by an etching process by which the insulating film IF is at least partially removed. The molding structures 130 can be formed in a direction perpendicular to the exposed one surface (e.g., the top surface) of the first insulating layer 120. For example, in a cross-sectional view along the Y-Z plane, the molding patterns 130 can be formed on the first insulating layer 120 such that the height (in the Z-axis direction) of each of the molding patterns 130 is greater than its width (in the X-axis direction), thereby forming a rectangular shape. The molding structures 130 can include an insulating layer formed by a chemical vapor deposition (CVD) process. Each of the molding structures 130 can be a plurality of stacked patterns including a first silicon nitride pattern 131, a silicon oxide pattern 132, a second silicon nitride pattern 133, and a first metal layer 134. The first silicon nitride pattern 131 and the second silicon nitride pattern 133 can be formed of at least one of silicon carbon nitride (SiCN), silicon carbon oxygen nitride (SiCON), or silicon nitride (SiN). The silicon oxide pattern 132 can include (or be formed of) one of hafnium oxide (HfO), aluminum oxide (AlO), and tantalum oxide (TaO). In some embodiments, the first metal layer 134 can be a conductive molding pattern formed of doped polysilicon, Al, Cu, Ti, Ta, Ru, W, Mo, Pt, Ni, Co, TiN, TaN, WN, NbN, TiAl, TiAlN, TiSi, TiSiN, TaSi, TaSiN, RuTiN, NiSi, CoSi, IrOx, RuOx, or a combination thereof.

[0071] Referring to Figure 6 The first channel layer 140 and the gate insulating layer 150 can be formed by a physical vapor deposition (PVD) process, a CVD process, or an atomic layer deposition (ALD) process. The first channel layer 140 can be formed on the molding structures 130, the first insulating layer 120, and the storage node contacts BC between the molding structures 130. The gate insulating layer 150 can be formed on the first channel layer 140. For example, the first channel layer 140 and the gate insulating layer 150 can be sequentially formed on the molding structures 130.

[0072] Referring to Figure 7 An etch-back process can be performed on the upper surface of the first channel layer 140, thereby forming a first channel pattern. An etch-back process can be performed on the top surface of the gate insulating layer 150 between the molding structures 130, thereby partially removing the same.

[0073] Referring to Figure 8The removed portions of the gate insulating layer 150 can be re-deposited, and word lines WL can be formed on the gate insulating layer 150. The first metal layer 134 can be included in the molded structure 130 such that a position level (height) of the molded structure 130 is increased, and accordingly, a position level (height) of the word lines WL can also be increased. The word lines WL can include or be formed of a conductive material. In some embodiments, the word lines WL can include an insulating material. The word lines WL can be chamfered by a wet etching process.

[0074] Referring to Figure 9 A second insulating layer 160 can be deposited on the word lines WL, and a third insulating layer 170 can be formed on the second insulating layer 160. The second insulating layer 160 can be formed of silicon nitride, and the third insulating layer 170 can be formed of silicon oxide. Upon (or before) formation of the second insulating layer 160 and the third insulating layer 170, an entire top surface can be planarized by a chemical mechanical polishing (CMP) process, and a top surface of each of the molded structures 130 can be exposed, thereby forming a gate insulating pattern 150 and a first channel pattern 140.

[0075] Referring to Figure 10 An etch-back process can expose an upper portion of the first channel pattern 140, the second insulating layer 160, and the third insulating layer 170, and / or an oxide deposition process and a CMP process can be performed. Accordingly, the second insulating layer 160 can be divided into a plurality of segments. During the etch-back process, an upper portion of the first channel pattern 140, the gate insulating pattern 150, the second insulating layer 160, the third insulating layer 170, and the first metal layer 134 can be partially removed.

[0076] Referring to Figure 11A , Figure 11B and Figure 11C A second metal layer 190 can be deposited on the first channel pattern 140. The second metal layer 190 can be a bit line BL. The bit line 190 (BL) can be formed of or include the same or different conductive material as the conductive molded pattern 134.

[0077] Figure 11B is a diagram illustrating a portion of a cross-section taken along a line B-B' of Figure 2 An upper end portion of the word line WL can be disposed at a higher level than a lower end portion of the second silicon nitride pattern 133.

[0078] Figure 11C is a diagram illustrating a portion of a cross-section taken along a line B-B' of Figure 2is a view of a portion of a cross section taken by a line C-C' of the semiconductor device 100. The first metal layer 134 and the second metal layer 190 can be disposed to protrude more upward than the second silicon nitride pattern 133. For example, the first metal layer 134 and the second metal layer 190 can be located at a higher position than the second silicon nitride pattern 133.

[0079] Figure 12 is a cross-sectional view illustrating another example of a semiconductor device according to an embodiment. Figure 12 illustrates a cross section obtained by cutting the memory cell of the semiconductor device 100 along a line A-A' in a direction perpendicular to the substrate (e.g., a cross section corresponding to the Y-Z plane). Figure 2

[0080] The semiconductor device 100 can include a data storage pattern DSP, a storage node contact BC, a first insulating layer 120, a second insulating layer 160, a third insulating layer 170, a molding structure 130, a first channel pattern 140, a gate insulating pattern 150, a first metal layer 134, a second metal layer 190, a word line WL1, a bit line BL, and a second channel pattern 180.

[0081] The second channel pattern 180 can extend from one end of the first channel pattern 140 in a first direction.

[0082] According to an embodiment, the first channel pattern 140 and the second channel pattern 180 can include a same type or different types of semiconductor oxide as each other. The semiconductor oxide can include or be any one or any combination of IGZO, InxO, ZnxO, SnxO, InxZnyO, InxSnyZnzO, AlxZnySnzO, YbxGayZnzO, HfxInyZnzO, but the present application is not limited thereto. For example, the first channel pattern 140 can be formed of indium gallium zinc oxide (IGZO), and the second channel pattern 180 can be formed of indium tin oxide (ITO). The semiconductor oxide can include a high proportion of some elements. For example, the IGZO can be a gallium (Ga)-rich IGZO, and at least one of the first channel pattern 140 or the second channel pattern 180 can include the Ga-rich IGZO.

[0083] According to an embodiment, the first metal layer 134 and the second metal layer 190 can include a same type or different types of conductive material as each other.

[0084] According to an embodiment, the bit line BL can be formed of the second metal layer 190. For example, the second metal layer 190 can include or be formed of a conductive material, and can be formed on the first metal layer 134.

[0085] Hereinafter, Figure 13 and Figure 14 are used to describe manufacturing​Figure 12 A diagram illustrating the method for developing semiconductor devices.

[0086] Reference Figures 4-9 The provided description can also be applied to manufacturing. Figure 12 Methods for semiconductor devices. For example, they can be performed in accordance with reference to Figures 4-9 The process steps described are the same as the process steps.

[0087] Subsequently, referring to Figure 13 The upper portions of the first channel pattern 140, the second insulating layer 160, and the third insulating layer 170 can be exposed via an etch-back process, and / or an oxide deposition process and a CMP process can be performed. Therefore, the second insulating layer 160 can be divided into multiple segments. During the etch-back process, the upper portions of the first channel pattern 140, the gate insulating pattern 150, the second insulating layer 160, the third insulating layer 170, and the first metal layer 134 can be partially removed. The second channel layer 180 can be deposited on the surface exposed by the etch-back process. A portion of the second channel layer 180 located on the top surface of the first metal layer 134 can be removed by cutting (removing) to form the second channel pattern. The upper portion of the second channel pattern 180 can protrude upwards beyond the first metal layer 134. (See reference...) Figure 14 A second metal layer 190 may be formed (or deposited) on the first channel pattern 140. The second metal layer 190 may be a bit line BL. The bit line 190 (BL) may be formed of or include a conductive material that is the same as or different from the conductive electron molding pattern 134. The second channel pattern 180 may extend from one end of the first channel pattern 140 along a first direction.

[0088] According to an embodiment, the first channel pattern 140 and the second channel pattern 180 may include semiconductor oxides of the same or different types.

[0089] Figure 15 This is a cross-sectional view showing another example of a semiconductor device according to an embodiment. Figure 15 It shows along Figure 2 The line A-A' is the cross section obtained by cutting the memory cell of the semiconductor device in a direction perpendicular to the substrate (e.g., the cross section corresponding to the YZ plane).

[0090] The semiconductor device 100 may include a data storage pattern DSP, a memory node contact BC, a first insulating layer 120, a second insulating layer 160, a third insulating layer 170, a molded structure 130, a first channel pattern 140, a gate insulating pattern 150, a first metal layer 134, a second metal layer 190, a word line WL1, a bit line BL, and an oxide layer Ox.

[0091] The oxide layer Ox can include or be formed of an oxide of at least one selected from nickel (Ni), titanium (Ti), vanadium (V), iron (Fe), chromium (Cr), cobalt (Co), hafnium (Hf), and tantalum (Ta). For example, the oxide layer Ox can include or be formed of titanium oxide (TiO). The oxide layer Ox can be disposed directly on the lower end portion of the word line WL, and can be in contact with one side surface of each of the gate insulating pattern 150 and the second insulating layer 160. The oxide layer Ox can be included in a space between the lower end portion of the word line WL and the storage node contact portion BC to complement reliability of the semiconductor device.

[0092] It will be understood that when an element is referred to as being "connected" or "coupled" to another element, it can be directly connected or coupled to the other element or indirectly connected or coupled to the other element through intervening elements. In contrast, when an element is referred to as being "directly connected" or "directly coupled" to another element, there are no intervening elements.

[0093] According to an embodiment, the second channel pattern 180 can extend in a first direction from one end of the first channel pattern 140.

[0094] According to an embodiment, the first channel pattern 140 and the second channel pattern 180 can include semiconductor oxides of the same type or different types from each other. The semiconductor oxides can include or be any one or any combination of IGZO, InxO, ZnxO, SnxO, InxZnyO, InxSnyZnzO, AlxZnySnzO, YbxGayZnzO, HfxInyZnzO, but the present application is not limited thereto. For example, the first channel pattern 140 can be formed of IGZO, and the second channel pattern 180 can be formed of ITO. The semiconductor oxides can include a high proportion of some elements (a high concentration of certain elements). For example, the IGZO can be Ga-rich IGZO, and at least one of the first channel pattern 140 or the second channel pattern 180 can include Ga-rich IGZO.

[0095] Hereinafter, Figures 16-20 is a diagram for describing a method of manufacturing Figure 15 a semiconductor device.

[0096] The description provided with reference to Figures 4-7 may be equally applicable to a method of manufacturing Figure 15 a semiconductor device. For example, the same or similar operations can be performed as described with reference toFigures 4-7 The described process steps are the same process steps.

[0097] Referring to Figure 16 The removed portion of the gate insulating layer 150 can be re-deposited, and an oxide layer Ox can be formed between the gate insulating layer 150 and the molding structure 130. The oxide layer Ox can include or be formed of an oxide of at least one selected from nickel (Ni), titanium (Ti), vanadium (V), iron (Fe), chromium (Cr), cobalt (Co), hafnium (Hf), and tantalum (Ta), and can be formed through an ALD process.

[0098] Referring to Figure 17 A word line WL can be formed on the oxide layer Ox. The word line WL can include a conductive material. The word lines WL1 and WL2 can be chamfered through a wet etching process. The oxide layer Ox can be located at a lower end portion of the word line WL.

[0099] Referring to Figure 18 A second insulating layer 160 can be deposited on the word line WL, and a third insulating layer 170 can be formed on the second insulating layer 160. The second insulating layer 160 can be formed of silicon nitride, and the third insulating layer 170 can be formed of silicon oxide. Upon (or before) forming the second insulating layer 160 and the third insulating layer 170, the entire top surface can be planarized through a CMP process, and a top surface of each of the molding structures 130 can be exposed, thereby forming a gate insulating pattern 150 and a first channel pattern 140.

[0100] Referring to Figure 19 An upper portion of the first channel pattern 140, the second insulating layer 160, and the third insulating layer 170 can be exposed through an etch-back process, and / or an oxide deposition process and a CMP process can be performed. Accordingly, the second insulating layer 160 can be divided into a plurality of segments.

[0101] Referring to Figure 20 A second metal layer 190 can be deposited on the first channel pattern 140. The second metal layer 190 can be a bit line BL. The bit line 190 (BL) can be formed of or include the same or different conductive material as the conductive molding pattern 134.

[0102] Figure 20 The area 300 represents a structure in which the oxide layer Ox is deposited at a lower end portion of the word line WL.

[0103] Figure 21 is a cross-sectional view illustrating another example of a semiconductor device according to an embodiment.Figure 21 A cross-section of a memory cell of the semiconductor device is shown, obtained by cutting along the line A-A' of Figure 2 FIG. 1A in a direction perpendicular to the substrate (e.g., a cross-section corresponding to the Y-Z plane).

[0104] Referring to Figure 21 , a lower end portion of the first metal layer 134 can be disposed at a higher level than an upper end portion of the word line WL1. The position level of the upper end portion of the word line WL1 can be lower than the level of the lower end portion of the first metal layer 134, and accordingly, the bit line BL and the word line WL1 can form an underlap structure. According to an aspect of the present application, time dependent dielectric breakdown (TDDB) (which can occur when a high voltage is continuously applied during operation of the semiconductor device) can be reduced by the underlap structure (e.g., by lowering the position level of the word line WL1).

[0105] According to an embodiment, the second channel pattern 180 can extend from one end of the first channel pattern 140 in a first direction.

[0106] According to an embodiment, the first channel pattern 140 and the second channel pattern 180 can include semiconductor oxides of the same type or different types from each other. The semiconductor oxides can include or be formed of any one or any combination of IGZO, InxO, ZnxO, SnxO, InxZnyO, InxSnyZnzO, AlxZnySnzO, YbxGayZnzO, HfxInyZnzO, but the present application is not limited thereto. For example, the first channel pattern 140 can be formed of IGZO, and the second channel pattern 180 can be formed of ITO. The semiconductor oxides can include a high proportion of some elements. For example, the IGZO can be Ga-rich IGZO, and at least one of the first channel pattern 140 or the second channel pattern 180 can include Ga-rich IGZO.

[0107] According to an embodiment, the first channel pattern 140 can have a plurality of surfaces, the first metal layer 134 can be in contact with a first surface of the plurality of surfaces, and the second metal layer 190 can be in contact with a second surface of the plurality of surfaces different from the first surface.

[0108] According to an embodiment, the first metal layer 134 and the second metal layer 190 can include conductive materials of the same type or different types from each other.

[0109] The contact area between each of the first metal layer 134 and the second metal layer 190 and the first channel pattern 140 can exceed the thickness of the first channel pattern 140. Each of the first channel pattern 140 and a corresponding one of the conductive molding patterns can be in contact with each other at the contact area, and the height of the contact area in the Z-axis direction can exceed the thickness of the first channel pattern 140 in the Y direction.

[0110] According to embodiments, the bit line BL can be formed of the second metal layer 190. For example, the second metal layer 190 can include or be formed of a conductive material, and can be formed on the first metal layer 134.

[0111] According to embodiments, an oxide layer can be further provided on the lower end portion of the word line WL1.

[0112] In the following, Figures 22-25 is a diagram for describing a method of manufacturing Figure 21 a semiconductor device.

[0113] The description provided with reference to Figures 4-7 may equally apply to a method of manufacturing Figure 21 a semiconductor device. For example, the same process steps as described with reference to Figures 4-7 may be performed.

[0114] With reference to Figure 22 , the removed portions of the gate insulating layer 150 can be re-deposited, and the word lines WL can be formed on the gate insulating pattern 150. The word lines WL can include or be formed of a conductive material. In some embodiments, the word lines WL can include an insulating material. The word lines WL can be chamfered by a wet etching process. The word lines WL can be formed by the chamfering process such that the position of the word lines WL is horizontally lowered.

[0115] With reference to Figure 23 , a second insulating layer 160 can be deposited on the word lines WL, and a third insulating layer 170 can be formed on the second insulating layer 160. The second insulating layer 160 can be formed of silicon nitride, and the third insulating layer 170 can be formed of silicon oxide. Upon (or before) forming the second insulating layer 160 and the third insulating layer 170, the entire top surface can be planarized by a CMP process, and the top surface of each of the molding structures 130 can be exposed, thereby forming the gate insulating pattern 150 and the first channel pattern 140.

[0116] With reference to Figure 24 , the upper portions of the first channel pattern 140, the second insulating layer 160, and the third insulating layer 170 can be exposed by an etch-back process, and / or an oxide deposition process and a CMP process can be performed. Accordingly, the second insulating layer 160 can be divided into a plurality of segments.

[0117] Referring to Figure 25 A second metal layer 190 can be deposited on the first channel pattern 140. The second metal layer 190 can be a bit line BL. The bit line 190 (BL) can be formed of or include the same or different conductive material as the conductive molding pattern 134.

[0118] As shown in area 400, a lower end portion of the first metal layer 134 can be disposed at a higher level than an upper end portion of the word line WL. Figure 25

[0119] It should be understood that certain embodiments of the disclosure and the terms used therein are not intended to limit the technical features set forth herein to particular embodiments, but include various changes, equivalents, or alternatives of the corresponding embodiments.

[0120] It should be understood that the description of the singular of a noun corresponding to an item can refer to one or more things, unless the relevant context clearly indicates otherwise.

[0121] As used herein, each of phrases such as "A or B", "at least one of A and B", "at least one of A or B", "A, B, or C", "at least one of A, B, and C", and "at least one of A, B, or C" can include any one or all possible combinations of the items listed together in the corresponding phrase.

[0122] As used herein, terms such as "1st" and "2nd" or "first" and "second" can be used to simply distinguish the corresponding components from other components, and do not otherwise limit the components in terms of, for example, importance or order, unless the context clearly indicates otherwise. In addition, a term referred to with a specific ordinal (e.g., "first") in a specific claim can be described with a different ordinal (e.g., "second") in the specification or elsewhere in another claim.

[0123] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which embodiments belong. Terms such as defined in a generally used dictionary should be interpreted as having a meaning consistent with the meaning in the context of related technology and the present disclosure, and should not be interpreted as ideally or overly formally, unless clearly defined herein.

[0124] When embodiments are described with reference to the drawings, like numerals refer to like components, and repetitive description thereof can be omitted. In the description of the embodiments, when it is considered that detailed description of related structures or functions known to be redundant to the explanation of the disclosure, such detailed description can be omitted. ​

[0125] The effects obtainable by the present application are not limited to the above-mentioned effects, and other effects not mentioned can be clearly understood by those skilled in the art from the present disclosure.

Claims

1. A semiconductor device comprising: bit lines extending along a first direction parallel to a substrate; first channel patterns connected to the bit lines and disposed perpendicular to the substrate; gate insulating patterns disposed on the first channel patterns; word lines disposed on the gate insulating patterns and extending along a second direction parallel to the substrate and perpendicular to the first direction; data storage patterns spaced apart from each other in the first direction and the second direction; storage node contacts, each of the storage node contacts disposed on a respective one of the data storage patterns; and molding patterns extending along the second direction and configured to support the first channel patterns, wherein the molding patterns comprise conductive molding patterns. The bit lines are formed from a conductive bit line layer and disposed on the first channel patterns.

2. The semiconductor device of claim 1, wherein, Upper end portions of the word lines are disposed at a higher level than lower end portions of the conductive molding patterns.

3. The semiconductor device of claim 1, wherein, 4. The semiconductor device of claim 2, wherein: the first channel patterns have a plurality of surfaces; the conductive molding patterns are in contact with a first surface of the plurality of surfaces; the conductive bit line layer is in contact with a second surface of the plurality of surfaces; and the second surface is different from the first surface. The conductive molding patterns and the conductive bit line layer are formed from a same metal as each other.

6. The semiconductor device of claim 1, further comprising second channel patterns extending along the first direction from one end of the first channel patterns.

5. The semiconductor device of claim 4, wherein, The second channel patterns and the first channel patterns are formed from a same semiconductor oxide material.

8. The semiconductor device of claim 1, further comprising an oxide layer disposed directly on lower end portions of the word lines.

7. The semiconductor device of claim 6, wherein, Upper end portions of the word lines are disposed at a lower level than lower end portions of the conductive molding patterns.

10. A method of manufacturing a semiconductor device, the method comprising:

9. The semiconductor device of claim 1, wherein, preparing storage node contacts connected to data storage patterns; forming molding patterns longitudinally positioned along a first direction, the molding patterns comprising conductive molding patterns; forming first channel patterns on the molding patterns; forming a gate insulating layer on the molding patterns; partially removing top surfaces of the first channel patterns and the gate insulating layer disposed on the molding patterns, thereby forming gate insulating patterns; forming word lines on the gate insulating patterns, the word lines extending along a second direction perpendicular to the first direction; forming a second insulating layer and a third insulating layer on the word lines; performing planarization, thereby partially removing the second insulating layer and the third insulating layer and exposing top surfaces of the molding patterns and the first channel patterns; and forming bit lines by depositing a conductive bit line layer on the first channel patterns. After exposing the top surfaces of the molding patterns and the first channel patterns, forming second channel patterns extending along a third direction, wherein the bit lines extend along the third direction, and the third direction is perpendicular to the first direction and the second direction. ​ ​ 11. The method of claim 10, further comprising: ​ 12. The method of claim 11, wherein, The second channel pattern and the first channel pattern are formed of the same semiconductor oxide material.

13. The method of claim 10, further comprising: An oxide layer is provided on the storage node contact and the data storage pattern before the word line is formed.

14. A semiconductor device, comprising: a bit line extending in a first direction parallel to a substrate; a word line extending in a second direction perpendicular to the first direction; a storage node contact connected to the word line; a data storage pattern connected to a lower portion of the storage node contact; a mold pattern extending in the second direction, the mold pattern including a conductive mold pattern; a first channel pattern provided on the mold pattern; and a gate insulating pattern provided on the first channel pattern; wherein the bit line is formed of a conductive bit line layer provided in the first direction.

15. The semiconductor device according to claim 14, further comprising a second channel pattern extending in the first direction from an end of the first channel pattern.

16. The semiconductor device according to claim 15, wherein: the first channel pattern has a plurality of surfaces; the conductive mold pattern is in contact with a first surface of the plurality of surfaces; the conductive bit line layer is in contact with a second surface of the plurality of surfaces; and the second surface is different from the first surface. An upper end portion of the first channel pattern is provided at a higher level than an upper end portion of the word line. An upper end portion of the word line is provided at a higher level than a lower end portion of the conductive mold pattern.

17. The semiconductor device of claim 14, wherein, 19. The semiconductor device according to claim 14, further comprising an oxide layer provided on a lower end portion of the word line.

18. The semiconductor device of claim 14, wherein, The second channel pattern and the first channel pattern are formed of the same semiconductor oxide material. ​ 20. The semiconductor device of claim 15, wherein, ​

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