Semiconductor structure and preparation method thereof, memory and memory system

Abstract

The embodiment of the invention provides a semiconductor structure and a preparation method thereof, a memory and a memory system, and the semiconductor structure comprises a first doping layer; the semiconductor main body is positioned on one side of the first doped layer along the first direction, the semiconductor main body comprises a first semiconductor part and a second semiconductor part, and the second semiconductor part is positioned on one side, deviating from the first doped layer along the first direction, of the first semiconductor part; and a gate layer located on at least one side of the semiconductor body in the second direction, wherein the second direction intersects with the first direction.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of semiconductor, and more particularly, to a semiconductor structure, a preparation method of the semiconductor structure, a memory and a memory system. BACKGROUND

[0002] Taking a memory as an example, the memory can include a random access memory (RAM), a read only memory (ROM) and a cache. The random access memory can include a dynamic random access memory (DRAM) and a static random access memory (SRAM). The dynamic random access memory utilizes a capacitor to store an amount of electric charge to represent whether a binary bit is 1 or 0. Thus, compared with the static random access memory, only one capacitor and one transistor are needed to process the data of one bit in the dynamic random access memory, and the structure is relatively simple. The transistor in the semiconductor structure such as the dynamic random access memory includes a vertical transistor.

[0003] However, the performance of the semiconductor structure taking the memory as an example needs to be improved. SUMMARY

[0004] The present application provides a semiconductor structure, a preparation method of the semiconductor structure, a memory and a memory system which can at least partially solve the above problems or other problems in the art.

[0005] In an aspect, the present application provides a semiconductor structure, comprising: a first doped layer; a semiconductor body located on one side of the first doped layer along a first direction, the semiconductor body comprising a first semiconductor part and a second semiconductor part, the second semiconductor part located on a side of the first semiconductor part away from the first doped layer along the first direction; and a gate layer located on at least one side of the semiconductor body along a second direction; wherein the second direction intersects the first direction.

[0006] In some embodiments, a size of the first semiconductor part along the first direction is less than or equal to 60 nm.

[0007] In some embodiments, a size of the second semiconductor part along the first direction is 80 nm to 200 nm.

[0008] In some embodiments, a material of the first semiconductor part is the same as a material of the second semiconductor part; or the material of the first semiconductor part is different from the material of the second semiconductor part.

[0009] In some embodiments, the material of the first semiconductor portion comprises any one of silicon, silicon-germanium, silicon-carbon, and a III-V compound semiconductor material; and the material of the second semiconductor portion comprises any one of silicon, silicon-germanium, silicon-carbon, and a III-V compound semiconductor material.

[0010] In some embodiments, the first doped layer comprises: a first doped region; and a second doped region located on a side of the first doped region facing the semiconductor body; wherein the second doped region and the first doped region have the same doping type, and the doping concentration of the second doped region is less than the doping concentration of the first doped region.

[0011] In some embodiments, the first doped region has a size of 30-70 nm along the first direction.

[0012] In some embodiments, the second doped region has a size of 5-35 nm along the first direction.

[0013] In some embodiments, the doping concentration of the first doped region is distributed in different regions of the first doped region from a first doping concentration to a second doping concentration, and the second doping concentration is greater than the first doping concentration; wherein the second doping concentration is less than or equal to 50 times the first doping concentration.

[0014] In some embodiments, the doping concentration of the second doped region is distributed in different regions of the second doped region from a third doping concentration to a fourth doping concentration, and the fourth doping concentration is greater than the third doping concentration; wherein the fourth doping concentration is less than or equal to 10 times the third doping concentration.

[0015] In some embodiments, the semiconductor structure further comprises: a second doped layer located in the second semiconductor portion; wherein the second doped layer is a source region, and the first doped layer is a drain region; or the second doped layer is a drain region, and the first doped layer is a source region.

[0016] In some embodiments, the semiconductor structure further comprises: an isolation structure located between the semiconductor bodies adjacent along a third direction and between the first doped layers adjacent along the third direction; wherein the third direction intersects the first direction and the second direction, respectively.

[0017] In some embodiments, the isolation structure comprises: a first isolation portion located between the semiconductor bodies adjacent along the third direction; and a second isolation portion located between the first doped layers adjacent along the third direction; wherein the materials of the first isolation portion and the second isolation portion are different, or the materials of the first isolation portion and the second isolation portion are the same.

[0018] In some embodiments, the semiconductor structure further comprises: a storage unit located on a side of the second doped layer facing away from the first doped layer and connected with the second doped layer.

[0019] Another aspect of the present application provides a method for manufacturing a semiconductor structure, comprising: forming a first doped layer; forming a semiconductor body, the semiconductor body being located on one side of the first doped layer along a first direction, the semiconductor body comprising a first semiconductor portion and a second semiconductor portion, the second semiconductor portion being located on one side of the first semiconductor portion along the first direction away from the first doped layer; and forming a gate layer, the gate layer being located on at least one side of the semiconductor body along a second direction; wherein the second direction intersects the first direction.

[0020] In some embodiments, the forming of the first doped layer and the semiconductor body comprises: forming the first doped layer in the first semiconductor layer; and in response to the forming of the first doped layer, forming the second semiconductor layer on one side of the first semiconductor layer along the first direction; wherein the method further comprises: forming a plurality of isolation structures spaced apart along a third direction and the second direction, the isolation structures penetrating the second semiconductor layer, the first doped layer, and a portion of the first semiconductor layer between the second semiconductor layer and the first doped layer along the first direction; wherein the portions of the first semiconductor layer and the second semiconductor layer located on one side of the first doped layer along the first direction and between adjacent isolation structures along the third direction constitute the semiconductor body; and wherein the third direction intersects the first direction and the second direction respectively.

[0021] In some embodiments, the forming of the first doped layer in the first semiconductor layer comprises: implanting ions in the first semiconductor layer to form a first initial doped layer; and performing annealing treatment on the first initial doped layer to form the first doped layer.

[0022] In some embodiments, the implanting of ions in the first semiconductor layer to form the first initial doped layer comprises: using an ion implantation process to form the first initial doped layer comprising a first initial doped region and a second initial doped region in the first semiconductor layer; wherein the performing of the annealing treatment on the first initial doped layer comprises: performing annealing treatment on the first initial doped region and the second initial doped region to form a first doped region and a second doped region respectively; wherein the second doped region is located on one side of the first doped region facing the semiconductor body, the second doped region and the first doped region have the same type of doping, and the doping concentration of the second doped region is less than the doping concentration of the first doped region.

[0023] In some embodiments, the method further comprises: forming a protective layer on a first surface of the first semiconductor layer on one side of the first semiconductor layer along the first direction; and after the performing of the annealing treatment and before the forming of the second semiconductor layer, removing part or all of the protective layer on the first surface; wherein the implanting of ions in the first semiconductor layer to form the first initial doped layer comprises: implanting ions into the first semiconductor layer through the protective layer to form the first initial doped layer.

[0024] In some embodiments, the material of the protective layer comprises an insulating dielectric material.

[0025] In some embodiments, forming the isolation structure comprises: forming a plurality of initial isolation structures spaced apart along the third direction and extending along the second direction, the initial isolation structures penetrating the first doped layer, and the portion of the first semiconductor layer and the second semiconductor layer on the same side of the first doped layer along the first direction; forming a cut groove extending along the third direction in the first semiconductor layer, the second semiconductor layer, and the initial isolation structures, the cut groove exposing the first doped layer, wherein the initial isolation structures are divided into the isolation structures by the cut groove.

[0026] In some embodiments, forming the isolation structure comprises: forming a plurality of first initial isolation portions on one side of the first semiconductor layer along the first direction, the plurality of first initial isolation portions being spaced apart along the third direction and extending along the second direction; wherein forming the second semiconductor layer on one side of the first semiconductor layer along the first direction comprises: forming the second semiconductor layer between adjacent first initial isolation portions; wherein forming the isolation structure further comprises: forming a cut groove extending along the third direction in the first semiconductor layer, the second semiconductor layer, and the first initial isolation portions, the cut groove exposing the first doped layer, the first initial isolation portions being divided into first isolation portions by the cut groove; and forming a second isolation portion penetrating the first doped layer and the portion of the first semiconductor layer between the first doped layer and the first isolation portions along the first direction, the second isolation portion and the first isolation portion constituting the isolation structure.

[0027] In some embodiments, forming the gate layer comprises: forming the gate layer in the cut groove.

[0028] In some embodiments, the preparation method further comprises: removing the portion of the first semiconductor layer on the side of the first doped layer away from the second semiconductor layer; and forming a bit line extending along the second direction on the side of the first doped layer away from the semiconductor body.

[0029] In some embodiments, the preparation method further comprises: forming a second doped layer in the portion of the second semiconductor portion; wherein the second doped layer is a source region, and the first doped layer is a drain region; or the second doped layer is a drain region, and the first doped layer is a source region.

[0030] In some embodiments, the preparation method further comprises: forming a memory cell on the side of the second doped layer away from the first doped layer, the memory cell being connected to the second doped layer.

[0031] In another aspect, the present application provides a memory, comprising: a memory cell array comprising a peripheral circuit and a semiconductor structure as mentioned in any of the embodiments above; the peripheral circuit being coupled to the memory cell array.

[0032] In another aspect, the present application provides a memory system, comprising a controller and a memory as mentioned in any of the embodiments above, the controller being coupled to the memory and configured to control the memory to store data. Attached Figure Description

[0033] Other features, objects, and advantages of this application will become more apparent from the following detailed description of non-limiting embodiments with reference to the accompanying drawings. Wherein:

[0034] Figure 1 This is a cross-sectional view of a semiconductor structure;

[0035] Figure 2 This is a flowchart of a method for fabricating a semiconductor structure according to an exemplary embodiment of this application;

[0036] Figures 3 to 21 This is a schematic diagram of the fabrication process of a semiconductor structure according to one embodiment of this application;

[0037] Figures 22 to 36 This is a schematic diagram of the fabrication process of a semiconductor structure according to another embodiment of this application;

[0038] Figure 37 This is a schematic diagram of a memory according to one embodiment of the present application;

[0039] Figure 38 This is a schematic diagram of a memory system according to one embodiment of the present application. Detailed Implementation

[0040] To better understand this application, various aspects of this application will be described in more detail with reference to the accompanying drawings. It should be understood that these detailed descriptions are merely illustrative of exemplary embodiments of this application and are not intended to limit the scope of this application in any way. Throughout the specification, the same reference numerals refer to the same elements. The expression "and / or" includes any and all combinations of one or more of the associated listed items.

[0041] It should be noted that in this specification, the terms "first," "second," "third," etc., are used only to distinguish one feature from another and do not imply any limitation on the features, especially not any order of precedence.

[0042] In the accompanying drawings, the thickness, dimensions, and shapes of the parts have been slightly adjusted for ease of illustration. The drawings are for illustrative purposes only and are not drawn to scale. As used herein, the terms “approximately,” “about,” and similar terms are used as expressions of approximation, not as expressions of degree, and are intended to illustrate inherent deviations in measured or calculated values ​​that will be recognized by one of ordinary skill in the art.

[0043] It should also be understood that all references to the application herein using expressions such as "including", "having", "including having", "containing" and / or "comprising" or "comprises" or "comprised of" etc. shall be understood in the context of this specification as referring to the more limiting term "comprising". Similarly, all references to the application herein using expressions such as "consisting essentially of" or "consisting of" shall be understood in the context of this specification as referring to the more limiting term "consisting of". Furthermore, when describing the embodiments of the application, the use of "can", "might" and "may" represents that "one or more embodiments of the application". Also, the use of the term "exemplary" is intended to represent that an example or illustration.

[0044] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. It will be further understood that terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning that is consistent with their meaning in the context of the relevant art and will not be interpreted in an overly literal or overly formal sense unless expressly so defined herein.

[0045] It should be noted that the embodiments and features of the application can be combined with each other, as far as they are not incompatible. In addition, the specific steps of the methods recited in the present application are not necessarily limited to the recited order, but can be executed in any order or in parallel, unless explicitly limited or contradicted by context.

[0046] Furthermore, when using "connected" or "coupled" in the present application, it can mean direct contact or indirect contact between the corresponding components, unless there is an explicit other limitation or it can be derived from the context.

[0047] The application will be described in detail below with reference to the attached drawings and embodiments.

[0048] Figure 1 A vertical transistor in a semiconductor structure is shown. The semiconductor structure includes a vertical transistor (reference Figure 1 ) and a capacitor structure (not shown) located on one side of the vertical transistor along a first direction Z.

[0049] A method of forming the vertical transistor includes: ion implantation from a first side of a semiconductor layer (not shown) to form a first doped layer in the semiconductor layer, the first doped layer including a first doped region 10 and a second doped region 11, the second doped region 11 having a doping concentration less than that of the first doped region 10; then patterning a portion of the semiconductor layer on a side of the first doped layer facing the first side to form a semiconductor body 12; forming a gate layer 15 on at least one side of the semiconductor body 12 in a second direction intersecting the first direction Z; and forming a second doped layer 13 in a portion of the semiconductor body 12. The capacitor structure is located on a side of the second doped layer 13 facing away from the first doped layer.

[0050] Since the semiconductor body 12 in the vertical transistor has a relatively large size along the first direction Z, the distance between the first doped layer and the surface of the semiconductor layer facing the first side is relatively large, which is not conducive to precisely controlling the position of ion implantation into the semiconductor layer by the ion implantation process, and thus is not conducive to improving the position accuracy of the first doped layer.

[0051] Another method of forming the vertical transistor includes: patterning the semiconductor layer from a first side of the semiconductor layer to form a semiconductor body 12; forming a gate layer 15 on at least one side of the semiconductor body 12 in a second direction; and forming a second doped layer 13 in a portion of the semiconductor body 12; ion implantation from a second side of the semiconductor layer opposite the first side to form a first doped layer in the semiconductor layer. In this case, in order to simplify the overall process of preparing the semiconductor structure as much as possible, ion implantation needs to be performed from the second side of the semiconductor layer to form the first doped layer in the semiconductor layer after the capacitor structure is formed. However, due to the relatively weak high-temperature resistance of the capacitor structure, annealing treatment of the first doped layer will affect the performance of the capacitor structure, and if the first doped layer is not annealed, it is difficult to reduce defects introduced by ion implantation.

[0052] Some embodiments of the present application provide a method 10000 of preparing a semiconductor structure, referring to Figure 2 , the method of preparing a semiconductor structure can include:

[0053] S1: forming a first doped layer;

[0054] S2: forming a semiconductor body, the semiconductor body being located on a side of the first doped layer along a first direction, the semiconductor body including a first semiconductor part and a second semiconductor part, the second semiconductor part being located on a side of the first semiconductor part facing away from the first doped layer along the first direction;

[0055] S3: forming a gate layer, the gate layer being located on at least one side of the semiconductor body in a second direction; wherein the second direction intersects the first direction.

[0056] The following will be described in detail Figures 3 to 21 The detailed description of each step of the method for manufacturing the semiconductor structure is the specific process in the present application.

[0057] Step S1 and Step S2

[0058] Figure 3 The cross-sectional view after forming the first semiconductor layer. Figure 4 The cross-sectional view after forming the protective layer. Figure 5 The cross-sectional view after forming the first initial doped layer. Figure 6 The cross-sectional view after forming the first doped layer. Figure 7 The cross-sectional view after removing the protective layer. Figure 8 The cross-sectional view after forming the second semiconductor layer. Figure 9 The cross-sectional view after forming the isolation groove. Figure 10 and Figure 11 The schematic view after forming the initial isolation structure. Figure 12 and Figure 13 The schematic view after forming the cut groove and the isolation structure.

[0059] With reference to Figures 3 to 13 , the first doped layer D1 is formed; the semiconductor body F is formed, the semiconductor body F is located on one side of the first doped layer D1 along the first direction Z, and the semiconductor body F includes the first semiconductor part F1 and the second semiconductor part F2, the second semiconductor part F2 is located on one side of the first semiconductor part F1 along the first direction Z away from the first doped layer D1.

[0060] With reference to Figure 3 and Figure 4 , Figure 4 The schematic view based on Figure 3 , the protective layer 110 is formed on the first surface 1000 on one side of the first semiconductor layer 100 along the first direction Z.

[0061] In some embodiments, the process of forming the first semiconductor layer 100 is a deposition process, which can include a thin film deposition process such as chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), or any combination thereof.

[0062] In some embodiments, the material of the first semiconductor layer 100 includes any one of silicon, silicon-germanium, carbon-silicon, and a group III-V compound semiconductor material.

[0063] In some embodiments, the process for forming the protective layer 110 is a deposition process, including thin film deposition processes such as chemical vapor deposition, physical vapor deposition, atomic layer deposition, or any combination thereof.

[0064] In some embodiments, the material of the protective layer 110 includes an insulating dielectric material, such as silicon oxide, silicon nitride, silicon oxynitride, or silicon oxycarbide.

[0065] In other embodiments, the protective layer 110 may not be formed.

[0066] refer to Figures 5 to 6 , Figure 5 In order to be in Figure 4 A basic diagram. Figure 6 In order to be in Figure 5 The schematic diagram shows that forming a first doped layer D1 in the first semiconductor layer 100 includes: implanting ions into the first semiconductor layer 100 to form a first initial doped layer D11; and annealing the first initial doped layer D11 to form the first doped layer D1.

[0067] refer to Figure 5 Ions are implanted in the first semiconductor layer 100 to form a first initial doped layer D 11.

[0068] In some embodiments, implanting ions into the first semiconductor layer 100 to form a first initial doped layer D11 includes: implanting ions into the first semiconductor layer 100 through a protective layer 110 to form the first initial doped layer D11. During the formation of the first initial doped layer D11, the protective layer 110 can protect the first surface 1000 and reduce ion implantation damage to the first surface 1000 of the first semiconductor layer 100.

[0069] In some implementations, reference Figure 5 Implanting ions into the first semiconductor layer 100 to form a first initial doped layer D11 includes: forming a first initial doped layer D11 including a first initial doped region 130a and a second initial doped region 120a in the first semiconductor layer 100 using an ion implantation process.

[0070] In some embodiments, a second initial doped region 120a is formed after the first initial doped region 130a is formed.

[0071] In another embodiment, the first initial doped region 130a is formed after the second initial doped region 120a is formed.

[0072] In some embodiments, the second initial doped region 120a and the first initial doped region 130a have the same doping type, and the doping concentration of the second initial doped region 120a is less than the doping concentration of the first initial doped region 130a.

[0073] In other embodiments, the first initial doping region 130a can be formed without forming the second initial doping region 120a.

[0074] In some embodiments, the first initial doping layer D11 is of N-type; or, the first initial doping layer D11 is of P-type.

[0075] In some embodiments, a defect layer 140 is formed in the first semiconductor layer 100 during the process of implanting ions to form the first initial doping layer D11. The defect layer 140 can be removed by a subsequent annealing process.

[0076] In some embodiments, the distance between the second initial doping region 120a and the first surface 1000 along the first direction Z is greater than zero.

[0077] In some embodiments, the distance between the first initial doping region 130a and the first surface 1000 along the first direction Z is greater than zero.

[0078] It should be noted that, Figure 5 In order to better show the position of the defect layer 140 in the first semiconductor layer 100, the defect layer 140 and the first initial doping layer D11 are shown separately. In fact, the defect layer 140 can also extend to connect with the first initial doping layer D11.

[0079] Reference is made to Figure 6 The first initial doping layer D11 (reference Figure 5 ) is subjected to an annealing process to form a first doping layer D1.

[0080] The annealing process is used to activate the ions in the first initial doping layer D11 and remove the defect layer 140.

[0081] In some embodiments, reference Figure 6 The first initial doping layer D11 is subjected to an annealing process, including: the first initial doping region 130a and the second initial doping region 120a are subjected to an annealing process to form a first doping region 130 and a second doping region 120, respectively. The second doping region 120 and the first doping region 130 are of the same doping type, and the doping concentration of the second doping region 120 is less than that of the first doping region 130. The second doping region 120 is located on the side of the first doping region 130 facing the first surface 1000.

[0082] The annealing of the first initial doped region 130a and the second initial doped region 120a to form the first doped region 130 and the second doped region 120 respectively means that the first initial doped region 130a is annealed to form the first doped region 130, and the second initial doped region 120a is annealed to form the second doped region 120.

[0083] In some embodiments, the distance between the second doped region 120 and the first surface 1000 along the first direction Z is greater than zero, and the distance between the first doped region 130 and the first surface 1000 along the first direction Z is greater than zero.

[0084] In some embodiments, the size of the first doped region 130 along the first direction Z is 30nm-70nm. In other embodiments, the size of the first doped region 130 along the first direction Z is not limited.

[0085] In some embodiments, the size of the second doped region 120 along the first direction Z is 5nm-35nm. It should be noted that in other embodiments, the size of the second doped region 120 along the first direction Z is not limited.

[0086] In some embodiments, the size of the surface of the first doped layer D1 on the side facing the first surface 1000 to the first surface 1000 along the first direction Z is less than or equal to 60nm.

[0087] In some embodiments, the doping concentration of the first doped region 130 is distributed in different regions of the first doped region 130 from the first doping concentration to the second doping concentration, and the second doping concentration is greater than the first doping concentration. Wherein, the second doping concentration is less than or equal to 50 times the first doping concentration.

[0088] In some embodiments, the doping concentration of the second doped region 120 is distributed in different regions of the second doped region 120 from the third doping concentration to the fourth doping concentration, and the fourth doping concentration is greater than the third doping concentration. Wherein, the fourth doping concentration is less than or equal to 10 times the third doping concentration.

[0089] Since the ion implantation depth for forming the first initial doping layer D11 in the first semiconductor layer 100 is relatively small, that is, the dimension of the first initial doping layer D11 from the surface towards the first surface 1000 to the first surface 1000 along the first direction Z is small, the distribution range of the implanted ions in the first semiconductor layer 100 can be controlled more accurately, the ion distribution in the first initial doping region 130a is more concentrated, the ion distribution in the second initial doping region 120a is more concentrated, and the position accuracy of the first initial doping layer D11 in the first semiconductor layer 100 is improved. After the annealing process, the first initial doping layer D11 forms the first doping layer D1, and accordingly, the position accuracy of the first doping layer D1 in the first semiconductor layer 100 is improved, and the difference of the doping concentration of the first doping region 130 in different regions of the first doping region 130 is relatively small, and the difference of the doping concentration of the second doping region 120 in different regions of the second doping region 120 is relatively small.

[0090] Reference Figure 7 After the annealing process of the first initial doping layer D11, part or all of the protective layer 110 located at the first surface 1000 is removed.

[0091] In some embodiments, the process of removing part or all of the protective layer 110 located at the first surface 1000 is an etching process, which includes one of a dry etching process and a wet etching process or a combination thereof.

[0092] In some embodiments, all of the protective layer 110 located at the first surface 1000 is removed. In other embodiments, part of the protective layer 110 located at the first surface 1000 is removed. Figure 7 In some embodiments, all of the protective layer 110 located at the first surface 1000 is removed as an example.

[0093] Reference Figure 8 In response to forming the first doping layer D1, a second semiconductor layer 150 is formed on one side of the first semiconductor layer 100 along the first direction Z.

[0094] After forming the first doping layer D1, a second semiconductor layer 150 is formed on one side of the first semiconductor layer 100 along the first direction Z.

[0095] In some embodiments, after removing part or all of the protective layer 110 located at the first surface 1000, a second semiconductor layer 150 is formed on one side of the first semiconductor layer 100 along the first direction Z.

[0096] In some embodiments, the process of forming the second semiconductor layer 150 is a deposition process, which includes a thin film deposition process of chemical vapor deposition, physical vapor deposition, atomic layer deposition, or any combination thereof.

[0097] In some embodiments, the material of the first semiconductor layer 100 and the material of the second semiconductor layer 150 are the same; or, the material of the first semiconductor layer 100 and the material of the second semiconductor layer 150 are different.

[0098] In some embodiments, the material of the second semiconductor layer 150 comprises any one of silicon, silicon-germanium, silicon-carbon, and a III-V compound semiconductor material.

[0099] In some embodiments, the size of the second semiconductor layer 150 along the first direction Z is 80 nm to 200 nm. It should be noted that in other embodiments, the size of the second semiconductor layer 150 along the first direction Z is not limited.

[0100] Since the first doped layer D1 is formed in the first semiconductor layer 100 before the second semiconductor layer 150 is formed, the distance from the first doped layer D1 to the first surface 1000 is small, so that the position accuracy of the first doped layer D1 is improved.

[0101] Reference Figures 9 to 13 The plurality of isolation structures 180 are formed along the third direction X and the second direction Y, and the isolation structures 180 penetrate the second semiconductor layer 150, the first doped layer D1, and the portion of the first semiconductor layer 100 between the second semiconductor layer 150 and the first doped layer D1 along the first direction Z. The portion of the first semiconductor layer 100 and the second semiconductor layer 150 located on the side of the first doped layer D1 along the first direction Z and between the adjacent isolation structures 180 along the third direction X constitutes a semiconductor body F. The formation of the isolation structures 180 comprises: referring to Figures 9 to 11 The plurality of initial isolation structures 180a are formed along the third direction X and extend along the second direction Y, and the initial isolation structures 180a penetrate the first doped layer D1, and the portion of the second semiconductor layer 150 and the first semiconductor layer 100 on the same side of the first doped layer D1 along the first direction Z; referring to Figure 12 and Figure 13 The cutting groove 190 extending along the third direction X is formed in the first semiconductor layer 100, the second semiconductor layer 150, and the initial isolation structure 180a, and the cutting groove 190 exposes the first doped layer D1, wherein the initial isolation structure 180a is divided into the isolation structure 180 by the cutting groove 190.

[0102] Reference Figure 9 The plurality of isolation grooves 170 are formed along the third direction X and extend along the second direction Y, and the isolation grooves 170 penetrate the first doped layer D1, and the portion of the second semiconductor layer 150 and the first semiconductor layer 100 on the same side of the first doped layer D1 along the first direction Z.

[0103] In some embodiments, forming the plurality of isolation grooves 170 spaced along the third direction X and extending along the second direction Y comprises: forming a mask layer 160 on a side of the second semiconductor layer 150 facing away from the first semiconductor layer 100; and etching the second semiconductor layer 150 and the portion of the first semiconductor layer 100 on the same side of the first doped layer D1 and the first doped layer D1 with the mask layer 160 as a mask to form the isolation grooves 170.

[0104] In some embodiments, the mask layer is a single-layer structure or a multi-layer structure.

[0105] In some embodiments, the mask layer 160 comprises a first mask layer 161 and a second mask layer 162, the second mask layer 162 is on a side of the first mask layer 161 facing away from the second semiconductor layer 150. The first mask layer 161 and the second mask layer 162 are made of different materials. For example, the first mask layer 161 is made of silicon oxide and the second mask layer 162 is made of silicon nitride. It should be noted that the materials of the first mask layer 161 and the second mask layer 162 are not limited to the above.

[0106] In some embodiments, the etching process for etching the second semiconductor layer 150 and the portion of the first semiconductor layer 100 on the same side of the first doped layer D1 and the first doped layer D1 with the mask layer 160 as a mask is one of a dry etching process and a wet etching process or a combination thereof.

[0107] In some embodiments, the isolation grooves 170 extend along the second direction Y by a dimension greater than a dimension along which the isolation grooves 170 extend along the third direction X.

[0108] In some embodiments, the isolation grooves 170 extend along the first direction Z through the first doped layer D1, the second semiconductor layer 150, the portion of the first semiconductor layer 100 on the same side of the first doped layer D1, and a portion of the first semiconductor layer 100 on a side of the first doped layer D1 facing away from the second semiconductor layer 150.

[0109] In some other embodiments, the isolation grooves extend along the first direction Z through the first doped layer D1, the second semiconductor layer 150, the portion of the first semiconductor layer 100 on the same side of the first doped layer D1, and do not extend to the portion of the first semiconductor layer 100 on the side of the first doped layer D1 facing away from the second semiconductor layer 150.

[0110] The first direction Z and the second direction Y intersect, for example, the first direction Z and the second direction Y are perpendicular. The third direction X intersects the first direction Z and the second direction Y, for example, the third direction X is perpendicular to the first direction Z and the third direction X is perpendicular to the second direction Y.

[0111] In combination with reference toFigure 10 and Figure 11 , Figure 10 In order to be in Figure 9 A basic diagram. Figure 11 for Figure 10 Top view, Figure 10 For along Figure 11 A cross-sectional view along the dicing line M1-N1 shows an initial isolation structure 180a formed in the isolation trench 170. Multiple initial isolation structures 180a are spaced apart along the third direction X and extend along the second direction Y. The initial isolation structure 180a penetrates the first doped layer D1 along the first direction Z, and the portions of the second semiconductor layer 150 and the first semiconductor layer 100 located on the same side of the first doped layer D1.

[0112] In some embodiments, forming an initial isolation structure 180a in the isolation trench 170 includes: forming an initial isolation structure material layer in the isolation trench 170 and on the side of the mask layer 160 opposite to the second semiconductor layer 150; planarizing the initial isolation structure material layer and the mask layer 160 until the second semiconductor layer 150 is exposed to form the initial isolation structure 180a.

[0113] In some embodiments, the process for forming the initial isolation structure material layer includes a deposition process, which includes thin film deposition processes such as chemical vapor deposition, physical vapor deposition, atomic layer deposition, or any combination thereof. The process for planarizing the initial isolation structure material layer and the mask layer 160 includes a chemical mechanical polishing process.

[0114] In some embodiments, the initial isolation structure 180a extends along the second direction Y by a dimension greater than the initial isolation structure 180a extends along the third direction X.

[0115] In some embodiments, the initial isolation structure 180a extends along the first direction Z through the first doped layer D1, the second semiconductor layer 150, and the portion of the first semiconductor layer 100 located on the same side of the first doped layer D1 and to the portion of the first semiconductor layer 100 located on the first doped layer D1 away from the second semiconductor layer 150.

[0116] In other embodiments, the initial isolation structure extends along the first direction Z through the portion of the first doped layer D1, the second semiconductor layer 150, and the first semiconductor layer 100 located on the same side of the first doped layer D1, and does not extend to the portion of the first semiconductor layer 100 located on the first doped layer D1 away from the second semiconductor layer 150.

[0117] In some embodiments, the material of the initial isolation structure 180a includes an insulating dielectric material, such as silicon oxide, silicon nitride, silicon oxynitride, or silicon oxycarbide.

[0118] refer to Figure 12 andFigure 13 , Figure 12 for Figure 11 A basic diagram. Figure 13 for Figure 10 A basic diagram. Figure 13 For along Figure 12 A cross-sectional view of the dicing line M1-N1 shows a groove 190 extending in the third direction X in the first semiconductor layer 100, the second semiconductor layer 150, and the initial isolation structure 180a. The groove 190 exposes the first doped layer D1. The initial isolation structure 180a is divided into isolation structures 180 by the groove 190.

[0119] An isolation structure 180 extends along a first direction Z through a second semiconductor layer 150, a first doped layer D1, and a portion of the first semiconductor layer 100 located between the second semiconductor layer 150 and the first doped layer D1. The portion of the first semiconductor layer 100 and the second semiconductor layer 150 located on one side of the first doped layer D1 along the first direction Z and between adjacent isolation structures 180 along a third direction X constitutes a semiconductor body F. The semiconductor body F includes a first semiconductor portion F1 and a second semiconductor portion F2, with the second semiconductor portion F2 located on the side of the first semiconductor portion F1 facing away from the first doped layer D1 along the first direction Z. The portion of the first semiconductor layer 100 located between the first doped layer D1 and the second semiconductor layer 150 and between adjacent isolation structures 180 along a third direction X constitutes the first semiconductor portion F1, and the portion of the second semiconductor layer 150 located between adjacent isolation structures 180 constitutes the second semiconductor portion F2.

[0120] The isolation structure 180 is located between adjacent semiconductor bodies F along the third direction X and between adjacent first doped layers D1.

[0121] In some embodiments, the dimension of the first semiconductor portion F1 along the first direction Z is less than or equal to 60 nm.

[0122] In some embodiments, the size of the second semiconductor section F2 along the first direction Z is 80nm to 200nm.

[0123] In some embodiments, the materials of the first semiconductor part F1 and the second semiconductor part F2 are the same; or, the materials of the first semiconductor part F1 and the second semiconductor part F2 are different.

[0124] In some embodiments, the material of the first semiconductor unit F1 includes any one of silicon, germanium silicon, silicon carbon, and group III-V compound semiconductor materials. The material of the second semiconductor unit F2 includes any one of silicon, germanium silicon, silicon carbon, and group III-V compound semiconductor materials.

[0125] In some embodiments, the isolation structure 180 can also extend to a portion of the first semiconductor layer 100 located at the side of the first doped layer D1 facing away from the semiconductor body F. In other embodiments, the isolation structure does not extend to the portion of the first semiconductor layer 100 located at the side of the first doped layer D1 facing away from the semiconductor body F.

[0126] In some embodiments, the second doped region 120 is located at the side of the first doped region 130 facing towards the semiconductor body F.

[0127] In some embodiments, the process of forming the cut groove 190 is an etching process, which includes one or a combination of dry etching process and wet etching process.

[0128] In some embodiments, the material of the isolation structure 180 includes an insulating dielectric material, such as silicon oxide, silicon nitride, silicon oxynitride or silicon oxycarbide.

[0129] Step S3

[0130] Figure 14 and Figure 15 is a schematic view after forming the gate layer.

[0131] In combination with reference to Figure 14 and Figure 15 , Figure 14 is Figure 12 a schematic view, Figure 15 is a cross-sectional view along the cutting line M2-N2 in Figure 14 the semiconductor body F in the second direction Y.

[0132] In some embodiments, forming the gate layer 321 includes forming the gate layer 321 in the cut groove 190.

[0133] In some embodiments, the process of forming the gate layer 321 in the cut groove 190 includes a deposition process, which includes a thin film deposition process of chemical vapor deposition, physical vapor deposition, atomic layer deposition or any combination thereof.

[0134] In some embodiments, the material of the gate layer 321 includes any one of a metal gate material and a polysilicon gate material. The material of the gate layer 321 can be, for example, any one or a combination of tungsten (W), cobalt (Co), copper (Cu), aluminum (Al), doped crystalline silicon or silicide.

[0135] In some embodiments, the method of fabricating a semiconductor structure further comprises forming a gate dielectric layer 322 between the gate layer 321 and the semiconductor body F controlled by the gate layer 321. Exemplarily, the gate dielectric layer 322 is formed in the trench 190. The process of forming the gate dielectric layer 322 comprises a deposition process, which includes chemical vapor deposition, physical vapor deposition, atomic layer deposition, or any combination thereof.

[0136] In some embodiments, the material of the gate dielectric layer 322 can be a high-K (dielectric constant) dielectric material, for example, the dielectric constant K can be greater than 3.9. The material of the gate dielectric layer 322 can include any one of aluminum oxide, hafnium dioxide, zirconium dioxide, lanthanum oxide, and titanium oxide. In other embodiments, the material of the gate dielectric layer 322 is silicon oxide.

[0137] In some embodiments, the method of fabricating a semiconductor structure further comprises forming an isolation dielectric layer 310, exemplarily, the isolation dielectric layer 310 is formed in the trench 190. The process of forming the isolation dielectric layer 310 comprises a deposition process, which includes chemical vapor deposition, physical vapor deposition, atomic layer deposition, or any combination thereof. The material of the isolation dielectric layer 310 is an insulating dielectric material, for example, silicon oxide, silicon nitride, silicon oxynitride, or silicon oxycarbide.

[0138] In some embodiments, the isolation dielectric layer 310 is located on the side of the gate layer 321 facing away from the gate dielectric layer 322 and on the side of the gate layer 321 facing away from the first doped layer D1.

[0139] It should be noted that there is an isolation material between the gate layer 321 and the first doped layer D1, Figure 15 In order to simplify the illustration, the isolation material between the gate layer 321 and the first doped layer D1 is not shown in the figure.

[0140] It should be noted that in order to facilitate the illustration of the gate dielectric layer 322 and the gate layer 321, Figure 14 In the figure, the part of the isolation dielectric layer 310 located on the side of the gate layer 321 facing away from the first doped layer D1 is not shown.

[0141] Figure 16 And Figure 17 is a cross-sectional view after forming the second doped layer. Figure 18 And Figure 19 is a cross-sectional view after forming the storage unit. Figure 20 And Figure 21 is a cross-sectional view after forming the bit line.

[0142] Reference Figure 16 And Figure 17 , Figure 16 is a cross-sectional view after forming the second doped layer. Figure 14A schematic view of forming the second doped layer on the basis of the cross-sectional view along the cutting line M1-N1, Figure 17 A schematic view of forming the second doped layer on the basis of the cross-sectional view along the cutting line M1-N1, Figure 15 A schematic view of forming the second doped layer on the basis of the cross-sectional view along the cutting line M1-N1,

[0143] In some embodiments, the second doped layer D2 is a source region, and the first doped layer D1 is a drain region; or, the second doped layer D2 is a drain region, and the first doped layer D1 is a source region.

[0144] In some embodiments, the process of forming the second doped layer D2 in the partial second semiconductor portion F2 is an ion implantation process.

[0145] Referring to Figure 18 and Figure 19 , Figure 18 A schematic view of forming the second doped layer on the basis of the cross-sectional view along the cutting line M1-N1, Figure 16 A schematic view of forming the second doped layer on the basis of the cross-sectional view along the cutting line M1-N1, Figure 19 A schematic view of forming the second doped layer on the basis of the cross-sectional view along the cutting line M1-N1, Figure 17 A schematic view of forming the second doped layer on the basis of the cross-sectional view along the cutting line M1-N1,

[0146] In some embodiments, the storage unit 350 includes at least one of a dynamic random access memory unit, a phase change memory unit, and a ferroelectric memory unit.

[0147] In some embodiments, the storage unit 350 is a capacitor for storing an electric charge as binary information stored by the corresponding storage unit 350. In some embodiments, the storage unit 350 is a phase change memory (PCM) element (e.g., including a chalcogenide alloy) for storing binary information in different resistivities in amorphous and crystalline phases. In other embodiments, the storage unit 350 is a ferroelectric capacitor for storing binary information based on switching between two polarization states of a ferroelectric material under an external electric field.

[0148] In some embodiments, before forming the storage unit 350 on the side of the second doped layer D2 facing away from the first doped layer D1, further comprising: forming a connection layer 340 on the side of the second doped layer D2 facing away from the first doped layer D1. Forming the storage unit 350 on the side of the second doped layer D2 facing away from the first doped layer D1 includes: forming the storage unit 350 on the side of the connection layer 340 facing away from the first doped layer D1.

[0149] In some embodiments, the material of the connection layer 340 includes a metal silicide. The connection layer 340 can reduce the contact resistance between the storage unit 350 and the second doped layer D2.

[0150] Referring to Figure 20 and Figure 21 ,Figure 20 is a schematic view based on Figure 18 is a schematic view based on Figure 21 is a schematic view based on Figure 19 , removing a portion of the first semiconductor layer 100 located on a side of the first doped layer D1 facing away from the second semiconductor layer 150; and forming a bit line 400 extending along the second direction Y on a side of the first doped layer D1 facing away from the semiconductor body F.

[0151] In some embodiments, the second semiconductor portion F2 is formed from a portion of the second semiconductor layer 150. A portion of the first semiconductor layer 100 located on a side of the first doped layer D1 facing away from the second semiconductor layer 150 is removed, for example, a portion of the first semiconductor layer 100 located on a side of the first doped layer D1 facing away from the second semiconductor portion F2 is removed.

[0152] In some embodiments, after forming the memory cell 350, a portion of the first semiconductor layer 100 located on a side of the first doped layer D1 facing away from the second semiconductor layer 150 is removed; after removing the portion of the first semiconductor layer 100 located on a side of the first doped layer D1 facing away from the second semiconductor layer 150, a bit line extending along the second direction is formed on a side of the first doped layer D1 facing away from the semiconductor body F.

[0153] In some embodiments, a portion of the first semiconductor layer 100 located on a side of the first doped layer D1 facing away from the second semiconductor layer 150 is removed until a surface of the first doped layer D1 facing away from the semiconductor body F is exposed and the isolation structure 180 is exposed.

[0154] The process of removing the portion of the first semiconductor layer 100 located on a side of the first doped layer D1 facing away from the second semiconductor layer 150 is a planarization process, for example, a chemical mechanical polishing process.

[0155] In some embodiments, the process of forming the bit line 400 includes a deposition process, which includes a thin film deposition process of chemical vapor deposition, physical vapor deposition, atomic layer deposition, or any combination thereof.

[0156] Another embodiment of the present application further provides a method for manufacturing a semiconductor structure. The manufacturing process of the semiconductor structure will be described below in conjunction with Figures 22 to 36

[0157] Referring to Figures 22 to 26 , in response to forming the first doped layer D1, a second semiconductor layer 230 is formed on a side of the first semiconductor layer 100 along the first direction Z.

[0158] The process of forming the first doped layer D1 is described in the foregoing embodiments and will not be described in detail.

[0159] ​In some embodiments, the method for manufacturing the semiconductor structure further comprises forming the isolation structure, referring to Figures 22 to 26 The forming the isolation structure comprises: forming a plurality of first initial isolation portions 200 on one side of the first semiconductor layer 100 along the first direction Z. The plurality of first initial isolation portions 200 are arranged at intervals along the third direction X and extend along the second direction Y.

[0160] Referring to Figure 22 , a first initial isolation material layer 2000 is formed on one side of the first semiconductor layer 100 along the first direction Z; and an initial mask layer 2100 is formed on one side of the first initial isolation material layer 2000 away from the first semiconductor layer 100.

[0161] In some embodiments, the material of the first initial isolation material layer 2000 comprises an insulating dielectric material, such as silicon oxide, silicon nitride, silicon oxynitride, or silicon oxycarbide. The material of the initial mask layer 2100 comprises a photoresist.

[0162] In some embodiments, the process of forming the first initial isolation material layer 2000 comprises a deposition process, and the deposition process comprises a thin film deposition process of chemical vapor deposition, physical vapor deposition, atomic layer deposition, or any combination thereof. The process of forming the initial mask layer 2100 comprises a spin coating process.

[0163] The first initial isolation material layer 2000 covers the first surface 1000 of the first semiconductor layer 100 (referring to Figure 3 ).

[0164] Referring to Figure 23 , the initial mask layer 2100 is patterned, and the patterned initial mask layer 2100 forms a mask layer 210. The first initial isolation material layer 2000 is etched with the mask layer 210 as a mask to form the first initial isolation portions 200.

[0165] In some embodiments, the process of etching the first initial isolation material layer 2000 with the mask layer 210 as a mask is an etching process, and the etching process comprises one of a dry etching process and a wet etching process, or a combination thereof.

[0166] The first initial isolation portions 200 are located on one side of the first semiconductor layer 100 along the first direction Z. The plurality of first initial isolation portions 200 are arranged at intervals along the third direction X and extend along the second direction Y.

[0167] In some embodiments, the size of the first initial isolation portions 200 along the second direction Y is greater than the size of the first initial isolation portions 200 along the third direction X.

[0168] A first isolation groove 220 is provided between adjacent first initial isolation portions 200. The first isolation groove 220 extends along a second direction Y. The dimension of the first isolation groove 220 along the second direction Y is larger than the dimension of the first isolation groove 220 along the third direction X.

[0169] In some embodiments, the material of the first initial isolation portion 200 includes an insulating dielectric material, such as silicon oxide, silicon nitride, silicon oxynitride, or silicon oxycarbide.

[0170] refer to Figure 24 After the first initial isolation section 200 is formed, the inner wall of the first isolation tank 220 is cleaned.

[0171] Cleaning the inner wall of the first isolation trench 220 removes byproducts formed on the inner wall of the first isolation trench 220 during the etching of the first initial isolation material layer 2000, which helps to improve the quality of the subsequent formation of the second semiconductor layer.

[0172] It should be noted that in other embodiments, the inner wall of the first isolation groove 220 may not need to be cleaned.

[0173] In some embodiments, during the cleaning process of the inner wall of the first isolation tank 220, the cleaning solution used in the cleaning process will laterally etch the first semiconductor layer 100 exposed on the sidewall of the first isolation tank 220.

[0174] refer to Figure 25 and Figure 26 , Figure 25 In order to be in Figure 24 A basic diagram. Figure 26 for Figure 25 Top view, Figure 25 For along Figure 26 A cross-sectional view along dicing line M1-N1 shows that forming a second semiconductor layer 230 on one side of the first semiconductor layer 100 along the first direction Z includes forming the second semiconductor layer 230 between adjacent first initial isolation portions 200. For example, the second semiconductor layer 230 is formed in a first isolation trench 220.

[0175] In some embodiments, the process of forming the second semiconductor layer 230 includes a deposition process, which includes thin film deposition processes such as chemical vapor deposition, physical vapor deposition, atomic layer deposition, or any combination thereof.

[0176] The material of the second semiconductor layer 230 is as described in the foregoing embodiment.

[0177] The dimensions of the second semiconductor layer 230 along the first direction Z are described with reference to the description of the aforementioned embodiment.

[0178] refer to Figure 27 andFigure 28 , Figure 27 is a schematic view based on Figure 26 , Figure 28 is a top view of Figure 25 , Figure 28 is a sectional view along cutting line M1-N1 in Figure 27 , forming the isolation structure further comprises: forming a cutting groove 290 extending along the third direction X in the first semiconductor layer 100, the second semiconductor layer 230 and the first initial isolation part 200, the cutting groove 290 exposing the first doped layer D1, wherein the first initial isolation part 200 is divided into a first isolation part 2001 by the cutting groove 290.

[0179] In some embodiments, the process of forming the cutting groove 290 is an etching process, and the etching process comprises one or a combination of a dry etching process and a wet etching process.

[0180] In some embodiments, the size of the cutting groove 290 along the second direction Y is greater than the size of the cutting groove 290 along the third direction X.

[0181] In some embodiments, the part of the second semiconductor layer 230 between the first isolation parts 2001 adjacent along the third direction X constitutes a second semiconductor part F2.

[0182] In some embodiments, the size of the second semiconductor part F2 along the first direction Z is 80-200 nm.

[0183] In some embodiments, the material of the first semiconductor part F1 and the material of the second semiconductor part F2 are the same; or the material of the first semiconductor part F1 and the material of the second semiconductor part F2 are different. The material of the first semiconductor part F1 and the material of the second semiconductor part F2 refer to the description of the foregoing embodiments.

[0184] Reference is made to Figure 29 and Figure 30 , Figure 29 is a schematic view based on Figure 27 , Figure 30 is a sectional view along cutting line M3-N3 in Figure 29 , forming the gate layer 321.

[0185] In some embodiments, the gate layer 321 is located on at least one side of the second semiconductor part F2 in the second direction Y.

[0186] In some embodiments, forming the gate layer 321 comprises: forming the gate layer 321 in the cutting groove 290.

[0187] In some embodiments, the process of forming the gate layer 321 in the trench 290 includes a deposition process, which includes a thin film deposition process of chemical vapor deposition, physical vapor deposition, atomic layer deposition, or any combination thereof.

[0188] In some embodiments, the method of preparing the semiconductor structure further includes forming a gate dielectric layer 322 between the gate layer 321 and the second semiconductor portion F2 controlled by the gate layer 321. Illustratively, the gate dielectric layer 322 is formed in the trench 290. The process of forming the gate dielectric layer 322 includes a deposition process, which includes a thin film deposition process of chemical vapor deposition, physical vapor deposition, atomic layer deposition, or any combination thereof.

[0189] In some embodiments, the method of preparing the semiconductor structure further includes forming an isolation dielectric layer 310, illustratively in the trench 290. The process of forming the isolation dielectric layer 310 includes a deposition process, which includes a thin film deposition process of chemical vapor deposition, physical vapor deposition, atomic layer deposition, or any combination thereof.

[0190] In some embodiments, the isolation dielectric layer 310 is located on a side of the gate layer 321 facing away from the gate dielectric layer 322 and on a side of the gate layer 321 facing away from the first doped layer D1.

[0191] In some embodiments, the material of the gate layer 321, the material of the gate dielectric layer 322, and the material of the isolation dielectric layer 310 are as described with reference to the foregoing embodiments.

[0192] It is noted that there is an isolation material between the gate layer 321 and the first doped layer D1, Figure 30 In order to simplify the illustration, the isolation material between the gate layer 321 and the first doped layer D1 is not shown in the drawings.

[0193] It is noted that in order to facilitate the illustration of the gate dielectric layer 322 and the gate layer 321, Figure 29 In the drawings, the portion of the isolation dielectric layer 310 located on the side of the gate layer 321 facing away from the first doped layer D1 is not shown.

[0194] Reference is made to Figure 31 and Figure 32 , Figure 31 for forming the second doped layer based on the cross-sectional view along the cutting line M1-N1, Figure 29 for forming the second doped layer D2 in the partial second semiconductor portion F2 based on the cross-sectional view along the cutting line M1-N1. Figure 32 Figure 30

[0195] ​​In some embodiments, the second doped layer D2 is a source region, and the first doped layer D1 is a drain region; or, the second doped layer D2 is a drain region, and the first doped layer D1 is a source region.

[0196] In some embodiments, the process of forming the second doped layer D2 in the partial second semiconductor portion F2 is an ion implantation process.

[0197] Reference is made to Figure 33 and Figure 34 , Figure 33 schematic diagram based on Figure 31 , Figure 34 schematic diagram based on Figure 32 , a storage unit 350 is formed on the side of the second doped layer D2 facing away from the first doped layer D1, and the storage unit 350 is connected with the second doped layer D2.

[0198] In some embodiments, before forming the storage unit 350 on the side of the second doped layer D2 facing away from the first doped layer D1, further comprising: forming a connection layer 340 on the side of the second doped layer D2 facing away from the first doped layer D1. Forming the storage unit 350 on the side of the second doped layer D2 facing away from the first doped layer D1 comprises: forming the storage unit 350 on the side of the connection layer 340 facing away from the first doped layer D1.

[0199] In some embodiments, the material of the connection layer 340 comprises a metal silicide.

[0200] The storage unit 350 is described with reference to the description of the foregoing embodiments.

[0201] Reference is made to Figure 35 and Figure 36 , Figure 35 schematic diagram based on Figure 33 , Figure 36 schematic diagram based on Figure 34 , a portion of the first semiconductor layer 100 on the side of the first doped layer D1 facing away from the second semiconductor layer 150 is removed.

[0202] The second semiconductor portion F2 is formed by a portion of the second semiconductor layer 150. A portion of the first semiconductor layer 100 on the side of the first doped layer D1 facing away from the second semiconductor layer 150 is removed, for example, a portion of the first semiconductor layer 100 on the side of the first doped layer D1 facing away from the second semiconductor portion F2 is removed.

[0203] In some embodiments, after forming the storage unit 350, a portion of the first semiconductor layer 100 on the side of the first doped layer D1 facing away from the second semiconductor portion F2 is removed.

[0204] In some embodiments, the process of removing the portion of the first semiconductor layer 100 located on the side of the first doped layer D1 facing away from the second semiconductor portion F2 is a planarization process, such as a chemical mechanical polishing process.

[0205] In some embodiments, forming the isolation structure further comprises: Figure 35 and Figure 36 forming a second isolation portion 2002 extending through the first doped layer D1 and the portion of the first semiconductor layer 100 located between the first doped layer D1 and the first isolation portion 2001 along the first direction Z, the second isolation portion 2002 and the first isolation portion 2001 constituting an isolation structure 2003.

[0206] In some embodiments, the material of the second isolation portion 2002 is the same as the material of the first isolation portion 2001.

[0207] In other embodiments, the material of the second isolation portion 2002 is different from the material of the first isolation portion 2001.

[0208] The portion of the first semiconductor layer 100 located between the first doped layer D1 and the second semiconductor portion F2 and between the second isolation portions 2002 along the third direction X constitutes a first semiconductor portion F1. The second semiconductor portion F2 is located on the side of the first semiconductor portion F1 facing away from the first doped layer D1 along the first direction Z. The first semiconductor portion F1 and the second semiconductor portion F2 constitute a semiconductor body F. The gate layer 321 is located on at least one side of the semiconductor body F along the second direction Y. In some embodiments, the second doped region 120 is located on the side of the first doped region 130 facing the semiconductor body F.

[0209] In some embodiments, the size of the first semiconductor portion F1 along the first direction Z is less than or equal to 60 nm.

[0210] In some embodiments, the size of the second semiconductor portion F2 along the first direction Z is 80 nm to 200 nm.

[0211] With reference to Figure 35 and Figure 36 a bit line 400 extending along the second direction Y is formed on the side of the first doped layer D1 facing away from the semiconductor body F.

[0212] After removing the portion of the first semiconductor layer 100 located on the side of the first doped layer D1 facing away from the second semiconductor layer 150 and forming the second isolation portion 2002, a bit line 400 extending along the second direction Y is formed on the side of the first doped layer D1 facing away from the semiconductor body F.

[0213] In some embodiments, the process of forming the bit line 400 includes a deposition process, which includes a thin film deposition process of chemical vapor deposition, physical vapor deposition, atomic layer deposition, or any combination thereof.

[0214] Some embodiments of the present application also provide a semiconductor structure. Referring to Figure 20 and Figure 21 , the semiconductor structure includes a first doped layer D1, a semiconductor body F, and a gate layer 321.

[0215] In some embodiments, referring to Figure 20 and Figure 21 , the semiconductor body F is located at one side of the first doped layer D1 along a first direction Z, the semiconductor body F includes a first semiconductor portion F1 and a second semiconductor portion F2, and the second semiconductor portion F2 is located at one side of the first semiconductor portion F1 along the first direction Z away from the first doped layer D1.

[0216] In some embodiments, the gate layer 321 is located at least one side of the semiconductor body F along a second direction Y.

[0217] wherein the second direction Y intersects the first direction Z. For example, the first direction Z and the second direction Y are perpendicular.

[0218] The semiconductor structure can be a memory cell array, and the semiconductor structure can also be a part of a memory cell array.

[0219] In some embodiments, a dimension of the first semiconductor portion F1 along the first direction Z is less than or equal to 60 nm. It is to be noted that in other embodiments, the dimension of the first semiconductor portion F1 along the first direction Z is not limited.

[0220] In some embodiments, a dimension of the second semiconductor portion F2 along the first direction Z is 80 nm to 200 nm. In other embodiments, the dimension of the second semiconductor portion F2 along the first direction Z is not limited.

[0221] In some embodiments, a material of the first semiconductor portion F1 is the same as a material of the second semiconductor portion F2.

[0222] In other embodiments, a material of the first semiconductor portion F1 is different from a material of the second semiconductor portion F2.

[0223] In some embodiments, the material of the first semiconductor portion F1 includes any one of silicon, silicon germanium, silicon carbon, and a group III-V compound semiconductor material. The material of the second semiconductor portion F2 includes any one of silicon, silicon germanium, silicon carbon, and a group III-V compound semiconductor material.

[0224] In some embodiments, referring toFigure 20 and Figure 21 The first doped layer D1 includes a first doped region 130 and a second doped region 120, and the second doped region 120 is located on a side of the first doped region 130 facing the semiconductor body F.

[0225] In some embodiments, the second doped region 120 and the first doped region 130 have the same doping type, and the doping concentration of the second doped region 120 is less than the doping concentration of the first doped region 130.

[0226] In some embodiments, the first doped region 130 has a size along the first direction Z of 30 nm to 70 nm. In other embodiments, the size of the first doped layer D1 along the first direction Z is not limited.

[0227] In some embodiments, the second doped region 120 has a size along the first direction Z of 5 nm to 35 nm. It should be noted that in other embodiments, the size of the second doped region 120 along the first direction Z is not limited.

[0228] In some embodiments, the doping concentration of the first doped region 130 is distributed in different regions of the first doped region 130 from a first doping concentration to a second doping concentration, and the second doping concentration is greater than the first doping concentration. Wherein, the fourth doping concentration is less than or equal to 50 times the third doping concentration. The difference in doping concentration of the first doped region 130 in different regions of the first doped region 130 is relatively small.

[0229] In some embodiments, the doping concentration of the second doped region 120 is distributed in different regions of the second doped region 120 from a third doping concentration to a fourth doping concentration, and the fourth doping concentration is greater than the third doping concentration. Wherein, the fourth doping concentration is less than or equal to 10 times the third doping concentration. The difference in doping concentration of the second doped region 120 in different regions of the second doped region 120 is relatively small.

[0230] In some embodiments, the second doped region 120 is located on a side of the first doped region 130 facing the semiconductor body F.

[0231] In some embodiments, referring to Figure 20 and Figure 21 The semiconductor structure further includes a second doped layer D2 located in part of the second semiconductor portion F2. Wherein, the second doped layer D2 is a source region, and the first doped layer D1 is a drain region; or, the second doped layer D2 is a drain region, and the first doped layer D1 is a source region.

[0232] In some embodiments, referring to Figure 20 and Figure 21The semiconductor structure further includes an isolation structure 180 between the semiconductor bodies F adjacent along the third direction X and between the first doped layers D1 adjacent along the third direction X.

[0233] The third direction X intersects the first direction Z and the second direction Y, respectively. For example, the third direction X is perpendicular to the first direction Z and the third direction X is perpendicular to the second direction Y.

[0234] In some embodiments, the material of the isolation structure 180 includes an insulating dielectric material, such as silicon oxide, silicon nitride, silicon oxynitride, or silicon oxycarbide.

[0235] In some embodiments, the material of the gate layer 321 includes any one of a metal gate material and a polysilicon gate material. The material of the gate layer 321 can be, for example, any one or a combination of tungsten (W), cobalt (Co), copper (Cu), aluminum (Al), doped crystalline silicon, or silicide.

[0236] In some embodiments, referring to Figure 20 and Figure 21 The semiconductor structure further includes a gate dielectric layer 322 between the gate layer 321 and the semiconductor body F controlled by the gate layer 321.

[0237] In some embodiments, the material of the gate dielectric layer 322 can be a high-K (dielectric constant) dielectric material, for example, the dielectric constant K can be greater than 3.9. The material of the gate dielectric layer 322 can include any one of aluminum oxide, hafnium dioxide, zirconium dioxide, lanthanum oxide, and titanium oxide. In other embodiments, the material of the gate dielectric layer 322 is silicon oxide.

[0238] In some embodiments, referring to Figure 20 and Figure 21 The semiconductor structure further includes an isolation dielectric layer 310 on a side of the gate layer 321 facing away from the gate dielectric layer 322 and on a side of the gate layer 321 facing away from the first doped layer D1.

[0239] In some embodiments, the material of the isolation dielectric layer 310 is an insulating dielectric material, such as silicon oxide, silicon nitride, silicon oxynitride, or silicon oxycarbide.

[0240] It should be noted that in some embodiments, there is an isolation material between the gate layer 321 and the first doped layer D1.

[0241] In some embodiments, referring to Figure 20 and Figure 21 The semiconductor structure further includes a storage unit 350 on a side of the second doped layer D2 facing away from the first doped layer D1 and connected to the second doped layer D2.

[0242] In some embodiments, referring to Figure 20 and Figure 21 the semiconductor structure further comprises a connecting layer 340 between the memory cell 350 and the second doped layer D2. The connecting layer 340 can reduce the contact resistance between the memory cell 350 and the second doped layer D2.

[0243] In some embodiments, the material of the connecting layer 340 comprises a metal silicide.

[0244] In some embodiments, the memory cell 350 comprises at least one of a dynamic random access memory cell, a phase change memory cell, and a ferroelectric memory cell.

[0245] In some embodiments, the memory cell 350 is a capacitor for storing electric charges as binary information stored by the corresponding memory cell 350. In some embodiments, the memory cell 350 is a phase change memory (PCM) element (e.g., comprising a chalcogenide alloy) for storing binary information in different resistivities in amorphous and crystalline phases. In other embodiments, the memory cell 350 is a ferroelectric capacitor for storing binary information based on switching between two polarization states of a ferroelectric material under an external electric field.

[0246] In some embodiments, the memory cell 350 is a capacitor comprising a first electrode layer, a second electrode layer, and a capacitor dielectric layer. The capacitor dielectric layer is between the first electrode layer and the second electrode layer. Illustratively, the capacitor dielectric layer can enable storage and release of electric charges by changing a voltage state between the first electrode layer and the second electrode layer, thereby enabling storage and reading of information of the memory cell 350. The capacitor dielectric layer can be an insulating material such as silicon dioxide or silicon nitride, or other suitable materials. The material of the first electrode layer includes, but is not limited to, single crystalline silicon, polycrystalline silicon, doped single crystalline silicon, doped polycrystalline silicon, tungsten, copper, aluminum, platinum, titanium, or ruthenium, etc. The material of the second electrode layer includes, but is not limited to, single crystalline silicon, polycrystalline silicon, doped single crystalline silicon, doped polycrystalline silicon, tungsten, copper, aluminum, platinum, titanium, or ruthenium, etc. One of the first electrode layer and the second electrode layer is connected to the connecting layer 340.

[0247] In some embodiments, referring to Figure 20 and Figure 21 the semiconductor structure further comprises a bit line 400 on the side of the first doped layer D1 facing away from the semiconductor body F and extending along the second direction Y.

[0248] Some embodiments of the present application further provide a semiconductor structure. Referring to Figure 35 and Figure 36The semiconductor structure is different from the semiconductor structure of the foregoing embodiment in that the isolation structure 2003 includes a first isolation portion 2001 and a second isolation portion 2002. The first isolation portion 2001 is located between second semiconductor portions F2 adjacent in the third direction X. The second isolation portion 2002 is located between first doped layers D1 adjacent in the third direction X and between first semiconductor portions F1 adjacent in the third direction X.

[0249] In some embodiments, the material of the second isolation portion 2002 is the same as the material of the first isolation portion 2001.

[0250] In some other embodiments, the material of the second isolation portion 2002 is different from the material of the first isolation portion 2001.

[0251] For other details of the semiconductor structure in the present embodiment, refer to the semiconductor structure of the foregoing embodiment, and no longer be described in detail.

[0252] Another embodiment of the present application further provides a memory, referring to Figure 37 , comprising: a memory cell array 402 including the semiconductor structure provided by the foregoing embodiments of the present application; and a peripheral circuit 401 coupled to the memory cell array 402.

[0253] The semiconductor structure can be the same as the semiconductor structure described in any of the foregoing embodiments, and the embodiments of the present application will not be described again.

[0254] In some embodiments, the memory cell array 402 includes a DRAM cell array. For ease of description, the DRAM cell array can be used as an example for describing the memory cell array 402 in the present application. However, it should be understood that the memory cell array 402 is not limited to the DRAM cell array, and can include any other suitable type of memory cell array that can use transistors as switching and selector devices, such as a PCM cell array, a static random-access memory (SRAM) cell array, a ferroelectric random-access memory cell array, a resistive memory cell array, a magnetic memory cell array, a spin transfer torque (STT) memory cell array, just to name a few, or any combination thereof.

[0255] In some embodiments, the peripheral circuitry 401 (also referred to as control and sensing circuitry) can include any suitable digital, analog, and / or mixed-signal circuitry for facilitating the operation of the memory cell array 402. For example, the peripheral circuitry 401 can include one or more of a page buffer, decoders (e.g., row decoders and column decoders), sense amplifiers, drivers (e.g., word line drivers), input / output (I / O) circuitry, charge pumps, voltage sources or generators, current or voltage references, any portion of the aforementioned functional circuitry (e.g., sub-circuitry), or any active or passive components of the circuitry (e.g., transistors, diodes, resistors, or capacitors).

[0256] Yet another embodiment of the present application also provides a memory system 30000, referring to Figure 38 The memory system 30000 includes a controller 32200 and a memory 32100 provided by the above-mentioned embodiments of the present application. The controller 32200 is coupled to the memory 32100 and configured to control the memory 32100 to store data.

[0257] The memory system 30000 can be a mobile phone, a desktop computer, a laptop computer, a tablet computer, an in-vehicle computer, a game console, a printer, a positioning device, a wearable electronic device, a smart sensor, a virtual reality (VR) device, an argument reality (AR) device, or any other suitable electronic device having a storage device located therein. As shown in Figure 38 Figure 38 The memory system 30000 also includes a host 31000. The host 31000 can be a processor of an electronic device, such as a central processing unit (CPU), or can be a system-on-chip (SoC), such as an application processor (AP). The host 31000 can be configured to send or receive data to or from the memory 32100.

[0258] According to some embodiments, the controller 32200 is coupled to the memory 32100 and the host 31000, and is configured to control the memory 32100. The controller 32200 can manage data stored in the memory 32100 and communicate with the host 31000. In some embodiments, the controller 32200 is designed to work in a low duty cycle environment, such as a secure digital (SD) card, a compact Flash (CF) card, a universal serial bus (USB) flash drive, or other media used in electronic devices such as personal computers, digital cameras, mobile phones, etc. In some embodiments, the controller 32200 is designed to work in a high duty cycle environment, such as an SSD used as data storage for mobile devices such as smart phones, tablets, laptops, etc., and enterprise storage arrays, and embedded multi-media-cards (eMMC). The controller 32200 can be configured to control operations of the memory 32100, such as read, erase, and program operations. The controller 32200 can also be configured to manage various functions related to data stored in or to be stored in the memory 32100, including but not limited to bad block management, garbage collection, logical to physical address translations, wear leveling, etc. In some embodiments, the controller 32200 is further configured to process error correction codes (ECCs) related to data read from or written to the memory 32100. Any other appropriate functions can also be performed by the controller 32200, for example, formatting the memory 32100. The controller 32200 can communicate with external devices (e.g., the host 31000) according to a particular communication protocol.For example, the controller 32200 can communicate with external devices through at least one of various interface protocols, such as a USB protocol, an MMC protocol, a peripheral component interconnection (PCI) protocol, a PCI-express (PCI-E) protocol, an advanced technology attachment (ATA) protocol, a serial ATA protocol, a parallel ATA protocol, a small computer small interface (SCSI) protocol, an enhanced small disk interface (ESDI) protocol, an integrated drive electronics (IDE) protocol, a Firewire protocol, or the like.

[0259] Although exemplary methods of fabrication and structures of semiconductor structures are described herein, it is understood that one or more features can be omitted, substituted, or added from the structures of the semiconductor structures. Further, the materials of the example layers are merely exemplary.

[0260] The above description is merely exemplary of the application and of the application of the principles of the application. It is understood that variations in the described embodiments can be made by those skilled in the art without departing from the scope of the application. For example, the features of the described embodiments can be combined with other features disclosed herein (but not limited to) that have similar functions without departing from the scope of the application.

Claims

1. A semiconductor structure, comprising: a first doped layer; a semiconductor body located on one side of the first doped layer along a first direction, the semiconductor body comprising a first semiconductor portion and a second semiconductor portion, the second semiconductor portion located on a side of the first semiconductor portion away from the first doped layer along the first direction; and a gate layer located on at least one side of the semiconductor body along a second direction; wherein the second direction intersects the first direction. The first semiconductor portion has a dimension along the first direction less than or equal to 60 nm. The second semiconductor portion has a dimension along the first direction of 80 nm to 200 nm. The first semiconductor portion and the second semiconductor portion have the same material, or the first semiconductor portion and the second semiconductor portion have different materials. The material of the first semiconductor portion comprises any one of silicon, silicon germanium, silicon carbon and a III-V compound semiconductor material. The material of the second semiconductor portion comprises any one of silicon, silicon germanium, silicon carbon and a III-V compound semiconductor material. The first doped layer comprises: a first doped region; and a second doped region located on a side of the first doped region facing the semiconductor body; wherein the second doped region and the first doped region have the same doping type, and the second doped region has a doping concentration less than that of the first doped region. The first doped region has a dimension along the first direction of 30 nm to 70 nm. The second doped region has a dimension along the first direction of 5 nm to 35 nm. The first doped region has a doping concentration distributed in different regions of the first doped region from a first doping concentration to a second doping concentration, the second doping concentration being greater than the first doping concentration; wherein the second doping concentration is less than or equal to 50 times the first doping concentration. The second doped region has a doping concentration distributed in different regions of the second doped region from a third doping concentration to a fourth doping concentration, the fourth doping concentration being greater than the third doping concentration; wherein the fourth doping concentration is less than or equal to 10 times the third doping concentration. The semiconductor structure further comprises: a second doped layer located in part of the second semiconductor portion; wherein the second doped layer is a source region, and the first doped layer is a drain region; or the second doped layer is a drain region, and the first doped layer is a source region. The semiconductor structure further comprises: an isolation structure located between the semiconductor bodies adjacent along a third direction and between the first doped layers adjacent along the third direction; wherein the third direction intersects the first direction and the second direction respectively. The isolation structure comprises: a first isolation portion located between the semiconductor bodies adjacent along the third direction; and a second isolation portion located between the first doped layers adjacent along the third direction; wherein the first isolation portion and the second isolation portion have different materials, or the first isolation portion and the second isolation portion have the same material. The semiconductor structure further comprises: ​ ​ ​ ​ ​ 2. The semiconductor structure of claim 1, wherein, ​ 3. The semiconductor structure of claim 1, wherein, ​ 4. The semiconductor structure of claim 1, wherein, ​ 5. The semiconductor structure of claim 1 or 4, wherein, ​ 6. The semiconductor structure of claim 1, wherein, ​ ​ ​ ​ 7. The semiconductor structure of claim 6, wherein, ​ 8. The semiconductor structure of claim 6, wherein, ​ 9. The semiconductor structure of claim 6, wherein, ​ ​ 10. The semiconductor structure of claim 6, wherein, ​ ​ 11. The semiconductor structure of claim 1, wherein, ​ ​ ​ 12. The semiconductor structure of claim 1, wherein, ​ ​ ​ 13. The semiconductor structure of claim 12, wherein, ​ ​ ​ ​ 14. The semiconductor structure of claim 11, wherein, ​ a storage unit located on a side of the second doped layer away from the first doped layer and connected with the second doped layer.

15. A method for manufacturing a semiconductor structure, comprising: forming a first doped layer; forming a semiconductor body located on a side of the first doped layer along a first direction, the semiconductor body comprising a first semiconductor portion and a second semiconductor portion located on a side of the first semiconductor portion along the first direction away from the first doped layer; forming a gate layer located on at least one side of the semiconductor body along a second direction; wherein the second direction intersects the first direction.

16. The method of producing a semiconductor structure according to claim 15, wherein, forming the first doped layer and the semiconductor body comprises: forming a first doped layer in a first semiconductor layer; in response to forming the first doped layer, forming a second semiconductor layer on a side of the first semiconductor layer along a first direction; wherein the method further comprises: forming a plurality of isolation structures spaced apart along a third direction and the second direction, the isolation structures penetrating the second semiconductor layer, the first doped layer, and a portion of the first semiconductor layer between the second semiconductor layer and the first doped layer along the first direction; wherein the first semiconductor layer and the second semiconductor layer, on a side of the first doped layer along the first direction and between isolation structures adjacent along the third direction, constitute the semiconductor body; wherein the third direction intersects the first direction and the second direction respectively.

17. The method of making according to claim 16, wherein, forming the first doped layer in the first semiconductor layer comprises: implanting ions in the first semiconductor layer to form a first initial doped layer; and performing annealing treatment on the first initial doped layer to form the first doped layer.

18. The method of making according to claim 17, wherein, implanting ions in the first semiconductor layer to form the first initial doped layer comprises: forming, by an ion implantation process, a first initial doped layer comprising a first initial doped region and a second initial doped region in the first semiconductor layer; wherein performing annealing treatment on the first initial doped layer comprises: performing annealing treatment on the first initial doped region and the second initial doped region to form a first doped region and a second doped region respectively; wherein the second doped region is located on a side of the first doped region facing the semiconductor body, the second doped region and the first doped region have the same type of doping, and the second doped region has a doping concentration less than that of the first doped region.

19. The method of making according to claim 17, wherein, the method further comprises: forming a protective layer on a first surface of the first semiconductor layer on a side of the first semiconductor layer along the first direction; and after performing the annealing treatment and before forming the second semiconductor layer, removing part or all of the protective layer on the first surface; wherein implanting ions in the first semiconductor layer to form the first initial doped layer comprises: implanting the ions into the first semiconductor layer through the protective layer to form the first initial doped layer.

20. The method of making according to claim 19, wherein, a material of the protective layer comprises an insulating dielectric material.

21. The method of fabricating a semiconductor structure of claim 16, wherein, forming the isolation structures comprises: forming a plurality of initial isolation structures spaced along the third direction and extending along the second direction, the initial isolation structures penetrating the first doped layer, and portions of the second semiconductor layer and the first semiconductor layer on the same side of the first doped layer along the first direction; forming a cut groove extending along the third direction in the first semiconductor layer, the second semiconductor layer, and the initial isolation structures, the cut groove exposing the first doped layer, wherein the initial isolation structures are divided into the isolation structures by the cut groove.

22. The method of fabricating a semiconductor structure of claim 16, wherein, forming the isolation structures includes forming a plurality of first initial isolation portions on one side of the first semiconductor layer along the first direction, the first initial isolation portions being spaced along the third direction and extending along the second direction; forming the second semiconductor layer on one side of the first semiconductor layer along the first direction includes forming the second semiconductor layer between adjacent first initial isolation portions; forming the isolation structures further includes: forming a cut groove extending along the third direction in the first semiconductor layer, the second semiconductor layer, and the first initial isolation portions, the cut groove exposing the first doped layer, the first initial isolation portions being divided into first isolation portions by the cut groove; and forming second isolation portions penetrating the first doped layer, and portions of the first semiconductor layer between the first doped layer and the first isolation portions along the first direction, the second isolation portions and the first isolation portions constituting the isolation structures.

23. The method of producing a semiconductor structure according to claim 21 or 22, wherein, forming the gate layer includes forming the gate layer in the cut groove.

24. The method of fabricating a semiconductor structure according to any one of claims 16 to 22, wherein, The preparation method further includes: removing portions of the first semiconductor layer on the side of the first doped layer away from the second semiconductor layer; and forming a bit line extending along the second direction on the side of the first doped layer away from the semiconductor body.

25. The method of manufacturing according to claim 15, wherein, The preparation method further includes: forming a second doped layer in portions of the second semiconductor portion; wherein the second doped layer is a source region, and the first doped layer is a drain region; or the second doped layer is a drain region, and the first doped layer is a source region.

26. The method of manufacturing according to claim 25, wherein, The preparation method further includes: forming a memory cell on the side of the second doped layer away from the first doped layer, the memory cell being connected to the second doped layer.

27. A memory wherein, comprising: a memory cell array including the semiconductor structure as claimed in any one of claims 1 to 14 or the semiconductor structure formed by the preparation method as claimed in any one of claims 15 to 26; and a peripheral circuit coupled to the memory cell array. comprising:

28. A memory system, wherein, the memory as claimed in claim 27; and a controller coupled to the memory and configured to control the memory to store data. comprising: the memory as claimed in claim 27; and a controller coupled to the memory and configured to control the memory to store data.

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