Display device, display module, and electronic apparatus

Abstract

Provided is a novel display device having excellent convenience, practicality, and reliability. The display device comprises a first functional layer, a second functional layer, a first substrate and a second substrate. The first functional layer includes a first region and a second region, and the first functional layer is bent in the second region. The first region is sandwiched between the second functional layer and the first substrate, the first region including a first layer and a pixel circuit sandwiched between the second functional layer and the first layer. The second region is adjacent to the first region, the second region includes a second layer and a first shift register, the second layer is continuous with the first layer, and the first shift register is formed on the second layer. The second functional layer is sandwiched between the second substrate and the first area, and the second functional layer comprises a display device which is electrically connected with the pixel circuit.

Description

TECHNICAL FIELD

[0001] One embodiment of the present application relates to a display device, a display module, an electronic device, or a semiconductor device.

[0002] Note that one embodiment of the present application is not limited to the technical field described above. The technical field of one embodiment of the present application disclosed in this specification and the like relates to an object, a method, or a manufacturing method. In addition, one embodiment of the present application relates to a process, a machine, a manufacture, or a composition of matter. Thus, more specifically, examples of the technical field of one embodiment of the present application disclosed in this specification are a semiconductor device, a display device, a light-emitting device, a power storage device, a memory device, a driving method thereof, or a manufacturing method thereof. BACKGROUND

[0003] Mobile devices such as smartphones are required to be small and light to improve portability, and are also required to have a display region of a display enlarged to improve visibility to display more information. In addition, there is a significant demand for head-mounted displays (HMDs) typified by augmented reality (AR) and virtual reality (VR), and there is a great demand for narrow bezelization, which is a technique for reducing a region of a display that is not useful for display.

[0004] In addition, a flexible printed circuit board and an external driver IC and the like for extracting a terminal to the outside exist in a bezel portion of a liquid crystal display (LCD). Thus, a method in which a display portion and an input portion are connected to the same flexible printed circuit board or a method in which a gate driver is built in, or the like is employed for the purpose of narrow bezelization.

[0005] Note that a flexible display in which a display element and a driver circuit are provided over a substrate having flexibility and can be bent has been put into practical use. In addition, since the flexible display is thin and light, it is suitable for portable information terminal devices such as smartphones. Patent Document 1 describes a structure in which a connection terminal is folded back to the side opposite to a display surface by bending a portion of a display device having flexibility.

[0006] [Prior Art Documents]

[0007] [Patent Documents]

[0008] [Patent Document 1] Japanese Published Patent Application No. 2014-197181 SUMMARY

[0009] Technical problem to be solved by the invention

[0010] As described above, various inventions are disclosed in prior art documents, but there are many problems in convenience, practicality, or reliability, and thus they are not satisfactory. Thus, one of objects of one embodiment of the present application is to provide a novel display device which is excellent in convenience, practicality, or reliability. In addition, one of objects of the present application is to provide a novel display module which is excellent in convenience, practicality, or reliability. In addition, one of objects of the present application is to provide a novel electronic device which is excellent in convenience, practicality, or reliability. In addition, one of objects of the present application is to provide a novel display device, a novel display module, a novel electronic device, or a novel semiconductor device.

[0011] Note that the description of these objects does not preclude the existence of other objects. Note that one embodiment of the present application does not need to achieve all the above-described objects. In other words, an object other than those described above can be apparent from the description of the specification, the attached drawings, and the like, and can be derived from the description of the specification, the attached drawings, and the like.

[0012] Means of solving the technical problem

[0013] (1) One embodiment of the present application is a display device including a first functional layer, a second functional layer, a first substrate, and a second substrate.

[0014] The first functional layer includes a first region and a second region, and the first functional layer is bent in the second region.

[0015] The first region is interposed between the second functional layer and the first substrate, and the first region includes a first layer and a pixel circuit. The pixel circuit is interposed between the second functional layer and the first layer.

[0016] The second region is adjacent to the first region, and the second region includes a second layer and a first shift register.

[0017] The second layer is continuous with the first layer, and the first shift register is formed over the second layer.

[0018] The second functional layer is interposed between the second substrate and the first region, and the second functional layer includes a display element. The display element is electrically connected to the pixel circuit.

[0019] (2) In addition, one embodiment of the present application is the above-described display device including a first driver circuit.

[0020] The first driver circuit includes the first shift register, and the first functional layer includes a signal line. The signal line electrically connects the first driver circuit and the pixel circuit, and the signal line transmits an image signal.

[0021] Thus, the first drive circuit can be provided in the second region to supply an image signal to the signal line. In addition, the pixel circuit and the display element can be provided in the first region adjacent to the second region to display an image. Further, since the first functional layer is bent in the second region, the second region can be difficult to be recognized in a state of being directly opposite to the first region. In addition, a region surrounding the first region in a frame shape in a state of being directly opposite to the first region can be difficult to be recognized. As a result, a novel display device excellent in convenience, practicality, or reliability can be provided.

[0022] (3) In addition, one embodiment of the present application is the above display device including a second drive circuit.

[0023] The second drive circuit includes a second shift register, the first functional layer includes a third region and a scan line, and the first functional layer is bent in the third region.

[0024] The third region is adjacent to the first region, and the third region includes a third layer and the second shift register. In addition, the third layer is continuous with the first layer, and the second shift register is formed over the third layer.

[0025] The scan line electrically connects the second drive circuit and the pixel circuit, and the scan line transmits a selection signal.

[0026] Thus, the second drive circuit can be provided in the third region to supply a selection signal to the scan line. In addition, the pixel circuit and the display element can be provided in the first region adjacent to the third region to display an image. Further, since the first functional layer is bent in the third region, the third region can be difficult to be recognized in a state of being directly opposite to the first region. In addition, a region surrounding the first region in a frame shape in a state of being directly opposite to the first region can be difficult to be recognized. As a result, a novel display device excellent in convenience, practicality, or reliability can be provided.

[0027] (4) In addition, one embodiment of the present application is the above display device including a first electrode and a third drive circuit.

[0028] The second functional layer is interposed between the first electrode and the first functional layer, and the third drive circuit includes a third shift register.

[0029] The first functional layer includes a fourth region and a second electrode, and the first functional layer is bent in the fourth region.

[0030] The fourth region is adjacent to the first region, and the fourth region includes a fourth layer and the third shift register. In addition, the fourth layer is continuous with the first layer, and the third shift register is formed over the fourth layer.

[0031] The second electrode and the first electrode form a capacitor, the second electrode is electrically connected to the third drive circuit, and the second electrode transmits a pulse signal.

[0032] Thus, the third driver circuit is provided in the fourth region, and a pulse signal can be supplied to the second electrode. Further, the first electrode is provided over the adjacent first region, and a change in a projected capacitance generated between the second electrode can be detected. Further, a position of a finger of a user approaching the display device can be detected. Further, since the first functional layer is bent in the fourth region, the fourth region can be hardly recognized in a state where the first region is directly opposite. Further, a region surrounding the first region in a frame-like manner in a state where the first region is directly opposite can be hardly recognized. As a result, a novel display device which is excellent in convenience, practicality, or reliability can be provided.

[0033] (5) Further, one embodiment of the present application is the above display device including a first functional layer including a spacer and a transistor.

[0034] The spacer includes a first surface, a second surface, a third surface, and a first opening portion. The first surface, the second surface, and the third surface have insulating properties. The second surface is opposite to the first surface, and the second surface is closer to the second functional layer than the first surface. The third surface connects the first surface and the second surface, and the third surface is positioned on a side surface of the first opening portion.

[0035] The transistor includes a third electrode, a fourth electrode, a fifth electrode, a semiconductor layer, and an insulating layer. The third electrode includes a region in contact with the first surface and a region overlapping with the first opening portion.

[0036] The fourth electrode includes a region in contact with the second surface, a second opening portion, and a fourth surface. The fourth surface is positioned on a side surface of the second opening portion, and the second opening portion overlaps with the first opening portion.

[0037] The fifth electrode includes a region opposite to the third surface, and the insulating layer includes a region sandwiched between the third surface and the fifth electrode.

[0038] The semiconductor layer includes a region sandwiched between the third surface and the insulating layer, and the semiconductor layer is in contact with the third electrode in the first opening portion. Further, the semiconductor layer is in contact with the fourth electrode on the fourth surface.

[0039] (6) Further, one embodiment of the present application is the above display device including a first shift register including the above transistor.

[0040] Thus, the occupied area of the transistor can be reduced. Further, the channel length of the transistor can be reduced. Further, the on-state current of the transistor can be increased. Further, unevenness in the operation characteristics of the transistor can be reduced. Further, at least part of the first shift register can be formed in a process of forming a pixel circuit. Further, the manufacturing process of the display device can be simplified. As a result, a novel display device which is excellent in convenience, practicality, or reliability can be provided.

[0041] (7) In addition, one embodiment of the present application is the display device including the pixel circuit including the transistor described above.

[0042] Thus, the area occupied by the transistor can be reduced. In addition, the channel length of the transistor can be reduced. In addition, the on-state current of the transistor can be increased. In addition, the unevenness of the operation characteristics of the transistor can be reduced. In addition, the area occupied by the pixel circuit can be reduced. Furthermore, the resolution of the display device can be increased. As a result, a novel display device which is excellent in convenience, utility, or reliability can be provided.

[0043] (8) In addition, one embodiment of the present application is the display device including the fifth layer and the fifth layer includes a liquid crystal material.

[0044] Thus, for example, a reflective display using external light can be performed. Furthermore, the power consumption of the display device can be reduced. In addition, since the first functional layer is bent in the second region, the second region can be hardly recognized in a state in which the first region is directly opposite to the second region. In addition, a region which surrounds the first region in a frame shape in a state in which the first region is directly opposite to the second region can be hardly recognized. As a result, a novel display device which is excellent in convenience, utility, or reliability can be provided.

[0045] (9) In addition, one embodiment of the present application is a display module including the display device described above and at least one of a connector and an integrated circuit.

[0046] (10) In addition, one embodiment of the present application is a display module including the display device described above and a light source.

[0047] The first layer has a transmittance of 80 % or more in a visible light region.

[0048] The first substrate includes a first end portion and a second end portion which is opposite to the first end portion and is positioned between the first end portion and the second layer. In addition, the first substrate has a function of distributing light incident from the first end portion to the second substrate.

[0049] The light source is opposite to the first end portion and emits light to the first end portion.

[0050] Thus, the range of light irradiation by the light source can be made narrower than in a structure in which the light source is arranged with the first substrate interposed between the first region. In addition, the thickness of the display device can be made thinner than in a structure in which the light source is arranged with the first substrate interposed between the first region. Further, since the first functional layer is bent in the second region, the second region can be difficult to be recognized in a state in which the second region is directly opposite the first region. In addition, a region surrounding the first region in a frame-like manner can be difficult to be recognized in a state in which the region is directly opposite the first region. As a result, a novel display device which is excellent in convenience, practicality, or reliability can be provided.

[0051] (11) Furthermore, one embodiment of the present application is an electronic device including the above display device, and at least one of a battery, a camera, a speaker, and a microphone.

[0052] In the drawings of the present specification, a block diagram in which constituent elements are shown as blocks independent of one another according to their functions is shown, but actual constituent elements are difficult to be completely classified according to their functions, and one constituent element can involve a plurality of functions.

[0053] Note that the light-emitting device in this specification includes an image display device using a light-emitting element. Furthermore, the light-emitting device sometimes includes a module in which a light-emitting element is mounted on a connector such as an anisotropic conductive film or a TCP (Tape Carrier Package); a module in which a printed wiring board is provided at an end portion of a TCP; or a module in which an IC (Integrated Circuit) is directly mounted on a light-emitting element by a COG (Chip On Glass) method. Further, an illumination device or the like sometimes includes a light-emitting device.

[0054] Effects of Invention

[0055] According to one embodiment of the present application, a novel display device which is excellent in convenience, practicality, or reliability can be provided. In addition, according to one embodiment of the present application, a novel display module which is excellent in convenience, practicality, or reliability can be provided. Further, according to one embodiment of the present application, a novel electronic device which is excellent in convenience, practicality, or reliability can be provided. In addition, a novel display device can be provided. In addition, a novel display module can be provided. Further, a novel electronic device can be provided.

[0056] Note that the description of these effects does not preclude the presence of other effects. One embodiment of the present application does not necessarily achieve all the effects described above. In addition, an effect other than those described above can be derived from the description, the drawings, and the like. BRIEF DESCRIPTION OF DRAWINGS

[0057] FIG. 1A and FIG. 1B is a diagram illustrating a structure of a display device according to an embodiment.

[0058] FIGS. 2A-2C is a diagram illustrating a structure of a display device according to an embodiment.

[0059] FIG. 3 is a diagram illustrating a structure of a display device according to an embodiment.

[0060] FIG. 4A and FIG. 4B is a diagram illustrating a structure of a display device according to an embodiment.

[0061] FIG. 5 is a diagram illustrating a structure of a display device according to an embodiment.

[0062] FIG. 6A and FIG. 6B is a diagram illustrating a structure of a display device according to an embodiment.

[0063] FIGS. 7A-7C is a diagram illustrating a structure of a display device according to an embodiment.

[0064] FIG. 8A , FIG. 8C and FIG. 8D is a diagram illustrating a structure of a display device according to an embodiment. FIG. 8B is a diagram illustrating an operation of a display device according to an embodiment.

[0065] FIG. 9 is a diagram illustrating a structure of a touch panel module according to an embodiment.

[0066] FIGS. 10A-10C is a diagram illustrating a structure of a touch panel module according to an embodiment.

[0067] FIGS. 11A-11C is a diagram illustrating a structure of a shift register according to an embodiment.

[0068] FIG. 12 is a diagram illustrating a structure of a signal output circuit according to an embodiment.

[0069] FIG. 13 is a diagram illustrating a structure of a signal output circuit according to an embodiment.

[0070] FIG. 14 is a diagram illustrating a structure of a signal output circuit according to an embodiment.

[0071] FIGS. 15A-15D is a diagram illustrating a structure of a transistor according to an embodiment.

[0072] FIGS. 16A-16F FIG. 1 is a diagram illustrating a structure of a transistor according to an embodiment.

[0073] FIG. 17A and FIG. 17B FIG. 1 is a diagram illustrating a structure of a transistor according to an embodiment.

[0074] FIG. 18A and FIG. 18B FIG. 1 is a diagram illustrating a structure of a transistor according to an embodiment.

[0075] FIGS. 19A-19D FIG. 1 is a diagram illustrating a structure of a transistor according to an embodiment.

[0076] FIGS. 20A-20D FIG. 1 is a diagram illustrating a structure of a transistor according to an embodiment.

[0077] FIG. 21 FIG. 1 is a diagram illustrating a structure of a signal output circuit according to an embodiment.

[0078] FIG. 22A and FIG. 22B FIG. 1 is a diagram illustrating a structure of a signal output circuit according to an embodiment.

[0079] FIG. 23A and FIG. 23B FIG. 1 is a diagram illustrating a structure of a signal output circuit according to an embodiment.

[0080] FIG. 24 FIG. 1 is a diagram illustrating a structure of a signal output circuit according to an embodiment.

[0081] FIG. 25 FIG. 1 is a diagram illustrating an operation of a signal output circuit according to an embodiment.

[0082] FIG. 26 FIG. 1 is a diagram illustrating an operation of a signal output circuit according to an embodiment.

[0083] FIG. 27 FIG. 1 is a diagram illustrating an operation of a signal output circuit according to an embodiment.

[0084] FIG. 28 FIG. 1 is a diagram illustrating an operation of a signal output circuit according to an embodiment.

[0085] FIG. 29 FIG. 1 is a diagram illustrating an operation of a signal output circuit according to an embodiment.

[0086] FIG. 30 FIG. 1 is a diagram illustrating an operation of a signal output circuit according to an embodiment.

[0087] FIG. 31is a view that explains the operation of a signal output circuit according to an embodiment.

[0088] FIG. 32 is a view that explains the operation of a signal output circuit according to an embodiment.

[0089] FIG. 33 is a view that explains the structure of a transistor according to an embodiment.

[0090] FIG. 34 is a view that explains the operation of a shift register according to an embodiment.

[0091] FIG. 35 is a view that explains the structure of a display module according to an embodiment.

[0092] FIG. 36 is a view that explains the structure of a display module according to an embodiment.

[0093] FIG. 37 is a view that explains the structure of a display module according to an embodiment.

[0094] FIG. 38 is a view that explains the structure of a display module according to an embodiment.

[0095] FIG. 39 is a view that explains the structure of a display module according to an embodiment.

[0096] FIG. 40 is a view that explains the structure of a display module according to an embodiment.

[0097] FIGS. 41A-41F is a view that explains the structure of an electronic device according to an embodiment.

[0098] Embodiment of the Invention

[0099] A display device of one embodiment of the present application includes a first functional layer, a second functional layer, a first substrate, and a second substrate. The first functional layer includes a first region and a second region, and the first functional layer is bent in the second region. The first region is interposed between the second functional layer and the first substrate, and the first region includes a first layer and a pixel circuit, the pixel circuit being interposed between the second functional layer and the first layer. The second region is adjacent to the first region, and the second region includes a second layer and a first shift register, the second layer being continuous with the first layer, and the first shift register being formed over the second layer. The second functional layer is interposed between the second substrate and the first region, and the second functional layer includes a display element electrically connected to the pixel circuit.

[0100] Therefore, a first driving circuit can be configured in the second region to supply image signals to the signal line. Additionally, pixel circuits and display devices can be configured in the adjacent first region to display images. Furthermore, because the first functional layer is curved in the second region, the second region is difficult to identify when it is directly opposite the first region. Also, the area surrounding the first region in a border-like shape when directly opposite the first region is difficult to identify. As a result, a novel display device with excellent convenience, practicality, and reliability can be provided.

[0101] The embodiments will be described in detail with reference to the accompanying drawings. Note that the present invention is not limited to the following description, and those skilled in the art will readily understand that its methods and details can be varied in many ways without departing from the spirit and scope of the invention. Therefore, the present invention should not be construed as being limited only to the contents described in the embodiments shown below. Note that in the inventive structures described below, the same reference numerals are used in different drawings to denote the same parts or parts having the same function, and repeated descriptions are omitted. (Implementation Method 1)

[0102] In this embodiment, the structure of a display device according to one aspect of the present invention will be described with reference to Figures 1 to 6.

[0103] FIG. 1A This is a perspective view schematically illustrating the structure of a display device according to one aspect of the present invention. FIG. 1B This is a cross-sectional view schematically illustrating the structure of a display device according to one aspect of the present invention.

[0104] FIG. 2A This is an explanation FIG. 1B The image shows a front view of a portion of a display device according to one embodiment of the present invention. Additionally, FIG. 2B It is along FIG. 2A The cross-sectional view of the cut-off line Q1-Q2 is shown below. FIG. 2C It is along FIG. 2A The cross-sectional view of the cut-off line Q3-Q4 is shown.

[0105] FIG. 3 This is a front view of a display device illustrating one aspect of the present invention.

[0106] FIG. 4A This is an explanation FIG. 3 The image shows a front view of a portion of a display device according to one aspect of the present invention. FIG. 4B It is along FIG. 4A The cross-sectional view of the cut-off line P1-P2 is shown.

[0107] FIG. 5 This is a detailed explanation. FIG. 4BA diagram of a part of the structure shown. Note that hatching of part of the components is omitted for simplicity.

[0108] FIG. 6A is a perspective view schematically illustrating a structure of a display device of one embodiment of the present application, FIG. 6B is a cross-sectional view taken along the line FIG. 6A of the cutting line Q1-Q2 shown.

[0109] <Structure Example 1 of Display Device>

[0110] A display device of one embodiment of the present application includes a functional layer 510, a functional layer 520, a substrate SUB1, and a substrate SUB2 (see FIG. 1A). FIG. 1A and FIG. 1B ).

[0111] <<Structure Example 1 of Functional Layer 510>

[0112] The functional layer 510 includes a region 510_1 and a region 510_2, and the functional layer 510 is bent in the region 510_2 (see FIG. 1A). FIG. 1B ).

[0113] The region 510_1 is interposed between the functional layer 520 and the substrate SUB1, and includes a layer 511_1 and a pixel circuit 530. The pixel circuit 530 is interposed between the functional layer 520 and the layer 511_1. The functional layer 510 includes a transistor 200.

[0114] The region 510_2 is adjacent to the region 510_1, and includes a layer 511_2 and a shift register SR1 (see FIG. 1A). FIG. 2A and FIG. 2B Note that for simplicity of explanation, the region 510_2 is deformed from a bent state to an extended state to FIG. 2A and FIG. 2B the functional layer 510 is shown.

[0115] The layer 511_2 is continuous to the layer 511_1, and the shift register SR1 is formed over the layer 511_2.

[0116] [Structure Example of Layer 511]

[0117] The layer 511 includes the layer 511_1 and the layer 511_2. For example, an inorganic material, an organic material, and a material in which an inorganic material and an organic material are stacked can be used for the layer 511.

[0118] Specifically, a material containing oxygen and silicon, a material containing nitrogen and silicon, and a material containing oxygen and tungsten can be used for the layer 511.

[0119] In addition, epoxy resin, acrylic resin, silicone resin, phenolic resin, polyimide resin, imide resin, PVC (polyvinyl chloride) resin, PVB (polyvinyl butyral) resin, EVA (ethylene vinyl acetate) resin, etc. can be used for layer 511. In particular, polyimide resin with excellent heat resistance can be suitable for use as layer 511.

[0120] The above structure allows layer 511_2 to be bent. Furthermore, pixel circuitry 530 and shift register SR1 can be formed on layer 511. Additionally, degradation and deterioration of layer 511 caused by heat applied during the manufacturing process can be suppressed.

[0121] Alternatively, functional layers 510 and 520 can be fabricated using a manufacturing process substrate with layer 511 formed thereon, bonded to substrate SUB2, and then the manufacturing process substrate can be peeled off from functional layer 510. For example, the manufacturing process substrate can be peeled off from functional layer 510 by irradiating functional layer 510 with a laser through it. This allows a portion of the manufacturing process to be performed while the workpiece is rigid. Furthermore, after separating the manufacturing process substrate, the substrate can be made flexible.

[0122] <<Structural Example 1 of Functional Layer 520>>

[0123] Functional layer 520 is sandwiched between substrate SUB2 and region 510_1 (see reference). FIG. 1B ).

[0124] The functional layer 520 includes a display device 550, which is electrically connected to the pixel circuit 530.

[0125] <<Structure Example of Display Device 550>>

[0126] For example, a liquid crystal device 550LC can be used in a display device 550 (see reference). FIG. 3 Note that the invention is not limited to liquid crystal devices; various display devices can be used in the display apparatus according to one aspect of the invention. For example, light-emitting devices and the like can be used in display device 550.

[0127] Furthermore, the liquid crystal device 550LC includes an electrode 551LC, an electrode 552LC, and a layer 553LC containing liquid crystal. The electrode 552LC is arranged such that it forms an electric field with the electrode 551LC to control the orientation of the liquid crystal material (see reference). FIG. 4B Electrode 551LC is a pixel electrode.

[0128] For example, electrode 551LC can be in a comb-like shape, and electrode 552LC can be configured to form a transverse electric field or a marginal electric field with electrode 552LC (see reference). FIG. 3). Note that the electrode 551LC is sandwiched between the layer 553LC including liquid crystal and the electrode 552LC.

[0129] For example, the electrode 551LC can be arranged so as to form a longitudinal electric field with the electrode 552LC. Further, the layer 553LC including liquid crystal is sandwiched between the electrode 551LC and the electrode 552LC.

[0130] Further, the liquid crystal device 550LC includes an alignment film AF1 and an alignment film AF2 (see FIG. 5B). FIG. 4B The alignment film AF1 is sandwiched between the layer 553LC including liquid crystal and the electrode 551LC, and the layer 553LC including liquid crystal is sandwiched between the alignment film AF2 and the alignment film AF1.

[0131] For example, a transmissive liquid crystal device operating in a vertical alignment (VA) mode can be used as the liquid crystal device 550LC. As the vertical alignment mode, a MVA (Multi-Domain Vertical Alignment) mode, a PVA (Patterned Vertical Alignment) mode, an ASV (Advanced Super View) mode, or the like can be used.

[0132] Further, the operation mode is not limited to the VA mode, and a liquid crystal device operating in various modes can be used as the liquid crystal device 550LC. For example, the liquid crystal device 550LC can operate in an FFS mode, a TN (Twisted Nematic) mode, an IPS mode, an ASM (Axially Symmetric aligned Micro-cell) mode, an OCB (Optically Compensated Birefringence) mode, an FLC (Ferroelectric Liquid Crystal) mode, an AFLC (Anti Ferroelectric Liquid Crystal) mode, an ECB (Electrically Controlled Birefringence) mode, a guest-host mode, or the like.

[0133] Here, liquid crystal devices utilize the optical modulation effect of polarized light and liquid crystals to control the transmission or non-transmission of light. The optical modulation effect of liquid crystals is controlled by an electric field (including a transverse electric field, a longitudinal electric field, or a tilting electric field) applied to the liquid crystal. As liquid crystals that can be used in liquid crystal devices, thermotropic liquid crystals, low-molecular-weight liquid crystals, high-molecular-weight liquid crystals, polymer-dispersed liquid crystals (PDLCs), polymer-network liquid crystals (PNLCs), ferroelectric liquid crystals, antiferroelectric liquid crystals, etc., can be used. These liquid crystal materials exhibit cholesteric phases, smectic phases, cubic phases, chiral nematic phases, isotropic phases, etc., depending on the conditions. Furthermore, either positive or negative liquid crystals can be used as liquid crystal materials; the appropriate liquid crystal material can be selected based on the mode or design used.

[0134] <<Structural Example 2 of Functional Layer 520>>

[0135] Functional layer 520 includes a light-shielding film BM, a colored layer CF, layer 522, and layer KB (see reference). FIG. 4B The light-shielding film BM includes an opening, and the colored layer CF overlaps with the opening of the light-shielding film BM. Layer 522 is sandwiched between the colored layer CF and the liquid crystal-containing layer 553LC, and has insulating properties. Layer KB is sandwiched between the opening 518_4 and the light-shielding film BM, and layer KB controls the thickness of the liquid crystal-containing layer 553LC. Furthermore, the functional layer 520 includes layer 521. Layer 521 is sandwiched between the liquid crystal-containing layer 553LC and the functional layer 510.

[0136] Therefore, for example, reflective displays utilizing external light can be implemented. Furthermore, power consumption of the display device 550 can be suppressed. Additionally, transmissive displays are possible. Moreover, since the functional layer 510 is curved in region 510_2, region 510_2 is difficult to identify when it is directly opposite region 510_1. Furthermore, the area surrounding region 510_1 in a border-like shape when it is directly opposite region 510_1 is difficult to identify. As a result, a novel display device with excellent convenience, practicality, and reliability can be provided.

[0137] <<Structural Example 2 of Functional Layer 510>>

[0138] Functional layer 510 includes layer 516, layer 518, spacer 210, and transistor 200 (see reference). FIG. 4B ).

[0139] [Structure examples of layers 518 and 516]

[0140] The layer 518 is interposed between the functional layer 520 and the spacer 210. The layer 518 includes an opening portion 518_4 and has insulating properties. The layer 516 is interposed between the layer 518 and the spacer 210 and overlaps with the transistor 200.

[0141] For example, an insulating inorganic material, an insulating organic material, or an insulating composite material including an inorganic material and an organic material can be used for the layer 518.

[0142] Specifically, an inorganic oxide, an inorganic nitride, an inorganic oxynitride, or the like can be used for the layer 518. Alternatively, a stacked-layer material formed by stacking a plurality of layers selected from an inorganic oxide, an inorganic nitride, and an inorganic oxynitride, or the like can be used for the layer 518.

[0143] Specifically, silicon oxide, silicon nitride, silicon oxynitride, aluminum oxide, or the like can be used for the layer 518. Note that a silicon nitride film is a dense film and thus has an excellent function of inhibiting diffusion of impurities. In addition, a film having an excellent function of inhibiting diffusion of impurities can be appropriately used for the layer 516. Thus, diffusion of impurities from the outside of the transistor 200 into the inside of the transistor 200, which causes a decrease in the characteristics of the transistor 200, can be inhibited.

[0144] Further, for example, a polyester, a polyolefin, a polyamide, a polyimide, a polycarbonate, a polysiloxane, an acrylic resin, or the like can be used for the layer 518. In addition, a material having photosensitivity can be used to form the layer 518. Further, a polyimide has characteristics such as heat resistance, insulating properties, toughness, a low dielectric constant, a low thermal expansion rate, chemical resistance, and the like, which are superior to those of other organic materials.

[0145] In addition, the layer 518 can planarize a step due to the structure of the substrate by being formed over the substrate.

[0146] [Structure Example of Spacer 210]

[0147] The spacer 210 includes a surface 210_1, a surface 210_2, a surface 210_3, and an opening portion 210_4 (see FIG. 5A). FIG. 5 The surfaces 210_1, 210_2, and 210_3 have insulating properties.

[0148] The surface 210_2 is opposite to the surface 210_1 and is closer to the layer 518 than the surface 210_1.

[0149] For example, a structure in which the layer 210A, the layer 210B, and the layer 210C are stacked can be used for the spacer 210. When the layer 210C is positioned between the layer 210A and the layer 210B, for example, the layer 210A forms the surface 210_1 and the layer 210B forms the surface 210_2.

[0150] The face 210_3 connects the face 210_1 and the face 210_2, and is located on a side of the opening portion 210_4. Note that the face or the opening is not limited to the range of the dotted line in the drawing.

[0151] For example, in the case where the structure of the stacked layer 210A, the layer 210B, and the layer 210C is used for the spacer 210, the face 210_3 is formed of a side of the opening portion of the layer 210A, a side of the opening portion of the layer 210B, and a side of the opening portion of the layer 210C.

[0152] [Structure Example of Transistor 200]

[0153] The transistor 200 includes the electrode 212A, the electrode 212B, the electrode 204, the semiconductor layer 208, and the insulating layer 206 (see FIG. 2A). FIG. 4B FIG. 5 ).

[0154] The electrode 212A includes a region in contact with the face 210_1 and a region overlapping with the opening portion 210_4.

[0155] The electrode 212B includes a region in contact with the face 210_2, the opening portion 212B_4, and the face 212B_3. The face 212B_3 is located on a side of the opening portion 212B_4, and the opening portion 212B_4 overlaps with the opening portion 210_4.

[0156] The electrode 204 includes a region opposite to the face 210_3. In addition, the electrode 204 is used as a gate electrode of the transistor 200.

[0157] The insulating layer 206 includes a region sandwiched between the face 210_3 and the electrode 204. In addition, the insulating layer 206 is used as a gate insulating film of the transistor 200.

[0158] The semiconductor layer 208 includes a region sandwiched between the face 210_3 and the insulating layer 206. Note that a channel of the transistor 200 is formed in the semiconductor layer 208.

[0159] The semiconductor layer 208 is in contact with the electrode 212A in the opening portion 210_4, and the semiconductor layer 208 is in contact with the electrode 212B on the face 212B_3. In addition, the electrode 212A is used as one of a source electrode and a drain electrode of the transistor 200, and the electrode 212B is used as the other of the source electrode and the drain electrode of the transistor 200. Further, a detailed structure that can be used for the transistor 200 is described in Embodiment 4.

[0160] ​Thus, the aperture area of the transistor can be reduced. Further, the channel length of the transistor can be reduced. Further, the on-state current of the transistor can be increased. Further, the unevenness in the characteristics of the transistor can be reduced. Further, the aperture area of the pixel circuit 530 can be reduced. Further, the resolution of the display device can be increased. As a result, a novel display device with high convenience, utility, or reliability can be provided.

[0161] <Structure Example of Conductive Layer 519A>

[0162] The conductive layer 519A electrically connects the electrode 212B and the electrode 551LC through the opening portion 518_4 (see FIG. 5B). FIG. 4B ).

[0163] For example, a conductive film is formed on the layer 518 in which the opening portion 518_4 overlaps with the electrode 212B, whereby the conductive film can be electrically connected to the electrode 212B in the opening portion 518_4. Further, the conductive film can be processed into a predetermined shape to form the conductive layer 519A and the electrode 551LC. Note that in the case where the conductive layer 519A and the electrode 551LC are formed of the same conductive layer, a portion of the conductive layer overlapping with the opening portion 518_4 of the layer 518 is used as the conductive layer 519A and a portion of the conductive layer overlapping with a flat region of the layer 518 is used as the electrode 551LC.

[0164] As the conductive layer 519A, an inorganic conductive material, an organic conductive material, a metal, a conductive oxide, or the like can be used.

[0165] Specifically, a metal element selected from aluminum, gold, platinum, silver, copper, chromium, tantalum, titanium, molybdenum, tungsten, nickel, iron, cobalt, palladium, and manganese can be used for the conductive layer 519A. Alternatively, an alloy or the like including the above metal element can be used for the conductive layer 519A.

[0166] Specifically, as the conductive layer 519A, a two-layer structure in which a titanium film is stacked over an aluminum film, a two-layer structure in which a titanium film is stacked over a titanium nitride film, a two-layer structure in which a tungsten film is stacked over a titanium nitride film, a two-layer structure in which a tungsten film is stacked over a tantalum nitride film or a tungsten nitride film, a three-layer structure in which a titanium film, an aluminum film, and a titanium film are sequentially stacked, or the like can be used.

[0167] For example, a conductive oxide including indium can be used for the conductive layer 519A. Specifically, indium oxide, indium tin oxide (referred to as ITO), indium tin oxide including silicon or silicon oxide (referred to as ITSO), indium zinc oxide, indium oxide including tungsten oxide and zinc oxide (referred to as IWZO), or the like can be used.

[0168] Further, for example, a conductive oxide containing zinc can be used for the conductive layer 519A. Specifically, zinc oxide, zinc oxide to which gallium is added, zinc oxide to which aluminum is added, or the like can be used.

[0169] <Structure Example of Substrate SUB1, Substrate SUB2>

[0170] For example, a glass substrate can be used for the substrate SUB1 and the substrate SUB2. Specifically, an alkali-free glass can be used for the substrate SUB1 and the substrate SUB2.

[0171] <Structure Example 2 of Display Device>

[0172] The display device of one embodiment of the present application includes a driver circuit SD. The driver circuit SD includes a shift register SR1 (see FIG. 2A ).

[0173] The functional layer 510 includes a signal line S. The signal line S electrically connects the driver circuit SD and the pixel circuit 530, and the signal line S transmits an image signal. Note that the function of the driver circuit SD which can be used for the display device of one embodiment of the present application is described in detail in Embodiment 2. Further, a detailed structure which can be used for the shift register SR1 is described in Embodiment 4.

[0174] Thus, the driver circuit SD can be provided in the region 510_2 to supply an image signal to the signal line S. Further, the pixel circuit 530 and the display element 550 can be provided in the adjacent region 510_1 to display an image. Further, since the functional layer 510 is curved in the region 510_2, the region 510_2 can be hardly recognized in a state in which the region 510_2 faces the region 510_1. Further, a region which surrounds the region 510_1 in a frame-like manner can be hardly recognized in a state in which the region faces the region 510_1. As a result, a novel display device which is excellent in convenience, utility, or reliability can be provided.

[0175] Further, the signal line S is electrically connected to the electrode 212A (see FIG. 4B ). For example, a wiring for supplying a signal to the liquid crystal element 550 LC can be used for the signal line S. Note that in the case where the signal line S and the electrode 212A are formed of the same conductive layer, a portion of the conductive layer which overlaps with the opening portion 210_4 of the spacer 210 is referred to as the electrode 212A. Further, a portion of the conductive layer which overlaps with the flat region of the spacer 210 is referred to as the signal line S.

[0176] The signal line S has a light-blocking property. For example, a material which can be used for the conductive layer 519A can be used for the signal line S. In particular, a metal or an alloy can be appropriately used.

[0177] The signal line S overlaps with the opening portion 518_4. In other words, the opening portion 518_4 overlaps with the electrode 212B and the signal line S.

[0178] Thus, a step formed on the opening portion 518_4 can be overlapped with the signal line S. In addition, a flat region can be formed in a region which does not overlap with the signal line S. Further, an electrode of the display device 550 can be formed in the flat region. Further, a flat region can be formed in the electrode. Further, a layer containing liquid crystal can be formed on the flat region of the electrode, for example. Further, the signal line S can be arranged between the layer containing liquid crystal and the backlight, for example. Further, in order to prevent light of the backlight from reaching a region of alignment disorder formed in the layer containing liquid crystal due to the step on the opening portion 518_4, light shielding can be performed using the signal line S. In addition, the aperture ratio of the liquid crystal device can be improved. In addition, the luminance of the display device can be improved. In addition, power consumption can be suppressed. As a result, a novel display device which is excellent in convenience, practicality, or reliability can be provided.

[0179] <Structure Example 3 of Display Device>

[0180] The display device of one embodiment of the present application includes a driver circuit GD. The driver circuit GD includes a shift register SR2 (see FIG. 5A). FIG. 2A Note that the function of the driver circuit GD which can be used for the display device of one embodiment of the present application is described in detail in Embodiment 2. In addition, a detailed structure which can be used for the shift register SR2 is described in Embodiment 4.

[0181] The functional layer 510 includes a region 510_3 and a scan line G. The functional layer 510 is curved in the region 510_3.

[0182] In addition, as FIG. 1A indicated, when an axis around which the region 510_2 is curved with respect to the region 510_1 intersects with an axis around which the region 510_3 is curved with respect to the region 510_1, a notch is provided between the region 510_2 and the region 510_3. Various shapes can be used for the outer shape of the notch, for example, as indicated in FIG. 5B, by using dotted lines Q5-Q6, by adopting an outer shape in the form of a gentle curve, stress concentration due to the curvature can be prevented. Specifically, it is preferable to adopt an outer shape in the form of a curve with a radius of curvature of 0.1 mm or more and 10 mm or less. FIG. 2A

[0183] The region 510_3 is adjacent to the region 510_1, and the region 510_3 includes a layer 511_3 and a shift register SR2 (see FIG. 5A and FIG. 5B). FIG. 2A FIG. 2C

[0184] ​​​Layer 511_3 is continuous with layer 511_1, and shift register SR2 is formed on layer 511_3.

[0185] The scan line G is electrically connected to the drive circuit GD and the pixel circuit 530, and the scan line G transmits the selection signal.

[0186] Therefore, a drive circuit GD can be configured in region 510_3 to supply a selection signal to the scan line G. Additionally, a pixel circuit 530 and a display device 550 can be configured in the adjacent region 510_1 to display an image. Furthermore, because the functional layer 510 is curved in region 510_3, region 510_3 is difficult to identify when it is directly opposite region 510_1. Also, the area surrounding region 510_1 in a border-like shape when it is directly opposite region 510_1 is difficult to identify. As a result, a novel display device with excellent convenience, practicality, and reliability can be provided.

[0187] <Example 4 of a display device structure>

[0188] One embodiment of the present invention includes an electrode RX and a driving circuit TD.

[0189] Functional layer 520 is located between electrode RX and functional layer 510. In other words, functional layer 520 is sandwiched between electrode RX and functional layer 510 (see reference). FIG. 4B ).

[0190] The driver circuit TD includes shift register SR3 (see reference). FIG. 2A Note that the function of the driving circuit TD of the display device, which can be used in one aspect of the present invention, is described in detail in Embodiment 3. Furthermore, the detailed structure of the shift register SR3 is described in Embodiment 4.

[0191] The functional layer 510 includes region 510_4 and electrode TX. The functional layer 510 is bent in region 510_4.

[0192] Region 510_4 is adjacent to region 510_1. Region 510_4 includes layer 511_4 and shift register SR3 (see reference). FIG. 2A and FIG. 2C ).

[0193] Layer 511_4 is continuous with layer 511_1, and shift register SR3 is formed on layer 511_4.

[0194] A capacitor is formed between electrodes TX and RX (see reference). FIG. 6B). In other words, a capacitance is formed between the electrode TX and the electrode RX. In addition, the electrode TX and the electrode RX constitute a sensor element. Note that in the case where the liquid crystal device is used for the display device 550, the electrode TX can be used as a common electrode of the liquid crystal device. Specifically, the electrode TX can be used as the electrode 552LC (see FIG. 5B) of the display device 550. FIG. 4B ).

[0195] The electrode TX is electrically connected to the driver circuit TD, and the electrode TX transmits a pulse signal.

[0196] Thus, the driver circuit TD is provided in the region 510_4, and a pulse signal can be supplied to the electrode TX. In addition, the electrode RX is provided over the adjacent region 510_1, and a change in a projected capacitance generated between the electrode TX and the electrode RX can be detected. In addition, a position of a finger of a user of the display device close to the region 510_1 can be detected. In addition, since the functional layer 510 is curved in the region 510_4, the region 510_4 can be hardly recognized in a state of being directly opposite to the region 510_1. In addition, a region surrounding the region 510_1 in a frame shape in a state of being directly opposite to the region 510_1 can be hardly recognized. As a result, a novel display device which is excellent in convenience, practicality, or reliability can be provided.

[0197] Note that the present embodiment can be combined with other embodiments shown in the present specification as appropriate.

[0198] (Embodiment 2)

[0199] In the present embodiment, a display device of one embodiment of the present application is described with reference to FIGS. 7 and 8.

[0200] FIG. 7A The display device illustrated in FIG. 7 includes a pixel portion 4502, a driver circuit portion 4504, a protection circuit 4506, and a terminal portion 4507. Alternatively, a structure in which the protection circuit 4506 is not provided can be employed.

[0201] The pixel portion 4502 includes a plurality of pixel circuits 4501 arranged in X rows and Y columns (X and Y are each independently a natural number of 2 or more). Each of the pixel circuits 4501 includes a circuit which drives a display element.

[0202] The driver circuit portion 4504 includes a gate driver 4504a, a source driver 4504b, and the like.

[0203] The gate driver 4504a outputs a scan signal to gate lines GL_1 to GL_X. The gate driver 4504a can employ a structure including at least a shift register. Note that the gate driver 4504a can be used as the driver circuit GD of the display device described in Embodiment 1, for example.

[0204] Further, the source driver 4504b supplies a data signal to the data line DL_1 to the data line DL_Y. Further, the source driver 4504b can be configured with a shift register, a digital-analog conversion circuit, a latch circuit, or the like. Note that the source driver 4504b can be used as the driver circuit SD described in Embodiment 1, for example.

[0205] The terminal portion 4507 refers to a portion provided with a terminal for inputting a power supply, a control signal, an image signal, or the like from an external circuit to the display device.

[0206] The protection circuit 4506 is a circuit that makes a wiring to which the protection circuit 4506 is connected and another wiring in a conductive state when a potential outside a certain range is supplied to the wiring. FIG. 7A The protection circuit 4506 illustrated in the drawing is connected to various wirings such as a gate line, a data line, and the like, for example. Further, in FIG. 7A In this embodiment, the protection circuit 4506 is distinguished from the pixel circuit 4501, and hatching is added to the protection circuit 4506.

[0207] Further, the gate driver 4504a and the source driver 4504b and the pixel portion 4502 can be provided over the same substrate, or an IC in which the gate driver circuit or the source driver circuit is separately formed can be mounted on a substrate over which the pixel portion 4502 is provided by a COG (Chip on glass) method or the like. Alternatively, an FPC (Flexible Printed Circuit) to which an IC is mounted can be attached to a substrate with an ACF (Anisotropic Conductive Film) or the like.

[0208] In particular, it is preferable that the pixel portion 4502 and the gate driver 4504a be manufactured over the same substrate by the same process. At this time, it is preferable that a transistor of one embodiment of the present application be provided in each of the pixel portion 4502 and the gate driver 4504a. Further, when the source driver 4504b uses an IC, it is preferable that a demultiplexer circuit be provided over the substrate, which can reduce the number of terminals of the IC. At this time, it is preferable that a transistor of one embodiment of the present application be used for the demultiplexer circuit.

[0209] FIG. 7B An example of a structure of a pixel circuit which can be used for the pixel circuit 4501 is described.

[0210] FIG. 7BThe pixel circuit 4501 illustrated includes a liquid crystal element 4570, a transistor 4550, and a capacitor 4560. Further, the pixel circuit 4501 is connected to a data line DL_n, a gate line GL_m, a potential supply line, and the like. Note that the data line DL_n can be used as the signal line S described in Embodiment 1, for example. Further, the gate line GL_m can be used as the scan line G. Further, a detailed structure of the transistor 4550 is described in Embodiment 4.

[0211] The potential of one of a pair of electrodes of the liquid crystal element 4570 is set in accordance with the specifications of the pixel circuit 4501. The alignment state of the liquid crystal element 4570 is set in accordance with data which is written. Further, the potential of one of a pair of electrodes of the liquid crystal element 4570 included in each of a plurality of pixel circuits 4501 can be supplied with a common potential. Further, the potential of one of a pair of electrodes of the liquid crystal element 4570 in the pixel circuits 4501 of each row can be supplied with different potentials.

[0212] Further, FIG. 7C The pixel circuit 4501 illustrated includes a transistor 4552, a transistor 4554, a capacitor 4562, and a light-emitting element 4572. Further, the pixel circuit 4501 is connected to a data line DL_n, a gate line GL_m, a potential supply line VL_a, and a potential supply line VL_b, and the like.

[0213] Further, one of the potential supply line VL_a and the potential supply line VL_b is applied with a high power supply potential VDD and the other is applied with a low power supply potential VSS. The current flowing through the light-emitting element 4572 is controlled in accordance with the potential applied to the gate of the transistor 4554, and thus the luminance of light emission from the light-emitting element 4572 is controlled.

[0214] Next, a pixel circuit provided with a memory for correcting the gray scale displayed by a pixel and a display device including the pixel circuit are described.

[0215] FIG. 8A A circuit diagram of the pixel circuit 4400 is illustrated. The pixel circuit 4400 includes a transistor Ml, a transistor M2, a capacitor Cl, and a circuit 4401. Further, the pixel circuit 4400 is connected to a wiring SI, a wiring S2, a wiring Gl, and a wiring G2. Further, a detailed structure of the transistor Ml and the transistor M2 is described in Embodiment 4.

[0216] The gate of the transistor Ml is connected to the wiring Gl, one of a source and a drain is connected to the wiring SI, and the other is connected to one electrode of the capacitor Cl. The gate of the transistor M2 is connected to the wiring G2, one of a source and a drain is connected to the wiring S2, and the other is connected to the other electrode of the capacitor Cl and the circuit 4401.

[0217] Circuit 4401 includes at least one display element. Here, the display element includes a liquid crystal device. However, it is not limited to this, and the display element can be a variety of components, typically including light-emitting elements such as organic EL elements, LED elements, or MEMS (Micro Electro Mechanical Systems) elements.

[0218] The node connecting transistor M1 and capacitor C1 is denoted as node N1, and the node connecting transistor M2 and circuit 4401 is denoted as node N2.

[0219] The pixel circuit 4400 can maintain the potential of node N1 by turning transistor M1 off. Furthermore, it can maintain the potential of node N2 by turning transistor M2 off. Moreover, by writing a predetermined potential to node N1 through transistor M1 while transistor M2 is off, the potential of node N2 can change in response to changes in the potential of node N1 due to capacitive coupling through capacitor C1.

[0220] Alternatively, one or both of transistors M1 and M2 can be made of oxide semiconductors. Because this transistor has extremely low off-state current, the potential of node N1 or node N2 can be maintained for a long time. Furthermore, when the potential maintenance period of each node is short (specifically, when the frame rate is 30Hz or higher, etc.), transistors using semiconductors such as silicon can also be used.

[0221] [Example of driver method]

[0222] Next, refer to FIG. 8B An example illustrating the operation of the pixel circuit 4400 is provided. FIG. 8B This is a timing diagram of the operation of the pixel circuit 4400. Note that, for ease of explanation, the effects of various resistors such as wiring resistors, parasitic capacitances, and transistor threshold voltages are not considered here.

[0223] exist FIG. 8B In the work shown, a frame period is divided into period T1 and period T2. Period T1 is the period for writing potential to node N2, and period T2 is the period for writing potential to node N1.

[0224] [Period T1]

[0225] During period T1, a potential that turns the transistor on is supplied to both wiring G1 and wiring G2. Additionally, a fixed potential V is supplied to wiring S1. ref Supply the first data potential V to wiring S2 w .

[0226] Node N1 is supplied with potential V from wiring S1 via transistor M1. ref Furthermore, node N2 is supplied with a first data potential V from wiring S2 via transistor M2. w Therefore, capacitor C1 becomes a capacitor that maintains the potential difference V. w -V ref The state.

[0227] [Period T2]

[0228] Next, during period T2, wiring G1 is supplied with a potential that turns transistor M1 on, and wiring G2 is supplied with a potential that turns transistor M2 off. Wiring S1 is supplied with the second data potential V. data In addition, a predetermined constant potential can be supplied to wiring S2 or it can be made to float.

[0229] Node N1 is supplied with the second data potential V from wiring S1 via transistor M1. data At this time, due to capacitive coupling through capacitor C1, the corresponding second data potential V... data The potential of node N2 changes by a value of dV. In other words, circuit 4401 is input with the first data potential V. w The potential added together with the potential dV. Note that, although... FIG. 8B The diagram shows a positive value for the potential dV, but it can also be negative. That is, the second data potential V... data It can also be compared to the potential V ref Low.

[0230] Here, the potential dV is primarily determined by the capacitance of capacitor C1 and the capacitance of circuit 4401. When the capacitance of capacitor C1 is sufficiently greater than the capacitance of circuit 4401, the potential dV becomes close to the second data potential V. data The potential.

[0231] As described above, since the pixel circuit 4400 can combine two data signals to generate a potential supplied to the circuit 4401 including the display element, grayscale correction can be performed within the pixel circuit 4400.

[0232] Furthermore, the pixel circuit 4400 can generate a potential exceeding the maximum potential that can be supplied to the source driver connected to wiring S1 and wiring S2. For example, when using a light-emitting element, high dynamic range (HDR) display can be achieved. Furthermore, when using a liquid crystal device, overdriving can be implemented.

[0233] [Application Example]

[0234] [Examples of using liquid crystal devices]

[0235] FIG. 8C The pixel circuit 4400LC illustrated includes a circuit 4401LC. The circuit 4401LC includes a liquid crystal device LC and a capacitor C2.

[0236] One electrode of the liquid crystal device LC is connected to the node N2 and one electrode of the capacitor C2, and the other electrode is connected to a wiring to which a potential V com2 is supplied. The other electrode of the capacitor C2 is connected to a wiring to which a potential V com1 is supplied.

[0237] The capacitor C2 is used as a storage capacitor. Further, the capacitor C2 can be omitted when not needed.

[0238] Since the pixel circuit 4400LC can supply a high voltage to the liquid crystal device LC, high-speed display can be achieved by overdrive, for example, and a liquid crystal material with a high driving voltage can be used. Further, by supplying a correction signal to the wiring S1 or the wiring S2, gradation correction can be performed in accordance with the use temperature, the deterioration state of the liquid crystal device LC, or the like.

[0239] Example of using a light emitting element

[0240] FIG. 8D The pixel circuit 4400EL illustrated includes a circuit 4401EL. The circuit 4401EL includes a light emitting element EL, a transistor M3, and a capacitor C2.

[0241] The gate of the transistor M3 is connected to the node N2 and one electrode of the capacitor C2, one of the source and the drain is connected to a wiring to which a potential V H is supplied, and the other of the source and the drain is connected to one electrode of the light emitting element EL. The other electrode of the capacitor C2 is connected to a wiring to which a potential V com is supplied. The other electrode of the light emitting element EL is connected to a wiring to which a potential V L is supplied.

[0242] The transistor M3 has a function of controlling current supplied to the light emitting element EL. The capacitor C2 is used as a storage capacitor. The capacitor C2 can be omitted when not needed.

[0243] Further, although a structure in which the anode side of the light emitting element EL is connected to the transistor M3 is illustrated here, a structure in which the cathode side is connected to the transistor M3 can be employed. At this time, the values of the potential V H and the potential V L may be changed as appropriate.

[0244] The pixel circuit 4400EL can cause a large current to flow through the light emitting element EL by applying a high potential to the gate of the transistor M3, and thus, for example, can achieve HDR display or the like. Further, an electric characteristic deviation of the transistor M3, the light emitting element EL, or the like can be corrected by supplying a correction signal to the wiring S1 or the wiring S2.

[0245] Further, the circuit illustrated in FIGS. 17A and 17B is not limited to FIG. 8C and FIG. 8D the circuit illustrated in FIGS. 17A and 17B, and another structure in which a transistor, a capacitor, or the like is further added can be employed.

[0246] At least a part of the present embodiment can be implemented in appropriate combination with the other embodiments described in the present specification.

[0247] (Embodiment 3)

[0248] In the present embodiment, a structure example of a touch panel module of one embodiment of the present application is described with reference to FIG. 9 and FIG. 10.

[0249] FIG. 9 is a block diagram of a touch panel module 6500.

[0250] FIGS. 10A-10C is a schematic view of the touch panel module 6500 to which an IC 6520 is attached.

[0251] <Structure Example 1 of Touch Panel Module>

[0252] The touch panel module 6500 includes a touch panel 6510 and an IC 6520 (see FIG. 9 ).

[0253] <Structure Example of Display Panel 6510>

[0254] The touch panel 6510 includes a display portion 6511, an input portion 6512, a scan line driver circuit 6513, a sensor driver circuit 6503, and a detection circuit 6504.

[0255] [Display Portion 6511, Input Portion 6512]

[0256] The display portion 6511 includes a plurality of pixels, a plurality of signal lines, and a plurality of scan lines, and has a function of displaying an image.

[0257] The display portion 6511 preferably has an extremely high resolution such as HD (number of pixels: 1280 x 720), FHD (number of pixels: 1920 x 1080), WQHD (number of pixels: 2560 x 1440), WQXGA (number of pixels: 2560 x 1600), 4K (number of pixels: 3840 x 2160), 8K (number of pixels: 7680 x 4320), or the like. It is particularly preferable to have a resolution of 4K, 8K, or more. In addition, the pixel density (definition) of pixels provided in the display portion 6511 is preferably 300 ppi or higher, more preferably 500 ppi or higher, still more preferably 800 ppi or higher, further more preferably 1000 ppi or higher, and yet further more preferably 1200 ppi or higher. Such a display portion 6511 having a high resolution and high definition can further improve the sense of reality, the sense of depth, and the like.

[0258] The input portion 6512 includes a plurality of sensor elements that sense contact or proximity of a sensing object to the touch panel 6510, and is used as a touch sensor. The scan line driver circuit 6513 has a function of outputting a scan signal to a scan line in the display portion 6511.

[0259] Here, although the display portion 6511 and the input portion 6512 are separately illustrated as structures of the touch panel 6510 for convenience of explanation, a so-called In-Cell touch panel that has both a function of displaying an image and a function of a touch sensor can be used. Note that, for example, the region 510_1 of the display device described in Embodiment 1 can be used as the display portion 6511.

[0260] As a method of a touch sensor that can be used for the input portion 6512, for example, an electrostatic capacitive method can be used. As the electrostatic capacitive method, there are a surface type electrostatic capacitive method, a projected type electrostatic capacitive method, and the like. As the projected type electrostatic capacitive method, there are a self capacitive method, a mutual capacitive method, and the like. The mutual capacitive method is preferably used, whereby multi-point detection can be performed at the same time.

[0261] Note that, the input portion 6512 is not limited thereto, and a sensor of various methods that can sense proximity, contact, or pressure of a sensing object such as a finger or a stylus pen can be used. As a method of the sensor, in addition to the electrostatic capacitive method, various methods such as a resistive film method, a surface acoustic wave method, an infrared method, an optical method, and the like can be used.

[0262] As the In-Cell type touch panel, there are typically a Hybrid-In-Cell type and a Full-In-Cell type. The Hybrid-In-Cell type refers to a structure in which an electrode or the like that constitutes a touch sensor is provided on both a substrate that supports a display element and a counter substrate or on the counter substrate. On the other hand, the Full-In-Cell type refers to a structure in which an electrode or the like that constitutes a touch sensor is provided on a substrate that supports a display element. By adopting the Full-In-Cell type touch panel, the structure of the counter substrate can be simplified, and thus the Full-In-Cell type is preferable. In particular, in the Full-In-Cell type, by using an electrode that constitutes a display element as an electrode that constitutes a touch sensor, the manufacturing process can be simplified, and thus the manufacturing cost can be reduced, and thus the Full-In-Cell type is preferable.

[0263] [Sensor drive circuit 6503]

[0264] The sensor drive circuit 6503 has a function of outputting a signal of a sensor element in the drive input section 6512. The sensor drive circuit 6503 can have, for example, a structure in which a shift register circuit and a buffer circuit are combined. Note that the sensor drive circuit 6503 can be used for the drive circuit TD described in Embodiment 1, for example.

[0265] [Detection circuit 6504]

[0266] The detection circuit 6504 has a function of amplifying and outputting an output signal from a sensor element in the input section 6512 to the AD conversion circuit 6507.

[0267] [Structure example of IC 6520]

[0268] The IC 6520 includes the circuit unit 6501, the signal line drive circuit 6502, and the AD conversion circuit 6507. The circuit unit 6501 includes the timing controller 6505, the image processing circuit 6506, and the like.

[0269] Thus, by assembling the function of driving the display section 6511 of the touch panel 6510 and the function of driving the input section 6512 in one IC, the number of ICs mounted in the touch panel module 6500 can be reduced, and thus the cost can be reduced.

[0270] [Signal line drive circuit 6502]

[0271] The signal line drive circuit 6502 has a function of outputting an image signal (also referred to as a video signal) as an analog signal to the signal line in the display portion 6511. For example, the signal line drive circuit 6502 can have a structure including a shift register, a digital-analog convertor (DAC), a latch circuit, a buffer circuit, and the like. In addition, the touch panel 6510 can also include a demultiplexer circuit connected to the signal line.

[0272] [AD conversion circuit 6507]

[0273] The AD conversion circuit 6507 has a function of converting an analog signal input from the detection circuit 6504 into a digital signal and outputting the same to the circuit unit 6501. For example, the AD conversion circuit 6507 can include an analog-digital convertor (ADC) and an amplification circuit.

[0274] [Circuit unit 6501]

[0275] The image processing circuit 6506 in the circuit unit 6501 has a function of generating and outputting a signal for driving the display portion 6511 of the touch panel 6510, generating and outputting a signal for driving the input portion 6512, and analyzing a signal output from the input portion 6512 and outputting the same to the CPU 6540.

[0276] More specifically, the image processing circuit 6506 has a function of generating an image signal in accordance with an instruction from the CPU 6540, for example. In addition, the image processing circuit 6506 has a function of performing signal processing on the image signal in accordance with the specifications of the display portion 6511, converting the same into an analog image signal, and supplying the same to the signal line drive circuit 6502. In addition, the image processing circuit 6506 has a function of generating a drive signal for the sensor drive circuit 6503 in accordance with an instruction from the CPU 6540. In addition, the image processing circuit 6506 also has a function of analyzing a signal input from the detection circuit 6504 via the AD conversion circuit 6507 and outputting the same as position information to the CPU 6540.

[0277] The timing controller 6505 has a function of generating and outputting a signal (a clock signal, a start pulse signal, or the like) to be output to the scan line driver circuit 6513 and the sensor driver circuit 6503 in accordance with a synchronization signal in an image signal or the like processed by the image processing circuit 6506. The timing controller 6505 can also have a function of generating and outputting a signal that defines the timing of an output signal of the detection circuit 6504. Here, the timing controller 6505 preferably outputs signals that are synchronized with the signal output to the scan line driver circuit 6513 and the signal output to the sensor driver circuit 6503, respectively. In particular, it is preferable to separate a period in which data of a pixel of the display portion 6511 is rewritten and a period in which sensing is performed in the input portion 6512. For example, the touch panel 6510 can be driven in a manner in which one frame period is divided into a period in which data of a pixel is rewritten and a period in which sensing is performed. In addition, for example, by providing two or more sensing periods in one frame period, the detection sensitivity and the detection accuracy can be improved.

[0278] The image processing circuit 6506 can include a processor, for example. A microprocessor such as a DSP (Digital Signal Processor), a GPU (Graphics Processing Unit), or the like can be used, for example. The microprocessor can also be formed of a PLD (Programmable Logic Device) such as an FPGA (Field Programmable Gate Array) or an FPAA (Field Programmable Analog Array). The image processing circuit 6506 performs various data processing, program control, and the like by interpreting and executing instructions from various programs by the processor. A program that can be executed by the processor can be stored in a memory region in the processor or in a storage device provided separately.

[0279] Structure Example 2 of Touch Panel Module

[0280] It is preferable that one or more of the display portion 6511, the input portion 6512, the scan line driver circuit 6513, the sensor driver circuit 6503, and the detection circuit 6504 included in the touch panel 6510 each include a transistor in which an oxide semiconductor is used for a channel formation region and which has extremely low off-state current.

[0281] Since the off-state current of the transistor is extremely low, long-term retention of data can be ensured by using the transistor as a switch for retaining charges (data) flowing into a capacitor serving as a storage element. In addition, the transistor can be used in the circuit unit 6501 included in the IC 6520, the signal line driver circuit 6502, the AD conversion circuit 6507, or the like provided outside the CPU 6540. For example, by applying the characteristics to a register or a cache memory or the like of the image processing circuit 6506, the image processing circuit 6506 can be operated only when necessary, and in other cases, previous processing information can be stored in the storage element, whereby so-called normally off computing in which power supply to the image processing circuit 6506 is turned off when the image processing circuit 6506 is not used can be realized, and low power consumption of the touch panel module 6500 and an electronic device in which the touch panel module 6500 is mounted can be realized.

[0282] Note that, although a structure in which the circuit unit 6501 includes the timing controller 6505 and the image processing circuit 6506 is illustrated here, the image processing circuit 6506 itself or a circuit having part of the functions of the image processing circuit 6506 can be provided outside the IC 6520. Alternatively, the CPU 6540 can be provided with all or part of the functions of the image processing circuit 6506. For example, a structure in which the circuit unit 6501 includes the signal line driver circuit 6502, the timing controller 6505, and the AD conversion circuit 6507 can be employed.

[0283] In addition, although an example in which the IC 6520 includes the circuit unit 6501 is illustrated here, the circuit unit 6501 can not be included in the IC 6520. In this case, the IC 6520 can have a structure including the signal line driver circuit 6502 and the AD conversion circuit 6507. For example, when a plurality of ICs are mounted in the touch panel module 6500, a plurality of ICs 6520 not including the circuit unit 6501 can be provided in addition to an IC including the circuit unit 6501. Alternatively, ICs including only the IC 6520 and the signal line driver circuit 6502 can be combined and arranged.

[0284] <Structure Example 3 of Touch Panel Module>

[0285] FIG. 10A The touch panel module 6500 illustrated includes a substrate 6531, a counter substrate 6532, a plurality of FPCs 6533, an IC 6520, and an IC 6530. Between the substrate 6531 and the counter substrate 6532, a display portion 6511, an input portion 6512, a scan line driver circuit 6513, a sensor driver circuit 6503, and a detection circuit 6504 are included. The IC 6520 and the IC 6530 are mounted on the substrate 6531 by a COG (Chip On Glass) method or the like.

[0286] IC 6530 is an IC including only the signal line drive circuit 6502 or including the signal line drive circuit 6502 and the circuit unit 6501 in the IC 6520 described above. The IC 6520 and the IC 6530 are supplied with signals from the outside through the FPC 6533. In addition, signals can also be output from the IC 6520 or the IC 6530 to the outside through the FPC 6533.

[0287] FIG. 10A An example of a structure in which two scan line drive circuits 6513 are provided so as to sandwich the display portion 6511 is shown. A structure in which the IC 6530 is further included in addition to the IC 6520 is shown. Such a structure can be applied to a case in which the resolution of the display portion 6511 is extremely high.

[0288] <Structure Example 4 of Touch Panel Module>

[0289] FIG. 10B An example in which one IC 6520 and one FPC 6533 are mounted is shown. In this way, by concentrating the functions in one IC 6520, the number of components can be reduced, so this is preferable. In addition, in the structure shown in FIG. 10B , an example in which the scan line drive circuit 6513 is arranged along the side of the two short sides of the display portion 6511 closer to the FPC 6533 is shown.

[0290] In addition, as shown in FIG. 10A and FIG. 10B , a structure in which the FPC 6533, the IC 6520 (and the IC 6530), and the like are arranged on the short side of the display portion 6511 can achieve narrow frame, so this can be applied to, for example, electronic devices such as smartphones, mobile phones, or tablet terminals.

[0291] <Structure Example 5 of Touch Panel Module>

[0292] FIG. 10C An example of a structure including a PCB (Printed Circuit Board) 6534 on which an image processing circuit 6506 and the like are mounted is shown. The IC 6520 and the IC 6530 on the substrate 6531 are electrically connected to the PCB 6534 by the FPC 6533. Here, the IC 6520 can also not include the image processing circuit 6506 described above.

[0293] In addition, as shown in FIG. 10C , a structure using the PCB 6534 can be applied to, for example, television devices, display devices, tablet terminals, or notebook personal computers.

[0294] In addition, as shown in FIGS. 10A-10CIn this case, the IC 6520 or the IC 6530 can also be mounted on the FPC 6533 instead of the substrate 6531. For example, the IC 6520 and the IC 6530 can be mounted on the FPC 6533 in a COF manner or a TAB manner or the like.

[0295] At least a part of the present embodiment can be implemented in appropriate combination with other embodiments described in the present specification.

[0296] (Embodiment 4)

[0297] In the present embodiment, one example of a signal output circuit of a semiconductor device and a shift register including the signal output circuit is described with reference to the drawings.

[0298] <Structure of Shift Register 100>

[0299] FIG. 11A The shift register 100 illustrated includes n (n is an integer of 1 or more) signal output circuits 110. In the present specification and the like, the first stage (first) signal output circuit 110 is sometimes referred to as signal output circuit 110[1], and the n-th stage (n-th) signal output circuit 110 is sometimes referred to as signal output circuit 110[n].

[0300] In addition, the i-th stage (i is an integer of 1 or more and n or less) signal output circuit 110 is sometimes referred to as signal output circuit 110[i]. Note that when an arbitrary stage number is referred to as i+α and α is a positive value, i+α is not more than n. In addition, when an arbitrary stage number is referred to as i-α and α is a positive value, i-α is not less than 1.

[0301] In addition, the shift register 100 includes two signal output circuits 110 (signal output circuit 110[n+1], signal output circuit 110[n+2]) as dummy circuits.

[0302] Note that a terminal and an input and output signal and the like included in the signal output circuit 110 are sometimes described as the same as described above. For example, the signal OUT of the signal output circuit 110[i] is sometimes referred to as signal OUT[i].

[0303] Further, the shift register 100 includes wirings 101 to 104 of four signals CLK (signals CLK_1 to CLK_4) respectively supplied with a clock signal and wirings 105 to 108 of four signals PWC (signals PWC_1 to PWC_4) respectively supplied. The wiring 101 is supplied with the signal CLK_1, the wiring 102 is supplied with the signal CLK_2, the wiring 103 is supplied with the signal CLK_3, and the wiring 104 is supplied with the signal CLK_4. The wiring 105 is supplied with the signal PWC_1, the wiring 106 is supplied with the signal PWC_2, the wiring 107 is supplied with the signal PWC_3, and the wiring 108 is supplied with the signal PWC_4.

[0304] The signal output circuit 110 includes terminals 111 to 118 (refer to FIG. 11B ). The terminal 111, the terminal 112, and the terminal 113 are electrically connected to any different one of the wirings 101 to 104, respectively. For example, in FIG. 11A , in the 1st stage signal output circuit 110[1], the terminal 111 is electrically connected to the wiring 101, the terminal 112 is electrically connected to the wiring 102, and the terminal 113 is electrically connected to the wiring 103. That is, the terminal 111 is supplied with the signal CLK_1, the terminal 112 is supplied with the signal CLK_2, and the terminal 113 is supplied with the signal CLK_3.

[0305] Further, in the 2nd stage signal output circuit 110[2], the terminal 111 is electrically connected to the wiring 102, the terminal 112 is electrically connected to the wiring 103, and the terminal 113 is electrically connected to the wiring 104. That is, the terminal 111 is supplied with the signal CLK_2, the terminal 112 is supplied with the signal CLK_3, and the terminal 113 is supplied with the signal CLK_4.

[0306] That is, the terminal 111[i] of the signal output circuit 110[i] is supplied with the signal CLK_k (refer to FIG. 11C ). Here, k is an integer of 1 or more and 4 or less, and k is equal to i when i is 4 or less, and k is equal to i-4xg when i is 5 or more. g is a quotient obtained by dividing i by 4.

[0307] Further, the terminal 112[i] of the signal output circuit 110[i] is supplied with the signal CLK_k+1. Here, k is an integer of 1 or more and 4 or less, and k is 1 when k+1 is 5. Further, k is equal to i when i is 3 or less, and k is equal to i-4xg when i is 4 or more.

[0308] Further, the terminal 113[i] of the signal output circuit 110[i] is supplied with a signal CLK_k+2. Here, k+1 is an integer of 1 or more and 4 or less, k+2 is 1 when k+2 is 5, and k+2 is 2 when k+2 is 6. Further, k is equal to i when i is 2 or less, and k is equal to i-4xg when i is 3 or more.

[0309] Further, the terminal 114[i] is electrically connected to the terminal 117[i+1] (not shown) of the next stage signal output circuit 110[i+1] (not shown). Therefore, the terminal 117[i] is electrically connected to the terminal 114[i-1] (not shown). For example, the terminal 114 of the signal output circuit 110[1] is electrically connected to the terminal 117 of the signal output circuit 110[2]. Further, the terminal 117 of the signal output circuit 110[1] is supplied with a start pulse SP.

[0310] Further, the terminal 115[i] is electrically connected to the terminal 114[i+2] (not shown) of the signal output circuit 110[i+2] (not shown) of the stage after the next stage. For example, the terminal 115 of the signal output circuit 110[1] is electrically connected to the terminal 114 of the signal output circuit 110[3], and the terminal 115 of the signal output circuit 110[2] is electrically connected to the terminal 114 of the signal output circuit 110[4]. Therefore, the terminal 115 of the signal output circuit 110[n-1] is electrically connected to the terminal 114 of the signal output circuit 110[n+1], and the terminal 115 of the signal output circuit 110[n] is electrically connected to the terminal 114 of the signal output circuit 110[n+2]. Note that the signal output circuit 110[n+1] and the signal output circuit 110[n+2] can not include the terminal 115.

[0311] Further, the terminal 118[i] is electrically connected to any one of the wirings 105 to 108. For example, the terminal 118 of the signal output circuit 110[1] is electrically connected to the wiring 105, and the terminal 118 of the signal output circuit 110[2] is electrically connected to the wiring 106. In other words, the terminal 118[i] of the signal output circuit 110[i] is supplied with a signal PWC_k. Here, k is an integer of 1 or more and 4 or less, and k is equal to i when i is 4 or less, and k is equal to i-4xg when i is 5 or more.

[0312] Further, the terminal 116[i] outputs a signal OUT[i]. For example, the terminal 116 of the signal output circuit 110[1] outputs a signal OUT[1]. Further, the terminal 116 of the nth stage signal output circuit 110[n] outputs a signal OUT[n]. The "the terminal 116[i] outputs a signal OUT[i]" can be also written as "the terminal 116[i] is supplied with a signal OUT[i]".

[0313] Further, the terminal 114[i] is supplied with the signal SROUT[i]. In other words, the terminal 114[i] outputs the signal SROUT[i]. For example, the terminal 114 of the signal output circuit 110[1] outputs the signal SROUT[1]. Further, the terminal 114 of the nth-stage signal output circuit 110[n] outputs the signal SROUT[n]. The "the terminal 114[i] outputs the signal SROUT[i]" can be also referred to as "the terminal 114[i] is supplied with the signal SROUT[i]".

[0314] [Structure Example of Signal Output Circuit 110]

[0315] Next, a structure of a signal output circuit 110a which can be used for the signal output circuit 110 will be described (see FIG. 6). FIG. 12 The signal output circuit 110a includes the transistors 10[1] to 10

[11] , the capacitors 20[1] to 20[3].

[0316] The gate of the transistor 10[1] is electrically connected to the terminal 117 and the gate of the transistor 10[6]. The source of the transistor 10[1] is electrically connected to the drain of the transistor 10[2], and the drain of the transistor 10[1] is electrically connected to the wiring 131. The gate of the transistor 10[2] is electrically connected to one terminal of the capacitor 20[1]. The source of the transistor 10[2] is electrically connected to the other terminal of the capacitor 20[1], the source of the transistor 10[6], and the wiring 132.

[0317] The gate of the transistor 10[3] is electrically connected to the terminal 113, the drain of the transistor 10[3] is electrically connected to the wiring 131, and the source of the transistor 10[3] is electrically connected to the drain of the transistor 10[4]. The gate of the transistor 10[4] is electrically connected to the terminal 112, the drain of the transistor 10[4] is electrically connected to the source of the transistor 10[3]. The source of the transistor 10[4] is electrically connected to the gates of the transistors 10[2], 10[9], and 10

[11] and one terminal of the capacitor 20[1], respectively.

[0318] Note that, in this specification and the like, a region in which the gates of the transistors 10[2], 10[9], and 10

[11] , the source of the transistor 10[4], and one terminal of the capacitor 20[1] are electrically connected is referred to as a node ND[1]. The capacitor 20[1] has a function of holding the potential of the node ND[1] when the node ND[1] is in a floating state, so as to suppress fluctuation in the potential of the node ND[1].

[0319] The gate of the transistor 10[5] is electrically connected to the terminal 115, and the drain of the transistor 10[5] is electrically connected to the wiring 131. The source of the transistor 10[5] is electrically connected to the gate of the transistor 10[2], the gate of the transistor 10[9], the gate of the transistor 10

[11] , and the drain of the transistor 10[6].

[0320] The gate of the transistor 10[7] is electrically connected to the wiring 131, and one of the source and the drain of the transistor 10[7] is electrically connected to the source of the transistor 10[1] and the drain of the transistor 10[2]. The other of the source and the drain of the transistor 10[7] is electrically connected to the gate of the transistor 10[8], one of the terminals of the capacitor 20[2], the gate of the transistor 10

[10] , and one of the terminals of the capacitor 20[3].

[0321] Note that in this specification and the like, a region in which one of the source and the drain of the transistor 10[7], the source of the transistor 10[1], and the drain of the transistor 10[2] are electrically connected is referred to as a node ND[2]. Furthermore, in this specification and the like, a region in which the other of the source and the drain of the transistor 10[7], the gate of the transistor 10[8], one of the terminals of the capacitor 20[2], the gate of the transistor 10

[10] , and one of the terminals of the capacitor 20[3] are electrically connected is referred to as a node ND[3].

[0322] The drain of the transistor 10[8] is electrically connected to the terminal 111. The source of the transistor 10[8] is electrically connected to the other terminal of the capacitor 20[2], the terminal 114, and the drain of the transistor 10[9]. The drain of the transistor 10

[10] is electrically connected to the terminal 118. The source of the transistor 10

[10] is electrically connected to the other terminal of the capacitor 20[3], the terminal 116, and the drain of the transistor 10

[11] .

[0323] The source of the transistor 10[9] and the source of the transistor 10

[11] are electrically connected to the wiring 132.

[0324] Note that the drain of the transistor 10[1], the drain of the transistor 10[3], the drain of the transistor 10[5], and the gate of the transistor 10[7] can be electrically connected to different wirings, respectively. Furthermore, the source of the transistor 10[6], the source of the transistor 10[9], and the source of the transistor 10

[11] can be electrically connected to different wirings, respectively.

[0325] For example, as FIG. 13As shown, the drain of the transistor 10[1] can also be electrically connected to the wiring 131[1], the drain of the transistor 10[3] can also be electrically connected to the wiring 131[2], the drain of the transistor 10[5] can also be electrically connected to the wiring 131[3], and the gate of the transistor 10[7] can also be electrically connected to the wiring 131[4]. In addition, the source of the transistor 10[6] can also be electrically connected to the wiring 132[1], the source of the transistor 10[9] can also be electrically connected to the wiring 132[2], and the source of the transistor 10

[11] can also be electrically connected to the wiring 132[3]. Note that, as shown in FIG. 1A, the drain of the transistor 10[2] can also be electrically connected to the wiring 131[1], the drain of the transistor 10[4] can also be electrically connected to the wiring 131[2], the drain of the transistor 10[6] can also be electrically connected to the wiring 131[3], and the gate of the transistor 10[8] can also be electrically connected to the wiring 131[4]. In addition, the source of the transistor 10[7] can also be electrically connected to the wiring 132[1], the source of the transistor 10

[10] can also be electrically connected to the wiring 132[2], and the source of the transistor 10

[12] can also be electrically connected to the wiring 132[3]. FIG. 14 As shown, the drain of the transistor 10[1] can also be electrically connected to the wiring 131[1], the drain of the transistor 10[3] can also be electrically connected to the wiring 131[2], the drain of the transistor 10[5] can also be electrically connected to the wiring 131[3], and the gate of the transistor 10[7] can also be electrically connected to the wiring 131[4]. In addition, the source of the transistor 10[6] can also be electrically connected to the wiring 132[1], the source of the transistor 10[9] can also be electrically connected to the wiring 132[2], and the source of the transistor 10

[11] can also be electrically connected to the wiring 132[3]. Note that, as shown in FIG. 1A, the drain of the transistor 10[2] can also be electrically connected to the wiring 131[1], the drain of the transistor 10[4] can also be electrically connected to the wiring 131[2], the drain of the transistor 10[6] can also be electrically connected to the wiring 131[3], and the gate of the transistor 10[8] can also be electrically connected to the wiring 131[4]. In addition, the source of the transistor 10[7] can also be electrically connected to the wiring 132[1], the source of the transistor 10

[10] can also be electrically connected to the wiring 132[2], and the source of the transistor 10

[12] can also be electrically connected to the wiring 132[3].

[0326] The terminal 115 is supplied with a signal RIN, the terminal 117 is supplied with a signal LIN, the terminal 114 is supplied with a signal SROUT, and the terminal 116 is supplied with a signal OUT. In the first-stage signal output circuit 110a, the terminal 111 is supplied with a signal CLK_1, the terminal 112 is supplied with a signal CLK_2, the terminal 113 is supplied with a signal CLK_3, and the terminal 118 is supplied with a signal PWC_1.

[0327] In the second-stage signal output circuit 110a, the terminal 111 is supplied with a signal CLK_2, the terminal 112 is supplied with a signal CLK_3, the terminal 113 is supplied with a signal CLK_4, and the terminal 118 is supplied with a signal PWC_2.

[0328] 〔Structure Example of Transistor〕

[0329] A structure example of a transistor which can be used as the transistor 10 will be described. FIG. 15A is a plan view of the transistor 10. FIG. 15B is a cross-sectional view of a portion along the dotted line Al-A2 in FIG. 15A . FIG. 15C is a perspective view of the transistor 10 with a portion thereof removed. FIG. 15D is an equivalent circuit diagram of the transistor 10. In order to easily understand the structure of the transistor 10, a part of the description of the constituent elements of the transistor 10 is omitted in FIG. 15A and FIG. 15C . For example, in FIG. 15A and FIG. 15C , the description of the insulating layer 164 and the like shown in FIG. 15B is omitted.

[0330] FIG. 16A and FIG. 16B are enlarged views of the transistor 10 shown in FIG. 15B . Furthermore, FIG. 16C is a view of the opening 159 when viewed in the Z direction.

[0331] In the transistor 10, an insulating layer 154 is included over a substrate 153, and a conductive layer 155 is included over the insulating layer 154. Furthermore, an insulating layer 156 is included over the conductive layer 155, an insulating layer 157 is included over the insulating layer 156, and an insulating layer 158 is included over the insulating layer 157. Furthermore, a conductive layer 160 is included over the insulating layer 158.

[0332] In a region overlapping with part of the conductive layer 155, an opening 159 is provided in the conductive layer 160, the insulating layer 158, the insulating layer 157, and the insulating layer 156 (see FIG. 1B). FIG. 15B FIG. 16A Furthermore, a semiconductor layer 161 is included in the opening 159. The semiconductor layer 161 has a region overlapping with a bottom of the opening 159 and a region overlapping with a side surface of the opening 159. The semiconductor layer 161 has a region in contact with a side surface of the insulating layer 158, a region in contact with a side surface of the insulating layer 157, and a region in contact with a side surface of the insulating layer 156. In addition, part of the semiconductor layer 161 is electrically connected to the conductive layer 160, and another part of the semiconductor layer 161 is electrically connected to the conductive layer 155.

[0333] An insulating layer 162 is included over the insulating layer 158, the conductive layer 160, and the semiconductor layer 161, and a conductive layer 163 is included over the insulating layer 162. Furthermore, an insulating layer 164 is included over the insulating layer 162 and the conductive layer 163. The insulating layer 162 has a region overlapping with a side surface of the opening 159 with the semiconductor layer 161 interposed therebetween. The conductive layer 163 is provided so as to cover the semiconductor layer 161. Thus, the conductive layer 163 has a region extending beyond an end portion of the semiconductor layer 161. Furthermore, the conductive layer 163 has a region overlapping with a side surface of the opening 159 with the insulating layer 162 and the semiconductor layer 161 interposed therebetween.

[0334] The conductive layer 155 has a region serving as one of a source electrode and a drain electrode of the transistor 10. Furthermore, the conductive layer 160 has a region serving as the other of the source electrode and the drain electrode of the transistor 10. For example, when the conductive layer 155 is used as the drain electrode of the transistor 10, the conductive layer 160 is used as the source electrode of the transistor 10.

[0335] The semiconductor layer 161 has a region serving as a channel-forming semiconductor layer of the transistor 10, the insulating layer 162 has a region serving as a gate insulating layer, and the conductive layer 163 has a region serving as a gate electrode. Thus, the transistor 10 is provided in a region including the opening 159.

[0336] ​In the transistor 10, the source electrode and the drain electrode are arranged in the Z direction. Thus, the source and the drain of the transistor 10 are arranged at different positions in the Z direction, respectively. For example, with the top surface of the substrate 153 as a reference, the source and the drain of the transistor 10 are arranged so as to be different from each other in distance from the top surface of the substrate 153 serving as the reference. Such a transistor is also referred to as a "vertical channel transistor", a "vertical transistor", or a "VFET (Vertical Field Effect Transistor)". In the vertical channel transistor, the direction in which Id (drain current) flows includes a component in the Z direction (vertical direction). For example, in the transistor 10 which is a vertical channel transistor, when a cross section passing through the center (or the barycenter) of the opening 159 seen in the Z direction is seen in the X direction or the Y direction, the angle θ (see FIG. 1B) formed by the formed surface of the semiconductor layer 161 on the conductive layer 155 and the direction in which Id flows is 5 degrees or more and 110 degrees or less, 10 degrees or more and 90 degrees or less, 30 degrees or more and 90 degrees or less, or 60 degrees or more and 90 degrees or less. FIG. 16A

[0337] In addition, as described above, the semiconductor layer 161 has a region which is in contact with the side surface of the insulating layer 157. Thus, Id flows along the side surface of the insulating layer 157. By this, the angle θ formed by the formed surface of the semiconductor layer 161 on the conductive layer 155 and the direction in which Id flows can also be referred to as the angle θ formed by the formed surface of the semiconductor layer 161 on the conductive layer 155 and the side surface of the insulating layer 157.

[0338] The vertical channel transistor can reduce the area occupied by the transistor because the source electrode and the drain electrode are arranged in the Z direction. By using the vertical channel transistor as a semiconductor device, the area occupied by the semiconductor device can be significantly reduced.

[0339] Here, one example of a material which can be used for the transistor 10 or the semiconductor device according to one embodiment of the present application is described.

[0340] [Substrate]

[0341] There is no particular limitation on the material used for the substrate. The material can be determined in consideration of the purpose, whether or not light-transmitting properties and heat resistance to the extent that can withstand heat treatment are needed, and the like. For example, a glass substrate such as barium borosilicate glass and aluminum borosilicate glass, a ceramic substrate, a quartz substrate, a sapphire substrate, or the like can be used as an insulating substrate. Alternatively, a semiconductor substrate, a flexible substrate, a bonding film, a base material film, or the like can be used.

[0342] ​For example, as the semiconductor substrate, a semiconductor substrate composed of silicon or germanium, or a compound semiconductor substrate composed of silicon carbide, silicon germanium, gallium arsenide, indium phosphide, zinc oxide, or gallium oxide can be given. Note that the semiconductor substrate can be a single-crystal semiconductor or a polycrystalline semiconductor.

[0343] As a substrate when the transistor 10 according to one embodiment of the present application is used for a display device, for example, a glass substrate having a large area of the sixth generation (1500 mm x 1850 mm), the seventh generation (1870 mm x 2200 mm), the eighth generation (2200 mm x 2400 mm), the ninth generation (2400 mm x 2800 mm), the tenth generation (2950 mm x 3400 mm), or the like can be used. Thus, a large display device can be manufactured. By making the substrate large, more display devices can be manufactured from one substrate, so that the manufacturing cost can be reduced.

[0344] As a material of a flexible substrate, an attachment film, a base film, or the like, for example, a polyester such as polyethylene terephthalate (PET) or polyethylene naphthalate (PEN), polyacrylonitrile, an acrylic resin, a polyimide, polymethyl methacrylate, polycarbonate (PC), polyethersulfone (PES), a polyamide (nylon, aramid, or the like), polysiloxane, a cyclic olefin resin, polystyrene, a polyamide-imide, a polyurethane, polyvinyl chloride, polyvinylidene chloride, polypropylene, polytetrafluoroethylene (PTFE), an ABS resin, and a cellulose nanofiber, or the like can be used.

[0345] By using the above material as a substrate, a lightweight semiconductor device including the transistor 10 can be provided. Furthermore, by using the above material as a substrate, a semiconductor device with high impact resistance can be provided. Furthermore, by using the above material as a substrate, a semiconductor device which is less likely to be broken can be provided.

[0346] The lower the linear expansion coefficient of the flexible substrate used as a substrate, the more the deformation of the flexible substrate due to the environment can be suppressed, and thus the flexible substrate is preferably low in linear expansion coefficient. For example, the flexible substrate used as a substrate can use a material having a linear expansion coefficient of 1 x 10 -3 / K or lower, 5 x 10 -5 / K or lower, or 1 x 10 -5 / K or lower. In particular, an aramid has a low linear expansion coefficient, and thus is suitable for a flexible substrate.

[0347] [Conductive layer]

[0348] As the conductive material that can be used for the conductive layer of the gate electrode, the source electrode, and the drain electrode of the transistor 10, various wirings, and electrodes constituting a semiconductor device, and the like, a metal element selected from aluminum (Al), chromium (Cr), copper (Cu), silver (Ag), gold (Au), platinum (Pt), tantalum (Ta), nickel (Ni), titanium (Ti), molybdenum (Mo), tungsten (W), hafnium (Hf), vanadium (V), niobium (Nb), manganese (Mn), magnesium (Mg), zirconium (Zr), beryllium (Be), and the like, an alloy including the above metal element, or an alloy in which the above metal elements are combined, and the like can be used. In addition, a semiconductor typified by polysilicon including an impurity element such as phosphorus, a silicide such as nickel silicide, and the like can be used. There is no particular limitation on a method for forming the conductive material, and various formation methods such as an evaporation method, an atomic layer deposition (ALD) method, a chemical vapor deposition (CVD) method, a sputtering method, a spin coating method, and the like can be used.

[0349] In addition, as the conductive material, a Cu-X alloy (X is Mn, Ni, Cr, Fe, Co, Mo, Ta, or Ti) can be used. A layer formed using the Cu-X alloy can be processed with a wet etching process, and thus manufacturing cost can be reduced. In addition, as the conductive material, an aluminum alloy including one or more elements selected from titanium, tantalum, tungsten, molybdenum, chromium, neodymium, and scandium can be used.

[0350] As the conductive material that can be used for the conductive layer, a conductive material including oxygen such as indium tin oxide, indium oxide including tungsten oxide, indium zinc oxide including tungsten oxide, indium oxide including titanium oxide, indium tin oxide including titanium oxide, indium zinc oxide, indium tin oxide to which silicon oxide is added, and the like can be used. In addition, a conductive material including nitrogen such as titanium nitride, tantalum nitride, tungsten nitride, and the like can be used. In addition, the conductive layer can have a stacked-layer structure in which the conductive material including oxygen, the conductive material including nitrogen, and the material including the above metal element are appropriately combined.

[0351] For example, the conductive layer can have a single-layer structure of an aluminum layer including silicon, a two-layer structure in which a titanium layer is stacked over an aluminum layer, a two-layer structure in which a titanium layer is stacked over a titanium nitride layer, a two-layer structure in which a tungsten layer is stacked over a titanium nitride layer, a two-layer structure in which a tungsten layer is stacked over a tantalum nitride layer, and a three-layer structure in which a titanium layer, an aluminum layer, and a titanium layer are sequentially stacked.

[0352] In addition, a plurality of conductive layers formed of the above-described conductive material can be stacked. For example, the conductive layer can also adopt a stacked structure combining a material containing the above-described metal element and a conductive material containing oxygen. In addition, a stacked structure combining a material containing the above-described metal element and a conductive material containing nitrogen can also be adopted. In addition, a stacked structure combining a material containing the above-described metal element, a conductive material containing oxygen, and a conductive material containing nitrogen can also be adopted.

[0353] For example, the conductive layer can also adopt a three-layer structure in which a conductive layer containing at least one of indium and zinc and oxygen, a conductive layer containing copper, and a conductive layer containing at least one of indium and zinc and oxygen are sequentially stacked. At this time, it is preferable that the side of the conductive layer containing copper is also covered with a conductive layer containing at least one of indium and zinc and oxygen. In addition, for example, a plurality of conductive layers containing at least one of indium and zinc and oxygen can be stacked as the conductive layer.

[0354] [Insulating layer]

[0355] As the insulating layer, a single layer or a stacked layer selected from aluminum nitride, aluminum oxide, aluminum oxynitride, aluminum nitride oxide, magnesium oxide, silicon nitride, silicon oxide, silicon oxynitride, silicon nitride oxide, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide, tantalum oxide, aluminosilicate, and the like can be used. In addition, a plurality of oxide materials, nitride materials, oxynitride materials, and nitride oxide materials can also be used.

[0356] The method for forming the insulating material is not particularly limited, and various formation methods such as an evaporation method, an ALD method, a CVD method, a sputtering method, a spin coating method, and the like can be used.

[0357] In the present specification and the like, a nitride oxide refers to a material in which the nitrogen content is greater than the oxygen content. In addition, an oxynitride refers to a material in which the oxygen content is greater than the nitrogen content. In addition, the content of each element can be measured using, for example, a Rutherford Backscattering Spectrometry (RBS) or the like.

[0358] For example, the insulating layer 154 and the insulating layer 164 are preferably formed using an insulating material that is less likely to allow impurities to pass therethrough. For example, a single layer or a stacked layer of an insulating material containing boron, carbon, nitrogen, oxygen, fluorine, magnesium, aluminum, silicon, phosphorus, chlorine, argon, gallium, germanium, yttrium, zirconium, lanthanum, neodymium, hafnium, or tantalum can be used. For example, as one example of an insulating material that is less likely to allow impurities to pass therethrough, aluminum oxide, aluminum nitride, aluminum oxynitride, aluminum nitride oxide, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide, tantalum oxide, silicon nitride, and the like can be given.

[0359] By using an insulating material that is less likely to allow impurities to pass therethrough as the insulating layer 154, diffusion of impurities from the substrate 153 side can be suppressed, and the reliability of the transistor 10 can be improved. That is, the reliability of a semiconductor device including the transistor 10 can be improved. By using an insulating material that is less likely to allow impurities to pass therethrough as the insulating layer 164, diffusion of impurities from above the insulating layer 164 can be suppressed, and the reliability of the transistor 10 can be improved. That is, the reliability of a semiconductor device including the transistor 10 can be improved.

[0360] In addition, as the insulating layer, an insulating layer used as a planarization layer can be used. As a material of the insulating layer used as a planarization layer, an acrylic resin, a polyimide, an epoxy resin, a polyamide, a polyimide amide, a silicone resin, a benzocyclobutene-based resin, a phenol resin, and a precursor of these resins, and the like can be given. In addition to the above-described organic material, a low-k material, a silicone resin, PSG (phosphosilicate glass), BPSG (borophosphosilicate glass), and the like can be used. In addition, a plurality of insulating layers formed of these materials can be stacked.

[0361] In addition, the silicone resin corresponds to a resin including a Si-O-Si bond formed using a silicone-based material as a starting material. The silicone resin can have an organic group (e.g., an alkyl group or an aryl group) or a fluorine group as a substituent. Further, the organic group can include a fluorine group.

[0362] In addition, the surface of the insulating layer or the like can be subjected to CMP treatment. By performing the CMP treatment, the unevenness of the surface of the insulating layer or the like can be reduced, and thus the coverage of the insulating layer and the conductive layer formed later can be improved.

[0363] [Semiconductor Layer]

[0364] As the semiconductor layer 161, a single-crystal semiconductor, a polycrystal semiconductor, a microcrystal semiconductor, or an amorphous semiconductor, or the like can be used alone or in combination. As a semiconductor material, for example, a semiconductor material having a band gap (a semiconductor material that is not a zero-bandgap semiconductor) such as silicon, germanium, or the like can be used. For example, a single-element semiconductor, a compound semiconductor, or a layered substance (also referred to as an atomic layer substance, a two-dimensional material, or the like), or the like is preferably used as a semiconductor material. As a compound semiconductor, an organic substance having semiconductor properties or a metal oxide having semiconductor properties (also referred to as an oxide semiconductor) can be used. Note that these semiconductor materials can include impurities as dopants.

[0365] For example, as the semiconductor layer 161, a single-crystal silicon, a polycrystal silicon, a microcrystal silicon, or an amorphous silicon can be used. As the polycrystal silicon, for example, a low-temperature polycrystal silicon (LTPS: Low Temperature Poly Silicon) can be used.

[0366] A transistor using amorphous silicon for the semiconductor layer 161 can be formed on a large-sized glass substrate and can be manufactured at low cost. A transistor using polycrystalline silicon for the semiconductor layer 161 has high field-effect mobility and can operate at high speed. Further, a transistor using microcrystalline silicon for the semiconductor layer 161 has high field-effect mobility and can operate at high speed as compared with a transistor using amorphous silicon.

[0367] As a compound semiconductor which can be used for a semiconductor material, silicon carbide, silicon germanium, gallium arsenide, indium phosphide, boron nitride, boron arsenide, and the like can be given. Boron nitride which can be used for a semiconductor layer preferably has an amorphous structure. Boron arsenide which can be used for a semiconductor layer preferably includes a crystal having a cubic crystal structure.

[0368] The semiconductor layer 161 can also include a layered material used as a semiconductor. The layered material is a general term for a group of materials having a layered crystal structure. The layered crystal structure is a structure in which layers formed by covalent bonds or ionic bonds are stacked by bonding such as van der Waals force which is weaker than covalent bonds and ionic bonds. The layered material has high conductivity in a unit layer, i.e., has high two-dimensional conductivity. By using a material used as a semiconductor and having high two-dimensional conductivity for a channel formation region, a transistor with a large on-state current can be provided.

[0369] As the layered material, for example, graphene, silicene, boron carbonitride, a chalcogenide, and the like can be given. In boron carbonitride as the layered material, carbon atoms, nitrogen atoms, and boron atoms are arranged in a hexagonal lattice structure on a plane. The chalcogenide is a compound containing a chalcogen element. Further, the chalcogen element is a general term for elements belonging to Group 16, which includes oxygen, sulfur, selenium, tellurium, polonium, and astatine. Further, as the chalcogenide, a transition metal chalcogenide, a Group 13 chalcogenide, and the like can be given. As the transition metal chalcogenide which can be used for a semiconductor layer of a transistor, specifically, molybdenum sulfide (typically, MoS2), molybdenum selenide (typically, MoSe2), molybdenum telluride (typically, MoTe2), tungsten sulfide (typically, WS2), tungsten selenide (typically, WSe2), tungsten telluride (typically, WTe2), hafnium sulfide (typically, HfS2), hafnium selenide (typically, HfSe2), zirconium sulfide (typically, ZrS2), zirconium selenide (typically, ZrSe2), and the like can be given. By using the above-described transition metal chalcogenide for a semiconductor layer, a storage device with a large on-state current can be provided.

[0370] The oxide semiconductor has a band gap of 2 eV or more, and thus a transistor (also referred to as an "OS transistor") using an oxide semiconductor among metal oxides in a semiconductor layer where a channel is formed has extremely low off-state current. Thus, power consumption of a semiconductor device including the OS transistor can be reduced. Furthermore, the OS transistor stably operates with little variation in characteristics even in a high-temperature environment. For example, the off-state current is hardly increased even in a high-temperature environment. Specifically, the off-state current is hardly increased even in an environment at a temperature higher than or equal to room temperature and lower than or equal to 200 °C. Moreover, the on-state current is not easily decreased even in a high-temperature environment. Thus, a semiconductor device including the OS transistor stably operates with high reliability even in a high-temperature environment.

[0371] In this embodiment and the like, an OS transistor is preferably used as the transistor 10. The OS transistor can have a short channel length because of high withstand voltage between a source and a drain. Thus, the on-state current can be increased. The OS transistor is suitable for a vertical channel transistor.

[0372] The channel length can be, for example, 5 nm or more, 7 nm or more, or 10 nm or more and smaller than 3 μm, 2.5 μm or less, 2 μm or less, 1.5 μm or less, 1.2 μm or less, 1 μm or less, 500 nm or less, 300 nm or less, 200 nm or less, 100 nm or less, 50 nm or less, 30 nm or less, or 20 nm or less. For example, the channel length L can be set to be 100 nm or more and 1 μm or less.

[0373] As the metal oxide which can be used for the semiconductor layer of the OS transistor, for example, an indium oxide, a gallium oxide, and a zinc oxide can be given. The metal oxide preferably contains at least indium (In) or zinc (Zn). Furthermore, the metal oxide preferably contains two or three of indium, an element M, and zinc. Note that the element M is a metal element or a semi-metal element having high bonding energy with oxygen, for example, a metal element or a semi-metal element having higher bonding energy with oxygen than indium.

[0374] As the element M, specifically, an aluminum, a gallium, a tin, a yttrium, a titanium, a vanadium, a chromium, a manganese, an iron, a cobalt, a nickel, a zirconium, a molybdenum, a hafnium, a tantalum, a tungsten, a lanthanum, a cerium, a neodymium, a magnesium, a calcium, a strontium, a barium, a boron, a silicon, a germanium, an antimony, and the like can be given. The element M contained in the metal oxide is preferably any one or a plurality of the above elements, more preferably one or a plurality of elements selected from an aluminum, a gallium, a tin, and a yttrium, and further preferably a gallium. Note that in this specification and the like, a metal element and a semi-metal element are collectively referred to as a "metal element", and sometimes the "metal element" described in this specification and the like includes a semi-metal element.

[0375] For example, indium-zinc oxide (In-Zn oxide), indium-tin oxide (In-Sn oxide), indium-titanium oxide (In-Ti oxide), indium-gallium oxide (In-Ga oxide), indium-gallium-aluminum oxide (In-Ga-Al oxide), indium-gallium-tin oxide (In-Ga-Sn oxide), gallium-zinc oxide (Ga-Zn oxide, also referred to as GZO), aluminum-zinc oxide (Al-Zn oxide, also referred to as AZO), indium-aluminum-zinc oxide (In-Al-Zn oxide, also referred to as IAZO), indium-tin-zinc oxide (In-Sn-Zn oxide), indium-titanium-zinc oxide (In-Ti-Zn oxide), indium-gallium-zinc oxide (In-Ga-Zn oxide, also referred to as IGZO), indium-gallium-tin-zinc oxide (In-Ga-Sn-Zn oxide, also referred to as IGZTO), indium-gallium-aluminum-zinc oxide (In-Ga-Al-Zn oxide, also referred to as IGAZO or IAGZO), or the like can be used. Alternatively, indium-tin oxide containing silicon, gallium-tin oxide (Ga-Sn oxide), aluminum-tin oxide (Al-Sn oxide), or the like can be used.

[0376] By increasing the proportion of the atomic number of indium included in the metal oxide to the sum of the atomic numbers of all metal elements, the field-effect mobility of the transistor can be increased.

[0377] The metal oxide can further contain one or more of a metal element having a large number of orbits. The larger the number of orbits of the metal element, the greater the tendency of the carrier to be easily conducted in the metal oxide. Thus, by containing a metal element having a large number of orbits, the field-effect mobility of the transistor can be increased in some cases. As the metal element having a large number of orbits, a metal element belonging to the fifth period and a metal element belonging to the sixth period, or the like can be given. Specifically, as the metal element, yttrium, zirconium, silver, cadmium, tin, antimony, barium, lead, bismuth, lanthanum, cerium, praseodymium, neodymium, promethium, samarium, and europium, or the like can be given. Note that lanthanum, cerium, praseodymium, neodymium, promethium, samarium, and europium are called light rare earth elements.

[0378] The metal oxide can further contain one or more of a non-metal element. By containing a non-metal element in the metal oxide, the field-effect mobility of the transistor can be increased in some cases. As the non-metal element, carbon, nitrogen, phosphorus, sulfur, selenium, fluorine, chlorine, bromine, hydrogen, or the like can be given.

[0379] By increasing the proportion of the atomic number of zinc included in the metal oxide to the sum of the atomic numbers of metal elements among the main component elements, the metal oxide can be made to have high crystallinity, and thus the diffusion of impurities in the metal oxide can be suppressed. Thus, the variation in electrical characteristics of the transistor can be suppressed and the reliability can be increased.

[0380] By increasing the proportion of the number of atoms of element M relative to the sum of the number of atoms of metal elements among the main component elements included in the metal oxide, formation of oxygen vacancies in the metal oxide can be inhibited. Thus, generation of carriers due to oxygen vacancies is inhibited, whereby a transistor with low off-state current can be realized. Furthermore, variation in electrical characteristics of the transistor is inhibited, whereby reliability can be improved.

[0381] The electrical characteristics and reliability of the transistor vary depending on the composition of the metal oxide used for the semiconductor layer. Thus, by varying the composition of the metal oxide depending on the electrical characteristics and reliability required for the transistor, a semiconductor device with excellent electrical characteristics and high reliability can be realized.

[0382] In the case where an In-Zn oxide is used for the semiconductor layer of the OS transistor, a metal oxide whose atomic proportion of indium is higher than that of zinc is preferably used. For example, a metal oxide whose atomic proportion of metal elements is In:Zn = 1 : 1, In:Zn = 2: 1, In:Zn = 3: 1, In:Zn = 4: 1, In:Zn = 5: 1, In:Zn = 7: 1, In:Zn = 10: 1, or the like can be used.

[0383] In the case where an In-Sn oxide is used for the semiconductor layer of the OS transistor, a metal oxide whose atomic proportion of indium is higher than that of tin is preferably used. For example, a metal oxide whose atomic proportion of metal elements is In:Sn = 1 : 1, In:Sn = 2: 1, In:Sn = 3: 1, In:Sn = 4: 1, In:Sn = 5: 1, In:Sn = 7: 1, In:Sn = 10: 1, or the like can be used.

[0384] In the case where an In-Sn-Zn oxide is used for the semiconductor layer of the OS transistor, a metal oxide in which the atomic ratio of indium is higher than that of tin can be used. Further, a metal oxide in which the atomic ratio of zinc is higher than that of tin is preferably used. For example, a metal oxide in which the atomic ratio of the metal elements is In:Sn:Zn = 2: 1 :3, In:Sn:Zn = 3: 1 :2, In:Sn:Zn = 4:2:3, In:Sn:Zn = 4:2:4.1, In:Sn:Zn = 5: 1 :3, In:Sn:Zn = 5: 1 :6, In:Sn:Zn = 5: 1 :7, In:Sn:Zn = 5: 1 :8, In:Sn:Zn = 6: 1 :6, In:Sn:Zn = 10: 1 :3, In:Sn:Zn = 10: 1 :6, In:Sn:Zn = 10: 1 :7, In:Sn:Zn = 10: 1 :8, In:Sn:Zn = 5:2:5, In:Sn:Zn = 10: 1 : 10, In:Sn:Zn = 20: 1 : 10, In:Sn:Zn = 40: 1 : 10, or the like can be used.

[0385] In the case where an In-Sn-Zn oxide is used for the semiconductor layer of the OS transistor, a metal oxide in which the atomic ratio of indium is higher than that of tin can be used. Further, a metal oxide in which the atomic ratio of zinc is higher than that of tin is preferably used. For example, a metal oxide in which the atomic ratio of the metal elements is In:Sn:Zn = 2: 1 :3, In:Sn:Zn = 3: 1 :2, In:Sn:Zn = 4:2:3, In:Sn:Zn = 4:2:4.1, In:Sn:Zn = 5: 1 :3, In:Sn:Zn = 5: 1 :6, In:Sn:Zn = 5: 1 :7, In:Sn:Zn = 5: 1 :8, In:Sn:Zn = 6: 1 :6, In:Sn:Zn = 10: 1 :3, In:Sn:Zn = 10: 1 :6, In:Sn:Zn = 10: 1 :7, In:Sn:Zn = 10: 1 :8, In:Sn:Zn = 5:2:5, In:Sn:Zn = 10: 1 : 10, In:Sn:Zn = 20: 1 : 10, In:Sn:Zn = 40: 1 : 10, or the like can be used.

[0386] In the case where an In-Ga-Zn oxide is used for the semiconductor layer of the OS transistor, a metal oxide whose atomic ratio of indium to the total of atomic numbers of metal elements is higher than the atomic ratio of gallium can be used. Further, a metal oxide whose atomic ratio of zinc to the total of atomic numbers of metal elements is higher than the atomic ratio of gallium is further preferable. For example, a metal oxide whose atomic ratio of metal elements is In:Ga:Zn = 2:1:3, In:Ga:Zn = 3:1:2, In:Ga:Zn = 4:2:3, In:Ga:Zn = 4:2:4.1, In:Ga:Zn = 5:1:3, In:Ga:Zn = 5:1:6, In:Ga:Zn = 5:1:7, In:Ga:Zn = 5:1:8, In:Ga:Zn = 6:1:6, In:Ga:Zn = 10:1:3, In:Ga:Zn = 10:1:6, In:Ga:Zn = 10:1:7, In:Ga:Zn = 10:1:8, In:Ga:Zn = 5:2:5, In:Ga:Zn = 10:1:10, In:Ga:Zn = 20:1:10, In:Ga:Zn = 40:1:10, or the like can be used.

[0387] In the case where an In-M-Zn oxide is used for the semiconductor layer of the OS transistor, a metal oxide whose atomic ratio of indium to the total of atomic numbers of metal elements is higher than the atomic ratio of element M can be used. Further, a metal oxide whose atomic ratio of zinc to the total of atomic numbers of metal elements is higher than the atomic ratio of element M is further preferable. For example, a metal oxide whose atomic ratio of metal elements is In:M:Zn = 2:1:3, In:M:Zn = 3:1:2, In:M:Zn = 4:2:3, In:M:Zn = 4:2:4.1, In:M:Zn = 5:1:3, In:M:Zn = 5:1:6, In:M:Zn = 5:1:7, In:M:Zn = 5:1:8, In:M:Zn = 6:1:6, In:M:Zn = 10:1:3, In:M:Zn = 10:1:6, In:M:Zn = 10:1:7, In:M:Zn = 10:1:8, In:M:Zn = 5:2:5, In:M:Zn = 10:1:10, In:M:Zn = 20:1:10, In:M:Zn = 40:1:10, or the like can be used.

[0388] Note that in the case where a plurality of metal elements are included as element M, the total of atomic ratios of the metal elements can be the atomic ratio of element M. For example, in the case of using an In-Ga-Al-Zn oxide including gallium and aluminum as element M, the total of the atomic ratio of gallium and the atomic ratio of aluminum can be the atomic ratio of element M. Further, the atomic ratios of indium, element M, and zinc are preferably in the above ranges.

[0389] It is preferable to use a metal oxide in which the proportion of the number of atoms of indium to the sum of the number of atoms of metal elements among the primary component elements contained in the metal oxide is 30 atomic % or more and 100 atomic % or less, preferably 30 atomic % or more and 95 atomic % or less, more preferably 35 atomic % or more and 95 atomic % or less, more preferably 35 atomic % or more and 90 atomic % or less, more preferably 40 atomic % or more and 90 atomic % or less, more preferably 45 atomic % or more and 90 atomic % or less, more preferably 50 atomic % or more and 80 atomic % or less, more preferably 60 atomic % or more and 80 atomic % or less, and more preferably 70 atomic % or more and 80 atomic % or less. For example, in the case where an In-M-Zn oxide is used as a semiconductor layer, the proportion of the number of atoms of indium to the total of the number of atoms of indium, element M, and zinc is preferably within the above range.

[0390] As described above, when the proportion of the number of atoms of indium to the sum of the number of atoms of metal elements among the primary component elements contained in the metal oxide is increased, the field-effect mobility of the transistor can be increased. By using the transistor, a circuit that operates at high speed can be manufactured. Furthermore, the area occupied by the circuit can be reduced. For example, in the case where the transistor is used for a large display device or a high-resolution display device, the signal delay of each wiring can be reduced even when the number of wirings is increased, and thus display unevenness can be suppressed. Moreover, since the area occupied by the circuit can be reduced, the frame of the display device can be made small.

[0391] The analysis of the composition of the metal oxide can be performed using, for example, energy dispersive X-ray spectroscopy (EDX), X-ray photoelectron spectroscopy (XPS), inductively coupled plasma-mass spectrometry (ICP-MS), or inductively coupled plasma-atomic emission spectrometry (ICP-AES). Alternatively, a plurality of the above methods can be combined and used for the analysis. Note that the actual content of an element with a low content ratio can be different from the content ratio obtained by analysis due to the analysis accuracy. For example, when the content of element M is low, the content of element M obtained by analysis can be lower than the actual content.

[0392] Metal oxides are preferably formed using sputtering or ALD methods. Note that when forming metal oxides using sputtering, the atomic ratio of the target material may differ from the atomic ratio of the metal oxide. In particular, the atomic ratio of zinc in the metal oxide is sometimes lower than the atomic ratio of zinc in the target material. Specifically, this zinc atomic ratio is sometimes about 40% to 90% of the zinc atomic ratio in the target material.

[0393] By using a metal oxide that does not contain gallium or has a low gallium content in the semiconductor layer, a transistor with high reliability under forward bias can be realized. In other words, a transistor with small variations in threshold voltage during PBTS testing can be achieved. Furthermore, when using a gallium-containing metal oxide, the gallium content is preferably lower than the indium content. This results in a transistor with high reliability.

[0394] One reason for the variation in threshold voltage during PBTS testing can be the presence of defect states at or near the interface between the semiconductor layer and the gate insulating layer. A higher defect state density results in more significant degradation during PBTS testing. The formation of these defect states can be suppressed by reducing the gallium content in the region of the semiconductor layer that contacts the gate insulating layer.

[0395] The reason why using a metal oxide containing little or no gallium as the semiconductor layer can suppress threshold voltage variations in PBTS testing is as follows: Gallium contained in metal oxides is more likely to draw oxygen than other metals (such as indium or zinc). Therefore, it can be inferred that at the interface between a metal oxide containing more gallium and the gate insulating layer, carrier (here, electron) trap sites are easily generated through gallium bonding with excess oxygen in the gate insulating layer. Therefore, when a positive potential is applied to the gate, carriers are trapped at the interface between the semiconductor layer and the gate insulating layer, and the threshold voltage changes.

[0396] More specifically, when using In-Ga-Zn oxide as the semiconductor layer, a metal oxide with an indium atomic ratio higher than that of gallium can be used. More preferably, a metal oxide with a zinc atomic ratio greater than that of gallium is used. In other words, a metal oxide with a metal element atomic ratio satisfying In>Ga and Zn>Ga is used as the semiconductor layer.

[0397] For example, the semiconductor layer of the OS transistor can use a metal oxide in which the atomic ratio of the metal elements is In:Ga:Zn = 2:1:3, In:Ga:Zn = 3:1:2, In:Ga:Zn = 4:2:3, In:Ga:Zn = 4:2:4.1, In:Ga:Zn = 5:1:3, In:Ga:Zn = 5:1:6, In:Ga:Zn = 5:1:7, In:Ga:Zn = 5:1:8, In:Ga:Zn = 6:1:6, In:Ga:Zn = 10:1:3, In:Ga:Zn = 10:1:6, In:Ga:Zn = 10:1:7, In:Ga:Zn = 10:1:8, In:Ga:Zn = 5:2:5, In:Ga:Zn = 10:1:10, In:Ga:Zn = 20:1:10, In:Ga:Zn = 40:1:10, or the like.

[0398] The semiconductor layer of the OS transistor preferably uses a metal oxide in which the atomic percentage of gallium with respect to the atomic number of the metal elements contained is higher than 0 atomic % and lower than or equal to 50 atomic %, preferably higher than or equal to 0.1 atomic % and lower than or equal to 40 atomic %, more preferably higher than or equal to 0.1 atomic % and lower than or equal to 35 atomic %, more preferably higher than or equal to 0.1 atomic % and lower than or equal to 30 atomic %, more preferably higher than or equal to 0.1 atomic % and lower than or equal to 25 atomic %, more preferably higher than or equal to 0.1 atomic % and lower than or equal to 20 atomic %, more preferably higher than or equal to 0.1 atomic % and lower than or equal to 15 atomic %, more preferably higher than or equal to 0.1 atomic % and lower than or equal to 10 atomic %. By reducing the atomic percentage of gallium with respect to the atomic number of the metal elements in the semiconductor layer, a transistor with high resistance to PBTS test can be achieved. Note that by containing gallium in the metal oxide, an effect of not easily generating oxygen vacancies (V O :Oxygen Vacancy) in the metal oxide is obtained.

[0399] A metal oxide not containing gallium can also be used as the semiconductor layer of the OS transistor. For example, an In-Zn oxide can be used for the semiconductor layer. At this time, when the atomic percentage of indium with respect to the atomic number of the metal elements contained in the metal oxide is increased, the field-effect mobility of the transistor can be increased. On the other hand, when the atomic percentage of zinc with respect to the atomic number of the metal elements contained in the metal oxide is increased, the metal oxide has high crystallinity, and thus fluctuation in electrical characteristics of the transistor is suppressed, and reliability can be increased. Furthermore, a metal oxide not containing gallium and zinc such as indium oxide can also be used as the semiconductor layer. By using a metal oxide not containing gallium, particularly, fluctuation in threshold voltage in PBTS test can be extremely small.

[0400] For example, an oxide containing indium and zinc can be used as the semiconductor layer. In that case, a metal oxide in which the atomic ratio of the metal elements is, for example, In:Zn = 2:3, In:Zn = 4:1, or the like can be used.

[0401] Note that the above description is given based on the case where gallium is used, but the above description can be applied to the case where element M is used instead of gallium. As the semiconductor layer, a metal oxide in which the atomic ratio of indium is higher than that of element M is preferably used. Further, a metal oxide in which the atomic ratio of zinc is higher than that of element M is preferably used.

[0402] By using a metal oxide in which the content of element M is low as the semiconductor layer, a transistor with high reliability against a positive bias stress can be realized. By using such a transistor as a transistor which needs to have high reliability against a positive bias stress, a semiconductor device with high reliability can be realized.

[0403] Next, the reliability of a transistor against light is described.

[0404] The electrical characteristics of a transistor sometimes fluctuate due to light incident on the transistor. It is particularly preferable that a transistor used in a region where light is likely to be incident have small fluctuation in electrical characteristics under light irradiation and have high reliability against light. The reliability against light can be evaluated by, for example, the amount of shift in threshold voltage in an NBTI S test.

[0405] By increasing the content of element M in a metal oxide used for a semiconductor layer, a transistor with high reliability against light can be realized. That is, a transistor with small amount of shift in threshold voltage in an NBTI S test can be realized. Specifically, a metal oxide in which the atomic ratio of element M is higher than or equal to that of indium has a larger band gap, and thus the amount of shift in threshold voltage in an NBTI S test of a transistor can be reduced. The band gap of a metal oxide included in a semiconductor layer is preferably higher than or equal to 2.0 eV, further preferably higher than or equal to 2.5 eV, still further preferably higher than or equal to 3.0 eV, yet further preferably higher than or equal to 3.2 eV, yet further preferably higher than or equal to 3.3 eV, yet further preferably higher than or equal to 3.4 eV, and yet further preferably higher than or equal to 3.5 eV.

[0406] For example, a metal oxide in which the atomic ratio of the metal elements is In:M:Zn = 1:1:1, In:M:Zn = 1:1:1.2, In:M:Zn = 1:3:2, In:M:Zn = 1:3:3, In:M:Zn = 1:3:4, or the like can be used as the semiconductor layer.

[0407] The semiconductor layer particularly preferably uses a metal oxide in which the proportion of the number of atoms of element M to the number of atoms of metal elements included is greater than or equal to 20 at.% and less than or equal to 70 at.%, preferably greater than or equal to 30 at.% and less than or equal to 70 at.%, more preferably greater than or equal to 30 at.% and less than or equal to 60 at.%, more preferably greater than or equal to 40 at.% and less than or equal to 60 at.%, more preferably greater than or equal to 50 at.% and less than or equal to 60 at.%.

[0408] When an In-Ga-Zn oxide is used as the semiconductor layer, a metal oxide in which the proportion of the number of atoms of indium to the number of atoms of gallium is lower than or equal to 1 can be used. For example, a metal oxide in which the proportion of the number of atoms of metal elements is In:Ga:Zn = 1:1:1, In:Ga:Zn = 1:1:1.2, In:Ga:Zn = 1:3:2, In:Ga:Zn = 1:3:3, In:Ga:Zn = 1:3:4, or the like can be used.

[0409] The semiconductor layer particularly preferably uses a metal oxide in which the proportion of the number of atoms of gallium to the number of atoms of metal elements included is greater than or equal to 20 at.% and less than or equal to 60 at.%, preferably greater than or equal to 20 at.% and less than or equal to 50 at.%, more preferably greater than or equal to 30 at.% and less than or equal to 50 at.%, more preferably greater than or equal to 40 at.% and less than or equal to 60 at.%, more preferably greater than or equal to 50 at.% and less than or equal to 60 at.%.

[0410] By using a metal oxide with a high content of element M for the semiconductor layer, a transistor with high reliability with respect to light can be realized. By using such a transistor as a transistor that needs to have high reliability with respect to light, a semiconductor device with high reliability can be realized.

[0411] The semiconductor layer can also have a stacked structure including two or more metal oxide layers. The composition of the two or more metal oxide layers included in the semiconductor layer can be the same or substantially the same as each other. By adopting a stacked structure of metal oxide layers with the same composition, the same sputtering target can be used, for example, so that manufacturing costs can be reduced.

[0412] The composition of the two or more metal oxide layers included in the semiconductor layer can be different from each other. For example, a two-layer stacked structure of a first metal oxide layer with a composition of In:M:Zn = 1:3:4 [atomic ratio] or the like and a second metal oxide layer with a composition of In:M:Zn = 1:1:1 [atomic ratio] or the like overlapping the first metal oxide layer can be used. Further, as element M, gallium or aluminum is particularly preferably used. For example, a stacked structure selected from any one of an indium oxide, an indium gallium oxide, and IGZO and any one of IAZO, IAGZO, and ITZO (registered trademark) or the like can be used.

[0413] For example, a first metal oxide layer of a composition of In:M:Zn = 1:1:1 [atomic ratio] or its neighborhood and a second metal oxide layer of a composition of In:Zn = 4:1 [atomic ratio] or its neighborhood provided over the first metal oxide layer can be used.

[0414] For example, a three-layer stacked structure in which a semiconductor layer of a metal element atomic ratio of In:Ga:Zn = 1:1:1 is used as a first layer, a semiconductor layer of a metal element atomic ratio of In:Zn = 4:1 is used as a second layer, and a semiconductor layer of a metal element atomic ratio of In:Ga:Zn = 1:1:1 is used as a third layer can be used. The band gap of the semiconductor layer of the first layer and the third layer is preferably larger than that of the semiconductor layer of the second layer. With this structure, the second layer can be used as a main current path, and thus a so-called buried channel structure can be achieved.

[0415] A metal oxide layer having crystallinity is preferably used as the semiconductor layer. For example, a metal oxide layer having a CAAC (c-axis aligned crystal) structure, a polycrystalline structure, an nc (nano-crystal) structure, or the like can be used. By using a metal oxide layer having crystallinity for the semiconductor layer, the density of defect states in the semiconductor layer can be reduced, and thus a display device with high reliability can be achieved.

[0416] The higher the crystallinity of the metal oxide layer used for the semiconductor layer is, the lower the density of defect states in the semiconductor layer can be. On the other hand, by using a metal oxide layer with low crystallinity, a transistor capable of flowing a large current can be achieved.

[0417] In the case where a metal oxide layer is formed by a sputtering method, the higher the substrate temperature (temperature of a stage) at the time of formation is, the higher the crystallinity of the metal oxide layer can be. Further, the higher the flow rate ratio of an oxygen gas to the entire deposition gas used at the time of formation (hereinafter also referred to as an oxygen flow ratio) is, the higher the crystallinity of the metal oxide layer can be.

[0418] The semiconductor layer of the OS transistor can also have a stacked-layer structure of two or more metal oxide layers having different crystallinity. For example, the semiconductor layer can have a stacked-layer structure of a first metal oxide layer and a second metal oxide layer provided over the first metal oxide layer, and the second metal oxide layer can include a region whose crystallinity is higher than that of the first metal oxide layer. Alternatively, the second metal oxide layer can include a region whose crystallinity is lower than that of the first metal oxide layer. The two or more metal oxide layers included in the semiconductor layer can also have the same or approximately the same composition. By using a stacked-layer structure of metal oxide layers having the same composition, the same sputtering target can be used, for example, so that the manufacturing cost can be reduced. For example, a stacked-layer structure of two or more metal oxide layers having different crystallinity can be formed by using the same sputtering target while changing the flow rate of oxygen. Note that the two or more metal oxide layers included in the semiconductor layer can also have different compositions.

[0419] The transistor 10 described in this embodiment can have a channel length L determined by the thickness of the insulating layer provided between the conductive layer 160 and the conductive layer 155. Thus, a transistor with a short channel length L can be manufactured with high precision. Further, the variation in characteristics among a plurality of transistors 10 can be reduced. Thus, the operation of a semiconductor device including the transistor 10 is stable, and the reliability can be improved. Further, when the variation in characteristics is reduced, the degree of freedom in circuit design of a semiconductor device is increased, and thus the operating voltage can be reduced. Thus, the power consumption of a semiconductor device can be reduced.

[0420] When the semiconductor layer 161 includes an oxide semiconductor, the insulating layer 156 and the insulating layer 158 are preferably formed using a material containing hydrogen. The oxide semiconductor in a region where the insulating layer is in contact with the oxide semiconductor is n-type by the contact with the insulating layer containing hydrogen, and thus can be used as a source region or a drain region. As the insulating layer, a material containing silicon, nitrogen, and hydrogen can be used, for example. Specifically, silicon nitride containing hydrogen, silicon oxynitride containing hydrogen, or the like can be used.

[0421] When the semiconductor layer 161 includes an oxide semiconductor, the conductive layer 155 in contact with the semiconductor layer 161 and the conductive layer 160 in contact with the semiconductor layer 161 are preferably formed using a conductive material that makes the oxide semiconductor n-type. For example, a conductive material containing nitrogen can be used. For example, a conductive material containing titanium or tantalum and nitrogen can be used. Alternatively, another conductive material can be provided so as to overlap with the conductive material containing nitrogen.

[0422] On the other hand, the insulating layer 157 is preferably formed using a material in which hydrogen is reduced and oxygen is contained. For example, a material containing silicon and oxygen can be used. Specifically, silicon oxide, silicon oxynitride, or the like can be used. Since hydrogen is an impurity element in an oxide semiconductor, when the semiconductor layer 161 functioning as an oxide semiconductor is in contact with the insulating layer 157 in which hydrogen is reduced, the semiconductor layer 161 is not easily n-type. When the semiconductor layer 161 functioning as an oxide semiconductor is in contact with the insulating layer 157 containing oxygen, oxygen vacancies in the semiconductor layer 161 are reduced, the characteristics of the transistor 10 are stable, and thus the reliability is improved.

[0423] When the semiconductor layer 161 includes an oxide semiconductor, the insulating layer 157 preferably contains excess oxygen. In this specification and the like, "excess oxygen" refers to oxygen which is released by heating. Further, when the insulating layer 157 includes a material containing excess oxygen, the insulating layer 156 and the insulating layer 158 are preferably formed using a material which is less likely to transmit oxygen. As the material which is less likely to transmit oxygen, for example, an oxide containing one or both of aluminum and hafnium, a nitride of silicon, or the like can be used. By using a material which is less likely to transmit oxygen for the insulating layer 156 and the insulating layer 158, excess oxygen contained in the insulating layer 157 is less likely to be released to the lower layer or the upper layer. Thus, the oxide semiconductor can be sufficiently supplied with oxygen. For example, an insulating layer containing silicon and oxygen (the insulating layer 157) can be included between two insulating layers containing silicon and nitrogen (the insulating layer 156 and the insulating layer 158).

[0424] When the semiconductor layer 161 includes an oxide semiconductor and the insulating layer 156 and the insulating layer 158 include a material containing hydrogen, a region of the semiconductor layer 161 in contact with the conductive layer 160 and a region of the semiconductor layer 161 in contact with the insulating layer 158 are used as one of a source (a source region) and a drain (a drain region). Further, a region of the semiconductor layer 161 in contact with the conductive layer 155 and a region of the semiconductor layer 161 in contact with the insulating layer 156 are used as the other of the source (the source region) and the drain (the drain region). Thus, the channel length L of the transistor 10 is determined depending on the thickness t of the insulating layer 157 (see FIG. 1B). FIG. 16A

[0425] ​Insulating layers 156 and 158 can also be made of materials containing no hydrogen or very little hydrogen. For example, silicon nitride or silicon oxynitride with very little hydrogen can also be used. In this case, the regions of semiconductor layer 161 that contact insulating layer 156 and semiconductor layer 161 that contact insulating layer 158 are not n-typed. Therefore, the region of semiconductor layer 161 that contacts conductive layer 160 is used as one of the source (source region) and drain (drain region). Furthermore, the region of semiconductor layer 161 that contacts conductive layer 155 is used as the other of the source (source region) and drain (drain region). In this case, the total thickness ts of insulating layers 156, 157, and 158 is equivalent to the channel length L of transistor 10 (refer to...). FIG. 16A ).

[0426] The channel length L can be controlled by adjusting the thickness of insulating layers 156, 157, and 158. The channel length L can be, for example, greater than 5 nm, greater than 7 nm, greater than 10 nm but less than 3 μm, less than 2.5 μm, less than 2 μm, less than 1.5 μm, less than 1.2 μm, less than 1 μm, less than 500 nm, less than 300 nm, less than 200 nm, less than 100 nm, less than 50 nm, less than 30 nm, or less than 20 nm. For example, the channel length L can also be set to greater than 100 nm and less than 1 μm.

[0427] Note that in this embodiment, three insulating layers (insulating layer 156, insulating layer 157, and insulating layer 158) are included between conductive layer 155 and conductive layer 160, but the number of insulating layers between conductive layer 155 and conductive layer 160 is not limited to this. The insulating layers between conductive layer 155 and conductive layer 160 can be one or two layers. Alternatively, there can be four or more layers.

[0428] The semiconductor layer 161 is disposed in the opening 159, and the perimeter p of the opening 159 is equal to the channel width W of the transistor 10 (refer to...). FIG. 16C The perimeter p can be calculated, for example, based on the position of half (t / 2) of the thickness t of the insulating layer 157 or half (ts / 2) of the thickness ts. Note that, as needed, the perimeter of any position of the opening 159 can also be set as the channel width W. For example, the perimeter p of the lowermost part of the opening 159 can be set as the channel width W, or the perimeter p of the uppermost part of the opening 159 can be set as the channel width W.

[0429] exist FIG. 16C In the diagram, the outline (planar shape) of the opening 159 as viewed from the Z direction is shown as a circle, but it is not limited to this. For example, the outline of the opening 159 as viewed from the Z direction can be elliptical (see reference). FIG. 16D Alternatively, it can be a rectangle (see reference). FIG. 16ENote that, FIG. 16E A rectangle in which the corner is bent is illustrated. Further, for example, the outline of the opening 159 viewed from the Z direction can also be a shape including one or both of a straight portion and a curved portion (see FIG. 1C). FIG. 16F ).

[0430] In the transistor 10 according to one embodiment of the present application, the capacitance value of the parasitic capacitance generated between the gate and the source is different from the capacitance value of the parasitic capacitance generated between the gate and the drain. Specifically, of the capacitance CI generated in the region where the conductive layer 160 overlaps with the conductive layer 163 over the insulating layer 154 and the capacitance C2 generated in the region where the conductive layer 155 overlaps with the conductive layer 163 in the opening 159, the capacitance value of the capacitance CI is larger than that of the capacitance C2 (see FIG. 1C). FIG. 15D and FIG. 16B ).

[0431] FIG. 17A and FIG. 17B A plan view of the same as FIG. 15A is illustrated. When the transistor 10 according to one embodiment of the present application is viewed from the Z direction, the conductive layer 163 overlaps with the conductive layer 160 in a manner that surrounds the opening 159 at the peripheral portion of the opening 159 and overlaps with the conductive layer 160 at the bottom portion of the opening 159.

[0432] In FIG. 17A , the region serving as the capacitance CI when viewed from the Z direction is hatched. The region where the conductive layer 160 and the conductive layer 163 overlap with each other with the semiconductor layer 161 and the insulating layer 162 interposed therebetween over the insulating layer 154 is used as the capacitance CI (see FIG. 1C). FIG. 16B and FIG. 17A ). Note that the insulating layer 154 and the insulating layer 162 are omitted in FIG. 17A .

[0433] In FIG. 17B , the region serving as the capacitance C2 when viewed from the Z direction is hatched. The region where the conductive layer 155 and the conductive layer 163 overlap with each other with the semiconductor layer 161 and the insulating layer 162 interposed therebetween at the bottom portion of the opening 159 is used as the capacitance C2 (see FIG. 1C). FIG. 16B and FIG. 17B ). Note that the insulating layer 154 and the insulating layer 162 are omitted in FIG. 17B .

[0434] As is apparent from FIG. 17A and FIG. 17B , the area of the region serving as the capacitance CI is larger than that of the region serving as the capacitance C2. By using the area of the region serving as the capacitance CI which is larger than that of the region serving as the capacitance C2, the capacitance value of the capacitance CI is larger than that of the capacitance C2.

[0435] When the overlapping area of the conductive layer 155 and the conductive layer 163 is changed to change the capacitance value of the capacitor C2, the shape of the opening 159 is changed, and thus the perimeter p of the opening 159 is changed. Since the change in the perimeter p directly affects the electrical characteristics of the transistor 10, adjustment of the capacitance value of the capacitor C2 is difficult.

[0436] On the other hand, adjustment of the overlapping area of the conductive layer 163 and the conductive layer 160 is easy, and has little effect on the electrical characteristics of the transistor 10. For example, the capacitance value of the capacitor C1 can be increased by increasing the overlapping area of the conductive layer 163 and the conductive layer 160.

[0437] As FIG. 18A shown in a cross-sectional view, a conductive layer 166 which is close to the semiconductor layer 161 can be provided in the insulating layer 157. Further, the conductive layer 166 is provided so as not to be in contact with the semiconductor layer 161. Further, the conductive layer 166 is preferably provided so as to surround the semiconductor layer 161. By providing the conductive layer 166 so as to be close to the semiconductor layer 161 without being in contact with the semiconductor layer 161, the conductive layer 166 can be used as a back gate electrode of the transistor 10. Thus, FIG. 18A the transistor 10 shown in FIG. 1A is used as a transistor including a back gate (back gate electrode). Further, FIG. 18B is FIG. 18A an equivalent circuit diagram of the transistor 10 shown in FIG. 1A.

[0438] Here, the back gate electrode is described. In general, the back gate electrode is formed of a conductive layer and is arranged so that the channel formation region of the semiconductor layer is sandwiched between the gate electrode and the back gate electrode. Thus, the back gate electrode can have the same function as the gate electrode. The potential of the back gate electrode can be the same as that of the gate electrode, or can be a GND potential or an arbitrary potential. By electrically connecting the gate electrode and the back gate electrode, the on-state current of the transistor can be increased. Further, by changing the potential of the back gate electrode independently of the potential of the gate electrode, the threshold voltage of the transistor can be changed.

[0439] In addition, since the gate electrode and the back gate electrode are formed using a conductive layer, the conductive layer has a function of preventing an electric field generated outside the transistor from affecting the channel formation region of the semiconductor layer (particularly, an electric field shielding function against static electricity or the like). As a result, the variation in characteristics of the transistors is reduced. Further, the degradation of the transistor characteristics caused by GBTS testing is suppressed. For example, by including the back gate electrode, the variation in threshold voltage before and after GBTS testing can be suppressed. In addition, the variation in threshold voltage of the transistor including the back gate electrode before and after GBTS testing is smaller than that of the transistor not including the back gate electrode.

[0440] The GBTS (NBTS and PBTS) test is a kind of accelerated test, which can evaluate the change in characteristics of a transistor (change over time) due to long-term use in a short time. In particular, the amount of change in threshold voltage of a transistor before and after the GBTS test is an important index for checking reliability. It can be said that the less the amount of change in threshold voltage before and after the GBTS test, the higher the reliability of the transistor.

[0441] In addition, when light is incident from the back gate electrode side, by forming the back gate electrode using a conductive film having light shielding properties, it is possible to prevent light from being incident on the semiconductor layer from the back gate electrode side. Similarly, by forming the gate electrode using a conductive film having light shielding properties, it is possible to prevent light from being incident on the semiconductor layer from the gate electrode side. By forming one or both of the gate electrode and the back gate electrode using a conductive film having light shielding properties, it is possible to prevent light degradation of the semiconductor layer and prevent degradation of electrical characteristics such as threshold voltage shift of the transistor.

[0442] Further, the gate electrode and the back gate electrode can shield the electric field generated by the drain electrode from affecting the semiconductor layer. Therefore, it is possible to suppress the variation in the rise voltage of the on-state current due to the variation in the drain voltage. Note that this effect is significant when the gate electrode and the back gate electrode are supplied with potentials.

[0443] By connecting a plurality of transistors 10 in parallel, it is possible to increase the channel width W of the transistor 10 in appearance. By increasing the channel width W, the resistance value between the source and the drain when the transistor 10 is in the on state becomes small, and it is possible to increase Id in the on state.

[0444] FIG. 19A is a plan view of the transistor 10 including the transistor 10a and the transistor 10b. FIG. 19B is a cross-sectional view of a portion along the dotted line A1-A2 in FIG. 19A . FIG. 19C is a perspective view in which a portion of the transistor 10 including the transistor 10a and the transistor 10b is removed. FIG. 19D is an equivalent circuit diagram of the transistor 10 including the transistor 10a and the transistor 10b. In order to easily understand the structure of the transistor 10, a part of the description of the constituent elements of the transistor 10 is omitted in FIG. 19A and FIG. 19C .

[0445] The transistor 10a and the transistor 10b have the same structure as the transistor 10 described with reference to FIG. 15 and FIG. 16. The transistor 10a is provided in a region including the opening 159a, and the transistor 10b is provided in a region including the opening 159b. The opening 159a and the opening 159b can be formed similarly to the opening 159.

[0446] A part of the conductive layer 155 is used as one of the source and drain electrodes of the transistor 10a, and another part of the conductive layer 155 is used as one of the source and drain electrodes of the transistor 10b. In addition, a part of the conductive layer 160 is used as the other of the source and drain electrodes of the transistor 10a, and another part of the conductive layer 160 is used as the other of the source and drain electrodes of the transistor 10b. In addition, a part of the conductive layer 163 is used as the gate electrode of the transistor 10a, and another part of the conductive layer 163 is used as the gate electrode of the transistor 10b.

[0447] In the equivalent circuit diagram of FIG. 18B, one of the source and drain electrodes of the transistor 10a is electrically connected to one of the source and drain electrodes of the transistor 10b, and the other of the source and drain electrodes of the transistor 10a is electrically connected to the other of the source and drain electrodes of the transistor 10b. In addition, the gate electrode of the transistor 10a is electrically connected to the gate electrode of the transistor 10b. Thus, the on and off states of the transistor 10a and the transistor 10b are switched at the same time, and the transistor 10a and the transistor 10b are used as one transistor 10. FIG. 19D

[0448] By connecting a plurality of transistors 10 (here, the transistor 10a and the transistor 10b) in series, the channel length L of the transistor 10 in appearance can be increased. By increasing the channel length L, the saturation characteristics of the transistor 10 can be improved.

[0449] FIG. 20A FIG. 18A is a plan view of the transistor 10 including the transistor 10a and the transistor 10b. FIG. 20B FIG. 18B is a cross-sectional view of a portion along the dotted line A1-A2 in FIG. 18A. FIG. 20A FIG. 18C is a perspective view of the transistor 10 including the transistor 10a and the transistor 10b. FIG. 20C FIG. 18D is an equivalent circuit diagram of the transistor 10 including the transistor 10a and the transistor 10b. In order to easily understand the structure of the transistor 10, part of the description of the components of the transistor 10 is omitted in FIGS. 18A to 18D. FIG. 20D FIG. 20A FIG. 20C

[0450] The transistor 10a and the transistor 10b have a structure similar to that of the transistor 10 described with using FIG. 19, but the conductive layer 155 is divided into the conductive layer 155a and the conductive layer 155b, which is different from the transistor 10 at this point.

[0451] ​​​​Conductive layer 155a is used as one of the source and drain electrodes of transistor 10a, and a portion of conductive layer 160 is used as the other of the source and drain electrodes of transistor 10a. Additionally, another portion of conductive layer 160 is used as one of the source and drain electrodes of transistor 10b, and conductive layer 155b is used as the other of the source and drain electrodes of transistor 10b. Furthermore, similar to transistor 10 illustrated using FIG. 19, a portion of conductive layer 163 is used as the gate electrode of transistor 10a, and another portion of conductive layer 163 is used as the gate electrode of transistor 10b.

[0452] In use FIG. 20D When illustrating the equivalent circuit diagram, one of the source and drain of transistor 10a is electrically connected to one of the source and drain of transistor 10b, and the gate of transistor 10a is electrically connected to the gate of transistor 10b. Therefore, the on and off states of transistors 10a and 10b switch simultaneously and are used as a single transistor 10.

[0453] [Example of the planar and cross-sectional structure of signal output circuit 110]

[0454] Next, examples of the planar and cross-sectional structure of the signal output circuit 110 will be described using the accompanying drawings. In this embodiment, the signal output circuit 110... FIG. 12 The planar and cross-sectional structures of the signal output circuit 110a shown are illustrated.

[0455] FIG. 21 This is a diagram showing an example of the planar structure of the signal output circuit 110a. Additionally, FIG. 22A It shows along FIG. 21 A diagram showing an example of the cross-sectional structure of the section marked with dashed lines A1-A2. FIG. 22A It shows along FIG. 21 The diagram shows an example of the cross-sectional structure of the section marked with dashed lines A2-A3. FIG. 23A It shows along FIG. 21 The diagram shows an example of the cross-sectional structure of the section marked with dashed lines A4-A5. FIG. 23B It shows along FIG. 21 The diagram shows an example of the cross-sectional structure of the section marked with dashed lines A6-A7.

[0456] In this embodiment, an example of using the above-described VFET structure for the transistor 10 as the signal output circuit 110a will be described. The signal output circuit 110a includes an insulating layer 154 on a substrate 148, and a conductive layer 155 (e.g., ...) on the insulating layer 154. FIG. 22A The conductive layer 155[1] and the conductive layer 155[3], FIG. 22B The conductive layer 155[3] and the conductive layer 155[4] FIG. 23AThe conductive layer 155

[10] and the conductive layer 155

[11] are formed over the conductive layer 155[9].

[0457] Note that the stack structure of the signal output circuit 110a using the above-described VFET and the structure example of the transistor 10 have a common part. Thus, here, a part different from the structure example of the transistor 10 is mainly described.

[0458] In this specification and the like, a symbol relating to a constituent element of the transistor 10[1] is sometimes attached with an identifier [1]. For example, the conductive layer 163 serving as a gate electrode of the transistor 10[1] is sometimes denoted by a conductive layer 163[1]. Note that a symbol relating to a constituent element common to a plurality of transistors 10 is sometimes attached with an identifier of any of the plurality of transistors 10. For example, the conductive layer 163 serving as a gate electrode of each of the transistor 10[2], the transistor 10[9], and the transistor 10

[11] is sometimes denoted by a conductive layer 163[2].

[0459] For example, the opening 159 and the semiconductor layer 161 relating to the transistor 10[3] are sometimes denoted by an opening 159[3] and a semiconductor layer 161[3], respectively. For example, the opening 159 and the semiconductor layer 161 relating to the transistor 10[4] are sometimes denoted by an opening 159[4] and a semiconductor layer 161[4], respectively. For example, the opening 159 and the semiconductor layer 161 relating to the transistor 10[7] are sometimes denoted by an opening 159[7] and a semiconductor layer 161[7], respectively. For example, the opening 159 and the semiconductor layer 161 relating to the transistor 10[8] are sometimes denoted by an opening 159[8] and a semiconductor layer 161[8], respectively. For example, the opening 159 and the semiconductor layer 161 relating to the transistor 10

[10] are sometimes denoted by an opening 159

[10] and a semiconductor layer 161

[10] , respectively.

[0460] The signal output circuit 110a includes conductive layers 181[1] to 181[4] over the insulating layer 158 (see FIG. 1A). FIG. 21 and FIG. 23A The conductive layers 181 (the conductive layers 181[1] to 181[4]) can be formed using the same material and method as the conductive layer 160. Further, the conductive layers 181 and the conductive layer 160 can be formed at the same time.

[0461] Furthermore, the signal output circuit 110a includes an insulating layer 187 on the insulating layer 164. The insulating layer 187 is preferably used as a planarization layer to reduce steps caused by transistors, capacitors, wiring, etc., formed on the underlying layer. An organic insulating film is preferably used as the material for the planarization layer. Alternatively, after forming the insulating layer 187 using inorganic or organic materials, the insulating layer 187 may be subjected to a planarization treatment using methods such as chemical mechanical polishing (CMP).

[0462] Additionally, the signal output circuit 110a includes conductive layers 191 to 199, wiring 131, and wiring 132 on the insulating layer 187 (see reference). FIG. 21 , FIG. 22A , FIG. 22B and FIG. 23A Conductive layers 191 to 199, wiring 131, and wiring 132 can be formed using the same materials and methods as the other conductive layers. Conductive layer 191 is used as... FIG. 24 The terminal 111 shown is used as terminal 112, conductive layer 192 is used as terminal 113, conductive layer 194 is used as terminal 114, conductive layer 195 is used as terminal 115, conductive layer 196 is used as terminal 116, conductive layer 197 is used as terminal 117, and conductive layer 198 is used as terminal 118.

[0463] In addition, in the signal output circuit 110a, conductive layers 160[2], 160[3], 181[1], 181[2], 181[3], and 181[4] are all provided with openings that penetrate insulating layers 162, 164, and 187. Wiring 132 is electrically connected to conductive layer 160[2] in the opening provided on conductive layer 160[2]. More specifically, wiring 132 is electrically connected to conductive layer 160[2] at the bottom of the opening provided on conductive layer 160[2].

[0464] Two openings are provided on the conductive layer 160[3]. Wiring 131 is electrically connected to the conductive layer 160[3] in one of the two openings. Conductive layer 199 is electrically connected to the conductive layer 160[3] in the other of the two openings.

[0465] Further, the conductive layer 191 and the conductive layer 181[1] are electrically connected in the opening provided in the conductive layer 181[1]. Further, the conductive layer 194 and the conductive layer 181[2] are electrically connected in the opening provided in the conductive layer 181[2]. Further, the conductive layer 198 and the conductive layer 181[3] are electrically connected in the opening provided in the conductive layer 181[3]. Further, the conductive layer 196 and the conductive layer 181[4] are electrically connected in the opening provided in the conductive layer 181[4].

[0466] Further, in the signal output circuit 110a, the conductive layer 163[1], the conductive layer 163[3], the conductive layer 163[4], the conductive layer 163[5], and the conductive layer 163[7] are provided with openings that penetrate the insulating layer 164 and the insulating layer 187.

[0467] In the opening provided in the conductive layer 163[1], the conductive layer 197 and the conductive layer 163[1] are electrically connected. Further, in the opening provided in the conductive layer 163[3], the conductive layer 193 and the conductive layer 163[3] are electrically connected. Further, in the opening provided in the conductive layer 163[4], the conductive layer 192 and the conductive layer 163[4] are electrically connected. Further, in the opening provided in the conductive layer 163[5], the conductive layer 195 and the conductive layer 163[5] are electrically connected. Further, in the opening provided in the conductive layer 163[7], the conductive layer 199 and the conductive layer 163[7] are electrically connected. The conductive layer 160[3] and the conductive layer 163[7] are electrically connected through the conductive layer 199.

[0468] Further, in the signal output circuit 110a, the conductive layer 155[1], the conductive layer 155[2], the conductive layer 155[3], the conductive layer 155[4], the conductive layer 155[8], the conductive layer 155[9], the conductive layer 155

[10] , and the conductive layer 155

[11] are provided with openings that penetrate the insulating layer 156, the insulating layer 157, and the insulating layer 158.

[0469] In the opening provided in the conductive layer 155[1], the conductive layer 160[3] and the conductive layer 155[1] are electrically connected. Further, in the opening provided in the conductive layer 155[2], the conductive layer 160[1] and the conductive layer 155[2] are electrically connected. Further, in the opening provided in the conductive layer 155[3], the conductive layer 160[4] and the conductive layer 155[3] are electrically connected. Further, in the opening provided in the conductive layer 155[8], the conductive layer 181[1] and the conductive layer 155[8] are electrically connected. Further, in the opening provided in the conductive layer 155

[10] , the conductive layer 181[3] and the conductive layer 155

[10] are electrically connected.

[0470] The conductive layer 155[9] is provided with two openings. The conductive layer 160[8] and the conductive layer 155[9] are electrically connected in one of the two openings. Further, the conductive layer 181[2] and the conductive layer 155[9] are electrically connected in the other of the two openings.

[0471] The conductive layer 155

[11] is provided with two openings. The conductive layer 160

[10] and the conductive layer 155

[11] are electrically connected in one of the two openings. Further, the conductive layer 181[4] and the conductive layer 155

[11] are electrically connected in the other of the two openings.

[0472] Further, in the signal output circuit 110a, the conductive layer 155[4] and the conductive layer 155[7] are each provided with an opening that penetrates the insulating layer 156, the insulating layer 157, and the insulating layer 158.

[0473] The conductive layer 163[2] and the conductive layer 155[4] are electrically connected in the opening provided in the conductive layer 155[4] (see FIG. 17B). FIG. 23B The conductive layer 163[8] and the conductive layer 155[7] are electrically connected in the opening provided in the conductive layer 155[7].

[0474] Note that the conductive layer 155[4] is also used as the conductive layer 155[5] and the conductive layer 155[6]. Further, the conductive layer 160[1] is also used as the conductive layer 160[7]. Further, the conductive layer 160[2] is also used as the conductive layer 160[6], the conductive layer 160[9], and the conductive layer 160

[11] . Further, the conductive layer 160[3] is also used as the conductive layer 160[5]. Further, the conductive layer 163[1] is also used as the conductive layer 163[6]. Further, the conductive layer 163[2] is also used as the conductive layer 163[9] and the conductive layer 163

[11] . Further, the conductive layer 163[8] is also used as the conductive layer 163

[10] .

[0475] The region where the conductive layer 155[4] and the conductive layer 160[6] overlap with each other with the insulating layer 156, the insulating layer 157, and the insulating layer 158 therebetween is used as the capacitor 20[1].

[0476] Further, by electrically connecting the conductive layer 160[8] and the conductive layer 155[9], the capacitor Cl of the transistor 10[8] can be used as the capacitor 20[2]. By using the capacitor Cl of the transistor 10[8] as the capacitor 20[2], it is not necessary to separately provide the capacitor 20[2], and thus a semiconductor device with a small area occupation can be implemented (see FIG. 17B). FIG. 21 Therefore, as the transistor 10[8], a VFET according to one embodiment of the present application is preferably used.

[0477] Further, by electrically connecting the conductive layer 160

[10] and the conductive layer 155

[11] , the capacitance CI of the transistor 10

[10] can be used as the capacitance 20 [3]. By using the capacitance CI of the transistor 10

[10] as the capacitance 20 [3], the capacitance 20 [3] need not be separately provided, and thus a semiconductor device with a small footprint can be implemented (see FIG. 1C). FIG. 21 and FIG. 23A Thus, as the transistor 10

[10] , a VFET according to one embodiment of the present application is preferably used.

[0478] FIG. 24 A circuit diagram of the signal output circuit 110a is shown in a case where the capacitance CI of the transistor 10 [8] is used as the capacitance 20 [2] and the capacitance CI of the transistor 10

[10] is used as the capacitance 20 [3].

[0479] The transistor 10

[10] and the transistor other than the transistor 10

[10] can be constituted by a transistor other than a VFET. Note that, in order to implement a semiconductor device with a reduced footprint, it is preferable that a transistor according to one embodiment of the present application be used more in the signal output circuit 110a. Thus, it is preferable that a transistor according to one embodiment of the present application be used as all the transistors included in the signal output circuit 110a.

[0480] [Operation Example of Signal Output Circuit]

[0481] Next, an operation example of the signal output circuit 110 is described with reference to drawings. In this embodiment, an operation example of the signal output circuit 110a shown in FIG. 1A is described. FIG. 12

[0482] FIG. 25 is a timing chart for explaining an operation example of the signal output circuit 110a[i]. FIGS. 26-32 is a circuit diagram for explaining an operation example of the signal output circuit 110a[i].

[0483] In the drawings and the like, in order to indicate the potential of a wiring or the like, "H" indicating a potential H or "L" indicating a potential L is sometimes attached to a position adjacent to the wiring or the like. Further, an electrode or the like in which a potential change occurs is sometimes attached with "H" or "L" in a boxed form. Further, when a transistor is in an off state, a symbol "X" is sometimes attached to the transistor in a superimposed manner.

[0484] The wiring 131 is supplied with a potential H (VDD) and the wiring 132 is supplied with a potential L (VSS). Further, the terminal 111 is supplied with a signal CLK_1, the terminal 112 is supplied with a signal CLK_2, the terminal 113 is supplied with a signal CLK_3, and the terminal 118 is supplied with a signal PWC_1. ​

[0485] As of the state before period T1, signal CLK_1 is at potential L, signal CLK_2 is at potential H, signal CLK_3 is at potential H, signal PWC_1 is at potential L, and signal LIN is at potential L. In addition, transistors 10[2], 10[3], 10[4], 10[9], and 10

[11] are in the on state. In addition, transistors 10[1], 10[5], 10[6], 10[7], 10[8], and 10

[10] are in the off state.

[0486] Additionally, signals CLK_4 and PWC_2 to PWC_4 are at potential L. Note that signals CLK_4 and PWC_2 to PWC_4 are not involved in the operation of the signal output circuit 110a[i] described here, and therefore are not used in the description of the operation of the signal output circuit 110a[i].

[0487] During period T1, signal CLK_2 changes to potential L, and signal LIN changes to potential H (refer to...). FIG. 25 and FIG. 26 Therefore, transistors 10[1] and 10[6] become on. At this time, the potential of node ND[1] becomes potential L and transistors 10[2], 10[9] and 10

[11] become off.

[0488] Additionally, the potentials of nodes ND[2] and ND[3] become lower than the potential H of transistor 10[1]'s Vth (potential H-Vth). Here, the value of potential H-Vth is higher than the Vth of the transistor. Therefore, transistors 10[8] and 10

[10] become on. Terminal 116 outputs potential L as signal OUT, and terminal 114 outputs potential L as signal SROUT.

[0489] During period T2, signal CLK_1 changes to potential H, signal CLK_3 changes to potential L, and signal PWC_1 changes to potential H (refer to...). FIG. 25 Therefore, transistor 10[3] is switched off. Additionally, at time T2a (refer to the starting point of period T2),... FIG. 27 The potential of node ND[3] is potential H-Vth, therefore the potential of terminal 114 becomes potential H-Vth-Vth, and the potential of terminal 116 becomes potential H-Vth-Vth.

[0490] On the other hand, the terminal 114 and the node ND[3] are connected (capacitively coupled) through the capacitor 20[2]. In addition, the terminal 116 and the node ND[3] are connected through the capacitor 20[3]. The capacitor 20[2] and the capacitor 20[3] are used as bootstrap capacitors. Thus, as the potentials of the terminal 114 and the terminal 116 rise, the potential of the node ND[3] rises.

[0491] At this time, the potential of the node ND[2] also rises, but at the instant when the potential of the node ND[2] exceeds the potential H-Vth, the transistor 10[1] and the transistor 10[7] become in the off state and the node ND[2] and the node ND[3] are in the floating state. In addition, the potential of the node ND[3] rises to the potential H-Vth+the potential H (2x the potential H-Vth) (time T2b. Refer to FIG. 25 and FIG. 28 ). This potential is higher than the potential H+Vth, and thus the potentials of the terminal 114 and the terminal 116 can be made the potential H.

[0492] In the period T3, the signal CLK_2 becomes the potential H, the signal PWC_1 becomes the potential L, and the signal LIN becomes the potential L (refer to FIG. 25 and FIG. 29 ). Thus, the transistor 10[4] becomes in the on state. In addition, the potential of the terminal 116 becomes the potential L. In addition, the transistor 10[6] becomes in the off state and the node ND[1] and the node ND[2] are in the floating state.

[0493] In the period T4, the signal CLK_1 becomes the potential L, the signal CLK_3 becomes the potential H, and the signal RIN becomes the potential H (refer to FIG. 25 and FIG. 30 ). Thus, the transistor 10[3] and the transistor 10[5] become in the on state and the potential of the node ND[1] becomes the potential H. When the potential of the node ND[1] becomes the potential H, the transistor 10[2], the transistor 10[9], and the transistor 10

[11] become in the on state.

[0494] When the transistor 10[2] becomes in the on state, the potential of the node ND[2] becomes the potential L. Thus, the transistor 10[7] becomes in the on state and the potential of the node ND[3] also becomes the potential L. Thus, the transistor 10[8] and the transistor 10

[10] become in the off state. In addition, since the transistor 10[9] and the transistor 10

[11] become in the on state, the terminal 114 is supplied with the potential L and the potential (the potential L) of the terminal 116 is maintained.

[0495] In the period T5, the signal CLK_2 becomes the potential L (refer to FIG. 25 and FIG. 31 ). Thus, the transistor 10[4] becomes in the off state.

[0496] During the period T6, the signal CLK_3 and the signal RIN become the potential L (see FIG. 25 and FIG. 32 ). Thus, the transistor 10[3] and the transistor 10[5] become in the off state. Since the transistor 10[5] becomes in the off state, the node ND[1] is in the floating state.

[0497] After that, until the terminal 117 is supplied with the potential H as the signal LIN, the terminal 114 and the terminal 116 are supplied with the potential L. That is, until the terminal 117 is supplied with the potential H as the signal LIN, the signal SROUT and the signal OUT are output with the potential L.

[0498] Thus, the signal output circuit [i] can output the pulse signal from the terminal 114 and the terminal 116 in synchronization with a specific signal group. Note that the pulse width (the time of being output with the potential H) of the signal SROUT which is the pulse signal output from the terminal 114 is linked with the signal CLK. In addition, the pulse width (the time of being output with the potential H) of the signal OUT which is the pulse signal output from the terminal 116 is linked with the signal PWC.

[0499] When the signal output circuit [i] according to one embodiment of the present application includes a capacitor serving as a bootstrap capacitor, the power supply potential (potential H) can be surely output from the terminal 114 and the terminal 116. Thus, in the signal output circuit [i] according to one embodiment of the present application, the output impedance is small, and the potential H can be surely supplied to a load such as a circuit connected to the terminal 114 or the terminal 116. Thus, the operation of a semiconductor device including the signal output circuit [i] according to one embodiment of the present application becomes stable, and the reliability of the semiconductor device can be improved.

[0500] The capacitor Cl of the transistor 10[1] is preferably formed between the node ND[1] and the gate of the transistor 10[1]. In addition, the capacitor C2 of the transistor 10[1] is preferably formed between the wiring 131 to which the power supply potential is supplied and the gate of the transistor 10[1] (see FIG. 33 ).

[0501] In addition, the node ND[1] is in the floating state during a period other than the period in which the signal CLK_2 and the signal CLK_3 are the potential H. In order to make the signal output circuit [i] according to one embodiment of the present application operate more stably by suppressing the potential fluctuation of the node ND[1] during the period, it is preferable that, in each of the transistor 10[2], the transistor 10[6], the transistor 10[9], and the transistor 10

[11] , the capacitor Cl be formed between the wiring 132 to which the power supply potential is supplied and the gate. Specifically, the conductive layer 160[2] is preferably electrically connected to the wiring 132 (see FIG. 21). The conductive layer 160[2] is used as a source electrode of the transistor 10[2], the transistor 10[6], the transistor 10[9], and the transistor 10

[11] .

[0502] By forming the capacitor C1 between the wiring 132 and the gate in each of the transistor 10[2], the transistor 10[9], and the transistor 10

[11] , the respective capacitors C1 can be connected in parallel to the capacitor 20[1]. Thus, the effect of suppressing the potential variation of the node ND[1] can be improved (see FIG. 17B). FIG. 33 ).

[0503] In addition, by forming the capacitor C2 of the transistor 10[6] between the node ND[1] and the gate of the transistor 10[6], the influence of the potential variation of the signal input to the gate of the transistor 10[6] on the node ND[1] can be reduced, as compared to the case where the capacitor C1 is formed between the node ND[1] and the gate of the transistor 10[6].

[0504] In addition, in order to stabilize the operation of the signal output circuit [i] according to one embodiment of the present application, which suppresses the potential variation of the node ND[1], it is preferable that the capacitor C2 be formed between the node ND[1] and the gate in each of the transistor 10[4] and the transistor 10[5]. In addition, it is preferable that the capacitor C1 of the transistor 10[5] be formed between the wiring 131 to which the potential of the power supply is supplied and the gate. Specifically, it is preferable that the conductive layer 160[3] be electrically connected to the wiring 131 (see FIG. 17A). FIG. 21 The conductive layer 160[3] is used as a drain electrode of the transistor 10[5].

[0505] In addition, it is preferable that the capacitor C1 of the transistor 10[4] be formed between the drain and the gate of the transistor 10[4]. In addition, it is preferable that the capacitor C1 of the transistor 10[3] be formed between the wiring 131 and the gate of the transistor 10[3]. Specifically, it is preferable that the conductive layer 160[3] be electrically connected to the wiring 131 (see FIG. 17A). FIG. 21 The conductive layer 160[3] is used as a drain electrode of the transistor 10[3]. In addition, it is preferable that the capacitor C2 of the transistor 10[3] be formed between the source and the gate of the transistor 10[3].

[0506] In addition, in order to stabilize the operation of the signal output circuit [i] according to one embodiment of the present application, the capacitance value of the parasitic capacitance generated between the node ND[3] and the gate of the transistor 10[7] is preferably smaller than the capacitance values of the capacitor 20[2] and the capacitor 20[3]. Thus, it is preferable that, in the transistor 10[7], the capacitor C1 be formed between one of the source and the drain of the transistor 10[7] and the gate, and the capacitor C2 be formed between the other of the source and the drain of the transistor 10[7] and the gate (see FIG. 17B).FIG. 33 ).

[0507] <Operation example of shift register 100>

[0508] Next, with reference to FIG. 34 Operation example of shift register 100 shown in FIG. 10 will be described. FIG. 11A is a timing chart for explaining the operation example of shift register 100. FIG. 34 The potential changes of the signal CLK_1 to the signal CLK_4 of the clock signal, the signal PWC_1 to the signal PWC_4 of the pulse width determining signal, the signal LIN[1] input to the signal output circuit 110[1], the signal OUT[1] to the signal OUT[4] output from the signal output circuit 110[1] to the signal output circuit 110[4], the signal OUT[n] output from the signal output circuit 110[n], the signal OUT[n+1] output from the signal output circuit 110[n+1], and the signal OUT[n+2] output from the signal output circuit 110[n+2] are shown. FIG. 34

[0509] First, in the period T51, the signal LIN[1] of the potential H is supplied to the signal output circuit 110[1]. In the period T52, the potential H is output as the signal OUT[1] in synchronization with the signal LIN[1], the signal CLK_1, the signal CLK_4, and the signal PWC_1.

[0510] Next, in the period T53, the potential L is output as the signal OUT[1]. In addition, the potential H is output as the signal OUT[2] in synchronization with the signal CLK_1, the signal CLK_2, and the signal PWC_2.

[0511] Next, in the period T54, the potential L is output as the signal OUT[2]. In addition, the potential H is output as the signal OUT[3] in synchronization with the signal CLK_3, the signal CLK_4, and the signal PWC_3.

[0512] Next, in the period T55, the potential L is output as the signal OUT[3]. In addition, the potential H is output as the signal OUT[4] in synchronization with the signal CLK_3, the signal CLK_4, and the signal PWC_4. In this way, the potential H is sequentially output as the signal OUT from the 1st stage to the n+2nd stage.

[0513] ​Then, when the signal output circuit 110[1] is supplied with the potential H as the signal LIN[1] again, the shift register 100 can be caused to repeatedly perform the above operation. A period from when the potential H is input to the signal output circuit 110[1] as the signal LIN[1] to when the potential H is input again as the signal LIN[1] is sometimes referred to as a frame period 176. Further, the signal LIN input to the signal output circuit 110[1] is sometimes referred to as a start pulse SP.

[0514] As the transistor of the semiconductor device used for the signal output circuit and the like according to one embodiment of the present application, a transistor having a structure other than the VFET, such as a planar transistor or an interdigitated transistor, can be used. Alternatively, the VFET and the transistor having a structure other than the VFET can be used in combination.

[0515] The structure described in this embodiment mode can be implemented in appropriate combination with the structures described in other embodiment modes.

[0516] (Embodiment 5)

[0517] In this embodiment mode, reference is made to FIGS. 35-40 The structure of a display module according to one embodiment of the present application is described.

[0518] FIG. 35 is a perspective view illustrating the structure of a display module according to one embodiment of the present application.

[0519] The display device of this embodiment mode can be a high-resolution display device or a large display device. Thus, for example, the display device of this embodiment mode can be used as a display portion of an electronic device having a large screen, such as a television device, a desktop or notebook personal computer, a display for a computer or the like, a digital signboard, a large game machine such as a pachinko machine, a digital camera, a digital video camera, a digital photo frame, a mobile phone, a portable game machine, a portable information terminal, a sound reproduction device.

[0520] Further, the display device of this embodiment mode can be a high-definition display device. Thus, for example, the display device of this embodiment mode can be used as a display portion of an information terminal device (wearable device) such as a watch-type and a bracelet-type, and a display portion of a wearable device such as a head-mounted display (HMD) and a glasses-type AR device that can be mounted on the head.

[0521] The semiconductor device of one embodiment of the present application can be used for a display device or a module including the display device. As the module including the display device, a module to which a flexible printed circuit (FPC) or a tape carrier package (TCP) or the like is attached can be given, a module having a integrated circuit (IC) mounted by a chip on glass (COG) method or a chip on film (COF) method, and the like.

[0522] The display device 5050A has a structure in which the substrate 5152 is attached to the substrate 5151. In FIG. 35 In FIG. 5A, the substrate 5152 is indicated by a dashed line.

[0523] The display device 5050A includes a display portion 5162, a connection portion 5140, a circuit portion 5164, a wiring 5165, and the like. FIG. 35 An example in which the display device 5050A is provided with an IC 5173 and an FPC 5172 is shown. Thus, the structure shown in FIG. 5A can be referred to as a display module including the display device 5050A, the IC, and the FPC. FIG. 35 An example in which the display device 5050A is provided with an IC 5173 and an FPC 5172 is shown. Thus, the structure shown in FIG. 5A can be referred to as a display module including the display device 5050A, the IC, and the FPC.

[0524] The connection portion 5140 is provided on the outer side of the display portion 5162. The connection portion 5140 can be provided along one side or a plurality of sides of the display portion 5162. The connection portion 5140 can be one or a plurality of connection portions. FIG. 35 An example in which the connection portion 5140 is provided along four sides of the display portion is shown. In the connection portion 5140, a common electrode of a display element is electrically connected to a conductive layer, and a potential can be supplied to the common electrode. When the common electrode is provided on the substrate 5151 side or the like, the connection portion 5140 can not be provided if unnecessary.

[0525] The circuit portion 5164 includes, for example, a scan line driver circuit (also referred to as a gate driver). The circuit portion 5164 can include both a scan line driver circuit and a signal line driver circuit (also referred to as a source driver).

[0526] The wiring 5165 has a function of supplying a signal and a power to the display portion 5162 and the circuit portion 5164. The signal and the power are input to the wiring 5165 from an external source through the FPC 5172 or from the IC 5173.

[0527] FIG. 35An example of disposing an IC 5173 over the substrate 5151 by a COG method or a COF method is shown. As the IC 5173, an IC including one or both of a scan line driver circuit and a signal line driver circuit can be used, for example. Note that the display device 5050A and the display module can have a structure in which no IC is provided. Alternatively, the IC can be mounted on an FPC by a COF method or the like.

[0528] The vertical transistor of one embodiment of the present application can be used in one or both of the display portion 5162 and the circuit portion 5164 of the display device 5050A, for example. Alternatively, the vertical transistor of one embodiment of the present application can be used in the IC 5173.

[0529] For example, when the vertical transistor of one embodiment of the present application is used in a pixel circuit of a display device, the area occupied by the pixel circuit can be reduced and a high-definition display device can be achieved. Further, for example, when the vertical transistor of one embodiment of the present application is used in a driver circuit (e.g., one or both of a gate line driver circuit and a source line driver circuit) of a display device, the area occupied by the driver circuit can be reduced and a display device with narrow bezels can be achieved. Furthermore, the vertical transistor of one embodiment of the present application has favorable electrical characteristics, and by using the vertical transistor in a display device, the reliability of the display device can be improved.

[0530] The display portion 5162 is an image display region in the display device 5050A and includes a plurality of pixels 5210 arranged periodically. FIG. 35 An enlarged view of one pixel 5210 is shown.

[0531] There is no particular limitation on the arrangement of the pixels in the display device of this embodiment, and various methods can be employed. As the arrangement of the pixels, for example, a stripe arrangement, an S stripe arrangement, a matrix arrangement, a Delta arrangement, a Bayer arrangement, and a Pentile arrangement can be given.

[0532] FIG. 35 The pixel 5210 shown includes a sub-pixel 5210R which emits red light, a sub-pixel 5210G which emits green light, and a sub-pixel 5210B which emits blue light. Each of the sub-pixel 5210R, the sub-pixel 5210G, and the sub-pixel 5210B includes a display element and a circuit which controls driving of the display element.

[0533] As the display element, a liquid crystal element can be used, for example. As the liquid crystal element, a transmissive liquid crystal element, a reflective liquid crystal element, or a semi-transmissive liquid crystal element can be given, for example.

[0534] In addition, a variety of elements other than liquid crystal elements can be used as the display element (e.g., a light-emitting element). As the light-emitting element, a self-luminous light-emitting element such as an LED (Light Emitting Diode), an OLED (Organic LED), a semiconductor laser, or the like can be given. As the LED, a small-size LED, a micro LED, or the like can be used, for example.

[0535] In addition to the above, a MEMS (Micro Electro Mechanical Systems) element of a shutter mode or an optical interference mode, or a display element using a microcapsule method, an electrophoretic method, an electrowetting method, an electronic ink (registered trademark) method, or the like can be used. In addition, a light source and a QLED (Quantum-dot LED) using a color conversion technology of a quantum dot material can be used.

[0536] [Structure Example 1 of Display Device]

[0537] FIG. 36 One example of a cross section of a portion of a region including the FPC 5172, the conductive material 5242, a portion of the circuit portion 5164, a portion of the display portion 5162, a portion of the connection portion 5140, and a portion of a region including an end portion of the display device 5050A is shown.

[0538] FIG. 36 The display device shown includes a liquid crystal device operating in a VA mode.

[0539] The substrate 5151 is attached to the substrate 5152 with an adhesive layer. A liquid crystal is sealed in a region surrounded by the substrate 5151, the substrate 5152, and the adhesive layer. A polarizing plate POL2 is provided on a side of the substrate 5152 on the outside. A polarizing plate POL1 is provided on a side of the substrate 5151 on the outside.

[0540] Although not shown, a backlight can be provided on the outside of the polarizing plate POL2 or on the outside of the polarizing plate POL1.

[0541] The transistor included in the circuit portion 5164 and the transistor included in the display portion 5162 can have the same structure or different structures. Further, as the plurality of transistors included in the circuit portion 5164, transistors having the same structure can be used, or transistors having different structures can be used in combination.

[0542] The conductive particles CP are electrically connected to the conductive layer provided on the side of the substrate 5151 in the connection portion 5140. Thus, a potential or a signal can be supplied from the FPC or the IC provided on the side of the substrate 5151.

[0543] As the conductive particles CP, particles having an organic resin or silica or the like covered with a metal material on the surface can be used. As the metal material, nickel or gold is preferably used because it can reduce the contact resistance. In addition, particles covered with two or more metal materials in a layered manner such as gold further covered on nickel are preferably used. In addition, the conductive particles CP preferably use a material that generates elastic deformation or plastic deformation. At this time, the conductive particles CP sometimes have a shape in which the longitudinal direction is flattened. By having this shape, the contact area of the conductive particles CP with the conductive layer electrically connected to the conductive particles CP can be increased, and thus the contact resistance can be reduced and problems such as connection failure can be suppressed from occurring.

[0544] [Structure example 2 of display device]

[0545] FIG. 37 The display device illustrated includes a liquid crystal device operating in an FFS mode. The pixel electrode has a comb-tooth shape or a shape provided with a slit when viewed from a planar surface. In addition, the common electrode is disposed so as to overlap the pixel electrode.

[0546] FIG. 38 is an example in which the upper and lower relationship of the pixel electrode and the common electrode is reversed. The common electrode has a comb-tooth shape or a shape provided with a slit when viewed from a planar surface and is disposed on the pixel electrode with the insulating layer interposed therebetween.

[0547] [Structure example 3 of display device]

[0548] FIG. 39 The display device illustrated includes a liquid crystal device operating in an IPS mode.

[0549] The pixel electrode and the common electrode are both disposed on the same insulating layer. The pixel electrode and the common electrode both have a comb-tooth shape when viewed from a planar surface and are disposed so as to engage with each other. The pixel electrode and the common electrode are preferably formed by processing the same conductive film.

[0550] [Structure example 4 of display device]

[0551] FIG. 40 The display module illustrated includes a display device having a liquid crystal device operating in an FFS mode and a light source LS. In addition, it also includes a substrate 5153 having flexibility. By attaching the substrate 5153 to the layer 511, the layer 511_2 can be reinforced while maintaining the flexibility of the layer 511_2.

[0552] The layer 511_1 has a transmittance of 80% or more in the visible light region. Thereby, the light of the backlight can efficiently reach the transmissive liquid crystal display device.

[0553] The substrate 5151LG includes an end portion EG1 and an end portion EG2.

[0554] The end portion EG2 is an end portion opposite to the end portion EG1. Note that the end portion EG2 is positioned between the end portion EG1 and the layer 511_2 because the layer 511_2 is curved.

[0555] In addition, the substrate 5151LG has a function of distributing light incident from the end portion EG1 to the substrate 5152. In other words, the substrate 5151LG is a light guide plate. In addition, for example, a diffusion plate can be used between the substrate 5151LG and the polarizing plate POL1.

[0556] The light source LS is opposite to the end portion EG1, and the light source LS irradiates light to the end portion EG1. For example, a white LED can be used as the light source LS.

[0557] Thus, the size of the light source LS can be made smaller than a structure in which the light source LS is arranged with the substrate SUB1 interposed between the light source LS and the region 510_1. Further, the thickness of the display device can be made thinner than a structure in which the light source LS is arranged with the substrate SUB1 interposed between the light source LS and the region 510_1. In addition, since the functional layer 510 is curved in the region 510_2, the region 510_2 can be difficult to be recognized in a state of being directly opposite to the region 510_1. In addition, a region surrounding the region 510_1 in a frame-like manner can be difficult to be recognized in a state of being directly opposite to the region 510_1. As a result, a novel display device excellent in convenience, practicality, or reliability can be provided.

[0558] At least a part of this embodiment mode can be implemented in appropriate combination with other embodiment modes described in this specification.

[0559] (Embodiment 6)

[0560] In this embodiment, an electronic device of one embodiment of the present application is described.

[0561] The electronic device of this embodiment mode includes the display device of one embodiment of the present application in a display portion. The display device of one embodiment of the present application is easy to achieve high definition and high resolution. Thus, it can be used for a display portion of various electronic devices.

[0562] In addition, the semiconductor device of one embodiment of the present application can also be used for a portion other than the display portion of an electronic device. For example, when the semiconductor device of one embodiment of the present application is used for a control portion or the like of an electronic device, low power consumption can be achieved, and thus it is preferable.

[0563] As the electronic device, for example, a television device, a desktop or notebook personal computer, a display for a computer or the like, a digital sign, a large game machine such as a pinball machine, and the like having a large screen can be given, in addition to a digital camera, a digital video camera, a digital photo frame, a mobile phone, a portable game console, a portable information terminal, a sound reproduction device, and the like.

[0564] In particular, since the display device of one embodiment of the present application can improve the definition, it can be used for electronic devices including a small display portion. As such electronic devices, for example, a wristwatch-type and bracelet-type information terminal device (wearable device), a head-mountable wearable device such as a head-mounted display, a glasses-type AR device, and a glasses-type MR device can be given.

[0565] The electronic device of this embodiment can also include a sensor having a function of detecting, sensing, or measuring a force, a displacement, a position, a velocity, an acceleration, an angular velocity, a rotational frequency, a distance, light, liquid, magnetism, temperature, a chemical substance, a sound, time, hardness, an electric field, an electric current, an electric voltage, an electric power, a radiation line, a flow rate, humidity, an inclination, a vibration, an odor, or an infrared ray.

[0566] The electronic device of this embodiment can have various functions. For example, it can have a function of displaying various information (still images, moving images, text images, and the like) on the display portion, a function of a touch panel, a function of displaying a calendar, a date, or a time, a function of executing various kinds of software (programs), a function of performing wireless communication, a function of reading a program or data stored in a storage medium, and the like.

[0567] FIG. 41A The electronic device 7500 shown is a portable information terminal device which can be used as a smartphone.

[0568] The electronic device 7500 includes a housing 7001, a display portion 7002, a power button 7003, a button 7004, a speaker 7005, a microphone 7006, a camera 7007, a light source 7008, and the like. The display portion 7002 has a function of a touch panel.

[0569] The display portion 7002 can apply the display device of one embodiment of the present application.

[0570] FIG. 41B FIG. 7B is a cross-sectional view of an end portion of the microphone 7006 side of the housing 7001.

[0571] The display surface side of the housing 7001 is provided with a protective member 7010 having a light-transmitting property, and a space surrounded by the housing 7001 and the protective member 7010 is provided with a display panel 7011, an optical member 7012, a touch sensor panel 7013, a printed board 7017, a battery 7018, and the like.

[0572] The display panel 7011, the optical member 7012, and the touch sensor panel 7013 are fixed to the protective member 7010 with an adhesive layer (not shown).

[0573] In a region outside the display portion 7002, a part of the display panel 7011 is folded, and the folded part is connected to the FPC 7015. The FPC 7015 is provided with the IC 7016. The FPC 7015 is connected to a terminal provided in the printed circuit board 7017.

[0574] The display panel 7011 can use a flexible display of one embodiment of the present application. Thus, an electronic device with a very small weight can be implemented. Furthermore, since the display panel 7011 is very thin, a battery 7018 with a large capacity can be mounted while the thickness of the electronic device is suppressed. Furthermore, by folding a part of the display panel 7011 to provide a connection portion to the FPC 7015 on the back of the pixel portion, an electronic device with narrow bezels can be implemented.

[0575] FIG. 41C An example of a television device is shown. In the television device 7100, the housing 7101 is provided with the display portion 7000. Here, a structure in which the housing 7101 is supported by a stand 7103 is shown.

[0576] The display portion 7000 can apply a display device of one embodiment of the present application.

[0577] The operation of the television device 7100 shown in FIG. 8 can be performed by operating the switches provided in the housing 7101 and the remote control 7111. FIG. 41C The display portion 7000 can apply a display device of one embodiment of the present application.

[0578] In addition, the television device 7100 is provided with a receiver and a modem or the like. By use of the receiver, general television broadcasts can be received. Furthermore, by connection to a communication network by cable or wireless, unidirectional (from a sender to a receiver) or bidirectional (between a sender and a receiver, between receivers, or the like) information communication can be performed.

[0579] FIG. 41D An example of a notebook personal computer is shown. The notebook personal computer 7200 includes a housing 7211, a keyboard 7212, a pointing device 7213, an external connection port 7214, and the like. The display portion 7000 is incorporated in the housing 7211.

[0580] The display portion 7000 can apply a display device of one embodiment of the present application.

[0581] FIG. 41E and FIG. 41F An example of a digital sign is shown.

[0582] FIG. 41E The digital sign 7300 shown includes a housing 7301, a display portion 7000, and a speaker 7303, and the like. Further, an LED lamp, an operation key (including a power switch or an operation switch), a connection terminal, various sensors, a microphone, and the like can be included.

[0583] FIG. 41F A digital sign 7400 provided on a cylindrical column 7401 is shown. The digital sign 7400 includes a display portion 7000 provided along the curved surface of the column 7401.

[0584] In FIG. 41E and FIG. 41F , the display device of one embodiment of the present application can be used for the display portion 7000.

[0585] The larger the display portion 7000 is, the more information can be provided at one time. The larger the display portion 7000 is, the more likely it is to attract attention, and for example, the effect of advertisement can be improved.

[0586] It is preferable to use a touch panel for the display portion 7000 because not only a still image or a moving image can be displayed on the display portion 7000 but also a user can intuitively operate the display portion 7000. In the case of use for providing information such as route information or traffic information, the ease of use can be improved by intuitive operation.

[0587] As shown in FIG. 41E and FIG. 41F , the digital sign 7300 or the digital sign 7400 can be linked to an information terminal device 7311 or an information terminal device 7411 carried by a user through wireless communication. For example, advertisement information displayed on the display portion 7000 can be displayed on the screen of the information terminal device 7311 or the information terminal device 7411. Further, by operating the information terminal device 7311 or the information terminal device 7411, the display of the display portion 7000 can be switched.

[0588] A game can be played on the digital sign 7300 or the digital sign 7400 with the screen of the information terminal device 7311 or the information terminal device 7411 as an operation unit (controller). Thus, a plurality of users can participate in the game at the same time and enjoy the game.

[0589] At least a part of this embodiment mode can be combined with other embodiment modes described in this specification as appropriate.

[0590] Symbol Explanation

[0591] BM: light shielding film, CF: colored layer, CLK: signal, CP: conductive particle, DL: data line, dV: potential, GD: drive circuit, GL: gate line, H: potential, KB: layer, LC: liquid crystal device, LIN: signal, LS: light source, OUT: signal, PWC: signal, RIN: signal, RX: electrode, SD: drive circuit, SP: start pulse, SROUT: signal, TD: drive circuit, TX: electrode, V com : potential, V data : second data potential, VDD: high power supply potential, VL: potential supply line, V ref : potential, VSS: low power supply potential, V w: first data potential, 10: transistor, 100: shift register, 101: wiring, 102: wiring, 103: wiring, 104: wiring, 105: wiring, 106: wiring, 107: wiring, 108: wiring, 110: signal output circuit, 111: terminal, 112: terminal, 113: terminal, 114: terminal, 115: terminal, 116: terminal, 117: terminal, 118: terminal, 131: wiring, 132: wiring, 148: substrate, 153: substrate, 154: insulating layer, 155: conductive layer, 156: insulating layer, 157: insulating layer, 158: insulating layer, 159: opening, 160: conductive layer, 161: semiconductor layer, 162: insulating layer, 163: conductive layer, 164: insulating layer, 166: conductive layer, 176: frame period, 181: conductive layer, 187: insulating layer, 191: conductive layer, 192: conductive layer, 193: conductive layer, 194: conductive layer, 195: conductive layer, 196: conductive layer, 197: conductive layer, 198: conductive layer, 199: conductive layer, 200: transistor, 204: electrode, 206: insulating layer, 208: semiconductor layer, 210_1: surface, 210_2: surface, 210_3: surface, 210_4: opening portion, 210A: layer, 210B: layer, 210C: layer, 210: spacer, 212A: electrode, 212B: electrode, 212B_3: surface, 212B_4: opening portion, 510_1: region, 510_2: region, 510_3: region, 510_4: region, 510: functional layer, 511_1: layer, 511_2: layer, 511_3: layer, 511_4: layer, 511: layer, 516: layer, 518_4: opening portion, 518: layer, 519A: conductive layer, 520: functional layer, 521: layer, 522: layer, 530: pixel circuit, 550LC: liquid crystal device, 550: display device, 551LC: electrode, 552LC: electrode, 553LC: layer, 4400EL: pixel circuit, 4400LC: pixel circuit, 4400: pixel circuit, 4401EL: circuit, 4401LC: circuit, 4401: circuit, 4501: pixel circuit, 4502: pixel portion, 4504a: gate driver, 4504b: source driver, 4504: driver circuit portion, 4506: protection circuit, 4507: terminal portion, 4550: transistor, 4552: transistor, 4554: transistor, 4560: capacitor, 4562: capacitor, 4570: liquid crystal device, 4572: light-emitting element, 5050A: display device, 5140: connection portion, 5151LG: substrate, 5151: substrate, 5152: substrate, 5153: substrate, 5162: display portion, 5164: circuit portion, 5165: wiring, 5172: FPC, 5173: IC, 5210B: subpixel,5210G: subpixel, 5210R: subpixel, 5210: pixel, 6500: touch panel module, 6501: circuit unit, 6502: signal line drive circuit, 6503: sensor drive circuit, 6504: detection circuit, 6505: timing controller, 6506: image processing circuit, 6507: AD conversion circuit, 6510: touch panel, 6511: display portion, 6512: input portion, 6513: scan line drive circuit, 6520: IC, 6530: IC, 6531: substrate, 6532: counter substrate, 6533: FPC, 6534: PCB, 6540: CPU, 7000: display portion, 7001: housing, 7002: display portion, 7003: power button, 7004: button, 7005: speaker, 7006: microphone, 7007: camera, 7008: light source, 7010: protective member, 7011: display panel, 7012: optical member, 7013: touch sensor panel, 7015: FPC, 7016: IC, 7017: printed circuit board, 7018: battery, 7100: television device, 7101: housing, 7103: stand, 7111: remote control, 7200: notebook personal computer, 7211: housing, 7212: keyboard, 7213: pointing device, 7214: external connection port, 7300: digital sign, 7301: housing, 7303: speaker, 7311: information terminal device, 7400: digital sign, 7401: column, 7411: information terminal device, 7500: electronic device,

Claims

1. A display device comprising: a first functional layer; a second functional layer; a first substrate; and a second substrate, wherein the first functional layer includes a first region and a second region, the first functional layer is bent in the second region, the first region is sandwiched between the second functional layer and the first substrate, the first region includes a first layer and a pixel circuit, the pixel circuit is sandwiched between the second functional layer and the first layer, the second region is adjacent to the first region, the second region includes a second layer and a first shift register, the second layer is continuous with the first layer, the first shift register is formed on the second layer, the second functional layer is sandwiched between the second substrate and the first region, the second functional layer includes a display element, and the display element is electrically connected to the pixel circuit.

2. The display device according to claim 1, further comprising: a first drive circuit, wherein the first drive circuit includes the first shift register, the first functional layer includes a signal line, the signal line electrically connects the first drive circuit and the pixel circuit, and the signal line transmits an image signal.

3. The display device according to claim 1, further comprising: a second drive circuit, wherein the second drive circuit includes a second shift register, the first functional layer includes a third region and a scan line, the first functional layer is bent in the third region, the third region is adjacent to the first region, the third region includes a third layer and the second shift register, the third layer is continuous with the first layer, the second shift register is formed on the third layer, the scan line electrically connects the second drive circuit and the pixel circuit, and the scan line transmits a selection signal.

4. The display device according to claim 1, further comprising: a first electrode; and a third drive circuit, wherein the second functional layer is sandwiched between the first electrode and the first functional layer, the third drive circuit includes a third shift register, the first functional layer includes a fourth region and a second electrode, the first functional layer is bent in the fourth region, the fourth region is adjacent to the first region, the fourth region includes a fourth layer and the third shift register, the fourth layer is continuous with the first layer, the third shift register is formed on the fourth layer, a capacitor is formed between the second electrode and the first electrode, the second electrode is electrically connected to the third drive circuit, and the second electrode transmits a pulse signal.

5. The display device according to claim 1, wherein the first functional layer includes a spacer and a transistor, the spacer includes a first face, a second face, a third face, and a first opening portion, the first face, the second face, and the third face have insulating properties, the second face is opposite to the first face, the second face is closer to the second functional layer than the first face, the third face connects the first face and the second face, the third face is located on a side of the first opening portion. ​ ​ The transistor includes a third electrode, a fourth electrode, a fifth electrode, a semiconductor layer, and an insulating layer, The third electrode includes a region in contact with the first surface and a region overlapping with the first opening portion, The fourth electrode includes a region in contact with the second surface, a second opening portion, and a fourth surface, The fourth surface is located on a side surface of the second opening portion, The second opening portion overlaps with the first opening portion, The fifth electrode includes a region opposite to the third surface, The insulating layer includes a region sandwiched between the third surface and the fifth electrode, The semiconductor layer includes a region sandwiched between the third surface and the insulating layer, The semiconductor layer is in contact with the third electrode in the first opening portion, and the semiconductor layer is in contact with the fourth electrode on the fourth surface.

6. The display device according to claim 5, wherein the first shift register includes the transistor.

7. The display device according to claim 5, wherein the pixel circuit includes the transistor.

8. The display device according to claim 1, wherein the display element includes a fifth layer, and the fifth layer contains a liquid crystal material.

9. A display module comprising: the display device according to claims 1 to 8; and at least one of a connector and an integrated circuit.

10. A display module comprising: the display device according to claim 8; and a light source, wherein the first layer has a transmittance of 80% or more in a visible light region, the first substrate includes a first end portion and a second end portion, the second end portion is opposite to the first end portion, the second end portion is located between the first end portion and the second layer, the light source is opposite to the first end portion, the light source irradiates light to the first end portion, and the first substrate has a function of distributing light incident from the first end portion toward the second substrate.

11. An electronic device comprising: the display device according to claims 1 to 8; and at least one of a battery, a camera, a speaker, and a microphone. ​ ​ ​

Images