Storage node contact (SNC) interface formation for three-dimensional dynamic random access memory (DRAM)

Abstract

Examples herein relate to three-dimensional (3D) dynamic random access memory (DRAM) and corresponding methods. In an example, a stacked semiconductor structure is provided, where the stacked semiconductor structure includes a plurality of cell stacks formed on a substrate. Each cell stack has a semiconductor layer, a first dielectric layer, a first gate electrode, and a second dielectric layer of a capacitor portion. The side recess of the capacitor portion is open to the first opening through the cell stack. The method includes conformally depositing a doped silicon layer on a side end of the semiconductor layer in the side recess, and performing a thermal annealing process after forming the doped silicon layer on the second side end. The method further includes forming a capacitor disposed on the side recess, the capacitor contacting the doped silicon layer on the second side end of the semiconductor layer.

Description

Technical Field

[0001] The examples described herein are generally related to the field of semiconductor processing, and more specifically to three-dimensional (3D) dynamic random access memory (DRAM) and methods for forming storage node contact (SNC) mating surfaces for 3D DRAM. Background Technology

[0002] Technological advancements in semiconductor processing have led to integrated circuits reaching the physical limits of Moore's Law. These advancements have resulted in new paradigms for components and structures in integrated circuits. For example, various three-dimensional (3D) designs are being developed for DRAM. However, such 3D components may present a new set of processing and manufacturing challenges. Summary of the Invention

[0003] Embodiments of this disclosure include a method for semiconductor processing. A stacked semiconductor structure is provided. This stacked semiconductor structure includes a plurality of cell stacks formed on a substrate, each cell stack having a transistor portion and a capacitor portion laterally adjacent to the transistor portion. The transistor portion has a semiconductor layer, a first dielectric layer formed on the semiconductor layer, and a first gate electrode formed on the first dielectric layer. The first gate electrode extends through a row of memory cells of a memory element, and the first gate electrode forms a gate structure with the semiconductor layer. A first side of the semiconductor layer is doped and coupled to a bit line node of the memory element. A second side of the semiconductor layer is opposite to the first side, and the second side is adjacent to a side recess formed in a second dielectric layer of the capacitor portion. A doped silicon layer is conformally deposited in the side recess and included on the second side of the semiconductor layer. After the doped silicon layer is formed on the second side, an optional thermal annealing process is performed. A capacitor is formed in the capacitor region where the side recess is provided, and the capacitor contacts the doped silicon layer on the second side of the semiconductor layer.

[0004] Embodiments of this disclosure also include another method for semiconductor processing. This method includes providing a stacked semiconductor structure comprising a plurality of cell stacks formed on a substrate. Each cell stack has a semiconductor layer having a first side and a second side, a first dielectric layer formed on the semiconductor layer, a first gate electrode formed on the first dielectric layer, and a second dielectric layer for a capacitor portion. A side recess is defined at the top and bottom by the second dielectric layer, and at the first side by the second side of the semiconductor layer. The side recess opens to a first opening at the second side via the cell stack of the stacked semiconductor structure. The method further includes conformally depositing a doped silicon layer on the second side of the semiconductor layer within the side recess. The method further includes performing an optional thermal annealing process after forming the doped silicon layer on the second side. The method further includes forming a capacitor disposed on the side recess, the capacitor contacting the doped silicon layer on the second side of the semiconductor layer.

[0005] Embodiments of this disclosure also include another method for semiconductor processing. This method includes forming a stacked semiconductor structure comprising a plurality of cell stacks formed on a substrate. Each cell stack includes a semiconductor layer, a first dielectric layer formed on the semiconductor layer, and a second dielectric layer for a capacitor portion of the stacked semiconductor structure, the semiconductor layer having a first side end and a second side end opposite to the first side end. The method further includes forming a first opening through the cell stack. The method further includes pulling the second dielectric layer back from the first opening to form a side recess exposing the second side end of the semiconductor layer. The method further includes conformally depositing a doped silicon layer in the side recess, the doped silicon layer including a vertical portion on the second side end and a lateral portion coupled to the vertical portion. The method further includes forming a third dielectric layer on the doped silicon layer in the side recess. The method further includes pulling back the third dielectric layer to expose the vertical portions of the doped silicon layer. The method further includes pulling back the vertical portions and the lateral portions of the doped silicon layer. The method further includes removing (e.g., completely removing) the sacrificial third dielectric layer. This method further includes performing an optional thermal annealing process after conformally depositing the doped silicon layer, or after depositing the third dielectric layer, or after pulling back the doped silicon layer, or after completely removing the sacrificial third dielectric layer. Attached Figure Description

[0006] To gain a more detailed understanding of the features described above, a more specific description of the above brief overview can be provided by reference to examples, some of which are shown in the accompanying drawings. However, it should be noted that the accompanying drawings show only a few examples and should not be considered as limiting the scope of this disclosure, as other equally valid examples are permissible.

[0007] Figure 1 This is a circuit diagram of a dynamic random access memory (DRAM) cell based on some examples of this disclosure.

[0008] Figure 2 This is a perspective view of a mirrored DRAM pair based on some examples of this disclosure.

[0009] Figure 3 This is a perspective view of a mirrored DRAM pair based on some examples of this disclosure.

[0010] Figures 4 to 10 This is a cross-sectional view of an intermediate structure during a method of forming a memory element (such as a 3D DRAM cell) according to some examples of this disclosure.

[0011] Figures 11 to 13 This is a flowchart of a semiconductor processing method according to one or more embodiments.

[0012] To facilitate understanding, the same component symbols are used as much as possible to designate the same components used in the accompanying drawings. Detailed Implementation

[0013] The examples described herein generally relate to the field of semiconductor processing, and more specifically, to memory elements (including three-dimensional (3D) dynamic random access memory (DRAM)) and methods for semiconductor processing (including forming storage node contact (SNC) bonding surfaces for memory elements such as 3D DRAM). According to various examples, stacked semiconductor structures are formed on a substrate. The stacked semiconductor structure includes multiple cell stacks (e.g., up to one hundred or more cell stacks), each cell stack including layers selected from a different set of materials, and vertically repeating the structure of the cell stacks (e.g., each cell stack being a transposition or vertical mirror of adjacent cell stacks), each cell stack including one or more semiconductor layers and one or more dielectric layers. The cell stacks are used to form memory elements, such as 3D DRAM elements. Specifically, the stacked semiconductor structure is used to form vertically stacked memory elements having capacitor structures (e.g., capacitor portions) laterally disposed from the transistors (e.g., transistor portions) of the cell stacks. The formation of the memory elements of the cell stacks utilizes doped semiconductor layers laterally positioned in an opening-down recess in the film stack, this recess being formed by pulling back the semiconductor layers in the cell stack. A doped silicon layer is conformally deposited in the recessed cavity, including on a portion of the semiconductor layer exposed in the recessed cavity (e.g., a vertical portion of the semiconductor layer). In one example, the doped silicon layer is an amorphous silicon layer. In another example, the doped silicon layer is a polycrystalline layer. Depending on the situation, an undoped silicon layer may be deposited prior to the aforementioned doped silicon layer. An optional thermal annealing process (e.g., a rapid thermal processing operation) is then performed on the stacked semiconductor structure. Thus, a dopant (e.g., phosphorus, arsenic) from the doped silicon layer can be driven into the semiconductor layer and / or the optional undoped silicon layer by the thermal annealing process to form source or drain regions. The drain or source regions in the semiconductor layer may have been pre-formed opposite to the formed source or drain regions, respectively. A capacitor is then formed in the capacitor region of the recessed cavity, with a portion of the contact from the transistor to the capacitor formed by depositing the doped silicon layer.

[0014] Semiconductor processing as described herein, including the formation of stacked semiconductor structures, can ensure dopant implantation in off-line locations during the formation of memory elements (such as 3D DRAM elements) having recesses during formation. Additionally, the semiconductor processing described herein can provide desired doping levels in side recesses during the formation of memory elements, for example, in cases where the lateral width of the recess exceeds the vertical height of the recess, such as in side recesses with high aspect ratios.

[0015] Furthermore, various numbers of vertically stacked memory elements can be realized without adding other different materials, and capacitors of different sizes (e.g., with different capacitance values) can be implemented according to the disclosures herein, while maintaining the same or substantially similar set of process steps. The different examples in this document can also realize single- or dual-gate transistors for 3D DRAM.

[0016] Various different examples are described below. Although multiple features of different examples may be described together in a process flow or system, each feature may be implemented individually or separately and / or in different process flows or different systems. Furthermore, various process flows are described as sequential; other examples may implement process flows in different sequences and / or with more or fewer operations. Additionally, although source and drain nodes and source and drain regions are described in various examples, this description may more generally refer to source / drain nodes or source / drain regions. Moreover, in some examples, n-type transistors are described, but more generally, any type of transistor (e.g., p-type transistor) may be implemented.

[0017] Figure 1 This is a circuit diagram of a dynamic random access memory (DRAM) cell 100 according to some examples of this disclosure. The DRAM cell 100 includes an n-type transistor 2 and a capacitor 4. A first node 6 (e.g., a drain node) of the n-type transistor 2 is electrically connected to a bitline (BL) node 8. A second node 10 (e.g., a source node) of the n-type transistor 2 is electrically connected to a first terminal of the capacitor 4, and a second terminal of the capacitor 4 (opposite to the first terminal) is electrically connected to a power supply node (e.g., a ground node). A gate node 12 of the n-type transistor 2 is electrically connected to a wordline (WL) node 14.

[0018] Figure 2 This is a perspective view of DRAM based on some examples of this disclosure. Figure 2 Two DRAM cells mirrored along a vertical axis are depicted; for convenience, these two DRAM cells may be referred to herein as a mirrored DRAM pair 200. As will become apparent in the following description, multiple mirrored DRAM pairs (e.g., two pairs, three pairs, etc.) may be vertically stacked in a DRAM structure. To avoid unnecessarily obscuring the appearance of the figures, one DRAM cell of the mirrored DRAM pair is labeled with a component symbol, and those skilled in the art will readily understand the mirrored components in the other DRAM cell of the mirrored DRAM pair.

[0019] The DRAM cell includes an n-type transistor 22 (e.g., corresponding to n-type transistor 2) and a capacitor 24 (e.g., corresponding to capacitor 4). The n-type transistor 22 includes a semiconductor layer 26 forming the active region of the n-type transistor 22. In one or more embodiments, the semiconductor layer 26 is p-type doped, for example, lightly p-type doped (e.g., less than about 1 atom per 100 million atoms). In other embodiments, the semiconductor layer 26 is undoped. A first region 28 (e.g., corresponding to first node 6) and a second region 30 (e.g., corresponding to second node 10) are disposed in the semiconductor layer 26, wherein a channel region is located between the first region 28 and the second region 30 in the semiconductor layer 26. In one or more embodiments, in some cases (e.g., when the cell is programmed with a single charge), the first region 28 is a drain region, the first node 6 is a drain node, the second region 30 is a source region, and the second node 10 is a source node. In other cases (e.g., when programming the cells with zero charge), the first region 28 is the source region, the first node 6 is the source node, the second region 30 is the drain region, and the second node 10 is the drain node. In this example, the first region 28 and the second region 30 are n-type doped. A gate dielectric layer (first dielectric layer 32) is disposed on the semiconductor layer 26 (e.g., on the top surface of the semiconductor layer 26), and a gate electrode 34 (e.g., corresponding to gate node 12) is disposed on the first dielectric layer 32.

[0020] Capacitor 24 includes an outer plate 36 (e.g., corresponding to a first terminal of capacitor 4), a capacitor dielectric layer 38, and an inner plate 40 (e.g., corresponding to a second terminal of capacitor 4). The outer plate 36 is a conductive material, such as metal or a metal-containing material. The outer plate 36 typically has a single-capped cylinder, a single-capped rectangular prism, or the like. The outer plate 36 typically extends laterally from the n-type transistor 22 and has a second region 30 contacting the n-type transistor 22 to electrically connect the second region 30 to the capped terminal of capacitor 24. The end of the outer plate 36 opposite the n-type transistor 22 is open. The capacitor dielectric layer 38 is a dielectric material conformally disposed along the inner surface of the outer plate 36. The dielectric material of the capacitor dielectric layer 38 may be a high-k dielectric material (e.g., having a k value greater than 4.0). The inner plate 40 is a conductive material, such as metal or a metal-containing material, and is disposed on the capacitor dielectric layer 38 and fills the remaining interior portion of the outer plate 36.

[0021] Bit line contacts 42 (e.g., corresponding to BL node 8) are configured to laterally contact a first region 28 of the n-type transistor 22. Bit line contacts 42 extend vertically, and a mirrored DRAM pair extends along the mirrored vertical axis of the bit line contacts 42. Power contacts 44 (e.g., ground contacts) are configured to laterally contact the inner plate 40 of the capacitor 24.

[0022] Figure 3 This is a perspective view of a mirrored DRAM to 300 based on some examples of this disclosure. In one or more embodiments, Figure 3 The 3D DRAM cell is similar to Figure 2 The DRAM cell is described herein, and common descriptions are omitted for brevity. The DRAM cell includes an n-type transistor 52 (e.g., corresponding to n-type transistor 2) and a capacitor 24 (e.g., corresponding to capacitor 4). The n-type transistor 52 includes a semiconductor material 54 forming the active region of the n-type transistor 52. For example, the semiconductor material 54 may typically be undoped or lightly p-doped. A drain region 56 (e.g., corresponding to first node 6) and a source region 58 (e.g., corresponding to second node 10) are disposed in the semiconductor material 54, wherein a channel region is located between the drain region 56 and the source region 58 in the semiconductor material 54. In this example, the drain region 56 and the source region 58 are n-doped. A top gate dielectric layer 60 is disposed on the semiconductor material 54 (e.g., on the top surface of the semiconductor material 54), and a bottom gate dielectric layer 62 is disposed on the semiconductor material 54 on the side opposite to the top gate dielectric layer 60 (e.g., on the bottom surface of the semiconductor material 54). A top gate electrode 64 (e.g., corresponding to gate node 12) is disposed on a top gate dielectric layer 60 (e.g., above), and a bottom gate electrode 66 (e.g., corresponding to gate node 12) is disposed on a bottom gate dielectric layer 62 (e.g., below).

[0023] The capped end of the outer plate 36 (e.g., corresponding to the first terminal of the capacitor 4) contacts the source region 58 of the n-type transistor 52 to electrically connect the source region 58 to the capacitor 24. The bit line contact 42 (e.g., corresponding to the BL node 8) is configured to laterally contact the drain region 56 of the n-type transistor 52.

[0024] Figures 4 to 9 This is a cross-sectional view of an intermediate structure during a method of forming a memory element (such as a 3D DRAM cell) according to some examples of this disclosure. Figures 4 to 9 The memory element formed by the first method can be substantially similar to Figure 3 Those shown, or Figure 3 The parts shown. Figures 4 to 9 The stacked semiconductor structure shown is for illustrative purposes only. It should be understood that semiconductor structures and corresponding materials may vary depending on the manufacturing process.

[0025] refer to Figure 4This illustration shows a stacked semiconductor structure 400 according to some examples of this disclosure. In one or more embodiments, the stacked semiconductor structure 400 is one or more 3D DRAM cells in a group of partially formed memory elements, such as 3D DRAM elements. A complete group of 3D DRAM cells may include a number of additional cells (e.g., more than five and up to one hundred or more cells) stacked vertically in the z-direction and may be formed on a substrate (not shown for clarity) forming planes in the x and y directions. The stacked semiconductor structure 400 includes at least a portion of the memory element.

[0026] In one or more embodiments, the stacked semiconductor structure 400 is a partially formed memory element. The stacked semiconductor structure 400 includes an n-type transistor 22 and a capacitor 24 in the process of being formed. In one or more embodiments, the capacitor 24 is a capacitor portion of the cell stack 80. In one or more embodiments, the n-type transistor 22 may be referred to as a transistor and is a transistor portion of the cell stack 80. In one or more embodiments, the n-type transistor 22 may be a p-type transistor.

[0027] The transistor 22 portion of the stacked semiconductor structure 400 includes a semiconductor layer 26, a first dielectric layer 32, a gate electrode 34, and a dielectric layer 46. As can be seen with respect to the stacked semiconductor structure 400, a complete cell stack 80 and portions of two cell stacks are shown. Although a single-gate structure is referenced (e.g., reference...),... Figure 2 The stacked semiconductor structure 400 is described, but is shown as having two gates (e.g., reference 1). Figure 3 In one or more embodiments, the operations described herein can be applied to a single-gate structure. In some embodiments, the operations described herein can be applied to a dual-gate structure. In other embodiments, the operations described herein can be applied to a gate-all-around (GAA) structure (e.g., a quad-gate structure). In other embodiments, the operations described herein can be applied to memory elements employing such structures or combinations of other structures. In one or more embodiments, the cell stack 80 of the repeating film stack can enable the formation of additional layers of the memory element, including 3D DRAM cells. Furthermore, using an example of cell stacking in the film stack can enable the formation of a layer of 3D DRAM cells.

[0028] Gate electrode 34 is connected to the gate node of transistor 22, and gate electrode 34 may also be referred to herein as the gate node. Gate electrode 34 is formed on a first dielectric layer 32, which is formed on semiconductor layer 26. The first dielectric layer 32 may also be referred to as gate dielectric or gate oxide, and may be any suitable high dielectric constant (high K dielectric) material of suitable thickness for a field-effect transistor device. Gate electrode 34 may be deposited by any suitable deposition technique, such as conformal deposition processes, such as ALD.

[0029] In some embodiments, semiconductor layer 26 is silicon (e.g., single crystal, amorphous, or polycrystalline, which may be undoped or lightly p-type doped) or InGaZnO. Semiconductor layer 26 can be deposited by any suitable deposition technique, such as epitaxy or the like. In one or more embodiments, semiconductor layer 26 is formed by a stack of deposited silicon and silicon-germanium layers (e.g., alternating layers formed by epitaxial deposition), wherein the silicon-germanium layers are sacrificed and removed to leave a crystalline silicon layer.

[0030] In some embodiments, the first dielectric layer 32 is silicon oxide, silicon oxynitride, or another suitable dielectric material, such as a high-k dielectric. In one or more embodiments, the first dielectric layer 32 may be deposited by any suitable deposition technique, such as a conformal deposition process, such as atomic layer deposition (ALD). In one or more embodiments, the first dielectric layer 32 is an oxide formed by an oxidation process (e.g., by oxidizing the exposed surface of the semiconductor layer 26).

[0031] In some embodiments, the gate electrode 34 is made of any suitable conductive material, such as a metal (e.g., tungsten or molybdenum), a metal composite (e.g., titanium nitride), or polysilicon (n-type or p-type doped). In one or more embodiments, the gate electrode 34 may be deposited by any suitable deposition technique, such as a conformal deposition process, such as ALD. Although not shown for the stacked semiconductor structure 400, one or more gate barrier layers / tuning layers may be formed on the first dielectric layer 32 prior to the formation of the gate electrode 34, for example using a conformal deposition process, such as ALD.

[0032] In some embodiments, dielectric layer 46 is silicon dioxide, silicon nitride, another suitable dielectric material, such as a low-k or high-k dielectric material, or a combination of several materials. In one or more embodiments, dielectric layer 46 may be deposited by any suitable deposition technique, such as conformal deposition processes, such as atomic layer deposition (ALD).

[0033] In one or more embodiments, transistor 22 also includes dielectric filler 50 and dielectric filler 51 (which may be referred to as gate electrode filler). In some embodiments, dielectric filler 50, dielectric filler 51, or both are made of the same material as dielectric layer 46 or are formed as part of this dielectric layer. Dielectric filler 50 and dielectric filler 51 may be deposited by any suitable deposition technique, such as conformal deposition processes, such as ALD or chemical vapor deposition (CVD), or flowable deposition processes, such as flowable CVD (FCVD).

[0034] Bit line node 42 is a contact along the vertical axis (z direction). In one or more embodiments, bit line node 42 is along the vertical axis (z direction), and the DRAM pair is mirrored around this vertical axis.

[0035] The capacitor 24 portion of the stacked semiconductor structure 400 includes a second dielectric layer 72. A single cell stack 80 may include two portions of the second dielectric layer 72. In one or more embodiments, prior to stacking the semiconductor structure 400, the material stack includes a first set of dielectric layers (including the second dielectric layer 72) and a semiconductor layer (including semiconductor layer 26). The semiconductor layer (including semiconductor layer 26) may be laterally pulled back to expose a second side end 70 of the semiconductor layer 26. On the other hand, a first side end 69 of the semiconductor layer 26 opposite to the second side end 70 is coupled to a bit line node 42. The pull-back process may be any suitable isotropic etching that selectively etches the semiconductor layer (including semiconductor layer 26) to leave the first set of dielectric layers (including the second dielectric layer 72) and forms a side recess 71.

[0036] In one or more embodiments, for example after a pullback process that selectively etches semiconductor layers, a first set of dielectric layers (including a second dielectric layer 72) may be etched to thin the thickness of each dielectric layer to obtain a desired or appropriate size.

[0037] In one or more embodiments, a second set of one or more sacrificial layers may be deposited between the dielectric layer and the semiconductor layer. In some embodiments, the second set of one or more sacrificial layers may be a dielectric material different from that of the first set of dielectric layers. The second set of one or more sacrificial layers may then be selectively etched (e.g., before or after selectively etching the semiconductor layer) to remove these sacrificial layers.

[0038] refer to Figure 5 The present disclosure illustrates a stacked semiconductor structure 500 according to some examples. In one or more embodiments, a stacked semiconductor structure 500 is shown after the deposition of a doped silicon layer 74.

[0039] The doped silicon layer 74 can be deposited using any suitable deposition technique, such as conformal deposition processes, such as ALD or CVD. The doped silicon layer 74 can be a doped amorphous, polycrystalline, or non-crystalline silicon layer. In one or more embodiments, an undoped silicon layer 75 may be deposited prior to the deposition of the doped silicon layer 74, if appropriate. The undoped silicon layer 75 can be deposited using any suitable deposition technique, such as conformal deposition processes, such as ALD or CVD. In one or more embodiments, the undoped silicon layer 75 is an undoped amorphous or polycrystalline silicon layer.

[0040] In one or more embodiments, the doped silicon layer 74 has a thickness between 3 nanometers and 50 nanometers (e.g., average thickness). In some embodiments, the doped silicon layer 74 has a thickness of about 5 nanometers (e.g., average thickness), for example, on a portion of the doped silicon layer 74 at the second side end 70 of the contact semiconductor layer 26. In embodiments where an undoped silicon layer 75 is also deposited, the sum of the thicknesses of the undoped silicon layer 75 and the doped silicon layer 74 is not greater than 50 nanometers.

[0041] In one or more embodiments, the doped silicon layer 74 is doped with phosphorus. In one or more embodiments, the doped silicon layer 74 is doped with arsenic. In other embodiments, the doped silicon layer 74 is doped with any suitable n-type dopant, such as antimony. In other embodiments, the doped silicon layer 74 is doped with any suitable p-type dopant, such as boron, gallium, or indium. In one or more embodiments, the doped silicon layer 74 is doped with approximately 1 × 10⁻⁶ phosphorus per cubic centimeter. 21 Each atom (e.g., phosphorus or arsenic). In one or more embodiments, the doped silicon layer 74 is doped with approximately 5 × 10⁻⁶ atoms per cubic centimeter. 20 Approximately 2 × 10 atoms 21 Atoms. In some embodiments, a density greater than approximately 2 × 10⁻⁶ per cubic centimeter is used. 21 One atom.

[0042] In one or more embodiments, the stacked semiconductor structure 400 may undergo a native oxide pre-cleaning process prior to forming the doped silicon layer 74 as shown in the stacked semiconductor structure 500.

[0043] refer to Figure 6This disclosure illustrates a stacked semiconductor structure 600 according to some examples of this disclosure. In one or more embodiments, the stacked semiconductor structure 600 is shown after the deposition of a third dielectric layer 76, which may be any suitable sacrificial material. In one or more embodiments, the third dielectric layer 76 is silicon nitride. In one or more embodiments, the third dielectric layer 76 is aluminum oxide. In other embodiments, the third dielectric layer 76 may be SiON, SiCN, SiOCN, SiOC, SiGe, carbon, aluminum oxide, silicon, titanium nitride, Mo, or tungsten. The third dielectric layer 76 may be deposited by any suitable deposition technique, such as conformal deposition processes, such as ALD or CVD.

[0044] refer to Figure 7 This disclosure illustrates a stacked semiconductor structure 700 according to some examples of this disclosure. In one or more embodiments, the stacked semiconductor structure 700 is shown after etching a third dielectric layer 76 to expose a doped silicon layer 74. In one or more embodiments, the third dielectric layer 76 is isotopically etched to vertically separate the third dielectric layer 76 and expose the sidewalls of the doped silicon layer 74.

[0045] refer to Figure 8 This disclosure illustrates a stacked semiconductor structure 800 according to some examples of this disclosure. In one or more embodiments, the stacked semiconductor structure 700 is shown after a lateral portion of the doped silicon layer 74 has been pulled back, leaving a vertical portion 78 of the doped silicon layer 74 on a second side 70 of the semiconductor layer 26. In one or more embodiments, if an optional undoped silicon layer 75 is deposited, the lateral portion of the undoped silicon layer 75 is also pulled back, and the vertical portion 79 of the undoped silicon layer 75 is also retained on the second side 70 of the semiconductor layer 26. The pull-back process can be any suitable etching process that selectively etches the undoped silicon layer 75 (if deposited) and the doped silicon layer 74. For example, the etching process can use an ion screen to enhance selectivity, while primarily using free radicals for etching.

[0046] refer to Figure 9 This disclosure illustrates a stacked semiconductor structure 900 according to some examples of this disclosure. In one or more embodiments, the stacked semiconductor structure 900 is shown after the removal of the third dielectric layer 76. The removal (or pull-back) of the third dielectric layer 76 may be any suitable isotropic etching of the third dielectric layer 76 selectively. For example, when the third dielectric layer 76 is silicon nitride, a thermal phosphoric acid etching process may be used to pull back the third dielectric layer 76. Other isotropic etching processes may be used for silicon nitride, or when the third dielectric layer 76 is formed of another dielectric material.

[0047] refer to Figure 10This disclosure illustrates a stacked semiconductor structure 1000 according to some examples of this disclosure. In one or more embodiments, the stacked semiconductor structure 1000 is shown after a thermal annealing process is performed to drive dopant from a vertical portion 78 of a doped silicon layer 74 to a vertical portion 79 of an optional underlying undoped silicon layer 75 (if deposited) and / or a semiconductor layer 26 to create a doped region (second region 30). By using the thermal annealing process, the dopant (e.g., an n-type dopant, such as phosphorus, arsenic, or antimony, or a p-type dopant, such as boron, gallium, or indium) diffuses and can form a deeper gradient distribution as a lightly doped drain (LDD), which can reduce gate-induced drain leakage current in the transistor 22. In other embodiments, the driving in the thermal annealing can be skipped if a steep junction is desired according to device requirements. In yet another embodiment, a different thermal annealing process can be performed to activate the dopant in the silicon layer.

[0048] In one or more embodiments, the thermal annealing process includes performing a rapid thermal processing procedure. In one or more embodiments, the thermal annealing process includes applying heat between 600°C and 1100°C to the stacked semiconductor structure 900 for a period of less than 1 second and 30 minutes. According to one or more embodiments, a rapid thermal processing procedure with a higher temperature is used, such as applying a temperature above 600°C, a temperature below 1100°C, or both, to the doped silicon layer 74 on the second side 70 of the semiconductor layer 26. According to one or more embodiments, a rapid thermal processing procedure with a lower temperature is used, such as applying a temperature below 600°C and no greater than 1100°C to the doped silicon layer 74 on the second side 70 of the semiconductor layer 26. According to one or more embodiments, the rapid thermal processing procedure is performed within a period of less than 1 second and 30 minutes.

[0049] Figure 11 This is a flowchart of a semiconductor processing method 1100 according to some examples of this disclosure. In one or more embodiments, method 1100 includes one or more operations of a memory element manufacturing process, such as the manufacture of 3D DRAM. In one or more embodiments, method 1100 includes one or more operations described herein, for example, with reference to... Figures 1 to 10 One or more of them.

[0050] Operation 1105 of method 1100 includes providing a stacked semiconductor structure comprising a plurality of cell stacks formed on a substrate, each cell stack 80 comprising a transistor 22 portion and a capacitor 24 portion laterally adjacent to the transistor 22 portion. In one or more embodiments, the transistor 22 portion comprises a semiconductor layer 26, a first dielectric layer 32 formed on the semiconductor layer 26, and a gate electrode 34 formed on the first dielectric layer 32. The gate electrode 34 extends through a row of memory cells of a memory element to form a gate structure with the semiconductor layer 26. A first side 69 of the semiconductor layer 26 is doped and coupled to a bit line node 42 of the memory element. A second side 70 of the semiconductor layer 26 is opposite to the first side 69. The second side is adjacent to a side recess 71 formed in the second dielectric layer 72 of the capacitor 24 portion.

[0051] Operation 1107 of method 1100 includes conformally depositing an undoped silicon layer 75 on a second side end 70 of semiconductor layer 26 in the side recess 71. In one or more embodiments, operation 1107 is optional.

[0052] Operation 1110 of method 1100 includes conformally depositing a doped silicon layer 74. The doped silicon layer 74 is deposited in the side recess 71. If an undoped silicon layer 75 has been deposited, the doped silicon layer 74 is deposited on the undoped silicon layer 75. If the undoped silicon layer 75 has not been deposited, the doped silicon layer 74 is deposited on the second side end 70 of the semiconductor layer 26.

[0053] Operation 1115 of method 1100 includes performing a thermal annealing process after depositing the doped silicon layer 74. In one or more embodiments, operation 1115 is optional.

[0054] Operation 1120 of method 1100 includes forming a capacitor 24 in a portion of capacitor 24 where a side recess 71 is provided, the capacitor 24 contacting a doped silicon layer 74 (or optionally an undoped silicon layer 75) on a second side end 70 of semiconductor layer 26.

[0055] In one or more embodiments, method 1100 includes forming a third dielectric layer 76 on a doped silicon layer 74 in a side recess 71, the doped silicon layer 74 including a vertical portion 78 on a second side end 70 and a lateral portion coupled to the vertical portion 78. The lateral portion of the doped silicon layer is pulled back, and the third dielectric layer 76 is pulled back to expose the vertical portion 78 of the doped silicon layer 74. In one or more embodiments, pulling back the vertical portion 78 and the lateral portion of the doped silicon layer includes removing a portion of the doped silicon layer 74 between the third dielectric layer 76 and the second dielectric layer 72. In one or more embodiments, the third dielectric layer 76 comprises silicon nitride, aluminum oxide, or a combination of both silicon nitride and aluminum oxide. In one or more embodiments, if an optional undoped silicon layer 75 is deposited, the pull-back process also includes removing a portion of the undoped silicon layer 75 between the third dielectric layer 76 and the second dielectric layer 72, leaving a vertical portion 79 of the undoped silicon layer 75.

[0056] In one or more embodiments, the thermal annealing process includes a rapid thermal processing procedure following the formation of a doped silicon layer 74 on the second side 70. In one or more embodiments, the thermal annealing process includes applying heat of at least 600 degrees Celsius and not exceeding 1100 degrees Celsius to the stacked semiconductor structure for a period between less than 1 second and about 30 minutes. According to one or more embodiments, a rapid thermal processing procedure with higher or lower temperatures is used, such as applying a temperature above 1100 degrees Celsius or below 600 degrees Celsius to the doped silicon layer 74 (or optionally undoped silicon layer 75) on the second side 70 of the semiconductor layer 26.

[0057] In one or more embodiments, the doped silicon layer 74 has a thickness between 3 nanometers and 50 nanometers (e.g., average thickness). In some embodiments, the doped silicon layer 74 has a thickness of about 5 nanometers (e.g., average thickness), for example, on a portion of the doped silicon layer 74 at the second side end 70 of the contact semiconductor layer 26. In embodiments where an undoped silicon layer 75 is also deposited, the sum of the thicknesses of the undoped silicon layer 75 and the doped silicon layer 74 is not greater than 50 nanometers.

[0058] In one or more embodiments, the doped silicon layer 74 is doped with phosphorus. In one or more embodiments, the doped silicon layer 74 is doped with arsenic. In other embodiments, the doped silicon layer 74 is doped with any suitable n-type dopant, such as antimony. In other embodiments, the doped silicon layer 74 is doped with any suitable p-type dopant, such as boron, gallium, or indium. In one or more embodiments, the doped silicon layer 74 is doped with at least 1 × 10⁻⁶ ppm. 20 Individual atoms (e.g., phosphorus or arsenic).

[0059] Figure 12This is a flowchart of a semiconductor processing method 1200 according to one or more embodiments. In one or more embodiments, method 1200 includes one or more operations of a memory element manufacturing process, such as the manufacture of 3D DRAM. In one or more embodiments, method 1200 includes one or more operations described herein, for example, referring to... Figures 1 to 11 One or more of them.

[0060] Operation 1205 of method 1200 includes providing a stacked semiconductor structure comprising a plurality of cell stacks formed on a substrate. Each cell stack 80 includes a semiconductor layer 26 having a first side 69 and a second side 70. A first dielectric layer 32 of the cell stack 80 is formed on the semiconductor layer 26. A gate electrode 34 of the cell stack 80 is formed on the first dielectric layer 32. The cell stack 80 also includes a second dielectric layer 72 for a portion of a capacitor 24. A side recess 71 is defined at its top and bottom by the second dielectric layer 72 and at its first side by the second side 70 of the semiconductor layer 26. The side recess 71 opens to a first opening at its second side via the cell stack 80 of the stacked semiconductor structure.

[0061] Operation 1207 of method 1200 includes conformally depositing an undoped silicon layer 75 on a second side end 70 of semiconductor layer 26 in the side recess 71. In one or more embodiments, operation 1107 is optional.

[0062] Operation 1210 of method 1200 includes conformally depositing a doped silicon layer 74. The doped silicon layer 74 is deposited in the side recess 71. If an undoped silicon layer 75 has been deposited, the doped silicon layer 74 is deposited on the undoped silicon layer 75. If the undoped silicon layer 75 has not been deposited, the doped silicon layer 74 is deposited on the second side end 70 of the semiconductor layer 26.

[0063] Operation 1215 of method 1200 includes performing a thermal annealing process after forming a doped silicon layer on the second side. In one or more embodiments, operation 1215 is optional.

[0064] Operation 1220 of method 1200 includes forming a capacitor 24 with a side recess 71, the capacitor 24 contacting a doped silicon layer 74 on a second side end 70 of semiconductor layer 26.

[0065] Figure 13 This is a flowchart of a semiconductor processing method 1300 according to one or more embodiments. In one or more embodiments, method 1300 includes one or more operations of a memory element manufacturing process, such as the manufacture of 3D DRAM. In one or more embodiments, method 1300 includes one or more operations described herein, for example, referring to... Figures 1 to 12 One or more of them.

[0066] Operation 1305 of method 1300 includes forming a stacked semiconductor structure comprising a plurality of cell stacks formed on a substrate, wherein each cell stack 80 includes a semiconductor layer 26, a first dielectric layer 32 formed on the semiconductor layer 26, and a second dielectric layer 72 for a portion of a capacitor 24 of the stacked semiconductor structure. The semiconductor layer 26 has a first side end 69 and a second side end 70 opposite to the first side end 69.

[0067] Operation 1310 of method 1300 includes forming a first opening through the cell stack 80.

[0068] Operation 1315 of method 1300 includes forming a side recess 71 from the first opening to expose a second side end 70 of the semiconductor layer 26.

[0069] Operation 1317 of method 1300 includes conformally depositing an undoped silicon layer 75 on a second side end 70 of semiconductor layer 26 in the side recess 71. In one or more embodiments, operation 1317 is optional.

[0070] Operation 1320 of method 1300 includes conformally depositing a doped silicon layer 74 in the side recess 71. The doped silicon layer includes a vertical portion 78 (or a vertical portion 79 of an undoped silicon layer 75) on the second side end 70 and a lateral portion coupled to the vertical portion 78.

[0071] Operation 1325 of method 1300 includes forming a third dielectric layer 76 on the doped silicon layer 74 in the side recess 71.

[0072] Operation 1330 of method 1300 includes pulling back the third dielectric layer 76 to expose the vertical portion 78 of the doped silicon layer 74.

[0073] Operation 1335 of method 1300 includes pulling back the vertical portion 78 and the lateral portion of the doped silicon layer 74 (and optionally the undoped silicon layer 75, if deposited).

[0074] Operation 1340 of method 1300 includes removing the third dielectric layer 76, which serves as a sacrificial layer.

[0075] The operation 1345 of method 1300 includes performing a thermal annealing process after conformally depositing the doped silicon layer 74, after depositing the third dielectric layer 76, after pulling back the doped silicon layer 74, or after completely removing the sacrificial third dielectric layer 76.

[0076] It is considered that various objects disclosed herein may be combined. As examples, one or more forms, features, components, and / or properties of DRAM cell 100, mirrored DRAM pairs 200 to 300, stacked semiconductor structures 400 to 1000, and / or methods 1100 to 1300 may be combined. Furthermore, it is considered that various objects disclosed herein may include some or all of the foregoing benefits.

[0077] While the foregoing describes embodiments of this disclosure, other and further embodiments of this disclosure may be designed without departing from its basic scope. This disclosure also considers that one or more of the embodiments described herein may replace one or more of the other described embodiments. The scope of this disclosure is determined by the appended claims.

Claims

1. A method for semiconductor processing, comprising the steps of: providing a stacked semiconductor structure comprising a plurality of cell stacks formed on a substrate, each cell stack comprising a transistor portion and a capacitor portion laterally adjacent to the transistor portion, wherein the transistor portion comprises a semiconductor layer, a first dielectric layer formed on the semiconductor layer, and a first gate electrode formed on the first dielectric layer, wherein the first gate electrode extends through a column of memory cells of a memory element to form a gate structure with the semiconductor layer, a first side end of the semiconductor layer is doped and coupled to a bit line node of the memory element, and a second side end of the semiconductor layer opposite the first side end is adjacent to a side recess formed in a second dielectric layer of the capacitor portion; conformally depositing a doped silicon layer on the second side end of the semiconductor layer in the side recess; performing an optional thermal anneal process after forming the doped silicon layer on the second side end; and forming a capacitor in the capacitor portion where the side recess is disposed, the capacitor contacting the doped silicon layer on the second side end of the semiconductor layer.

2. The method of claim 1, further comprising the steps of: forming a third dielectric layer on the doped silicon layer in the side recess, the doped silicon layer including a vertical portion on the second side end and lateral portions coupled to the vertical portion; pulling back the vertical portion and the lateral portions of the doped silicon layer; and pulling back the third dielectric layer to expose the vertical portion of the doped silicon layer.

3. The method of claim 2, wherein the third dielectric layer comprises silicon nitride, aluminum oxide, or a combination thereof.

4. The method of claim 2, wherein the step of pulling back the vertical portion and the lateral portions of the doped silicon layer comprises the step of removing portions of the doped silicon layer between the third dielectric layer and the second dielectric layer.

5. The method of claim 1, wherein the step of performing the thermal anneal process comprises the step of: performing a rapid thermal process after forming the doped silicon layer on the second side end.

6. The method of claim 1, wherein the step of performing the thermal anneal process comprises the step of: applying heat of at least 600 degrees Celsius and no greater than 1100 degrees Celsius to the stacked semiconductor structure for a period of time between less than 1 second and 30 minutes.

7. The method of claim 1, wherein the doped silicon layer comprises an average thickness between 3 nanometers and 50 nanometers.

8. The method of claim 1, wherein the doped silicon layer comprises polysilicon doped with phosphorus, arsenic, or a combination thereof.

9. The method of claim 8, wherein the doped silicon layer comprises polysilicon, the doped concentration of the polysilicon comprising at least 1 x 1018 atoms of phosphorous per cubic centimeter. 20 9. The method of claim 8, wherein the doped silicon layer comprises polysilicon, the doped concentration of the polysilicon comprising at least 1 x 1018 atoms of phosphorous per cubic centimeter.

10. A method for semiconductor processing, comprising the steps of: A stacked semiconductor structure is provided, the stacked semiconductor structure including a plurality of cell stacks formed on a substrate, each cell stack including a semiconductor layer having a first side end and a second side end, a first dielectric layer formed on the semiconductor layer, a first gate electrode formed on the first dielectric layer, and a second dielectric layer of a capacitor portion, wherein a side recess is defined by the second dielectric layer at a top and a bottom and by the second side end of the semiconductor layer at a first side, and the side recess is open to a first opening through the cell stacks of the stacked semiconductor structure at a second side; a doped silicon layer is conformally deposited on the second side end of the semiconductor layer in the side recess; a thermal anneal process is performed after forming the doped silicon layer on the second side end; and a capacitor is formed that sets the side recess, the capacitor contacting the doped silicon layer on the second side end of the semiconductor layer.

11. The method of claim 10, further comprising: forming a third dielectric layer on the doped silicon layer in the side recess, the doped silicon layer including a vertical portion on the second side end and lateral portions coupled with the vertical portion; pulling back the vertical portion and the lateral portions of the doped silicon layer; and pulling back the third dielectric layer to expose the vertical portion of the doped silicon layer.

12. The method of claim 11, wherein the third dielectric layer includes silicon nitride, aluminum oxide, or a combination thereof.

13. The method of claim 11, wherein pulling back the vertical portion and the lateral portions of the doped silicon layer includes removing portions of the doped silicon layer between the third dielectric layer and the second dielectric layer.

14. The method of claim 10, wherein performing the thermal anneal process includes: performing a rapid thermal process after forming the doped silicon layer on the second side end.

15. The method of claim 10, wherein performing the thermal anneal process includes: applying heat of at least 600 degrees Celsius and no greater than 1100 degrees Celsius to the stacked semiconductor structure for a period of time between less than 1 second and 30 minutes.

16. The method of claim 10, wherein the doped silicon layer includes polysilicon doped with phosphorous, arsenic, or a combination thereof.

17. A method for semiconductor processing, comprising: forming a stacked semiconductor structure including a plurality of cell stacks formed on a substrate, each cell stack including a semiconductor layer having a first side end and a second side end opposite the first side end, a first dielectric layer formed on the semiconductor layer, and a second dielectric layer of a capacitor portion of the stacked semiconductor structure; forming a first opening through the cell stacks; forming a side recess from the first opening to expose the second side end of the semiconductor layer; conformally depositing a doped silicon layer in the side recess, the doped silicon layer including a vertical portion on the second side end and lateral portions coupled with the vertical portion; forming a third dielectric layer on the doped silicon layer in the side recess; pulling back the third dielectric layer to expose the vertical portion of the doped silicon layer; removing the third dielectric layer as a sacrificial layer; pulling back the vertical portion and the lateral portions of the doped silicon layer; and performing a thermal anneal process after conformally depositing the doped silicon layer, after depositing a third dielectric layer, or after pulling back the doped silicon layer, or after completely removing the third dielectric layer.

18. The method of claim 17, further comprising the steps of: forming a capacitor disposed in the undercut, the capacitor contacting the doped silicon layer on the second side end of the semiconductor layer.

19. The method of claim 17, further comprising the steps of: performing a rapid thermal process after forming the doped silicon layer on the second side end.

20. The method of claim 17, wherein the doped silicon layer comprises an average thickness of at least 3 nanometers and no greater than 20 nanometers, comprising polysilicon, the doped concentration of the polysilicon comprising at least 1 x 10 20 phosphorus atoms per cubic centimeter.

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