Method and device for determining wafer test abnormity

Abstract

The invention provides a method and equipment for determining wafer test abnormity. The method comprises the following steps: testing a wafer to be tested to obtain test data; if the test is abnormal, determining whether the abnormal type is an open circuit or a short circuit according to the test data; if not, generating a wafer graph based on the test data, and determining whether the abnormal type is misslaughtered or not according to the test data and the wafer graph; and according to the determined exception type, determining factors causing the test exception. According to the method provided by the invention, the factors causing the test abnormity are determined based on the determined abnormity type, so that the efficiency of determining the abnormal factors is improved, the test efficiency is effectively improved, and meanwhile, the test accuracy and the wafer yield are improved.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of semiconductor testing, and particularly relates to a wafer test abnormality determination method and device. BACKGROUND

[0002] After wafer manufacturing is completed, in order to ensure wafer quality, the wafer is usually tested to ensure that each chip in the wafer can meet design requirements.

[0003] At present, if a test abnormality occurs in the process of testing the wafer, a tester usually determines a factor causing the test abnormality based on experience. Since there is a certain difference in experience of different testers, and there are multiple factors causing the test abnormality, the tester cannot determine the factor causing the test abnormality in time, and the test efficiency is low. SUMMARY

[0004] The present application provides a wafer test abnormality determination method and device, to solve the problem in the prior art that a tester cannot determine a factor causing a test abnormality in time based on experience, and the test efficiency is low.

[0005] In a first aspect, the present application provides a wafer test abnormality determination method, comprising:

[0006] testing a wafer to be tested to obtain test data;

[0007] if a test abnormality occurs, determining whether an abnormality type is an open circuit or a short circuit according to the test data;

[0008] if not, generating a wafer map based on the test data, and determining whether the abnormality type is a false death according to the test data and the wafer map;

[0009] determining a factor causing the test abnormality according to the determined abnormality type.

[0010] In a second aspect, the present application provides a wafer test abnormality determination device, comprising a processor and a memory, the memory stores codes, and the processor executes the codes stored in the memory to perform the method in any one of the first aspect.

[0011] The application provides a wafer test abnormality determination method and device. The method comprises: testing a wafer to be tested to obtain test data. If the test is abnormal, determining whether the abnormality type is an open circuit or a short circuit according to the test data. If not, generating a wafer map based on the test data, and determining whether the abnormality type is a false death according to the test data and the wafer map. According to the determined abnormality type, a factor causing the test abnormality is determined. In the application, the abnormality type is divided into three types, i.e. an open circuit, a short circuit and a false death. The abnormality type corresponding to the test abnormality is determined preferentially. Since the factors caused by different types of abnormality are different, and the process of determining the factors is also different, the application determines the factors causing the abnormality based on the abnormality type, so that the abnormality factors can be determined quickly and accurately, the test efficiency and accuracy are improved, and the wafer yield is also improved. BRIEF DESCRIPTION OF DRAWINGS

[0012] The accompanying drawings, which are incorporated herein and form part of the specification, illustrate embodiments consistent with the application and, together with the description, further serve to explain the principles of the application.

[0013] Figure 1 A structure schematic diagram of a wafer test system provided by an embodiment of the application;

[0014] Figure 2 A wafer test abnormality determination method flowchart provided by an embodiment of the application;

[0015] Figure 3 A factor determination method flowchart for causing a false death when the abnormality type is a false death provided by an embodiment of the application;

[0016] Figure 4 A probe position offset determination schematic diagram provided by an embodiment of the application;

[0017] Figure 5 A factor determination method flowchart for causing a short circuit when the abnormality type is a short circuit provided by an embodiment of the application;

[0018] Figure 6 A factor determination method flowchart for causing an open circuit when the abnormality type is an open circuit provided by an embodiment of the application;

[0019] Figure 7 A wafer test abnormality determination device schematic diagram provided by an embodiment of the application;

[0020] Figure 8 A wafer test abnormality determination device schematic diagram provided by an embodiment of the application.

[0021] The specific embodiments of the application will be described in detail below with reference to the attached drawings. These drawings and the associated description are not intended to limit the scope of the application in any way, but merely to illustrate the concepts of the application to those skilled in the art. DETAILED DESCRIPTION

[0022] The exemplary embodiments will be described in detail below with reference to the attached drawings. The following description is not intended to limit the scope of the application in any way, but merely to illustrate the concepts of the application to those skilled in the art.

[0023] It should be noted that the user information (including but not limited to user equipment information, user personal information, etc.) and data (including but not limited to data for analysis, stored data, displayed data, etc.) involved in the present application are all information and data authorized by the user or authorized by all parties, and the collection, use and processing of related data need to comply with relevant laws, regulations and standards of relevant countries and regions, and provide corresponding operation portal for user to choose authorization or refusal.

[0024] When the wafer is tested, if the test is abnormal, the test personnel usually needs to determine the factors causing the test abnormality based on their own experience. Since there are certain differences in the experience of different test personnel, and there are multiple factors causing the test abnormality, the test personnel cannot determine the factors causing the test abnormality in time, which causes the test efficiency.

[0025] At the same time, when the test personnel with less experience cannot accurately determine the abnormal factors and blindly process, it may cause damage to the probe card, the probe station and the wafer, etc.

[0026] Therefore, the present application provides a wafer test abnormality determination method and device. When the wafer to be tested is abnormal, the method can determine whether the abnormal type is open circuit or short circuit according to the acquired test data. If not, the wafer map is generated based on the test data, and whether the abnormal type is misoperation is determined according to the test data and the wafer map. The factors causing the abnormality are determined based on the determined abnormal type. Since the factors caused by different types of abnormality exist certain differences, and the process of determining the factors also exists certain differences, the present application determines the factors causing the abnormality based on the determined abnormal type, which is beneficial to improve the efficiency of abnormal factors, and further beneficial to improve the test efficiency, and also beneficial to improve the accuracy of the test and the yield of the wafer, etc.

[0027] Figure 1A structural schematic diagram of a system for testing a wafer is provided for an embodiment of the present application, referring to FIG. 1. Figure 1 As shown in the figure, the system includes a tester 11, a probe station 12, and a probe card 13, etc. The tester 11 is a device for executing a test program and controlling a test process, which sends test signals and instructions to the probe station 12 and the probe card 13. The probe station 12 can be used to place a wafer under test 14 and can move the wafer under test 14. The probe card 13 is a device for connecting the tester 11 and the wafer under test 14, which can receive test signals from the tester 11 and transmit the test signals to the wafer under test 14 through probes 131 included in the probe card 13. At the same time, the response signals of the wafer under test 14 can also be transmitted back to the tester 11 through the probe card 13 for analysis and processing.

[0028] The technical solutions of the present application and how the technical solutions of the present application solve the above technical problems will be described in detail in the following specific embodiments. The following specific embodiments can be combined with each other, and the same or similar concepts or processes can not be described again in some embodiments. The embodiments of the present application will be described below with reference to the accompanying drawings.

[0029] Figure 2 A flow chart of a method for determining wafer test abnormalities is provided for an embodiment of the present application, referring to FIG. 2. Figure 2 As shown in the figure, the method can include:

[0030] S201: Test the wafer under test and obtain test data.

[0031] In one implementation scenario, the test data can include the electrical performance of each chip or device on the wafer under test, such as resistance, capacitance, voltage, etc.

[0032] In one implementation scenario, the test data can be text format data.

[0033] S202: If the test is abnormal, determine whether the abnormal type is an open circuit or a short circuit according to the test data.

[0034] In some embodiments, determining whether the abnormal type is an open circuit or a short circuit according to the test data includes:

[0035] Analyzing the test data to obtain the voltage value of the diode in the wafer under test;

[0036] If the absolute value of the voltage value is higher than a first threshold value, it is determined that the abnormal type is an open circuit.

[0037] If the absolute value of the voltage value is lower than a second threshold value, and the second threshold value is less than the first threshold value, it is determined that the abnormal type is a short circuit.

[0038] In an implementation scenario, the diode can be an upper diode or a lower diode included in the chip circuit of the wafer to be tested. Generally, the voltage drop of the upper diode is positive, the voltage drop of the lower diode is negative, and there is a normal voltage drop range, which is a range formed by the first threshold value and the second threshold value.

[0039] The above diode is used as an example to set the first threshold value as 800 mV and the second threshold value as 200 mV. Since the voltage drop of the upper diode is positive, if the voltage value of the upper diode obtained through the test data is greater than 800 mV, it can be determined that the upper diode is open circuit. If the voltage value of the upper diode obtained through the test data is less than 200 mV, it can be determined that the upper diode is short circuit.

[0040] S203: If no, generating a wafer map based on the test data, and determining whether the abnormal type is overkill according to the test data and the wafer map.

[0041] The wafer map is a map image generally showing the test results of each chip or device on the wafer. In the map image, each chip or device is generally represented by a small square or other shape, and different colors or marks represent different test results or states, such as pass, failure, and to be tested.

[0042] In some embodiments, when determining whether the abnormal type is overkill according to the test data and the wafer map, the distribution of fault points in the map image can be used to determine the abnormal type. Generally, if the fault points are regularly distributed, the corresponding test data can be used to determine that the abnormal type causing the test abnormality is overkill.

[0043] S204: Determining the factor causing the test abnormality according to the determined abnormal type.

[0044] As can be seen from the above, the abnormal type can include open circuit, short circuit, and overkill, and since the factors causing different abnormalities are different, the process of determining the factors corresponding to different abnormalities is also different. Therefore, the present application determines the factor causing the test abnormality based on the determined abnormal type, which is beneficial to quickly and accurately locate the abnormal factor.

[0045] In an implementation scenario, the factors causing open circuit include but are not limited to probe card failure, tester failure, etc. The probe card includes a probe, a pogo pin, and a circuit board, etc. The probe card failure causing open circuit can include a too short probe, a dirty pogo pin, and a circuit board failure, etc.

[0046] In an implementation scenario, the factors causing short circuit include but are not limited to probe card failure, tester failure, etc.

[0047] In an implementation scenario, factors causing mis-sacrifice include, but are not limited to, probe card failure. Specifically, the probe card failure causing mis-sacrifice can include probe contamination, probe position offset, and the like.

[0048] The embodiment of the present application provides a wafer test abnormality determination method. A wafer to be tested is tested to obtain test data. If the test is abnormal, it is determined whether the abnormality type is an open circuit or a short circuit according to the test data. If not, a wafer map is generated based on the test data, and it is determined whether the abnormality type is mis-sacrifice according to the test data and the wafer map. According to the determined abnormality type, factors causing the test abnormality are determined. Since the present application divides the abnormality into three types of open circuit, short circuit and mis-sacrifice, the factors caused by different types of abnormality have certain differences, and the process of determining the factors also has certain differences. Therefore, the present application determines the factors causing the test abnormality based on the determined abnormality type, improves the efficiency of determining the abnormality factors, and further effectively improves the test efficiency. At the same time, it is also beneficial to improve the test accuracy and wafer yield.

[0049] In one or more embodiments of the present application, Figure 3 For the determination method flowchart of factors causing mis-sacrifice when the abnormality type provided by the embodiment of the present application is mis-sacrifice, reference is made to Figure 3 When the abnormality type is mis-sacrifice, the factors causing the test abnormality are determined according to the determined abnormality type, including:

[0050] S301: If the abnormality type is mis-sacrifice, a shooting device is controlled to obtain an image including a probe.

[0051] In an implementation scenario, the shooting device includes, but is not limited to, a Camera (camera) of a probe station, a tool microscope, and the like. The tool microscope can be selected according to the actual required range and accuracy, for example, a tool microscope with a range of 0.01 μm and an accuracy of 0.1 μm can be selected.

[0052] S302: Whether the probe has contamination is determined according to the image.

[0053] In an implementation scenario, when the image based on the Camera irradiation is used to determine the contamination, the detection personnel usually visually inspect larger contamination, such as contamination with a diameter greater than 30 μm. For smaller contamination, the tool microscope can be used for confirmation.

[0054] In another implementation scenario, when the detection personnel uses the tool microscope, the height, length, width and the like of the probe tip can be accurately measured through the measurement function of the tool microscope. The general appearance feature of the contamination is irregular, while the tip is a regular circle, and the visual inspection is also easy to distinguish.

[0055] In another implementation scenario, the trained model can be used to determine whether the probe is contaminated according to the image, or the image can be processed according to an image processing method to determine whether the probe is contaminated, or the image can be sent to a terminal of a detection personnel for confirmation.

[0056] S303: If the probe is contaminated, cleaning the probe, and testing the wafer to be tested based on the cleaned probe.

[0057] When the probe is contaminated, the probe can be removed and cleaned to ensure that the probe is not contaminated and to avoid the impact of contamination on testing.

[0058] S304: If the test is normal, determining that the factor causing the misdiagnosis is that the probe is contaminated.

[0059] Since the probe is abnormal before cleaning and normal after cleaning, it can be determined that the factor causing misdiagnosis before cleaning is that the probe is contaminated.

[0060] In another implementation scenario, if the test is still abnormal, since the probe has been cleaned at this time, the factor causing the abnormality is not due to the contamination of the probe. At this time, the abnormal type corresponding to the abnormality can be re-determined, and the factor causing the abnormality can be determined.

[0061] S305: If the probe is not contaminated, determining the position of the probe.

[0062] In one implementation scenario, the position of the probe can be determined based on the Camera or tool microscope of the probe station.

[0063] S306: Based on the position of the probe and the standard position of the probe, determining the position offset of the probe.

[0064] In one implementation scenario, the position offset of the probe can be the distance between the current position of the probe and the standard position.

[0065] In one implementation scenario, when the tool microscope is used to determine the position offset of the probe, the position offset of the probe is mainly determined by the measurement method. Figure 4 A determination diagram of the position offset of the probe provided by the embodiment of the present application is shown in the figure. It is assumed that the to-be-tested needle tip is A, the standard position is A1, the current actual position is A2, and the two needle tips adjacent to the to-be-tested needle tip A are B and C. At this time, the needle tips B and C can be connected, and the distance between A2 and BC is measured. The distance is the position offset of the needle tip A.

[0066] In another implementation scenario, the Camera can be used to roughly determine the position offset of the probe.

[0067] S307: If the position offset of the probe is greater than the preset offset threshold, adjust the position of the probe, and test the wafer to be tested based on the adjusted probe.

[0068] The preset offset threshold can be adjusted according to actual conditions, for example, it can be 10 pm, or a needle tip diameter, etc., which is not limited in the present application. Generally, the needle tip diameter is 15-30 pm.

[0069] S308: If the test is normal, it is determined that the factor causing the false death is that the probe has a position offset.

[0070] Since the position of the probe has been adjusted at this time and the test is normal, the test can continue at this time.

[0071] In another implementation scenario, if the test is still abnormal at this time, since it has been determined that the probe is not dirty at this time, and the position of the probe has also been adjusted, that is, there is no position offset or the position offset is within a preset range, therefore, the factor causing this abnormality is not that the probe is dirty, nor that the probe has a position offset. At this time, the abnormal type corresponding to the abnormality can be re-determined, and then the factor causing the abnormality is determined.

[0072] S309: If the position offset of the probe is less than the offset threshold, it is determined whether a chip with a fixed position causes the test abnormality in the multiple test processes.

[0073] In one implementation scenario, when testing the wafer, multiple chips on the wafer can be tested at the same time. Taking four chips tested at the same time as an example, the four chips can be denoted as site1, site2, site3 and site4, and the position of each site is fixed. If the chip of the same site has been in test abnormality in multiple test processes, this phenomenon can be called By site or By site overkill.

[0074] In one implementation scenario, a map obtained in the multiple test processes can be obtained, and the By site phenomenon can be determined by analyzing the map.

[0075] S310: If yes, the probe card is repaired, and the wafer to be tested is tested based on the repaired probe card, and if the test is normal, it is determined that the factor causing the false death is the probe card.

[0076] In one implementation scenario, the probe card is repaired, and specifically, the position of the probe can be checked and adjusted accordingly.

[0077] S311: If no, test the wafer under test based on the same test environment, and if the test is normal, determine that the factor causing the misoperation is the test machine.

[0078] In one implementation scenario, the current test machine can be checked to determine the fault of the test machine. If the time required to solve the fault is short, the fault of the test machine can be repaired, and the wafer under test is tested based on the repaired test machine. If the test is normal, it is determined that the factor causing the misoperation is the test machine.

[0079] In another implementation scenario, if the time required to solve the fault is long, another test machine can be used to build the same test environment, and the wafer under test is tested based on the other test machine. If the test is normal at this time, it can be further determined that the factor causing the misoperation is the current test machine.

[0080] In summary, when the abnormal type is misoperation, it can be determined whether the misoperation is caused by the contamination of the probe. If yes, the probe is removed for cleaning operation. If no, it is determined whether the misoperation is caused by the position offset of the probe. If yes, the position of the probe is adjusted. If no, it is determined whether the chip at the fixed position is the cause of the test abnormality in the multiple test processes. If yes, the misoperation is caused by the probe card fault. If no, the misoperation is caused by the test machine fault. The factor causing the misoperation can be quickly and accurately determined and timely processed, which effectively improves the abnormal determination efficiency and in turn improves the test efficiency.

[0081] In one or more embodiments of the present application, Figure 5 For the method flowchart for determining the factor causing the short circuit when the abnormal type is short circuit provided in the embodiments of the present application, reference is made to FIG. 6. Figure 5 As shown in FIG. 6, when the abnormal type is short circuit, the factor causing the test abnormality is determined according to the determined abnormal type, which includes:

[0082] S501: If the abnormal type is short circuit, the probe is separated from the wafer under test, and the wafer under test is tested.

[0083] In one implementation scenario, the probe is separated from the wafer under test, i.e., the two are not in contact, which can be achieved by the probe table. Specifically, the stage on which the wafer under test is located can be lowered by operating the probe table.

[0084] S502: If the test is normal, it is determined that the factor causing the short circuit is the probe card.

[0085] Since the probe does not contact the wafer to be tested at this time, theoretically, the signal sent by the tester cannot form a path, and the test will not pass, so if the test is normal, it means that the circuit board in the probe card and the needle tip form a path, and the factor causing the short circuit is that the circuit board of the probe card fails, at this time, the probe card can be repaired, and the probe position can be checked.

[0086] S503: If the test is abnormal, test the wafer to be tested after removing the probe card.

[0087] The test is abnormal, indicating that the probe card has no problem, so the probe card can be removed, and the tester runs the test program to see if it can pass the test.

[0088] S504: If the test is normal, determine that the factor causing the short circuit is the tester.

[0089] Since there is no probe card at this time, theoretically, the signal sent by the tester cannot form a path, and if the test is normal at this time, it means that there is a path inside the tester, that is, the tester has a fault, at this time, the tester can be repaired, and after the detection is completed, the test can continue.

[0090] In another implementation scenario, if the test is abnormal, it can indicate that the tester is normal, and the test can continue at this time.

[0091] In summary, when the abnormal type is short circuit, the probe is separated from the wafer to be tested, if the test is normal at this time, it can be determined that the factor causing the short circuit is the probe card, if the test is abnormal, further test after removing the probe card. If the test is normal at this time, it means that the factor causing the short circuit is the tester, which can quickly and accurately determine the factor causing the short circuit, and then quickly solve the problem, thereby facilitating the improvement of test efficiency.

[0092] In one or more embodiments of the present application, Figure 6 When the abnormal type is open circuit, the method for determining the factor causing the open circuit is provided in the embodiments of the present application, and the flow chart is shown in Figure 6 When the abnormal type is open circuit, according to the determined abnormal type, the factor causing the test abnormality is determined, including:

[0093] S601: If the abnormal type is open circuit, determine whether the fixed pins of different wafers cause the test abnormality in the multiple test processes.

[0094] In one implementation scenario, the test data obtained in the multiple test processes can be obtained, and after the test data is analyzed, the corresponding data can be viewed to determine whether the fixed pins of different wafers cause the test abnormality in the multiple test processes, wherein the number of fixed pins can be one or more.

[0095] If the fixed pins of different wafers cause the test abnormality in the multiple test processes, steps S602-S605 and S609 are executed; if the fixed pins of different wafers do not cause the test abnormality in the multiple test processes, steps S606-S608 and S609 are executed.

[0096] S602: If the fixed pins exist, the penetration depth of the probe is increased to test the wafer to be tested based on the current probe.

[0097] In an implementation scenario, if the fixed pins of different wafers cause the test abnormality in the multiple test processes, it is possible that the probe is too short, and therefore the penetration depth of the probe can be increased, that is, the OD (Overdrive, needle pressure) is increased.

[0098] In an implementation scenario, the increase of the penetration depth of the probe can be controlled by the probe table, and the accuracy can be 1 μm.

[0099] S603: If the absolute value of the voltage value of the diode obtained by the test is reduced by the difference from the first threshold value, it is determined that the factor causing the open circuit is the penetration depth of the probe, the penetration depth of the probe is increased, and the wafer to be tested is tested until the absolute value of the voltage value is less than the first threshold value.

[0100] In an implementation scenario, the test data can be obtained after the test is completed, and the voltage value of the corresponding diode can be obtained after the test data is analyzed.

[0101] After the penetration depth of the probe is increased, the absolute value of the voltage value of the diode obtained by the test is reduced by the difference from the first threshold value, which can indicate that the factor causing the open circuit is that the penetration depth of the probe is not enough, specifically, the probe is too short and does not make good contact with the wafer.

[0102] To eliminate the abnormality, the penetration depth of the probe can be continuously increased, the wafer to be tested can be tested, and the process can be repeated until the absolute value of the voltage value of the diode is less than the first threshold value.

[0103] S604: If the absolute value of the voltage value of the diode obtained by the test is not changed by the difference from the first threshold value, the pogo pin is cleaned, and the wafer to be tested is tested based on the cleaned pogo pin.

[0104] After the penetration depth of the probe is increased, the absolute value of the diode voltage value is not changed by the difference from the first threshold value, which indicates that the penetration depth of the probe has met the requirement and can make good contact with the wafer, and it can be determined whether the open circuit is caused by the dirt of the pogo pin.

[0105] The pogo pin is connected with the test machine board card and is used to conduct the electrical signal of the test machine to the probe card. If the pogo pin is dirty, the test open circuit can also be caused.

[0106] In an implementation scenario, an image of the pogo pin can be acquired before the pogo pin is cleaned, and whether the pogo pin is dirty is determined based on the image.

[0107] In an implementation scenario, since the pogo pin is large, usually with a diameter of more than 1 mm, a tester can determine whether the pogo pin is dirty by visual inspection.

[0108] In another implementation scenario, whether the pogo pin is dirty can also be determined by an image processing algorithm, a trained model, or the like.

[0109] S605: If the test is normal, it is determined that the factor causing the open circuit is the pogo pin.

[0110] Since the test is normal after the pogo pin is cleaned again, it is determined that the factor causing the open circuit is the pogo pin, specifically, because the pogo pin is dirty.

[0111] S606: If there is no fixed pin, the probe is cleaned online, and the wafer under test is tested according to the cleaned probe.

[0112] Generally, cleaning the probe online (online cleaning) is mainly used to remove oxides on the needle tip, and in the above embodiment, the probe is removed for cleaning, which is mainly used to clean dirt on the probe.

[0113] S607: If the absolute value of the voltage value of the diode obtained by the test decreases by the first threshold value, it is determined that the factor causing the open circuit is the probe.

[0114] If the absolute value of the voltage value of the diode obtained by the test decreases by the first threshold value, it indicates that cleaning the probe online is effective, and therefore it is determined that the factor causing the open circuit is the poor state of the probe. The poor state of the probe includes accelerated oxidation of the needle tip, dulling of the needle tip, and the like.

[0115] S608: Modify the cleaning parameter, and test the wafer under test until the absolute value of the voltage value is less than the first threshold value.

[0116] Since cleaning the probe online is effective, the cleaning parameter can be further modified, and the wafer under test is tested, and the process is repeated until the absolute value of the voltage value of the diode obtained by the test is less than the first threshold value, that is, the open circuit caused by the probe is eliminated.

[0117] The cleaning parameter can be a cleaning frequency, and specifically, the state of the probe can be improved by increasing the cleaning frequency.

[0118] It should be noted that when the cleaning frequency is too large, it will have a certain impact on the probe card, so the cleaning frequency needs to be increased according to the actual situation.

[0119] S609: If the test is abnormal when the spring needle is tested based on the cleaned spring needle, or the absolute value of the voltage value of the diode obtained by testing the wafer to be tested based on the cleaned probe does not change, and the difference between the first threshold value, it is determined whether there is a probe card spare part.

[0120] After the spring needle is cleaned, the test is still abnormal, or after the probe is cleaned online, the test is still abnormal, at this time, it can be determined whether it is caused by the open circuit of the circuit board in the probe card. Therefore, it can be determined whether there is a probe card spare part to replace the original probe card. If there is no probe card spare part, step S610 is performed; if there is a probe card spare part, steps S611-S613 are performed.

[0121] S610: If there is no, repair the probe card.

[0122] S611: If there is, replace the probe card with the probe card spare part, and test the wafer to be tested based on the probe card spare part.

[0123] S612: If the test is normal, it is determined that the factor causing the open circuit is the probe card.

[0124] Since the probe card spare part is used for testing, the original probe card is used for testing, and the original probe card is used for testing, it can be determined that the factor causing the open circuit is the probe card. At this time, the probe card spare part can be used for subsequent testing.

[0125] S613: If the test is abnormal, it is determined that the factor causing the open circuit is the tester.

[0126] Since the probe card spare part and the original probe card are both tested abnormally, and the abnormal type is consistent, that is, the problem is consistent, the probability of the tester causing the open circuit is large, at this time, the tester can be repaired and verified.

[0127] In summary, when the abnormal type is an open circuit, it can be determined whether the fixed pins of different wafers cause the test abnormality in the multiple test processes. If the abnormality is caused by the fixed pins of different wafers, the depth of the probe is increased to determine whether the open circuit is caused by the short probe. If the open circuit is not caused by the short probe, it is further determined whether the open circuit is caused by the contamination of the spring needle. If the test abnormality in the multiple test processes is not caused by the fixed pins of different wafers, the probe is cleaned online to determine whether the open circuit is caused by the probe. If the open circuit is not caused by the spring needle and the probe, it is further determined whether the open circuit is caused by the circuit board in the probe card or the test machine. The factors causing the open circuit can be quickly and accurately determined, and the problem can be solved in time, which is beneficial to improve the abnormality determination efficiency and the test efficiency.

[0128] Figure 7 A schematic diagram of a wafer test abnormality determination device provided by an embodiment of the present application is shown in FIG. 7. Figure 7 As shown in FIG. 7, the wafer test abnormality determination device 700 provided by an embodiment of the present application can include a test module 701, an acquisition module 702, and a processing module 703.

[0129] The test module 701 is configured to test a wafer to be tested.

[0130] The acquisition module 702 is configured to acquire test data.

[0131] The processing module 703 is configured to, if the test is abnormal, determine whether the abnormal type is an open circuit or a short circuit according to the test data.

[0132] The processing module 703 is further configured to, if not, generate a wafer map based on the test data, and determine whether the abnormal type is a false death according to the test data and the wafer map.

[0133] The processing module 703 is further configured to determine a factor causing the test abnormality according to the determined abnormal type.

[0134] The device of the embodiment can be used to execute the method embodiments shown in the above, and has similar implementation principles and technical effects, which will not be described herein again.

[0135] Figure 8 A schematic diagram of a wafer test abnormality determination device provided by an embodiment of the present application is shown in FIG. 7. Figure 8 As shown in FIG. 7, the wafer test abnormality determination device 700 provided by an embodiment of the present application can include a test module 701, an acquisition module 702, and a processing module 703.

[0136] In the specific implementation process, the memory 802 stores codes, and the processor 801 runs the codes stored in the memory 802 to execute the method of the above method embodiments.

[0137] The specific implementation process of the processor 801 can refer to the method embodiments described above, which have similar implementation principles and technical effects, and details are not described here.

[0138] In the above Figure 8 In the embodiment shown, it should be understood that the processor 801 can be a central processing unit (CPU), and can also be other general-purpose processors, digital signal processors (DSP), application specific integrated circuits (ASIC), etc. The general-purpose processor can be a microprocessor or any conventional processor. The steps of the method disclosed in combination with the application can be directly embodied as hardware processor execution or combined with hardware and software modules in the processor for execution.

[0139] The memory 802 can include a high-speed RAM memory, and can also include a non-volatile storage NVM.

[0140] The bus 803 can be an industry standard architecture (ISA) bus, a peripheral component interconnect (PCI) bus, or an extended industry standard architecture (EISA) bus, etc. The bus 803 can be divided into an address bus, a data bus, a control bus, etc. For ease of representation, the bus 803 in the drawings of the present application does not limit to only one bus or one type of bus.

[0141] The embodiment of the present application provides a computer readable storage medium, and the computer readable storage medium stores computer execution instructions. When the computer execution instructions are executed by a processor, a method for implementing the method embodiments described above is used.

[0142] The computer readable storage medium described above can be implemented by any type of volatile or non-volatile storage device or a combination thereof, such as static random access memory (SRAM), electrically erasable programmable read-only memory (EEPROM), erasable programmable read-only memory (EPROM), programmable read-only memory (PROM), read-only memory (ROM), flash memory or optical disc. The readable storage medium can be any available medium that can be accessed by a general-purpose or special-purpose computer.

[0143] An example readable storage medium is coupled to the processor such that the processor can read information from the readable storage medium and the readable storage medium can write information to the processor. Of course, the readable storage medium can be a part of the processor. Consistent with the teachings of this disclosure, a processor can be a means for writing data to a storage medium and a means for reading data from a storage medium. Consistent with the teachings of this disclosure, a storage medium can be a means for storing information associated with a processor or a means for storing information for use by a processor.

[0144] An embodiment of the present application provides a computer program product, comprising a computer program, wherein the computer program is executed by a processor to implement the method provided by any of the embodiments of the present application.

[0145] Other embodiments of the application will be apparent to those skilled in the art from consideration of the specification and practice of the application disclosed herein. It is intended that the specification and examples be considered as exemplary only, with the true scope and spirit of the application being indicated by the following claims.

[0146] It is to be understood that the application is not limited to the precise details of construction and the exemplary embodiments described above and illustrated in the drawings. The scope of the application is to be determined by the terms of the following claims.

Claims

1. A method for determining wafer testing anomalies, characterized in that, include: Test the wafer under test and obtain test data; If the test is abnormal, determine whether the abnormality type is open circuit or short circuit based on the test data; If not, generate a wafer map based on the test data, and determine whether the anomaly type is a mistaken slaughter based on the test data and the wafer map; Based on the identified anomaly type, determine the factors that caused the test anomaly.

2. The method according to claim 1, characterized in that, The step of determining whether the anomaly type is an open circuit or a short circuit based on the test data includes: The test data is analyzed to obtain the voltage value of the diode in the wafer under test; If the absolute value of the voltage is higher than the first threshold, the abnormality type is determined to be open circuit; If the absolute value of the voltage is lower than the second threshold, and the second threshold is less than the first threshold, the abnormality type is determined to be a short circuit.

3. The method according to claim 1, characterized in that, The process of determining the factors leading to the test anomaly based on the determined anomaly type includes: If the anomaly type is accidental slaughter, control the imaging device to acquire an image including the probe; Determine whether the probe is contaminated based on the image; If the probe is dirty, the probe is cleaned, and the wafer to be tested is tested based on the cleaned probe. If the test is normal, the cause of the accidental slaughter is determined to be dirt on the probe.

4. The method according to claim 3, characterized in that, The method further includes: If the probe is free of dirt, determine the position of the probe; The position offset of the probe is determined based on the probe's position and its standard position. If the position offset of the probe is greater than a preset offset threshold, the position of the probe is adjusted, and the wafer under test is tested based on the adjusted probe. If the test is normal, the factor causing the false kill is determined to be the positional offset of the probe.

5. The method according to claim 4, characterized in that, The method further includes: If the position offset of the probe is less than the offset threshold, determine whether the chip in a fixed position is causing the test abnormality during multiple tests. If so, the probe card is repaired, and the wafer to be tested is tested based on the repaired probe card. If the test is normal, the probe card is determined to be the factor causing the false test. If not, test the wafer under test in the same test environment. If the test is normal, the factor causing the false test is determined to be the test machine.

6. The method according to claim 1, characterized in that, The process of determining the factors leading to the test anomaly based on the determined anomaly type includes: If the anomaly type is a short circuit, the control probe is separated from the wafer under test, and the wafer under test is then tested. If the test is normal, the cause of the short circuit is determined to be the probe card; If the test fails, remove the probe card and test the wafer under test. If the test is normal, the cause of the short circuit is determined to be the testing machine.

7. The method according to claim 2, characterized in that, The process of determining the factors leading to the test anomaly based on the determined anomaly type includes: If the abnormality type is open circuit, determine whether the abnormality is caused by a fixed pin on a different wafer during multiple tests. If there are fixed pins, increase the probe depth to test the wafer under test based on the current probe. If the difference between the absolute value of the diode voltage obtained by the test and the first threshold decreases, it is determined that the factor causing the open circuit is the probe penetration depth. The probe penetration depth is increased, and the wafer under test is tested until the absolute value of the voltage is less than the first threshold. If the absolute value of the diode voltage obtained by the test is different from the first threshold, the spring pin is cleaned, and the test is performed on the wafer under test based on the cleaned spring pin. If the test is normal, the spring pin is identified as the cause of the open circuit.

8. The method according to claim 7, characterized in that, The method further includes: If there are no fixed pins, the probes are cleaned online, and the wafer under test is tested based on the cleaned probes; If the difference between the absolute value of the diode voltage obtained by the test and the first threshold decreases, the probe is determined to be the factor causing the open circuit. Modify the needle clearing parameters and test the wafer under test until the absolute value of the voltage is less than the first threshold.

9. The method according to claim 8, characterized in that, The method further includes: If an abnormality occurs when testing the wafer under test based on the cleaned spring, or if the absolute value of the diode voltage obtained by testing the wafer under test based on the cleaned probe remains unchanged compared with the first threshold, it is determined whether there is a spare probe card. If not, inspect the probe card; If present, the probe card is replaced using the probe card spare, and the wafer to be tested is tested based on the probe card spare; If the test is normal, the probe card is identified as the cause of the open circuit. If the test fails, the test machine is identified as the cause of the open circuit.

10. A device for determining wafer testing anomalies, comprising: A processor and a memory, wherein code is stored in the memory, and the processor executes the code stored in the memory to perform the method as described in any one of claims 1-9.

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