Uci receiver end skew calibration method, device and chip

Abstract

The present disclosure relates to a UCIe receiving end skew calibration method, device and chip, the method comprising: determining minimum phase interpolation and maximum phase interpolation of a clock signal in the case that a UCIe receiving end correctly receives data from a UCIe sending end based on preset minimum skew value and preset maximum skew value of data link skew coding of the UCIe receiving end; obtaining skew calibration value of the data link skew coding of the UCIe receiving end in the case that the clock signal adopts optimal phase interpolation according to the preset minimum skew value, the preset maximum skew value, the minimum phase interpolation, the maximum phase interpolation and the optimal phase interpolation of the clock signal. The present disclosure helps to solve the problem that the real optimal line delay point on the UCIe receiving end side is ignored due to the nonlinearity between the data link skew coding and the line delay, and helps to improve the robustness of data transmission.

Description

Technical Field

[0001] This disclosure relates to the field of chip technology, and in particular to a UCIe receiver skew calibration method, apparatus, electronic device, computer-readable storage medium, and chip. Background Technology

[0002] UCIe (Universal Chiplet Interconnect Express) is an open and unified interconnect protocol for chiplets. Its purpose is to enable high-speed, low-latency, and high-bandwidth interconnect communication between chips manufactured by different manufacturers and using different processes within the same package, thereby improving system performance and reducing power consumption and cost.

[0003] UCIe uses multiple parallel data lanes for high-speed data transmission between chips. Due to differences in packaging, wiring length, or process variations, slight differences in data arrival times on different data lanes are inevitable. This difference is called skew, and skew can occur at the data transmitter, data receiver, and other points. To ensure that the receiver can correctly sample the data, these skews must be calibrated; this process is called deskew. Summary of the Invention

[0004] In view of this, this disclosure provides a UCIe receiver skew calibration method, apparatus, electronic device, computer-readable storage medium, and chip to help solve the problem that the true optimal line delay point on the UCIe receiver side is erroneously ignored due to the nonlinearity between data link skew coding and line delay, thereby helping to improve the robustness of data transmission.

[0005] The technical solution disclosed herein is implemented as follows:

[0006] According to one aspect of the embodiments of this disclosure, a UCIe receiver skew calibration method is provided, comprising:

[0007] Based on the preset minimum skew value and preset maximum skew value of the data link skew coding at the UCIe receiver, the minimum phase interpolation and maximum phase interpolation of the clock signal are determined when the UCIe receiver correctly receives data from the UCIe transmitter.

[0008] Based on the preset minimum skew value, the preset maximum skew value, the minimum phase interpolation, the maximum phase interpolation, and the optimal phase interpolation of the clock signal, the skew calibration value of the data link skew coding of the UCIe receiver is obtained when the clock signal adopts the optimal phase interpolation.

[0009] In one possible implementation, determining the minimum and maximum phase interpolation of the clock signal when the UCIe receiver correctly receives data from the UCIe transmitter, based on preset minimum and maximum skew values ​​respectively determined by the data link skew coding at the UCIe receiver, includes:

[0010] Based on the preset minimum skew value of the data link skew coding of the UCIe receiver, the minimum phase interpolation of the clock signal is determined when the UCIe receiver correctly receives data from the UCIe transmitter.

[0011] Based on the preset maximum skew value of the data link skew coding of the UCIe receiver, the maximum phase interpolation of the clock signal is determined when the UCIe receiver correctly receives data from the UCIe transmitter.

[0012] In one possible implementation, determining the minimum phase interpolation of the clock signal when the UCIe receiver correctly receives data from the UCIe transmitter, based on the preset minimum skew value of the data link skew coding of the UCIe receiver, includes:

[0013] The UCIe receiver sets the data link skew coding to the preset minimum skew value;

[0014] The UCIe receiver initiates a first phase interpolation eye diagram scan based on the clock signal to the UCIe transmitter.

[0015] During the first phase interpolation eye diagram scan, the UCIe transmitter sends test data to the UCIe receiver at each phase interpolation stage of the scan.

[0016] The UCIe receiver receives the test data based on the preset minimum skew value;

[0017] The minimum phase interpolation value is determined based on the test data received by the UCIe receiver and the phase interpolation value corresponding to the test data.

[0018] In one possible implementation, determining the minimum phase interpolation value based on the test data received by the UCIe receiver and the phase interpolation value corresponding to the test data includes:

[0019] The UCIe receiver performs bit error rate analysis on the received test data to obtain the bit error rate, and determines whether the UCIe receiver has correctly received data from the UCIe transmitter based on the bit error rate and a preset bit error rate threshold.

[0020] The UCIe receiver determines the minimum phase interpolation value based on the range of phase interpolation values ​​during the first phase interpolation eye diagram scanning process corresponding to the correctly received data.

[0021] In one possible implementation, determining the minimum phase interpolation value based on the test data received by the UCIe receiver and the phase interpolation value corresponding to the test data includes:

[0022] The UCIe receiver performs bit error rate analysis on the received test data to obtain the bit error rate, and then sends the bit error rate to the UCIe transmitter.

[0023] The UCIe transmitter determines whether the UCIe receiver has correctly received data from the UCIe transmitter based on the bit error rate and a preset bit error rate threshold.

[0024] The UCIe transmitter sends the confirmation result of the UCIe receiver correctly receiving the data to the UCIe receiver.

[0025] The UCIe receiver determines the minimum phase interpolation value based on the range of phase interpolation values ​​during the first phase interpolation eye diagram scanning process corresponding to the correctly received data.

[0026] In one possible implementation, determining the minimum phase interpolation value based on the range of phase interpolation values ​​during the first phase interpolation eye diagram scan corresponding to the correctly received data includes:

[0027] The average of the two boundary values ​​of the phase interpolation range in the first phase interpolation eye diagram scanning process corresponding to the correctly received data is determined as the minimum phase interpolation.

[0028] In one possible implementation, determining the maximum phase interpolation of the clock signal when the UCIe receiver correctly receives data from the UCIe transmitter, based on the preset maximum skew value of the data link skew coding of the UCIe receiver, includes:

[0029] The UCIe receiver sets the data link skew coding to the preset maximum skew value;

[0030] The UCIe receiver initiates a second phase interpolation eye diagram scan based on the clock signal to the UCIe transmitter;

[0031] During the second phase interpolation eye diagram scan, the UCIe transmitter sends test data to the UCIe receiver at each phase interpolation stage of the scan.

[0032] The UCIe receiver receives the test data based on the preset maximum skew value;

[0033] The maximum phase interpolation value is determined based on the test data received by the UCIe receiver and the phase interpolation value corresponding to the test data.

[0034] In one possible implementation, determining the maximum phase interpolation value based on the test data received by the UCIe receiver and the phase interpolation value corresponding to the test data includes:

[0035] The UCIe receiver performs bit error rate analysis on the received test data to obtain the bit error rate, and determines whether the UCIe receiver has correctly received data from the UCIe transmitter based on the bit error rate and a preset bit error rate threshold.

[0036] The UCIe receiver determines the maximum phase interpolation value based on the range of phase interpolation values ​​during the second phase interpolation eye diagram scanning process corresponding to the correctly received data.

[0037] In one possible implementation, determining the maximum phase interpolation value based on the test data received by the UCIe receiver and the phase interpolation value corresponding to the test data includes:

[0038] The UCIe receiver performs bit error rate analysis on the received test data to obtain the bit error rate, and then sends the bit error rate to the UCIe transmitter.

[0039] The UCIe transmitter determines whether the UCIe receiver has correctly received data from the UCIe transmitter based on the bit error rate and a preset bit error rate threshold.

[0040] The UCIe transmitter sends the confirmation result of the UCIe receiver correctly receiving the data to the UCIe receiver.

[0041] The UCIe receiver determines the maximum phase interpolation value based on the range of phase interpolation values ​​during the second phase interpolation eye diagram scanning process corresponding to the correctly received data.

[0042] In one possible implementation, determining the maximum phase interpolation value based on the range of phase interpolation values ​​during the second phase interpolation eye diagram scan corresponding to the correctly received data includes:

[0043] The average of the two boundary values ​​of the phase interpolation range during the second phase interpolation eye diagram scanning process corresponding to the correctly received data is determined as the maximum phase interpolation.

[0044] In one possible implementation, obtaining the skew calibration value of the data link skew coding at the UCIe receiver when the clock signal uses the optimal phase interpolation, based on the preset minimum skew value, the preset maximum skew value, the minimum phase interpolation, the maximum phase interpolation, and the optimal phase interpolation of the clock signal, includes:

[0045] The difference between the preset maximum skew value and the preset minimum skew value is used as the skew interval length parameter;

[0046] The difference between the maximum phase interpolation and the minimum phase interpolation is used as the phase interpolation interval length parameter;

[0047] The ratio of the skew interval length parameter to the phase interpolation interval length parameter is used as a proportionality coefficient;

[0048] The difference between the maximum phase interpolation and the optimal phase interpolation is used as the first phase interpolation reference length parameter;

[0049] The product of the first phase interpolation reference length parameter and the scaling factor is used as the first skew value adjustment length parameter;

[0050] The difference between the preset maximum skew value and the first skew value adjustment length parameter is determined as the skew calibration value.

[0051] In one possible implementation, obtaining the skew calibration value of the data link skew coding at the UCIe receiver when the clock signal uses the optimal phase interpolation, based on the preset minimum skew value, the preset maximum skew value, the minimum phase interpolation, the maximum phase interpolation, and the optimal phase interpolation of the clock signal, includes:

[0052] The difference between the preset maximum skew value and the preset minimum skew value is used as the skew interval length parameter;

[0053] The difference between the maximum phase interpolation and the minimum phase interpolation is used as the phase interpolation interval length parameter;

[0054] The ratio of the skew interval length parameter to the phase interpolation interval length parameter is used as a proportionality coefficient;

[0055] The difference between the optimal phase interpolation and the minimum phase interpolation is used as the second phase interpolation reference length parameter;

[0056] The product of the second phase interpolation reference length parameter and the scaling factor is used as the second skew value adjustment length parameter;

[0057] The sum of the preset minimum skew value and the second skew value adjustment length parameter is determined as the skew calibration value.

[0058] According to another aspect of the embodiments of this disclosure, a UCIe receiver skew calibration device is provided, comprising:

[0059] The phase interpolation acquisition module is used to determine the minimum phase interpolation and maximum phase interpolation of the clock signal when the UCIe receiver correctly receives data from the UCIe transmitter, based on the preset minimum skew value and preset maximum skew value of the data link skew coding of the UCIe receiver, respectively.

[0060] The skew calibration value acquisition module is used to obtain the skew calibration value of the data link skew encoding of the UCIe receiver when the clock signal adopts the optimal phase interpolation, based on the preset minimum skew value, the preset maximum skew value, the minimum phase interpolation, the maximum phase interpolation, and the optimal phase interpolation of the clock signal.

[0061] In one possible implementation, the phase interpolation acquisition module includes:

[0062] The skew parameter configuration module, located at the UCIe receiver, is used to configure the skew parameter to a preset minimum skew value or a preset maximum skew value.

[0063] A phase interpolation acquisition submodule is used to determine, based on the skew parameter of the data link skew coding of the UCIe receiver, the phase interpolation parameter of the clock signal when the UCIe receiver correctly receives data from the UCIe transmitter. The phase interpolation parameter is associated with the skew parameter. When the skew parameter is a preset minimum skew value, the phase interpolation parameter is the minimum phase interpolation. When the skew parameter is a preset maximum skew value, the phase interpolation parameter is the maximum phase interpolation.

[0064] In one possible implementation, the phase interpolation acquisition submodule includes:

[0065] An eye diagram scan initiation module, located at the UCIe receiver, is used to initiate a phase interpolation eye diagram scan based on the clock signal to the UCIe transmitter.

[0066] The eye diagram scanning and data transmission module, located at the UCIe transmitter, is used to perform phase interpolation eye diagram scanning and, during the phase interpolation eye diagram scanning process, sends test data to the UCIe receiver at each phase interpolation stage of the scan.

[0067] The data receiving module, located at the UCIe receiver, is used to receive the test data based on the skew parameter;

[0068] The phase interpolation determination module is used to determine the phase interpolation parameter associated with the skew parameter based on the test data received by the UCIe receiver and the phase interpolation corresponding to the test data.

[0069] In one possible implementation, the phase interpolation determination module includes:

[0070] The first bit error rate analysis unit, located at the UCIe receiver, is used to perform bit error rate analysis on the received test data to obtain the bit error rate, and determine whether the UCIe receiver has correctly received data from the UCIe transmitter based on the bit error rate and a preset bit error rate threshold.

[0071] The first phase interpolation determination unit, located at the UCIe receiver, is used to determine the phase interpolation parameters based on the range of phase interpolation during the phase interpolation eye diagram scanning process corresponding to the correctly received data.

[0072] In one possible implementation, the phase interpolation determination module includes:

[0073] The second bit error rate analysis unit, located at the UCIe receiver, is used to perform bit error rate analysis on the received test data to obtain the bit error rate, and send the bit error rate to the UCIe transmitter.

[0074] The data correct reception judgment unit is located at the UCIe transmitter and is used to determine whether the UCIe receiver has correctly received data from the UCIe transmitter based on the bit error rate and a preset bit error rate threshold.

[0075] The data correct reception result sending unit, located at the UCIe transmitting end, is used to send the determination result of the UCIe receiving end correctly receiving the data to the UCIe receiving end.

[0076] The second phase interpolation determination unit, located at the UCIe receiver, is used to determine the phase interpolation parameters based on the range of phase interpolation during the phase interpolation eye diagram scanning process corresponding to the correctly received data.

[0077] In one possible implementation, the second phase interpolation determination unit is further configured to determine the average of two boundary values ​​of the phase interpolation range during the phase interpolation eye diagram scanning process corresponding to the correctly received data as the phase interpolation parameter.

[0078] In one possible implementation, the skew calibration value acquisition module is further configured to perform:

[0079] The difference between the preset maximum skew value and the preset minimum skew value is used as the skew interval length parameter;

[0080] The difference between the maximum phase interpolation and the minimum phase interpolation is used as the phase interpolation interval length parameter;

[0081] The ratio of the skew interval length parameter to the phase interpolation interval length parameter is used as a proportionality coefficient;

[0082] The difference between the maximum phase interpolation and the optimal phase interpolation is used as the first phase interpolation reference length parameter;

[0083] The product of the first phase interpolation reference length parameter and the scaling factor is used as the first skew value adjustment length parameter;

[0084] The difference between the preset maximum skew value and the first skew value adjustment length parameter is determined as the skew calibration value.

[0085] In one possible implementation, the skew calibration value acquisition module is further configured to perform:

[0086] The difference between the preset maximum skew value and the preset minimum skew value is used as the skew interval length parameter;

[0087] The difference between the maximum phase interpolation and the minimum phase interpolation is used as the phase interpolation interval length parameter;

[0088] The ratio of the skew interval length parameter to the phase interpolation interval length parameter is used as a proportionality coefficient;

[0089] The difference between the optimal phase interpolation and the minimum phase interpolation is used as the second phase interpolation reference length parameter;

[0090] The product of the second phase interpolation reference length parameter and the scaling factor is used as the second skew value adjustment length parameter;

[0091] The sum of the preset minimum skew value and the second skew value adjustment length parameter is determined as the skew calibration value.

[0092] According to another aspect of the embodiments of this disclosure, an electronic device is provided, comprising:

[0093] processor;

[0094] Memory for storing the executable instructions of the processor;

[0095] The processor is configured to execute the executable instructions to implement the UCIe receiver skew calibration method as described in any of the preceding claims.

[0096] According to another aspect of the present disclosure, a computer-readable storage medium is provided, which, when at least one instruction in the computer-readable storage medium is executed by a processor of an electronic device, enables the electronic device to implement the UCIe receiver skew calibration method as described in any of the preceding claims.

[0097] According to another aspect of the present disclosure, a chip is provided, including the UCIe receiver skew calibration device as described in any of the preceding claims.

[0098] As can be seen from the above scheme, by adopting the UCIe receiver skew calibration method, apparatus, electronic device, computer-readable storage medium and chip disclosed herein, clock signal phase interpolation scanning is introduced at the UCIe receiver. Based on a two-dimensional scan of data link skew coding and clock signal phase interpolation, a reference phase interpolation of the clock signal, which has already been determined in the UCIe process before the determination of data link skew coding at the UCIe receiver, is introduced. This leads to the optimal data link skew coding of the UCIe receiver corresponding to the optimal phase interpolation. This helps to solve the problem that the true optimal line delay point of the UCIe receiver is erroneously ignored due to the nonlinearity between the data link skew coding and data link delay at the UCIe receiver, and helps to improve the robustness of data transmission.

[0099] The UCIe receiver skew calibration method, apparatus, electronic device, computer-readable storage medium, and chip disclosed herein effectively decouple the nonlinear coupling between data link skew coding and data link delay at the UCIe receiver through joint optimization of two-dimensional parameters. Experiments show that, compared with traditional single-dimensional scanning schemes, the UCIe receiver skew calibration method, apparatus, electronic device, computer-readable storage medium, and chip disclosed herein improve the calibration accuracy of data link skew coding at the UCIe receiver and help reduce the consumption of related computing resources. The UCIe receiver skew calibration method, apparatus, electronic device, computer-readable storage medium, and chip disclosed herein can be widely used in high-speed serial communication, clock data recovery, and other scenarios, helping to improve system timing stability and signal integrity. Attached Figure Description

[0100] Figure 1 This is a schematic diagram illustrating the relationship between data link skew coding and line delay.

[0101] Figure 2 This is a schematic flowchart of a UCIe receiver skew calibration method according to an illustrative embodiment;

[0102] Figure 3 This is a schematic flowchart illustrating the process of determining a minimum phase interpolation value associated with a preset minimum skew value, according to an illustrative embodiment.

[0103] Figure 4 This is a schematic flowchart illustrating a process for determining the minimum phase interpolation according to an illustrative embodiment;

[0104] Figure 5 This is a schematic flowchart illustrating another process for determining the minimum phase interpolation according to an illustrative embodiment;

[0105] Figure 6 This is a schematic diagram illustrating the process of determining the maximum phase interpolation value associated with a preset maximum skew value, according to an illustrative embodiment.

[0106] Figure 7 This is a schematic flowchart illustrating a process for determining the maximum phase interpolation according to an illustrative embodiment;

[0107] Figure 8 This is a schematic flowchart illustrating another process for determining the maximum phase interpolation according to an illustrative embodiment;

[0108] Figure 9 This is a schematic diagram illustrating the linear relationship between the data link skew coding and the phase interpolation of the clock signal at a UCIe receiver, according to an illustrative embodiment.

[0109] Figure 10 This is a schematic diagram of the structure of a UCIe receiver skew calibration device according to an illustrative embodiment;

[0110] Figure 11 This is a schematic diagram of the phase interpolation acquisition module according to an illustrative embodiment;

[0111] Figure 12 This is a schematic diagram of the phase interpolation acquisition submodule according to an illustrative embodiment;

[0112] Figure 13 This is a schematic diagram illustrating one embodiment of a phase interpolation determination module according to an exemplary embodiment;

[0113] Figure 14 This is a schematic diagram of another embodiment of the phase interpolation determination module shown in one illustrative embodiment;

[0114] Figure 15 This is a block diagram of the application scenario structure of the PCIE receiver using the UCIe receiver skew calibration method and apparatus according to the embodiments of this disclosure;

[0115] Figure 16This is a schematic diagram of the state machine built into the phase interpolation scan control module in this application scenario;

[0116] Figure 17 This is a schematic diagram of the state machine built into the process control module in this application scenario;

[0117] Figure 18 This is a schematic diagram of the structure of an electronic device provided in an embodiment of this disclosure. Detailed Implementation

[0118] To make the objectives, technical solutions, and advantages of this disclosure clearer, the following detailed description is provided with reference to the accompanying drawings and embodiments.

[0119] It should be noted that the terms "first," "second," etc., in the specification, claims, and drawings of this disclosure are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence.

[0120] As used in the specification and claims of this disclosure, “coupled (or connected)” may refer to any direct or indirect means of connection. For example, if a first device is coupled (or connected) to a second device, it should be interpreted as the first device being directly connected to the second device, or the first device being indirectly connected to the second device through other devices or some means of connection.

[0121] In relevant UCIe technologies, the deskewing process at the UCIe receiver involves an eye diagram scan initiated by the UCIe receiver. This scan scans the skew codes of each data channel on the data link between the UCIe transmitter and receiver. Each data channel is scanned independently. By scanning, two boundary values ​​of the skew code for each data channel that allow for normal data transmission are found. The average of these two boundary values ​​is taken as the optimal skew code for the data channel. The skew code reflects the phase relationship between the data signal and the clock signal. Changing the skew code while keeping the clock phase constant is equivalent to changing the phase of the data signal relative to the clock signal.

[0122] Figure 1 This is a schematic diagram illustrating the relationship between data link skew coding and line delay, such as... Figure 1 As shown, there is a significant non-linearity between data link skew coding and line delay. This is because related techniques determine the optimal value of the data link skew coding by scanning to find the left and right boundary values ​​of the data link skew coding that allow normal data transmission, and then taking the average of the left and right boundary values ​​as the optimal value. This involves combining... Figure 1As shown, the left boundary value corresponds to the first line delay 'a', and the right boundary value corresponds to the second line delay 'b'. The first line delay 'a' is less than the second line delay 'b'. Because there is a large non-linearity between data link skew coding and line delay, the line delay corresponding to the optimal value of data link skew coding is not the midpoint between the first line delay 'a' and the second line delay 'b' corresponding to the left and right boundary values, respectively. The truly optimal line delay should be the midpoint between the first line delay 'a' and the second line delay 'b'. Therefore, in related technologies, simply taking the average of the two boundary values ​​will lead to the true optimal line delay point being incorrectly ignored, thereby reducing the robustness of data transmission.

[0123] Although there is a large nonlinearity between data link skew coding and line delay, in-depth research has revealed that there is a good linearity between the phase interpolation of the clock signal and the data link skew coding of the UCIe receiver. Thus, a more ideal data link skew coding for the UCIe receiver can be determined through this good linearity relationship. In view of this, embodiments of this disclosure provide a UCIe receiver skew calibration method, apparatus, and chip. A clock signal phase interpolation (PI) scan is introduced at the UCIe receiver. Based on a two-dimensional scan of the data link skew coding and the clock signal phase interpolation, a reference phase interpolation of the clock signal (referred to herein as the optimal phase interpolation) that was determined in the UCIe process before the determination of the data link skew coding at the UCIe receiver is also introduced. This yields the optimal data link skew coding at the UCIe receiver corresponding to the optimal phase interpolation (referred to herein as the skew calibration value). This helps to solve the problem that the true optimal line delay point at the UCIe receiver is incorrectly ignored due to the nonlinearity between the data link skew coding and data link delay at the UCIe receiver, thereby improving the robustness of data transmission.

[0124] Figure 2 This is a schematic flowchart illustrating a UCIe receiver skew calibration method according to an illustrative embodiment, as shown below. Figure 2 As shown, the UCIe receiver skew calibration method mainly includes the following steps 201 to 202.

[0125] Step 201: Based on the preset minimum skew value and preset maximum skew value of the data link skew coding at the UCIe receiver, determine the minimum phase interpolation and maximum phase interpolation of the clock signal when the UCIe receiver correctly receives data from the UCIe transmitter.

[0126] Step 202: Based on the preset minimum skew value, preset maximum skew value, minimum phase interpolation, maximum phase interpolation, and the optimal phase interpolation of the clock signal, obtain the skew calibration value of the data link skew coding of the UCIe receiver when the clock signal uses the optimal phase interpolation.

[0127] In the illustrative embodiment, the preset minimum skew value and the preset maximum skew value can be extreme values ​​set by the system, such as the system-on-a-chip of the chip where the UCIe receiver is located. If the data link skew coding is set to be less than the preset minimum skew value or greater than the preset maximum skew value, it can be considered that the UCIe receiver cannot correctly receive data from the UCIe transmitter. Alternatively, the preset minimum skew value and the preset maximum skew value are two extreme values ​​of the data link skew coding that can ensure the UCIe receiver correctly receives data.

[0128] Corresponding to the preset minimum skew value and the preset maximum skew value, there exist phase values ​​(or phase interpolations) of clock signals that enable the UCIe receiver to correctly receive data. Research has found that there is a good linearity between the phase interpolation of the clock signal of the UCIe receiver and the data link skew coding of the UCIe receiver. Therefore, in this embodiment of the present disclosure, both in step 201 and step 202, this linearity between the phase interpolation of the clock signal and the data link skew coding (skew value) is used to determine the final skew calibration value, as detailed in the following description.

[0129] In the illustrative embodiment, step 201 can obtain the minimum phase interpolation and maximum phase interpolation of the corresponding clock signals for the preset minimum skew value and preset maximum skew value, respectively. Based on this, step 201 can be divided into two steps, including:

[0130] Step 2011: Based on the preset minimum skew value of the data link skew coding at the UCIe receiver, determine the minimum phase interpolation of the clock signal when the UCIe receiver correctly receives data from the UCIe transmitter.

[0131] Step 2012: Based on the preset maximum skew value of the data link skew coding at the UCIe receiver, determine the maximum phase interpolation value of the clock signal when the UCIe receiver correctly receives data from the UCIe transmitter.

[0132] There is no necessary sequential order between steps 2011 and 2012. Step 2011 can be executed first and then step 2012, or step 2012 can be executed first and then step 2011. Steps 2011 and 2012 will be explained in detail below.

[0133] Figure 3This is a schematic flowchart illustrating the process of determining the minimum phase interpolation associated with a preset minimum skew value, according to an illustrative embodiment. Figure 3 As shown, the specific execution process of step 2011 may include the following steps 301 to 305.

[0134] Step 301: The UCIe receiver sets the data link skew coding to a preset minimum skew value;

[0135] Step 302: The UCIe receiver initiates a first phase interpolation eye diagram scan based on the clock signal to the UCIe transmitter;

[0136] Step 303: During the first phase interpolation eye diagram scan, the UCIe transmitter sends test data to the UCIe receiver in each phase interpolation stage of the scan.

[0137] Step 304: The UCIe receiver receives test data based on a preset minimum skew value;

[0138] Step 305: Determine the minimum phase interpolation value based on the test data received by the UCIe receiver and the phase interpolation value corresponding to the test data.

[0139] Figure 4 This is a schematic flowchart illustrating a process for determining the minimum phase interpolation according to an illustrative embodiment. In related technologies, determining whether a UCIe transmitter can correctly receive test data is achieved through bit error rate analysis. Combined with related technologies, such as... Figure 4 As shown, in an illustrative embodiment, step 305 may include steps 401 to 402 as follows.

[0140] Step 401: The UCIe receiver performs bit error rate analysis on the received test data to obtain the bit error rate, and determines whether the UCIe receiver has correctly received data from the UCIe transmitter based on the bit error rate and the preset bit error rate threshold.

[0141] Step 402: The UCIe receiver determines the minimum phase interpolation value based on the range of phase interpolation values ​​during the first phase interpolation eye diagram scanning process corresponding to the correctly received data.

[0142] The processes described in steps 401 to 402 are implemented in the UCIe receiver and do not require the participation of the UCIe transmitter.

[0143] Figure 5 This is a flowchart illustrating another process for determining the minimum phase interpolation according to an illustrative embodiment. Based on the relevant UCIe protocol, determining whether the UCIe receiver can correctly receive data from the UCIe transmitter can also be implemented by the UCIe transmitter. Therefore, as... Figure 5 As shown, in an illustrative embodiment, step 305 may include steps 501 to 504.

[0144] Step 501: The UCIe receiver performs bit error rate analysis on the received test data to obtain the bit error rate, and sends the bit error rate to the UCIe transmitter.

[0145] Step 502: The UCIe transmitter determines whether the UCIe receiver has correctly received data from the UCIe transmitter based on the bit error rate and the preset bit error rate threshold.

[0146] Step 503: The UCIe transmitter sends the confirmation result of the UCIe receiver correctly receiving the data to the UCIe receiver.

[0147] Step 504: The UCIe receiver determines the minimum phase interpolation value based on the range of phase interpolation values ​​during the first phase interpolation eye diagram scanning process corresponding to the correctly received data.

[0148] During eye diagram scanning, there may be situations where the UCIe receiver can correctly receive test data under certain phase interpolation conditions, while it cannot correctly receive test data under other phase interpolation conditions. The various phase interpolations corresponding to the correct test data reception by the UCIe receiver form a continuous phase interval. To ensure the stability of the UCIe receiver's correct data reception, prevent uncertainties caused by clock signal phase jitter, and improve robustness, in the illustrative embodiment, steps 402 and 504 may specifically include:

[0149] The average of the two boundary values ​​of the phase interpolation range during the first phase interpolation eye diagram scan process corresponding to the correctly received data is determined as the minimum phase interpolation.

[0150] Figure 6 This is a schematic flowchart illustrating the process of determining the maximum phase interpolation value associated with a preset maximum skew value, according to an illustrative embodiment. Figure 6 As shown, the specific execution process of step 2012 may include the following steps 601 to 605.

[0151] Step 601: The UCIe receiver sets the data link skew coding to a preset maximum skew value;

[0152] Step 602: The UCIe receiver initiates a second phase interpolation eye diagram scan based on the clock signal to the UCIe transmitter;

[0153] Step 603: During the second phase interpolation eye diagram scan, the UCIe transmitter sends test data to the UCIe receiver in each phase interpolation stage of the scan.

[0154] Step 604: The UCIe receiver receives test data based on a preset maximum skew value;

[0155] Step 605: Determine the maximum phase interpolation value based on the test data received by the UCIe receiver and the phase interpolation value corresponding to the test data.

[0156] Figure 7 This is a schematic flowchart illustrating a process for determining the maximum phase interpolation according to an illustrative embodiment, as shown below. Figure 7 As shown, in conjunction with related technologies, in an illustrative embodiment, step 605 may include steps 701 to 702 as follows.

[0157] Step 701: The UCIe receiver performs bit error rate analysis on the received test data to obtain the bit error rate, and determines whether the UCIe receiver has correctly received data from the UCIe transmitter based on the bit error rate and the preset bit error rate threshold.

[0158] Step 702: The UCIe receiver determines the maximum phase interpolation value based on the range of phase interpolation values ​​during the second phase interpolation eye diagram scanning process corresponding to the correctly received data.

[0159] The processes described in steps 701 to 702 are implemented in the UCIe receiver and do not require the participation of the UCIe transmitter.

[0160] Figure 8 This is a schematic flowchart illustrating another process for determining the maximum phase interpolation according to an illustrative embodiment, as shown below. Figure 8 As shown, in conjunction with UCIe-related technologies, in an illustrative embodiment, step 605 may include steps 801 to 804 as follows.

[0161] Step 801: The UCIe receiver performs bit error rate analysis on the received test data to obtain the bit error rate, and sends the bit error rate to the UCIe transmitter.

[0162] Step 802: The UCIe transmitter determines whether the UCIe receiver has correctly received data from the UCIe transmitter based on the bit error rate and the preset bit error rate threshold.

[0163] Step 803: The UCIe transmitter sends the confirmation result of the UCIe receiver correctly receiving the data to the UCIe receiver.

[0164] Step 804: The UCIe receiver determines the maximum phase interpolation value based on the range of phase interpolation during the second phase interpolation eye diagram scanning process corresponding to the correctly received data.

[0165] To ensure the stability of data reception at the UCIe receiver, prevent uncertainties caused by clock signal phase jitter, and improve robustness, steps 702 and 804 may specifically include the following in the illustrative embodiment:

[0166] The average of the two boundary values ​​of the phase interpolation range during the second phase interpolation eye diagram scanning process corresponding to the correctly received data is determined as the maximum phase interpolation.

[0167] Figure 9 This is a schematic diagram illustrating the linear relationship between the data link skew coding and the phase interpolation of the clock signal at a UCIe receiver, according to an illustrative embodiment. Figure 9 As shown, the horizontal axis (x-axis) represents phase interpolation, and the vertical axis (y-axis) represents data link skew coding (also known as skew value). There is a linear relationship between phase interpolation and data link skew coding. Therefore, this embodiment of the present disclosure uses this linear relationship to obtain the skew calibration value of the data link skew coding of the UCIe receiver when the clock signal uses optimal phase interpolation.

[0168] In an illustrative embodiment, step 202 may include:

[0169] The difference between the preset maximum skew value and the preset minimum skew value is used as the skew interval length parameter;

[0170] The difference between the maximum and minimum phase interpolation values ​​is used as the phase interpolation interval length parameter.

[0171] The ratio of the skew interval length parameter to the phase interpolation interval length parameter is used as the scaling factor;

[0172] The difference between the maximum phase interpolation and the optimal phase interpolation is used as the first phase interpolation reference length parameter;

[0173] The product of the first phase interpolation reference length parameter and the scaling factor is used as the first skew value adjustment length parameter;

[0174] The difference between the preset maximum skew value and the first skew value adjustment length parameter is determined as the skew calibration value.

[0175] In the illustrative embodiment, combined with Figure 9 As shown, if implemented using a formula, step 202 may include obtaining the skew calibration value using the following formula:

[0176]

[0177] in,

[0178]

[0179]

[0180] in, For maximum phase interpolation, For minimum phase interpolation, This is the parameter for the length of the phase interpolation interval. To preset the maximum skew value, To preset the minimum skew value, This is the parameter for the length of the skew interval. For optimal phase interpolation, This is the reference length parameter for the first phase interpolation. This is the skew calibration value.

[0181] From the formula:

[0182]

[0183] It can be deduced that:

[0184]

[0185] Therefore, it can be seen from the above formula that:

[0186] This indicates that the difference between the preset maximum skew value and the preset minimum skew value is used as the skew interval length parameter;

[0187] This indicates that the difference between the maximum and minimum phase interpolation values ​​is used as the phase interpolation interval length parameter.

[0188] This represents the ratio of the skew interval length parameter to the phase interpolation interval length parameter, used as a scaling factor.

[0189] This indicates that the difference between the maximum phase interpolation and the optimal phase interpolation is used as the first phase interpolation reference length parameter;

[0190] This indicates that the product of the first phase interpolation reference length parameter and the scaling factor is used as the first skew value adjustment length parameter;

[0191] Therefore, the skew calibration value can be obtained using the above formula. .

[0192] The above scheme is based on the maximum phase interpolation to obtain the skew calibration value. In addition, a scheme based on the minimum phase interpolation to obtain the skew calibration value can also be used.

[0193] In an illustrative embodiment, step 202 may include:

[0194] The difference between the preset maximum skew value and the preset minimum skew value is used as the skew interval length parameter;

[0195] The difference between the maximum and minimum phase interpolation values ​​is used as the phase interpolation interval length parameter.

[0196] The ratio of the skew interval length parameter to the phase interpolation interval length parameter is used as the scaling factor;

[0197] The difference between the optimal phase interpolation and the minimum phase interpolation is used as the reference length parameter for the second phase interpolation.

[0198] The product of the second phase interpolation reference length parameter and the scaling factor is used as the second skew value adjustment length parameter;

[0199] The sum of the preset minimum skew value and the second skew value adjustment length parameter is determined as the skew calibration value.

[0200] In the illustrative embodiment, combined with Figure 9 As shown, if implemented using a formula, step 202 may include obtaining the skew calibration value using the following formula:

[0201]

[0202] From this formula, we can derive:

[0203]

[0204] Therefore, it can be seen from the above formula that:

[0205] This indicates that the difference between the preset maximum skew value and the preset minimum skew value is used as the skew interval length parameter;

[0206] This indicates that the difference between the maximum and minimum phase interpolation values ​​is used as the phase interpolation interval length parameter.

[0207] This represents the ratio of the skew interval length parameter to the phase interpolation interval length parameter, used as a scaling factor.

[0208] This indicates that the difference between the optimal phase interpolation and the minimum phase interpolation is used as the second phase interpolation reference length parameter;

[0209] This indicates that the product of the second phase interpolation reference length parameter and the scaling factor is used as the second skew value adjustment length parameter;

[0210] Therefore, the skew calibration value can be obtained based on the minimum phase interpolation using the above formula. .

[0211] In an illustrative embodiment, the optimal phase interpolation can be obtained from the link training steps of UCIe, such as the link training steps prior to LTSM (Link Training State Machine).

[0212] This disclosure also provides a UCIe receiver skew calibration device, such as Figure 10 As shown, the UCIe receiver skew calibration device includes a phase interpolation acquisition module 1 and a skew calibration value acquisition module 2. The phase interpolation acquisition module 1 is used to determine the minimum and maximum phase interpolation values ​​of the clock signal when the UCIe receiver correctly receives data from the UCIe transmitter, based on preset minimum and maximum skew values ​​of the UCIe receiver's data link skew coding. The skew calibration value acquisition module 2 is used to obtain the skew calibration value of the UCIe receiver's data link skew coding when the clock signal uses the optimal phase interpolation value, based on the preset minimum skew value, preset maximum skew value, minimum phase interpolation value, maximum phase interpolation value, and the optimal phase interpolation value of the clock signal.

[0213] Figure 11 This is a schematic diagram of the phase interpolation acquisition module according to an illustrative embodiment, as shown below. Figure 11 As shown in the illustrative embodiment, the phase interpolation acquisition module 1 includes a skew parameter configuration module 11 and a phase interpolation acquisition submodule 12. The skew parameter configuration module 11, located at the UCIe receiver 100, is used to configure the skew parameter to a preset minimum skew value or a preset maximum skew value. The phase interpolation acquisition submodule 12 is used to determine the phase interpolation parameter of the clock signal when the UCIe receiver 100 correctly receives data from the UCIe transmitter, based on the skew parameter of the data link skew coding of the UCIe receiver 100. The phase interpolation parameter is associated with the skew parameter; when the skew parameter is the preset minimum skew value, the phase interpolation parameter is the minimum phase interpolation; when the skew parameter is the preset maximum skew value, the phase interpolation parameter is the maximum phase interpolation.

[0214] Figure 12 This is a schematic diagram of the phase interpolation acquisition submodule according to an illustrative embodiment, as shown below. Figure 12As shown in the illustrative embodiment, the phase interpolation acquisition submodule 12 includes an eye diagram scan initiation module 121, an eye diagram scan and data transmission module 122, a data receiving module 123, and a phase interpolation determination module 124. The eye diagram scan initiation module 121, located at the UCIe receiver 100, is used to initiate a clock-signal-based phase interpolation eye diagram scan to the UCIe transmitter 200. The eye diagram scan and data transmission module 122, located at the UCIe transmitter 200, is used to perform the phase interpolation eye diagram scan and, during the phase interpolation eye diagram scan, sends test data to the UCIe receiver 100 at each phase interpolation stage. The data receiving module 123, located at the UCIe receiver 100, is used to receive test data based on skew parameters. The phase interpolation determination module 124 is used to determine the phase interpolation parameters associated with the skew parameters based on the test data received by the UCIe receiver 100 and the corresponding phase interpolation values.

[0215] Figure 13 This is a schematic diagram illustrating one embodiment of a phase interpolation determination module, as shown in an illustrative embodiment. Figure 13 As shown in the illustrative embodiment, the phase interpolation determination module 124 includes a first bit error rate analysis unit 1241 and a first phase interpolation determination unit 1242. The first bit error rate analysis unit 1241, located at the UCIe receiver 100, is used to analyze the bit error rate of the received test data to obtain the bit error rate, and determine whether the UCIe receiver 100 has correctly received data from the UCIe transmitter based on the bit error rate and a preset bit error rate threshold. The first phase interpolation determination unit 1242, located at the UCIe receiver 100, is used to determine the phase interpolation parameters based on the range of phase interpolation during the phase interpolation eye diagram scanning process corresponding to the correctly received data.

[0216] Figure 14 This is a schematic diagram of another embodiment of the phase interpolation determination module shown in one illustrative embodiment, as follows: Figure 14As shown in the illustrative embodiment, the phase interpolation determination module 124 includes a second bit error rate analysis unit 1243, a data correct reception judgment unit 1244, a data correct reception result sending unit 1245, and a second phase interpolation determination unit 1246. The second bit error rate analysis unit 1243, located at the UCIe receiver 100, is used to analyze the bit error rate of the received test data to obtain the bit error rate and send the bit error rate to the UCIe transmitter 200. The data correct reception judgment unit 1244, located at the UCIe transmitter 200, is used to determine whether the UCIe receiver 100 has correctly received data from the UCIe transmitter based on the bit error rate and a preset bit error rate threshold. The data correct reception result sending unit 1245, located at the UCIe transmitter 200, is used to send the determination result of the UCIe receiver 100 correctly receiving data to the UCIe receiver 100. The second phase interpolation determination unit 1246, located at the UCIe receiver 100, is used to determine the phase interpolation parameters based on the range of phase interpolation during the phase interpolation eye diagram scanning process corresponding to the correctly received data.

[0217] In an illustrative embodiment, the second phase interpolation determination unit 1246 is further configured to determine the average of the two boundary values ​​of the phase interpolation range during the phase interpolation eye diagram scanning process corresponding to the correctly received data as the phase interpolation parameter.

[0218] In an illustrative embodiment, the skew calibration value acquisition module 2 is further configured to perform:

[0219] The difference between the preset maximum skew value and the preset minimum skew value is used as the skew interval length parameter;

[0220] The difference between the maximum and minimum phase interpolation values ​​is used as the phase interpolation interval length parameter.

[0221] The ratio of the skew interval length parameter to the phase interpolation interval length parameter is used as the scaling factor;

[0222] The difference between the maximum phase interpolation and the optimal phase interpolation is used as the first phase interpolation reference length parameter;

[0223] The product of the first phase interpolation reference length parameter and the scaling factor is used as the first skew value adjustment length parameter;

[0224] The difference between the preset maximum skew value and the first skew value adjustment length parameter is determined as the skew calibration value.

[0225] In an illustrative embodiment, the skew calibration value acquisition module 2 is further configured to perform:

[0226] The difference between the preset maximum skew value and the preset minimum skew value is used as the skew interval length parameter;

[0227] The difference between the maximum and minimum phase interpolation values ​​is used as the phase interpolation interval length parameter.

[0228] The ratio of the skew interval length parameter to the phase interpolation interval length parameter is used as the scaling factor;

[0229] The difference between the optimal phase interpolation and the minimum phase interpolation is used as the reference length parameter for the second phase interpolation.

[0230] The product of the second phase interpolation reference length parameter and the scaling factor is used as the second skew value adjustment length parameter;

[0231] The sum of the preset minimum skew value and the second skew value adjustment length parameter is determined as the skew calibration value.

[0232] Regarding the UCIe receiver skew calibration device in the above embodiments, the specific manner in which each unit performs its operation has been described in detail in the embodiments related to the UCIe receiver skew calibration method, and will not be elaborated here.

[0233] It should be noted that the above embodiments are only examples of the division of the above functional modules. In actual applications, the above functions can be assigned to different functional modules as needed, that is, the internal structure of the device can be divided into different functional modules to complete all or part of the functions described above.

[0234] In the illustrative embodiment, depending on the design, at least one of the following can be implemented as a combination of multiple hardware, firmware, and software components: phase interpolation acquisition module 1, skew parameter configuration module 11, phase interpolation acquisition submodule 12, eye diagram scan initiation module 121, eye diagram scan and data transmission module 122, data reception module 123, phase interpolation determination module 124, first bit error rate analysis unit 1241, first phase interpolation determination unit 1242, second bit error rate analysis unit 1243, data correct reception judgment unit 1244, data correct reception result transmission unit 1245, second phase interpolation determination unit 1246, and skew calibration value acquisition module 2.

[0235] In terms of hardware, at least one of the following modules can be implemented on an integrated circuit: phase interpolation acquisition module 1, skew parameter configuration module 11, phase interpolation acquisition submodule 12, eye diagram scan initiation module 121, eye diagram scan and data transmission module 122, data reception module 123, phase interpolation determination module 124, first bit error rate analysis unit 1241, first phase interpolation determination unit 1242, second bit error rate analysis unit 1243, data correct reception judgment unit 1244, data correct reception result transmission unit 1245, second phase interpolation determination unit 1246, and skew calibration value acquisition module 2. The logic circuits, such as the phase interpolation acquisition module 1, the skew parameter configuration module 11, the phase interpolation acquisition submodule 12, the eye diagram scan initiation module 121, the eye diagram scan and data transmission module 122, the data reception module 123, the phase interpolation determination module 124, the first bit error rate analysis unit 1241, the first phase interpolation determination unit 1242, the second bit error rate analysis unit 1243, the data correct reception judgment unit 1244, the data correct reception result transmission unit 1245, the second phase interpolation determination unit 1246, and the skew calibration value acquisition module 2, at least one of the related functions can be implemented in one or more hardware controllers. Controllers, microcontrollers, hardware processors, microprocessors, application-specific integrated circuits (ASICs), digital signal processors (DSPs), field programmable gate arrays (FPGAs), central processing units (CPUs), or various logic blocks, modules, and circuits in other processing units.The functions of at least one of the following modules—phase interpolation acquisition module 1, skew parameter configuration module 11, phase interpolation acquisition submodule 12, eye diagram scan initiation module 121, eye diagram scan and data transmission module 122, data reception module 123, phase interpolation determination module 124, first bit error rate analysis unit 1241, first phase interpolation determination unit 1242, second bit error rate analysis unit 1243, data correct reception judgment unit 1244, data correct reception result transmission unit 1245, second phase interpolation determination unit 1246, and skew calibration value acquisition module 2—can be implemented as hardware circuits, such as various logic blocks, modules, and circuits in an integrated circuit, using hardware description languages ​​(e.g., Verilog HDL or VHDL) or other suitable programming languages.

[0236] In software or firmware form, at least one of the following functions—phase interpolation acquisition module 1, skew parameter configuration module 11, phase interpolation acquisition submodule 12, eye diagram scan initiation module 121, eye diagram scan and data transmission module 122, data reception module 123, phase interpolation determination module 124, first bit error rate analysis unit 1241, first phase interpolation determination unit 1242, second bit error rate analysis unit 1243, data correct reception judgment unit 1244, data correct reception result transmission unit 1245, second phase interpolation determination unit 1246, and skew calibration value acquisition module 2—can be implemented as programming codes. For example, at least one of the following modules can be implemented using a general programming language (such as C, C++, or assembly language) or another suitable programming language: phase interpolation acquisition module 1, skew parameter configuration module 11, phase interpolation acquisition submodule 12, eye diagram scan initiation module 121, eye diagram scan and data transmission module 122, data reception module 123, phase interpolation determination module 124, first bit error rate analysis unit 1241, first phase interpolation determination unit 1242, second bit error rate analysis unit 1243, data correct reception judgment unit 1244, data correct reception result transmission unit 1245, second phase interpolation determination unit 1246, and skew calibration value acquisition module 2. The programming code can be recorded and stored in a non-transitory machine-readable storage medium. In some embodiments, the non-transitory machine-readable storage medium includes, for example, semiconductor memory and / or a storage device. Electronic devices (such as CPUs, hardware controllers, microcontrollers, hardware processors, or microprocessors) can read and execute programming code from a non-transient machine-readable storage medium to realize at least one of the related functions of the phase interpolation acquisition module 1, the skew parameter configuration module 11, the phase interpolation acquisition submodule 12, the eye diagram scan initiation module 121, the eye diagram scan and data transmission module 122, the data reception module 123, the phase interpolation determination module 124, the first bit error rate analysis unit 1241, the first phase interpolation determination unit 1242, the second bit error rate analysis unit 1243, the data correct reception judgment unit 1244, the data correct reception result transmission unit 1245, the second phase interpolation determination unit 1246, and the skew calibration value acquisition module 2.

[0237] In the illustrative embodiments, the UCIe receiver skew calibration method and UCIe receiver skew calibration device of this disclosure are applicable to SoC chips, etc., wherein the SoC chip can be any one of CPU (Central Processing Unit), GPU (Graphics Processing Unit), TPU (Tensor Processing Unit), NPU (Neural Network Processing Unit), DPU (Deep Learning Processing Unit), APU (Accelerated Processing Unit), and GPGPU (General-Purpose computing on Graphics Processing Unit).

[0238] The UCIe receiver skew calibration method and apparatus of this disclosure introduce clock signal phase interpolation scanning at the UCIe receiver. Based on a two-dimensional scan of data link skew coding and clock signal phase interpolation, a reference phase interpolation of the clock signal, which was determined in the UCIe process before the determination of data link skew coding at the UCIe receiver, is introduced. This results in the optimal data link skew coding of the UCIe receiver corresponding to the optimal phase interpolation. This helps to solve the problem that the true optimal line delay point of the UCIe receiver is erroneously ignored due to the nonlinearity between the data link skew coding and data link delay at the UCIe receiver, and helps to improve the robustness of data transmission.

[0239] The UCIe receiver skew calibration method and apparatus of this disclosure effectively decouple the nonlinear coupling between the data link skew coding and data link delay at the UCIe receiver through joint optimization of two-dimensional parameters. Experiments show that, compared with the traditional single-dimensional scanning scheme, the UCIe receiver skew calibration method and apparatus of this disclosure improve the calibration accuracy of the data link skew coding at the UCIe receiver and help reduce the consumption of related computing resources. The UCIe receiver skew calibration method and apparatus of this disclosure can be widely used in high-speed serial communication, clock data recovery (CDR) and other scenarios, helping to improve system timing stability and signal integrity.

[0240] Figure 15 This is a structural block diagram of an application scenario for a PCIE receiver using the UCIe receiver skew calibration method and apparatus according to embodiments of this disclosure. Figure 15As shown, based on PCIe specifications, there can be 64 data lanes between the PCIe transmitter and the PCIe receiver. Each lane of the PCIe receiver is equipped with a scan control module that implements the UCIe receiver skew calibration method and device functions of this embodiment. Corresponding to the 64 data lanes, this application scenario includes 64 scan control modules, namely, channel 0 scan control module 1501, channel 1 scan control module 1502, ..., channel 63 scan control module 1564. The structures of channel 0 scan control module 1501 to channel 63 scan control module 1564 are all the same, and they are responsible for the skew calibration of their respective channels. In addition, a process control module 1500 is included, which is coupled to channel 0 scan control module 1501 to channel 63 scan control module 1564.

[0241] Each of the channel 0 scanning control modules 1501 to the channel 63 scanning control modules 1564 includes a phase interpolation scanning control module 15001, a channel skew value scanning control module 15002, and a scanning result processing module 15003.

[0242] The phase interpolation scanning control module 15001 is used to initiate multiple rounds of phase interpolation scanning based on the input phase interpolation scanning boundary values, and obtain the optimal phase interpolation value under the current data link skew coding of the UCIe receiver based on the phase interpolation boundary values ​​corresponding to the correctly received test data of the UCIe receiver (for example, the average value of the phase interpolation boundary values ​​corresponding to the correctly received test data of the UCIe receiver is determined as the optimal phase interpolation value). If the current data link skew coding is a preset minimum skew value, the optimal phase interpolation value is the minimum phase interpolation value in the above embodiment. If the current data link skew coding is a preset maximum skew value, the optimal phase interpolation value is the maximum phase interpolation value in the above embodiment.

[0243] The phase interpolation scanning control module 15001 has a built-in state machine. Figure 16 This is a state diagram of the built-in state machine in the phase interpolation scan control module 15001, as shown below. Figure 16 As shown, the built-in state machine in the phase interpolation scan control module 15001 includes the following six states.

[0244] State 1: Idle state, which is the state in which phase interpolation scanning is not enabled. In this state, the internal related functional circuit units are turned off to reduce circuit power consumption.

[0245] State 2: Waiting for valid results. In this state, scanning has been started, and the relevant internal functional circuit units are activated, waiting to receive relevant information.

[0246] State 3: Scanning state. In this state, the internal functional circuits process the result of the clock signal phase interpolation of the previous scan and determine the clock signal phase interpolation for the next scan.

[0247] State 4: Waiting for adjustment to complete. At this point, the next phase interpolation scan has been triggered. We need to wait for this value to stabilize in the PCIe digital-to-analog interface for a period of time before switching to the next state.

[0248] State 5: End state. This state indicates that all related functions have been completed and the relevant calculation results have been obtained.

[0249] State 6: Error State. In this state, it indicates that no phase interpolation value was found during the entire scan process that allows the channel to transmit and receive data normally. The system enters this error state if no phase interpolation value is found during the entire scan process.

[0250] The channel skew value scanning control module 15002 is responsible for transmitting the preset minimum skew value and preset maximum skew value of the data link skew encoding to the PCIe digital-analog interface during the two-dimensional scanning process.

[0251] The function of the scan result processing module 15003 is to determine the optimal link skew value, i.e., the skew calibration value, based on the results of the two-dimensional scan. This ensures that the data channel reception at the PCIe receiver has the maximum skew margin, thereby improving the reliability of the data channel. The optimal link skew value, i.e., the skew calibration value, is calculated according to the following formula:

[0252]

[0253] Alternatively, the optimal link skew value, i.e. the skew calibration value, can be calculated using the following formula:

[0254]

[0255] For further explanation of the above two formulas, please refer to the relevant sections of the above embodiments.

[0256] The flow control module 1500 is used to control the entire two-dimensional scanning process of the algorithm and generate a sign that the algorithm is complete. The flow control module 1500 has a built-in state machine. Figure 17 This is a state diagram of the built-in state machine in the process control module 1500, as shown below. Figure 17 As shown, the built-in state machine in the process control module 1500 includes the following five states.

[0257] State 1: Idle state, i.e., the state where 2D scanning is not enabled. In the idle state, the relevant internal functional circuit units are turned off to reduce circuit power consumption.

[0258] State 2: Two-dimensional scan start state. In this state, the scan has received the start signal from the upper layer control module used for control link training, and the relevant internal functional circuit units are turned on to start the two-dimensional scan.

[0259] State 3: Two-dimensional scan completed. In this state, the internal functional circuit units have completed the two-dimensional scan process, and the clock signal phase interpolation and data link skew encoding have both reached the set maximum boundary values.

[0260] State 4: Calculate the optimal value state. In this state, the optimal link skew value, i.e. the skew calibration value, is calculated for each data channel according to the calculation formula mentioned above.

[0261] State 5: Analog-to-digital interface parameter adjustment state. Since the phase interpolation of the PCIe analog-to-digital interface is changed multiple times during the 2D scanning process, after calculating the optimal link skew value, the reference phase interpolation value (i.e., the optimal phase interpolation value) needs to be fed back to the analog-to-digital interface in this state. In this disclosed technical solution, adjusting the phase interpolation of the clock signal is only a means to obtain the optimal link skew value (i.e., the skew calibration value). In this state, the optimal link skew value calculated in the previous step is simultaneously fed back to the analog circuit of the PICE receiver through the analog-to-digital interface.

[0262] State 6: End state. In this state, the 2D scan has completed all relevant functions and obtained the optimal link skew value, i.e., the skew calibration value.

[0263] Figure 18 This is a schematic diagram of the structure of an electronic device provided in an embodiment of this disclosure. In some embodiments, the electronic device is a server. The electronic device 1800 can vary considerably due to different configurations or performance, and may include one or more Central Processing Units (CPUs) 1801 and one or more memories 1802, wherein the memory 1802 stores at least one line of program code, which is loaded and executed by the processor 1801 to implement the UCIe receiver skew calibration method provided in the various embodiments described above. Of course, the electronic device 1800 may also have wired or wireless network interfaces, a keyboard, and input / output interfaces for input and output. The electronic device 1800 may also include other components for implementing device functions, which will not be elaborated here.

[0264] In an exemplary embodiment, a computer-readable storage medium including at least one instruction, such as a memory including at least one instruction, is also provided, wherein the at least one instruction can be executed by a processor in a computer device to perform the UCIe receiver skew calibration method in the above embodiments.

[0265] Optionally, the aforementioned computer-readable storage medium may be a non-transitory computer-readable storage medium, such as ROM (Read-Only Memory), RAM (Random-Access Memory), CD-ROM (Compact Disc Read-Only Memory), magnetic tape, floppy disk, and optical data storage devices.

[0266] In an exemplary embodiment, a chip is also provided, including the UCIe receiver skew calibration device in the above embodiments.

[0267] The above description is merely a preferred embodiment of this disclosure and is not intended to limit this disclosure. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this disclosure should be included within the scope of protection of this disclosure.

Claims

1. A UCIe receiver skew calibration method, characterized in that, include: Based on the preset minimum skew value and preset maximum skew value of the data link skew coding at the UCIe receiver, the minimum phase interpolation and maximum phase interpolation of the clock signal are determined when the UCIe receiver correctly receives data from the UCIe transmitter. Based on the preset minimum skew value, the preset maximum skew value, the minimum phase interpolation, the maximum phase interpolation, and the optimal phase interpolation of the clock signal, the skew calibration value of the data link skew coding of the UCIe receiver is obtained when the clock signal adopts the optimal phase interpolation.

2. The UCIe receiver skew calibration method according to claim 1, characterized in that, The determination of the minimum and maximum phase interpolation values ​​of the clock signal when the UCIe receiver correctly receives data from the UCIe transmitter, based on the preset minimum and maximum skew values ​​of the data link skew coding at the UCIe receiver, includes: Based on the preset minimum skew value of the data link skew coding of the UCIe receiver, the minimum phase interpolation of the clock signal is determined when the UCIe receiver correctly receives data from the UCIe transmitter. Based on the preset maximum skew value of the data link skew coding of the UCIe receiver, the maximum phase interpolation of the clock signal is determined when the UCIe receiver correctly receives data from the UCIe transmitter.

3. The UCIe receiver skew calibration method according to claim 2, characterized in that, In the case of the preset minimum skew value based on the data link skew coding of the UCIe receiver, determining the minimum phase interpolation of the clock signal when the UCIe receiver correctly receives data from the UCIe transmitter includes: The UCIe receiver sets the data link skew coding to the preset minimum skew value; The UCIe receiver initiates a first phase interpolation eye diagram scan based on the clock signal to the UCIe transmitter. During the first phase interpolation eye diagram scan, the UCIe transmitter sends test data to the UCIe receiver at each phase interpolation stage of the scan. The UCIe receiver receives the test data based on the preset minimum skew value; The minimum phase interpolation value is determined based on the test data received by the UCIe receiver and the phase interpolation value corresponding to the test data.

4. The UCIe receiver skew calibration method according to claim 3, characterized in that, The step of determining the minimum phase interpolation value based on the test data received by the UCIe receiver and the phase interpolation value corresponding to the test data includes: The UCIe receiver performs bit error rate analysis on the received test data to obtain the bit error rate, and determines whether the UCIe receiver has correctly received data from the UCIe transmitter based on the bit error rate and a preset bit error rate threshold. The UCIe receiver determines the minimum phase interpolation value based on the range of phase interpolation values ​​during the first phase interpolation eye diagram scanning process corresponding to the correctly received data.

5. The UCIe receiver skew calibration method according to claim 3, characterized in that, The step of determining the minimum phase interpolation value based on the test data received by the UCIe receiver and the phase interpolation value corresponding to the test data includes: The UCIe receiver performs bit error rate analysis on the received test data to obtain the bit error rate, and then sends the bit error rate to the UCIe transmitter. The UCIe transmitter determines whether the UCIe receiver has correctly received data from the UCIe transmitter based on the bit error rate and a preset bit error rate threshold. The UCIe transmitter sends the confirmation result of the UCIe receiver correctly receiving the data to the UCIe receiver. The UCIe receiver determines the minimum phase interpolation value based on the range of phase interpolation values ​​during the first phase interpolation eye diagram scanning process corresponding to the correctly received data.

6. The UCIe receiver skew calibration method according to claim 4 or 5, characterized in that, The step of determining the minimum phase interpolation value based on the range of phase interpolation values ​​during the first phase interpolation eye diagram scan process corresponding to the correctly received data includes: The average of the two boundary values ​​of the phase interpolation range in the first phase interpolation eye diagram scanning process corresponding to the correctly received data is determined as the minimum phase interpolation.

7. The UCIe receiver skew calibration method according to claim 2, characterized in that, In the case of the preset maximum skew value based on the data link skew coding of the UCIe receiver, determining the maximum phase interpolation of the clock signal when the UCIe receiver correctly receives data from the UCIe transmitter includes: The UCIe receiver sets the data link skew coding to the preset maximum skew value; The UCIe receiver initiates a second phase interpolation eye diagram scan based on the clock signal to the UCIe transmitter; During the second phase interpolation eye diagram scan, the UCIe transmitter sends test data to the UCIe receiver at each phase interpolation stage of the scan. The UCIe receiver receives the test data based on the preset maximum skew value; The maximum phase interpolation value is determined based on the test data received by the UCIe receiver and the phase interpolation value corresponding to the test data.

8. The UCIe receiver skew calibration method according to claim 7, characterized in that, The step of determining the maximum phase interpolation value based on the test data received by the UCIe receiver and the phase interpolation value corresponding to the test data includes: The UCIe receiver performs bit error rate analysis on the received test data to obtain the bit error rate, and determines whether the UCIe receiver has correctly received data from the UCIe transmitter based on the bit error rate and a preset bit error rate threshold. The UCIe receiver determines the maximum phase interpolation value based on the range of phase interpolation values ​​during the second phase interpolation eye diagram scanning process corresponding to the correctly received data.

9. The UCIe receiver skew calibration method according to claim 7, characterized in that, The step of determining the maximum phase interpolation value based on the test data received by the UCIe receiver and the phase interpolation value corresponding to the test data includes: The UCIe receiver performs bit error rate analysis on the received test data to obtain the bit error rate, and then sends the bit error rate to the UCIe transmitter. The UCIe transmitter determines whether the UCIe receiver has correctly received data from the UCIe transmitter based on the bit error rate and a preset bit error rate threshold. The UCIe transmitter sends the confirmation result of the UCIe receiver correctly receiving the data to the UCIe receiver. The UCIe receiver determines the maximum phase interpolation value based on the range of phase interpolation values ​​during the second phase interpolation eye diagram scanning process corresponding to the correctly received data.

10. The UCIe receiver skew calibration method according to claim 8 or 9, characterized in that, The step of determining the maximum phase interpolation value based on the range of phase interpolation during the second phase interpolation eye diagram scan process corresponding to the correctly received data includes: The average of the two boundary values ​​of the phase interpolation range during the second phase interpolation eye diagram scanning process corresponding to the correctly received data is determined as the maximum phase interpolation.

11. The UCIe receiver skew calibration method according to claim 1, characterized in that, The step of obtaining the skew calibration value of the data link skew coding of the UCIe receiver when the clock signal uses the optimal phase interpolation, based on the preset minimum skew value, the preset maximum skew value, the minimum phase interpolation, the maximum phase interpolation, and the optimal phase interpolation of the clock signal, includes: The difference between the preset maximum skew value and the preset minimum skew value is used as the skew interval length parameter; The difference between the maximum phase interpolation and the minimum phase interpolation is used as the phase interpolation interval length parameter; The ratio of the skew interval length parameter to the phase interpolation interval length parameter is used as a proportionality coefficient; The difference between the maximum phase interpolation and the optimal phase interpolation is used as the first phase interpolation reference length parameter; The product of the first phase interpolation reference length parameter and the scaling factor is used as the first skew value adjustment length parameter; The difference between the preset maximum skew value and the first skew value adjustment length parameter is determined as the skew calibration value.

12. The UCIe receiver skew calibration method according to claim 1, characterized in that, The step of obtaining the skew calibration value of the data link skew coding of the UCIe receiver when the clock signal uses the optimal phase interpolation, based on the preset minimum skew value, the preset maximum skew value, the minimum phase interpolation, the maximum phase interpolation, and the optimal phase interpolation of the clock signal, includes: The difference between the preset maximum skew value and the preset minimum skew value is used as the skew interval length parameter; The difference between the maximum phase interpolation and the minimum phase interpolation is used as the phase interpolation interval length parameter; The ratio of the skew interval length parameter to the phase interpolation interval length parameter is used as a proportionality coefficient; The difference between the optimal phase interpolation and the minimum phase interpolation is used as the second phase interpolation reference length parameter; The product of the second phase interpolation reference length parameter and the scaling factor is used as the second skew value adjustment length parameter; The sum of the preset minimum skew value and the second skew value adjustment length parameter is determined as the skew calibration value.

13. A UCIe receiver skew calibration device, characterized in that, include: The phase interpolation acquisition module is used to determine the minimum phase interpolation and maximum phase interpolation of the clock signal when the UCIe receiver correctly receives data from the UCIe transmitter, based on the preset minimum skew value and preset maximum skew value of the data link skew coding of the UCIe receiver, respectively. The skew calibration value acquisition module is used to obtain the skew calibration value of the data link skew encoding of the UCIe receiver when the clock signal adopts the optimal phase interpolation, based on the preset minimum skew value, the preset maximum skew value, the minimum phase interpolation, the maximum phase interpolation, and the optimal phase interpolation of the clock signal.

14. The UCIe receiver skew calibration device according to claim 13, characterized in that, The phase interpolation acquisition module includes: The skew parameter configuration module, located at the UCIe receiver, is used to configure the skew parameter to a preset minimum skew value or a preset maximum skew value. A phase interpolation acquisition submodule is used to determine, based on the skew parameter of the data link skew coding of the UCIe receiver, the phase interpolation parameter of the clock signal when the UCIe receiver correctly receives data from the UCIe transmitter. The phase interpolation parameter is associated with the skew parameter. When the skew parameter is a preset minimum skew value, the phase interpolation parameter is the minimum phase interpolation. When the skew parameter is a preset maximum skew value, the phase interpolation parameter is the maximum phase interpolation.

15. The UCIe receiver skew calibration device according to claim 14, characterized in that, The phase interpolation acquisition submodule includes: An eye diagram scan initiation module, located at the UCIe receiver, is used to initiate a phase interpolation eye diagram scan based on the clock signal to the UCIe transmitter. The eye diagram scanning and data transmission module, located at the UCIe transmitter, is used to perform phase interpolation eye diagram scanning and, during the phase interpolation eye diagram scanning process, sends test data to the UCIe receiver at each phase interpolation stage of the scan. The data receiving module, located at the UCIe receiver, is used to receive the test data based on the skew parameter; The phase interpolation determination module is used to determine the phase interpolation parameter associated with the skew parameter based on the test data received by the UCIe receiver and the phase interpolation corresponding to the test data.

16. The UCIe receiver skew calibration device according to claim 15, characterized in that, The phase interpolation determination module includes: The first bit error rate analysis unit, located at the UCIe receiver, is used to perform bit error rate analysis on the received test data to obtain the bit error rate, and determine whether the UCIe receiver has correctly received data from the UCIe transmitter based on the bit error rate and a preset bit error rate threshold. The first phase interpolation determination unit, located at the UCIe receiver, is used to determine the phase interpolation parameters based on the range of phase interpolation during the phase interpolation eye diagram scanning process corresponding to the correctly received data.

17. The UCIe receiver skew calibration device according to claim 15, characterized in that, The phase interpolation determination module includes: The second bit error rate analysis unit, located at the UCIe receiver, is used to perform bit error rate analysis on the received test data to obtain the bit error rate, and send the bit error rate to the UCIe transmitter. The data correct reception judgment unit is located at the UCIe transmitter and is used to determine whether the UCIe receiver has correctly received data from the UCIe transmitter based on the bit error rate and a preset bit error rate threshold. The data correct reception result sending unit, located at the UCIe transmitting end, is used to send the determination result of the UCIe receiving end correctly receiving the data to the UCIe receiving end. The second phase interpolation determination unit, located at the UCIe receiver, is used to determine the phase interpolation parameters based on the range of phase interpolation during the phase interpolation eye diagram scanning process corresponding to the correctly received data.

18. The UCIe receiver skew calibration device according to claim 17, characterized in that: The second phase interpolation determination unit is further configured to determine the average of the two boundary values ​​of the phase interpolation range in the phase interpolation eye diagram scanning process corresponding to the correctly received data as the phase interpolation parameter.

19. The UCIe receiver skew calibration device according to claim 13, characterized in that, The skew calibration value acquisition module is further configured to perform: The difference between the preset maximum skew value and the preset minimum skew value is used as the skew interval length parameter; The difference between the maximum phase interpolation and the minimum phase interpolation is used as the phase interpolation interval length parameter; The ratio of the skew interval length parameter to the phase interpolation interval length parameter is used as a proportionality coefficient; The difference between the maximum phase interpolation and the optimal phase interpolation is used as the first phase interpolation reference length parameter; The product of the first phase interpolation reference length parameter and the scaling factor is used as the first skew value adjustment length parameter; The difference between the preset maximum skew value and the first skew value adjustment length parameter is determined as the skew calibration value.

20. The UCIe receiver skew calibration device according to claim 13, characterized in that, The skew calibration value acquisition module is further configured to perform: The difference between the preset maximum skew value and the preset minimum skew value is used as the skew interval length parameter; The difference between the maximum phase interpolation and the minimum phase interpolation is used as the phase interpolation interval length parameter; The ratio of the skew interval length parameter to the phase interpolation interval length parameter is used as a proportionality coefficient; The difference between the optimal phase interpolation and the minimum phase interpolation is used as the second phase interpolation reference length parameter; The product of the second phase interpolation reference length parameter and the scaling factor is used as the second skew value adjustment length parameter; The sum of the preset minimum skew value and the second skew value adjustment length parameter is determined as the skew calibration value.

21. An electronic device, characterized in that, include: processor; Memory for storing the executable instructions of the processor; The processor is configured to execute the executable instructions to implement the UCIe receiver skew calibration method as described in any one of claims 1 to 12.

22. A computer-readable storage medium, characterized in that, When at least one instruction in the computer-readable storage medium is executed by the processor of the electronic device, the electronic device is enabled to implement the UCIe receiver skew calibration method as described in any one of claims 1 to 12.

23. A chip, characterized in that, Includes the UCIe receiver skew calibration device as described in any one of claims 13 to 20.

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