Core grain pattern defect detection method and system

Abstract

The invention provides a core grain pattern defect detection method and system, and the method comprises the steps: obtaining a core grain pattern, positioning core grains of the same type according to the core grain pattern, and calculating a mean value diagram and a standard deviation diagram; performing morphological expansion on the standard deviation graph to obtain an expanded standard deviation graph, and performing k-th power calculation on the expanded standard deviation graph to generate an enhanced standard deviation graph; according to the mean value diagram and the enhanced standard deviation diagram, determining a Z-score value of the normal distribution core particle stack diagram; according to a Z-score value of a normal distribution core particle overlay, a bright defect area and a dark defect area are respectively positioned through a double-threshold strategy, specifically, a standard normal distribution score of an edge area is reduced through expansion operation, false detection caused by positioning errors is inhibited, in addition, a standard deviation of the edge area is selectively enhanced through power transformation, and the detection accuracy is improved. And further distinguishing real defects and edge noise.

Description

Technical Field

[0001] This invention belongs to the field of core particle inspection technology, and specifically relates to a method and system for detecting core particle pattern defects. Background Technology

[0002] In the wafer manufacturing process, the detection of pattern defects in chips is a key step in ensuring product quality.

[0003] The statistical die-to-die method for locating patterned defects in core particles typically calculates a normal distribution score map using the mean map and standard deviation map of the core particles, and finally locates the defect by comparing thresholds.

[0004] However, this method has the following problems: 1) Insufficient positioning accuracy and slight deviations in mechanical or optical systems can lead to positional and grayscale differences in image alignment; during die-to-die detection, a large number of false detections occur at the edges of the core pattern; 2) In the existing technology, improvements to edge false detection mostly rely on hardware calibration or additional complex algorithms such as image edge masks, which are costly and inefficient. Summary of the Invention

[0005] Based on this, the present invention provides a method and system for detecting core pattern defects, which aims to perform image processing on the core standard deviation image to significantly reduce false detections at the edges of the core pattern while maintaining the detection sensitivity of non-edge areas.

[0006] A first aspect of the present invention provides a method for detecting core pattern defects, the method comprising: Obtain the core pattern, locate cores of the same type based on the core pattern, and calculate the mean plot and standard deviation plot; Morphological dilation is performed on the standard deviation map to obtain a dilated standard deviation map, and the dilated standard deviation map is calculated to the power of k to generate an enhanced standard deviation map, where the value of k ranges from (1, 2]. Based on the mean plot and the enhanced standard deviation plot, determine the Z-score value of the normally distributed core-particle stack plot; Based on the Z-score value of the normally distributed core-particle stack, the bright defect region and the dark defect region are located respectively using a dual threshold strategy.

[0007] Furthermore, in the step of performing morphological dilation on the standard deviation map to obtain an dilated standard deviation map, a structuring element sizing is performed on the standard deviation map. The dilation operation yields a dilated standard deviation plot, where... The theoretical pixel width of the edge is measured by the core design drawings or images. c is the scaling factor, with a value range of [0.8, 1.2], and b is the compensation factor, with a value range of [1, 3].

[0008] Furthermore, the calculation formula for the expansion operation is as follows: ; in, The standard deviation plot after inflation shows the values ​​at (x, y). Let be the value of the standard deviation plot at (x+s, y+t), where (s, t) are the pixel coordinates of the structuring element, and B is the set of pixel coordinates of the structuring element.

[0009] Furthermore, in the step of determining the Z-score value of the normally distributed core-particle stack map based on the mean map and the enhanced standard deviation map, the formula for calculating the Z-score value of the normally distributed core-particle stack map is as follows: ; in, Let Z be the Z-score value of the pixel at (x, y) for the nth core. Let be the pixel value of the nth core at (x, y). Let be the pixel value at (x, y) in the mean plot. To enhance the value of the standard deviation plot at (x, y), ε is the minimum value.

[0010] Furthermore, the step of locating bright and dark defects respectively using a dual-threshold strategy based on the Z-score value of the normally distributed core-particle stack image includes: Calculate the overall distribution of Z-score values ​​of the normal distribution core overlay map for all cores of the same type, and determine the bright defect threshold and dark defect threshold by referring to the standard normal distribution table according to the requirements of false detection rate and false negative rate of defect detection. The Z-score value is compared with the bright defect threshold and the dark defect threshold to determine the bright defect pixel and the dark defect pixel; Connectivity analysis is performed on bright and dark defect pixels respectively, and adjacent defect pixels are merged into defect regions.

[0011] A second aspect of the present invention provides a core pattern defect detection system for implementing the core pattern defect detection method described in the first aspect, the system comprising: The acquisition module is used to acquire the core pattern, locate cores of the same type based on the core pattern, and calculate the mean plot and standard deviation plot. The calculation module is used to perform morphological dilation on the standard deviation map to obtain a dilated standard deviation map, and to perform k-th power calculation on the dilated standard deviation map to generate an enhanced standard deviation map, wherein the value of k ranges from (1, 2]. The determination module is used to determine the Z-score value of the normally distributed core particle overlay map based on the mean map and the enhanced standard deviation map; The positioning module is used to locate the bright defect region and the dark defect region respectively by means of a dual threshold strategy based on the Z-score value of the normally distributed core particle stack map.

[0012] A third aspect of the present invention provides a computer-readable storage medium having a computer program stored thereon, which, when executed by a processor, implements the core pattern defect detection method provided in the first aspect.

[0013] A fourth aspect of the present invention provides an electronic device, including a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor executes the program to implement the core pattern defect detection method provided in the first aspect.

[0014] The present invention provides a method and system for detecting core pattern defects. The method involves acquiring a core pattern, locating similar cores based on the pattern, and calculating a mean map and a standard deviation map. Morphological dilation is performed on the standard deviation map to obtain an dilated standard deviation map, and then a power-law calculation is performed on the dilated standard deviation map to generate an enhanced standard deviation map. Based on the mean map and the enhanced standard deviation map, the Z-score of the normally distributed core pattern is determined. Based on the Z-score of the normally distributed core pattern, a dual-threshold strategy is used to locate bright and dark defect regions. Specifically, the dilation operation reduces the standard normal distribution score of the edge regions to suppress false detections caused by positioning errors. Furthermore, the power-law transformation selectively enhances the standard deviation of the edge regions to further distinguish between real defects and edge noise. Attached Figure Description

[0015] Figure 1 This is a flowchart illustrating the implementation of a core pattern defect detection method according to Embodiment 1 of the present invention. Figure 2 This is a structural block diagram of a core pattern defect detection system provided in Embodiment 2 of the present invention; Figure 3 This is a structural block diagram of an electronic device provided in Embodiment 3 of the present invention. Detailed Implementation

[0016] To facilitate understanding of the present invention, a more complete description will be given below with reference to the accompanying drawings. Several embodiments of the invention are illustrated in the drawings. However, the invention can be implemented in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete.

[0017] It should be noted that when a component is said to be "fixed to" another component, it can be directly on the other component or there may be an intervening component. When a component is said to be "connected to" another component, it can be directly connected to the other component or there may be an intervening component. The terms "vertical," "horizontal," "left," "right," and similar expressions used in this document are for illustrative purposes only.

[0018] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention pertains. The terminology used herein in the description of the invention is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. The term "and / or" as used herein includes any and all combinations of one or more of the associated listed items.

[0019] Example 1 According to an embodiment of the present invention, a method for detecting core pattern defects is provided. It should be noted that the steps shown in the flowchart in the accompanying drawings can be executed in a computer system such as a set of computer-executable instructions. Furthermore, although a logical order is shown in the flowchart, in some cases, the steps shown or described may be executed in a different order than that shown here.

[0020] This first embodiment provides a method for detecting core pattern defects, which can be used in electronic devices, such as computers. Please refer to... Figure 1 , Figure 1 The flowchart of a core pattern defect detection method provided in Embodiment 1 of the present invention is shown, specifically including steps S01 to S04.

[0021] Step S01: Obtain the core pattern, locate cores of the same type based on the core pattern, and calculate the mean plot and standard deviation plot.

[0022] Specifically, during the wafer image scanning process, after locating the die positions, each die is overlaid according to the channel dimension. The mean and standard deviation of the same type of die in each batch of die overlays are dynamically calculated. The mean map reflects the average gray level of the same location among all the same type of die, and the calculation formula is as follows: ; Let be the gray value of the mean plot at (x, y), and N be the total number of the same type of core particles. Let be the gray value of the i-th core at (x, y). If (x, y) is not within any core region... The value can be 0 or the background grayscale value.

[0023] The standard deviation plot reflects the degree of grayscale dispersion at the same location among all the same type of core particles. The greater the dispersion, the more likely there is a defect at that location (such as a bright spot or a dark spot). The calculation formula is: ; Let x be the standard deviation of the standard deviation plot at (x, y). Let be the gray value of the mean plot at (x, y), and N be the total number of the same type of core particles. Let N be the gray value of the i-th core at (x, y). N-1 is used as the denominator to perform unbiased estimation and avoid statistical bias when the sample size is small.

[0024] Step S02: Perform morphological dilation on the standard deviation map to obtain an dilated standard deviation map, and perform k-power calculation on the dilated standard deviation map to generate an enhanced standard deviation map.

[0025] It should be noted that the structuring element size was applied to the standard deviation plot. The dilation operation yields a dilated standard deviation plot, where... The theoretical pixel width of the edge is measured by the core design drawings or images. c is the scaling factor, with a value range of [0.8, 1.2], and b is the compensation factor, with a value range of [1, 3].

[0026] In this embodiment of the invention, the structural element size d is calibrated based on the wafer fab process design rule file according to the chip process node, and remains unchanged within the same wafer batch. In addition, the dilation operation and the k-th power calculation only apply to the standard deviation map or the image obtained after dilation, without the need to generate or store the chip gradient map or edge mask.

[0027] It should be noted that the formula for the expansion operation is: ; in, The standard deviation plot after inflation shows the values ​​at (x, y). Let (x, t) be the value of the standard deviation map at (x+s, y+t), (s, t) be the pixel coordinates of the structuring element, and B be the set of pixel coordinates of the structuring element. By traversing all valid regions of the structuring element B, the maximum value is taken as the pixel value at that position after dilation, thus realizing the expansion of the high standard deviation region.

[0028] In the step of calculating the k-th power of the dilation standard deviation map to generate an enhanced standard deviation map, the calculation formula can be expressed as: ; where is the value of the optimized standard deviation map at (x, y), is the value of the dilated standard deviation map at (x, y), and the value range of k is (1, 2]. It can be understood that the value in the die edge region is higher than that in the non-edge region itself. When calculating the k-th power (1 < k ≤ 2) of , the increase of the high value will be significantly higher than that of the low value, thereby further enlarging the standard deviation difference between the edge region and the non-edge region and achieving edge-selective enhancement.

[0029] In some other embodiments of the present invention, the operation order of performing morphological dilation and performing k-th power calculation can be swapped.

[0030] Step S03, determine the Z-score value of the normal distribution die overlay map according to the mean map and the enhanced standard deviation map.

[0031] The calculation formula for determining the Z-score value of the normal distribution die overlay map is: ; where is the Z-score value of the pixel value at (x, y) for the n-th die, is the pixel value at (x, y) for the n-th die, is the pixel value of the mean map at (x, y), is the value of the enhanced standard deviation map at (x, y), and ε is a minimum value. It can be understood that Z-score (standardized score) is used to measure the multiple of the standard deviation by which a single data point (a certain pixel of a single die) deviates from its overall mean. The larger the absolute value of the value, the more abnormal the gray level of the pixel and the more likely it is a defect.

[0032] Step S04, locate the bright defect region and the dark defect region respectively according to the Z-score value of the normal distribution die overlay map through a double-threshold strategy.

[0033] Specifically, calculate the overall distribution of the Z-score values of the normal distribution die overlay maps of all the same type of dies (usually conforming to the normal distribution N(0, 1)), and determine the bright defect threshold and the dark defect threshold by looking up the standard normal distribution table according to the requirements of the false detection rate and the missed detection rate of defect detection; The Z-score value is compared with the bright defect threshold and the dark defect threshold to determine the bright defect pixel and the dark defect pixel. It can be understood that when the Z-score value is greater than or equal to the bright defect threshold, the (x, y) pixel of the corresponding core is determined to be a bright defect pixel and the pixel coordinate is recorded. When the Z-score value is less than or equal to the dark defect pixel, the (x, y) pixel of the corresponding core is determined to be a dark defect pixel and the pixel coordinate is recorded. Connectivity analysis is performed on bright and dark defect pixels respectively, and adjacent defect pixels are merged into defect regions.

[0034] In summary, the core pattern defect detection method in the above embodiments of the present invention obtains a core pattern, locates cores of the same type based on the core pattern, and calculates a mean map and a standard deviation map; morphologically dilates the standard deviation map to obtain an expanded standard deviation map, and calculates the expanded standard deviation map by a power of k to generate an enhanced standard deviation map; determines the Z-score value of the normally distributed core particle overlay map based on the mean map and the enhanced standard deviation map; and locates bright defect regions and dark defect regions respectively using a dual threshold strategy based on the Z-score value of the normally distributed core particle overlay map. Specifically, the dilation operation reduces the standard normal distribution score of the edge region to suppress false detections caused by positioning errors. In addition, the power transformation selectively enhances the standard deviation of the edge region to further distinguish between real defects and edge noise.

[0035] Example 2 Please see Figure 2 , Figure 2 This is a structural block diagram of a core pattern defect detection system according to Embodiment 2 of the present invention. This core pattern defect detection system 200 is used to implement the above embodiments and preferred embodiments; details already described will not be repeated. As used below, the term "module" can refer to a combination of software and / or hardware that performs a predetermined function. Although the apparatus described in the following embodiments is preferably implemented in software, hardware implementation, or a combination of software and hardware, is also possible and contemplated.

[0036] Specifically, the core pattern defect detection system 200 includes: an acquisition module 21, a calculation module 22, a determination module 23, and a positioning module 24, wherein: The acquisition module 21 is used to acquire the core pattern, locate cores of the same type based on the core pattern, and calculate the mean plot and standard deviation plot. Calculation module 22 is used to perform morphological dilation on the standard deviation map to obtain an dilated standard deviation map, and to perform k-th power calculation on the dilated standard deviation map to generate an enhanced standard deviation map, wherein the value of k ranges from (1, 2]. Structural element sizing is then applied to the standard deviation map. The dilation operation yields a dilated standard deviation plot, where... The theoretical pixel width of the edge is measured from the core design drawings or images. c is a scaling factor with a value range of [0.8, 1.2], and b is a compensation factor with a value range of [1, 3]. The calculation formula for the dilation operation is as follows: ; in, The standard deviation plot after inflation shows the values ​​at (x, y). Let (x, t) be the value of the standard deviation map at (x+s, y+t), (s, t) be the pixel coordinates of the structuring element, and B be the set of pixel coordinates of the structuring element. In addition, according to the dilated standard deviation map, k is adaptively adjusted to make the edge region obtain a stronger enhancement effect, while the non-edge region maintains a moderate enhancement. Module 23 is used to determine the Z-score value of the normally distributed core-particle stack map based on the mean map and the enhanced standard deviation map. The formula for calculating the Z-score value of the normally distributed core-particle stack map is as follows: ; in, Let Z be the Z-score value of the pixel at (x, y) for the nth core. Let be the pixel value of the nth core at (x, y). Let be the pixel value at (x, y) in the mean plot. To enhance the value of the standard deviation plot at (x, y), ε is the minimum value; The positioning module 24 is used to locate the bright defect region and the dark defect region respectively by means of a dual threshold strategy based on the Z-score value of the normally distributed core particle stack map.

[0037] Furthermore, in some optional embodiments of the present invention, the positioning module 24 includes: The calculation unit is used to calculate the overall distribution of the Z-score values ​​of the normal distribution core overlay map of all cores of the same type, and to determine the bright defect threshold and dark defect threshold by referring to the standard normal distribution table according to the requirements of the false detection rate and false detection rate of defect detection. The comparison unit is used to compare the Z-score value with the bright defect threshold and the dark defect threshold to determine the bright defect pixel and the dark defect pixel. The analysis unit is used to perform connected region analysis on bright defect pixels and dark defect pixels respectively, and merge adjacent defect pixels into defect regions.

[0038] Example 3 In another aspect, the present invention also proposes an electronic device, please refer to [link to relevant documentation]. Figure 3The image shows an electronic device according to Embodiment 3 of the present invention, including a memory 20, a processor 10, and a computer program 30 stored in the memory and executable on the processor. When the processor 10 executes the computer program 30, it implements the chip pattern defect detection method as described above.

[0039] In some embodiments, the processor 10 may be a central processing unit (CPU), controller, microcontroller, microprocessor or other data processing chip, used to run program code stored in memory 20 or process data, such as executing access restriction programs.

[0040] The memory 20 includes at least one type of readable storage medium, such as flash memory, hard disk, multimedia card, card-type memory (e.g., SD or DX memory), magnetic memory, magnetic disk, optical disk, etc. In some embodiments, the memory 20 can be an internal storage unit of an electronic device, such as the hard disk of the electronic device. In other embodiments, the memory 20 can also be an external storage device of the electronic device, such as a plug-in hard disk, smart media card (SMC), secure digital (SD) card, flash card, etc. Furthermore, the memory 20 can include both internal and external storage units of the electronic device. The memory 20 can be used not only to store application software and various types of data of the electronic device, but also to temporarily store data that has been output or will be output.

[0041] It should be pointed out that, Figure 3 The structure shown does not constitute a limitation on the electronic device. In other embodiments, the electronic device may include fewer or more components than shown, or combine certain components, or have different component arrangements.

[0042] This invention also proposes a computer-readable storage medium storing a computer program that, when executed by a processor, implements the core pattern defect detection method described above.

[0043] Those skilled in the art will understand that the logic and / or steps represented in the flowcharts or otherwise described herein, for example, can be considered as a ordered list of executable instructions for implementing logical functions, and can be embodied in any computer-readable medium for use by, or in conjunction with, an instruction execution system, apparatus, or device (such as a computer-based system, a processor-included system, or other system that can fetch and execute instructions from, an instruction execution system, apparatus, or device). For the purposes of this specification, "computer-readable medium" can mean any means that can contain, store, communicate, propagate, or transmit programs for use by, or in conjunction with, an instruction execution system, apparatus, or device.

[0044] More specific examples of computer-readable media (a non-exhaustive list) include: electrical connections (electronic devices) having one or more wires, portable computer disk drives (magnetic devices), random access memory (RAM), read-only memory (ROM), erasable and editable read-only memory (EPROM or flash memory), fiber optic devices, and portable optical disc read-only memory (CDROM). Furthermore, computer-readable media can even be paper or other suitable media on which the program can be printed, because the program can be obtained electronically, for example, by optically scanning the paper or other medium, followed by editing, interpreting, or otherwise processing as necessary, and then stored in computer memory.

[0045] It should be understood that various parts of the present invention can be implemented in hardware, software, firmware, or a combination thereof. In the above embodiments, multiple steps or methods can be implemented in software or firmware stored in memory and executed by a suitable instruction execution system. For example, if implemented in hardware, as in another embodiment, it can be implemented using any one or a combination of the following techniques known in the art: discrete logic circuits having logic gates for implementing logical functions on data signals, application-specific integrated circuits (ASICs) having suitable combinational logic gates, programmable gate arrays (PGAs), field-programmable gate arrays (FPGAs), etc.

[0046] In the description of this specification, references to terms such as "one embodiment," "some embodiments," "example," "specific example," or "some examples," etc., indicate that a specific feature, structure, material, or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of the invention. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples.

[0047] The above embodiments merely illustrate several implementation methods of the present invention, and their descriptions are relatively specific and detailed, but they should not be construed as limiting the scope of the present invention. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of the present invention, and these all fall within the protection scope of the present invention. Therefore, the protection scope of this patent should be determined by the appended claims.

Claims

1. A method for detecting core pattern defects, characterized in that, The method includes: Obtain the core pattern, locate cores of the same type based on the core pattern, and calculate the mean plot and standard deviation plot; Morphological dilation is performed on the standard deviation map to obtain a dilated standard deviation map, and the dilated standard deviation map is calculated to the power of k to generate an enhanced standard deviation map, where the value of k ranges from (1, 2]. Based on the mean plot and the enhanced standard deviation plot, determine the Z-score value of the normally distributed core-particle stack plot; Based on the Z-score value of the normally distributed core-particle stack, the bright defect region and the dark defect region are located respectively using a dual threshold strategy.

2. The method for detecting core pattern defects according to claim 1, characterized in that, In the step of performing morphological dilation on the standard deviation map to obtain a dilated standard deviation map, structural element sizing is performed on the standard deviation map. The dilation operation yields a dilated standard deviation plot, where... The theoretical pixel width of the edge is measured by the core design drawings or images. c is the scaling factor, with a value range of [0.8, 1.2], and b is the compensation factor, with a value range of [1, 3].

3. The method for detecting core pattern defects according to claim 2, characterized in that, The calculation formula for the expansion operation is as follows: ； in, The standard deviation plot after inflation shows the values ​​at (x, y). Let be the value of the standard deviation plot at (x+s, y+t), where (s, t) are the pixel coordinates of the structuring element, and B is the set of pixel coordinates of the structuring element.

4. The method for detecting core pattern defects according to claim 3, characterized in that, In the step of determining the Z-score value of the normally distributed core-particle stack based on the mean plot and the enhanced standard deviation plot, the formula for calculating the Z-score value of the normally distributed core-particle stack is as follows: ； in, Let Z be the Z-score value of the pixel at (x, y) for the nth core. Let be the pixel value of the nth core at (x, y). Let be the pixel value at (x, y) in the mean plot. To enhance the value of the standard deviation plot at (x, y), ε is the minimum value.

5. The method for detecting core pattern defects according to claim 4, characterized in that, The step of locating bright and dark defects respectively using a dual-threshold strategy based on the Z-score value of the normally distributed core-particle stack image includes: Calculate the overall distribution of Z-score values ​​of the normal distribution core overlay map for all cores of the same type, and determine the bright defect threshold and dark defect threshold by referring to the standard normal distribution table according to the requirements of false detection rate and false negative rate of defect detection. The Z-score value is compared with the bright defect threshold and the dark defect threshold to determine the bright defect pixel and the dark defect pixel; Connectivity analysis is performed on bright and dark defect pixels respectively, and adjacent defect pixels are merged into defect regions.

6. A core pattern defect detection system, characterized in that, For implementing the core pattern defect detection method as described in any one of claims 1-5, the system comprises: The acquisition module is used to acquire the core pattern, locate cores of the same type based on the core pattern, and calculate the mean plot and standard deviation plot. The calculation module is used to perform morphological dilation on the standard deviation map to obtain a dilated standard deviation map, and to perform k-th power calculation on the dilated standard deviation map to generate an enhanced standard deviation map, wherein the value of k ranges from (1, 2]. The determination module is used to determine the Z-score value of the normally distributed core particle overlay map based on the mean map and the enhanced standard deviation map; The positioning module is used to locate the bright defect region and the dark defect region respectively by means of a dual threshold strategy based on the Z-score value of the normally distributed core particle stack map.

7. A computer-readable storage medium having a computer program stored thereon, characterized in that, When executed by the processor, the program implements the core pattern defect detection method as described in any one of claims 1-5.

8. An electronic device, characterized in that, It includes a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor, when executing the program, implements the core pattern defect detection method as described in any one of claims 1-5.

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