A DRAM failed cell repair method based on SOC driving mapping adjustment

Abstract

The present application relates to the technical field of DRAM memory repair, in particular to a DRAM failure unit repair method based on SOC driving mapping adjustment.The present application detects the physical address of the failure CELL unit in the DRAM grain through a test device, generates repair mapping data, records the repair mapping data in the form of a two-dimensional code on the surface of the DRAM grain and stores the repair mapping data to a non-volatile memory, loads the repair mapping data to a driving program when the SOC starts, synchronously modifies the address mapping relationship of the MMU and the IOMMU through the driving program, and redirects the access to the failure physical address to a backup physical address.The present application simultaneously modifies the MMU and the IOMMU mapping at the driving level, realizes the unified address remapping of the CPU and the DMA device access path, makes the DRAM grain containing the failure unit be used in a reduced capacity, greatly reduces the PCBA cost, and does not need to be modified in hardware, and is flexible to implement.

Description

Technical Field

[0001] This invention relates to the field of DRAM memory repair technology, specifically a method for repairing DRAM faulty cells based on SOC driver mapping adjustment. Background Technology

[0002] With the increasing demand for storage capacity in electronic products, DRAM cost has become a crucial factor affecting product competitiveness. Improving the utilization rate of DRAM chips and reducing the chip scrap rate due to failed cells are among the problems that the industry needs to solve.

[0003] In existing technologies, during DRAM production testing, if even one cell fails, the entire DRAM chip is deemed defective and scrapped. This results in low DRAM yield and high costs. While ECC error correction and hardware redundancy technologies exist in the server field, these solutions rely on dedicated hardware, are costly and complex to implement, and are unsuitable for cost-sensitive applications such as consumer electronics. Furthermore, existing memory management technologies primarily perform virtual address mapping for CPU access paths, neglecting the direct memory access paths of DMA devices, thus failing to achieve system-level address remapping consistency. Summary of the Invention

[0004] This invention provides a DRAM failure cell repair method based on SOC driver mapping adjustment, which enables the de-capacitance use of DRAM chips containing failure cells and reduces PCBA costs.

[0005] To achieve the above objectives, the present invention provides the following technical solution:

[0006] A DRAM fault cell repair method based on SOC driver mapping adjustment includes:

[0007] S100: Detect the physical address of the failed cell in the DRAM chip, and generate repair mapping data based on the physical address of the failed cell;

[0008] S200: Record the repair mapping data in a recognizable form on or associated with the DRAM chip, and store the repair mapping data in non-volatile memory;

[0009] S300: When the SOC starts, it loads repair mapping data from the non-volatile memory into the driver.

[0010] S400: By modifying the mapping relationship between virtual addresses and physical addresses in the MMU and the mapping relationship between device addresses and physical addresses in the IOMMU through the driver, access to the failed physical address is redirected to the spare physical address, thereby enabling normal use of the DRAM chip containing the failed CELL cell.

[0011] As a preferred embodiment of the present invention, the generation of the repair mapping data includes:

[0012] Establish a mapping relationship between failed physical addresses and backup physical addresses;

[0013] Generate invalid address masking flags to mark the range of physical addresses that need to be masked;

[0014] Calculate the effective capacity of the DRAM after repair.

[0015] As a preferred embodiment of the present invention, the repair mapping data includes:

[0016] Physical address mapping table of the failed cell unit;

[0017] Alternate physical address mapping;

[0018] The unique identifier of a DRAM chip;

[0019] Data verification code.

[0020] As a preferred embodiment of the present invention, S300 specifically includes:

[0021] Perform integrity and validity checks on the repaired mapping data;

[0022] The repair mapping data is simultaneously loaded into the first driver module used to modify the MMU mapping and the second driver module used to modify the IOMMU mapping.

[0023] After the driver is loaded, a verification test is performed to confirm that the address mapping table has been correctly loaded into the MMU and IOMMU.

[0024] As a preferred embodiment of the present invention, modifying the mapping relationship between virtual addresses and physical addresses in the MMU includes:

[0025] By modifying the page table entries in the MMU, a mapping from CPU virtual addresses to spare physical addresses is established;

[0026] Maintain a blacklist of invalid addresses so that any access to an invalid address is remapped to an alternative physical address.

[0027] As a preferred embodiment of the present invention, modifying the mapping relationship between device address and physical address in the IOMMU includes:

[0028] By modifying the device address table in the IOMMU, a mapping from DMA device addresses to spare physical addresses is established.

[0029] As a preferred embodiment of the present invention, the realization of normal use of DRAM chips containing failed cell units includes:

[0030] The effective capacity of the repaired DRAM is equal to the original nominal capacity of the DRAM minus the capacity occupied by the failed cell.

[0031] The system reports the adjusted actual available DRAM capacity to the operating system or upper-layer applications.

[0032] As a preferred embodiment of the present invention, it further includes:

[0033] Set a threshold for the number of failed cells; when the number of failed cells exceeds the threshold, the cell is deemed unrepairable.

[0034] During system operation, address mapping consistency checks between the MMU and IOMMU are performed periodically.

[0035] When a mapping deviation is detected, an alarm is triggered and the mapping data is reloaded and repaired.

[0036] The present invention also proposes a computer device, including a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor executes the computer program to implement the above-described DRAM failure cell repair method based on SOC driver mapping adjustment.

[0037] The present invention also proposes a readable storage medium storing a computer program, which, when executed by a processor, implements the above-described DRAM failure cell repair method based on SOC driver mapping adjustment.

[0038] The beneficial effects of this invention are:

[0039] 1. This invention achieves unified address remapping for CPU access paths and DMA device access paths by simultaneously modifying the address mapping relationship between the MMU and IOMMU at the driver level. This solves the problem in the prior art of only processing CPU access while ignoring DMA device access, ensuring system-level access consistency and avoiding data errors or system crashes caused by inconsistent mapping between the two paths.

[0040] 2. This invention employs a purely software-driven approach to repair DRAM faulty cells, requiring no modifications to the SOC hardware or the addition of dedicated ECC hardware or redundant storage units. Compared to existing hardware ECC error correction solutions, this invention is low-cost, flexible in implementation, and particularly suitable for cost-sensitive applications such as consumer electronics. By binding repair information to DRAM chips in the form of QR codes, traceable repair at the chip level is achieved, allowing DRAM chips that would otherwise be scrapped to be degraded (e.g., from 4GB to 3GB), significantly improving DRAM chip utilization and substantially reducing the overall cost of the PCBA.

[0041] 3. This invention establishes a complete runtime mapping maintenance mechanism. By periodically performing address mapping consistency checks on the MMU and IOMMU, mapping anomalies are detected and handled promptly. When mapping deviations or data tampering are detected, the system automatically triggers an alarm and reloads and repairs the data, ensuring that the address remapping function remains effective throughout the system's entire lifecycle. This proactive monitoring and self-repair mechanism significantly improves the system's stability and reliability. Attached Figure Description

[0042] The accompanying drawings are provided to further illustrate the invention and form part of the specification. They are used in conjunction with embodiments of the invention to explain the invention and do not constitute a limitation thereof. In the drawings:

[0043] Figure 1 This is a flowchart illustrating a DRAM failure cell repair method based on SOC driver mapping adjustment according to the present invention. Detailed Implementation

[0044] The preferred embodiments of the present invention will be described below with reference to the accompanying drawings. It should be understood that the preferred embodiments described herein are for illustration and explanation only and are not intended to limit the present invention.

[0045] Example 1: As Figure 1 As shown, the present invention provides a DRAM fault cell repair method based on SOC driver mapping adjustment, comprising:

[0046] S100: Detect the physical address of the failed cell in the DRAM chip, and generate repair mapping data based on the physical address of the failed cell;

[0047] Furthermore, the generation of the repair mapping data includes:

[0048] Establish a mapping relationship between failed physical addresses and backup physical addresses;

[0049] Generate invalid address masking flags to mark the range of physical addresses that need to be masked;

[0050] Calculate the effective capacity of the DRAM after repair.

[0051] Furthermore, the repair mapping data includes:

[0052] Physical address mapping table of the failed cell unit;

[0053] Alternate physical address mapping;

[0054] The unique identifier of a DRAM chip;

[0055] Data verification code.

[0056] Specifically, the DRAM chips are placed on an FT test bench, and the SOC is set to test mode. The SOC runs a test algorithm to perform read and write tests on each cell of the DRAM chip, detecting the physical addresses of failed cells. The test algorithm uses a pattern test method, writing specific data patterns to the physical addresses of the DRAM, then reading and comparing them, recording the physical addresses of read / write errors. After the test is completed, the SOC generates a failure cell detection log (pattern log), which records the physical addresses of all failed cells. For example, if the DRAM chip has a capacity of 4GB, and the test finds that some cells at certain physical addresses are failed, these addresses are recorded in the failure cell detection log.

[0057] The FT machine analyzes the failure cell detection logs to determine whether the failed cell is repairable. The judgment criteria include:

[0058] Set a threshold for the number of failed cells and count the total number of failed cells in the DRAM chip. If the number of failed cells does not exceed the threshold (determined based on the acceptable derating ratio in actual application), the chip is considered repairable; if it exceeds the threshold, it is considered unrepairable and the chip is discarded.

[0059] Once a failed cell is determined to be repairable, the FT machine generates repair mapping data based on the failed physical address in the failed cell detection log, establishing a mapping relationship between the failed physical address and the backup physical address. The established mapping relationship is recorded in the form of a mapping table, and each record in the mapping table contains: the failed physical address block number, the corresponding backup physical address block number, and the block size.

[0060] Set a masking flag for a failed physical address or range of failed physical addresses to mark the range of physical addresses that need to be masked. The masking flag includes the start address, end address, and masking status indicator of the failed address range to prevent the system from directly accessing the failed area.

[0061] The total capacity occupied by all failed cells is calculated. The effective capacity of the repaired DRAM is equal to the original nominal capacity of the DRAM minus the capacity occupied by the failed cells. For example, for a 4GB DRAM chip, if a failed cell occupies 1GB of capacity, the effective capacity after repair is 3GB.

[0062] The generated repair mapping data includes the following:

[0063] The physical address mapping table records the correspondence between all failed physical addresses and their backup physical addresses in tabular form. Each record includes: the failed physical address block number (starting address); the corresponding backup physical address block number (starting address); and the block size.

[0064] Record all physical address ranges used as reserves. Reserved physical addresses are selected from the normal physical address regions in the DRAM chips that have not failed. The system reserves a portion of address space as reserve regions during memory initialization. These address ranges are specifically used to replace failed regions and are no longer used for normal memory allocation.

[0065] Each DRAM chip is assigned a unique identifier to associate repair mapping data with the specific DRAM chip. When multiple DRAM chips are installed in the same system, the unique identifier can distinguish the repair data of different chips, ensuring the traceability of the repair data.

[0066] A checksum is generated to repair the mapping data, which is used to verify the integrity of the data during subsequent loading. The checksum is calculated based on the entire content of the repaired mapping data.

[0067] The generated repair mapping data is converted into a QR code. Using a standard QR code encoding method (such as QR Code), the repair mapping data is encoded into a QR code graphic. The QR code is then printed onto the surface of the DRAM chip using a laser, achieving physical binding between the repair information and the chip.

[0068] The QR code stores the unique identifier of the DRAM chip, mapping table data, masking flags, and a checksum. Depending on the QR code version and error correction level, the data size of a single QR code typically ranges from several hundred bytes to several thousand bytes. When the number of faulty cells is large, causing the mapping table data to exceed 2KB, lossless compression algorithms (such as LZ77 or Huffman coding) are used to compress the mapping data to accommodate the QR code's capacity limitations. The compressed data is automatically decompressed by the driver when the S300 is loaded.

[0069] S200: Record the repair mapping data in a recognizable form on or associated with the DRAM chip, and store the repair mapping data in non-volatile memory;

[0070] Specifically, the repair mapping data is converted into a QR code and printed onto the surface of the DRAM chip using a laser. The QR code serves as an identifiable identifier, physically binding the repair information to the DRAM chip. Besides QR codes, the repair mapping data can also be recorded in other identifiable forms, including: barcode markings on the DRAM chip surface; storing the repair mapping data in a dedicated storage area inside the DRAM chip; or associating the repair mapping data with the unique identifier of the DRAM chip and storing it in an external database. This embodiment preferably uses QR codes because of their large information capacity, strong fault tolerance, and suitability for recording complete repair mapping data within the limited surface space of the DRAM chip.

[0071] DRAM chips with printed QR codes are then mounted onto the CPU, NandFlash, and other components to form a PCBA. Even after the PCBA assembly is complete, the QR codes on the surface of the DRAM chips can still be recognized and read.

[0072] The repair mapping data is read from the QR code on the surface of the DRAM chip using a scanning device. The scanning device can be a dedicated barcode scanner, camera, or other optical recognition device. The scanning device decodes the QR code image to restore the original content of the repair mapping data.

[0073] After reading the repair mapping data, perform the following processing:

[0074] Integrity Verification: QR Code Decoding Integrity Verification: Based on the QR code's built-in error correction mechanism and the checksum in the repair mapping data, this verifies whether the QR code reading and decoding process is correct and whether the data is complete. If the verification fails, the QR code is rescanned or an error is reported.

[0075] DRAM chip correlation verification: Compare the unique identifier of the DRAM chip in the repair mapping data with the physical identifier of the actual installed chip to ensure that the repair data correctly corresponds to the current chip. If the identifiers do not match, storage is rejected and an error is reported.

[0076] The verified repair mapping data is stored in non-volatile memory. This non-volatile memory can be a type of memory such as NandFlash, eMMC, NOR Flash, or EEPROM, which retains data even after power loss. Specifically, the repair mapping data is stored in a dedicated program area within the NandFlash. This dedicated program area is specifically used to store DRAM repair-related configuration data and is isolated from other data partitions such as operating system programs and application data to prevent the repair mapping data from being accidentally overwritten or corrupted.

[0077] During storage, the repair mapping data is written to non-volatile memory according to a fixed data format, including the unique identifier of the DRAM chip, the mapping table, the mask flag, the effective capacity information, and the checksum. After storage, the non-volatile memory stores the complete repair mapping data, providing a data source for loading repair data during subsequent SOC startup.

[0078] After repairing the mapped data storage, read the stored data from the non-volatile memory and perform an integrity check again to confirm that the data has been correctly written to the memory without errors. If the verification fails, re-execute the storage operation.

[0079] S300: When the SOC starts, it loads repair mapping data from the non-volatile memory into the driver.

[0080] Furthermore, S300 specifically includes:

[0081] Perform integrity and validity checks on the repaired mapping data;

[0082] The repair mapping data is simultaneously loaded into the first driver module used to modify the MMU mapping and the second driver module used to modify the IOMMU mapping.

[0083] After the driver is loaded, a verification test is performed to confirm that the address mapping table has been correctly loaded into the MMU and IOMMU.

[0084] Specifically, after the PCBA is powered on, the SOC begins executing the boot process. During boot, the SOC needs to initialize various hardware modules and load necessary drivers. The repair mapping data loading process of this invention is integrated into the SOC's boot process.

[0085] When the SOC starts up, it reads the stored repair mapping data from the program area of ​​non-volatile memory (such as NandFlash). The driver first locates the separate program area that stores the repair mapping data and reads the contents of the repair mapping data according to a predetermined data format.

[0086] The repair mapping data read from non-volatile memory is verified to ensure data reliability, specifically including:

[0087] Storage integrity verification: Based on the checksum in the repair mapping data, verify whether the data is stored intact in non-volatile memory and whether bit flips or corruption have occurred. Calculate the checksum of the read data and compare it with the stored checksum. If they do not match, it indicates that the memory data is corrupted, the loading process terminates, and an error is reported.

[0088] Logical validity check: This checks whether the failed physical address is within the valid address range of the current DRAM, whether the spare physical address conflicts with the failed address in terms of address space, and whether the mapping table entries meet the format requirements. If the data logic is invalid, the loading process is terminated and an error is reported.

[0089] After successful verification, the repair mapping data is loaded into the driver program. The driver program includes a Vremap driver and a Dremap driver, used to modify the address mapping relationships of the MMU and IOMMU, respectively. The repair mapping data is simultaneously loaded into both the first driver module (Vremap driver) used to modify the MMU mapping and the second driver module (Dremap driver) used to modify the IOMMU mapping. Both driver modules receive the same repair mapping data, ensuring that subsequently generated address mapping rules are based on a consistent repair scheme. Each driver module parses the repair mapping data into its internal data structure. The Vremap driver converts the mapping table into a format suitable for MMU page table operations, and the Dremap driver converts the mapping table into a format suitable for IOMMU mapping table operations.

[0090] After the driver is loaded, a verification test is performed to ensure that the repair mapping data has been loaded correctly. If the verification passes, the driver is ready to execute the address remapping function.

[0091] This step ensures that the repair mapping data is correctly loaded into the MMU and IOMMU drivers through multi-level verification and simultaneous loading of dual drivers. Loading the data simultaneously into both driver modules and verifying their consistency is crucial for achieving consistent CPU and DMA device access path address mappings, thus preventing system anomalies caused by inconsistencies.

[0092] S400: By modifying the mapping relationship between virtual addresses and physical addresses in the MMU and the mapping relationship between device addresses and physical addresses in the IOMMU through the driver, access to the failed physical address is redirected to the spare physical address, thereby enabling normal use of the DRAM chip containing the failed CELL cell.

[0093] Furthermore, modifying the mapping relationship between virtual addresses and physical addresses in the MMU includes:

[0094] By modifying the page table entries in the MMU, a mapping from CPU virtual addresses to spare physical addresses is established;

[0095] Maintain a blacklist of invalid addresses so that any access to an invalid address is remapped to an alternative physical address.

[0096] Specifically, when the CPU needs to access DRAM, the virtual address it issues needs to be translated into a physical address by the MMU. The Vremap driver modifies the address mapping relationship in the MMU based on the repair mapping data, redirecting access to the failed physical address to the backup physical address.

[0097] The Vremap driver establishes a mapping relationship between CPU virtual addresses and standby physical addresses by modifying page table entries in the MMU. Specifically, for a virtual address that was originally mapped to a failed physical address, its corresponding page table entry is modified to change the target physical address to a standby physical address. For example, a virtual address was originally mapped to a failed physical address A. According to the repair mapping data, the standby physical address corresponding to this failed address is B. The Vremap driver modifies the MMU page table to map this virtual address to the standby physical address B, thereby achieving address redirection.

[0098] The Vremap driver maintains a blacklist of failed addresses, recording all failed physical address ranges. When performing address translation, the MMU first queries the blacklist to determine if the target physical address is a failed address. If it is a failed address, the access is redirected to the corresponding backup physical address based on the repair mapping data; if it is a normal address, access is performed according to the original mapping. This mechanism ensures that any access to a failed address is transparently remapped to a backup physical address, preventing data errors or system anomalies caused by the CPU accessing a failed cell.

[0099] Furthermore, modifying the mapping relationship between device addresses and physical addresses in the IOMMU includes: establishing a mapping between DMA device addresses and backup physical addresses by modifying the device address table in the IOMMU.

[0100] Specifically, when a DMA device needs to access DRAM, the device address it issues needs to be translated into a physical address by the IOMMU. The Dremap driver modifies the address mapping relationship in the IOMMU based on the repair mapping data, redirecting access to the failed physical address to a backup physical address.

[0101] The Dremap driver establishes a mapping relationship between DMA device addresses and standby physical addresses by modifying the device address mapping table in the IOMMU. For device addresses that were originally mapped to failed physical addresses, the corresponding mapping table entries are modified to change the target physical address to a standby physical address. When a DMA device accesses DRAM via a device address, the IOMMU redirects the device address request to the standby physical address according to the modified mapping table, thereby avoiding access to failed cell units.

[0102] The Vremap and Dremap drivers generate mapping rules based on the same repair mapping data, ensuring consistency between the two drivers. Specifically, both driver modules use the same list of failed physical addresses and a spare physical address mapping table. For the same failed physical address, both the MMU and IOMMU redirect access to the same spare physical address. This consistency guarantees that whether it's CPU access or DMA device access, for the same memory region, both access paths see the same data, avoiding system errors caused by data inconsistency.

[0103] Furthermore, the realization of normal use of DRAM chips containing failed cell units includes:

[0104] The effective capacity of the repaired DRAM is equal to the original nominal capacity of the DRAM minus the capacity occupied by the failed cell.

[0105] The system reports the adjusted actual available DRAM capacity to the operating system or upper-layer applications.

[0106] Specifically, the effective capacity of the repaired DRAM is equal to the original nominal DRAM capacity minus the capacity occupied by the failed cells. The repair mapping data records the total number and physical address range of all failed cells, and the masked capacity is calculated based on this information. For example, if a 4GB DRAM chip has 1GB of capacity occupied by failed cells, then the effective capacity after repair is 3GB. The system reports the adjusted actual usable DRAM capacity to the operating system or upper-layer applications as 3GB, and the operating system only uses this 3GB effective area when allocating memory.

[0107] For the operating system and applications, the address remapping process is transparent. The operating system sees a contiguous 3GB of available memory space without needing to know which underlying physical addresses are masked or remapped. The Vremap and Dremap drivers perform address translation at the driver level, presenting a unified logical address space to the upper layers.

[0108] During normal system operation, when the CPU or DMA device accesses DRAM, the driver automatically performs address remapping. Requests to access non-failed regions are accessed directly according to the original mapping; requests to access failed regions are redirected to an alternate address based on the repaired mapping data. The entire process is transparent to the upper layer, ensuring normal read and write operations. In this way, DRAM chips that would otherwise be scrapped due to containing failed cells can be repaired and reused at reduced capacity, significantly reducing the overall cost of the PCBA.

[0109] The aforementioned address remapping mechanism enables DRAM chips containing faulty cell units to function normally. To ensure long-term stable system operation, in addition to correctly loading and configuring the address mapping relationships during startup, it is also necessary to continuously monitor and maintain these mapping relationships during system operation, and promptly detect and handle any mapping anomalies that may occur.

[0110] During system operation, address mapping consistency checks are performed periodically on the MMU and IOMMU to ensure that the mapping relationship between the two drivers remains synchronized.

[0111] Specifically, the system periodically reads the mapping configurations in the MMU and IOMMU and compares whether the remapping targets for the same failed physical address are consistent. If a discrepancy is detected in the mapping relationship between the two drivers, the system records an exception log and triggers an alarm.

[0112] If the system detects that the repair mapping data has been tampered with, it will reload the repair mapping data to ensure the continued effectiveness of the repair function.

[0113] In summary, this embodiment achieves effective repair of DRAM chips containing failed cell units through a complete closed-loop process. Specifically, QR code printing physically binds repair information to the chip and enables traceability, while the synchronous loading of Vremap and Dremap dual-drives ensures consistency of CPU and DMA device access paths. This allows chips that would otherwise be scrapped to function normally and be degraded for use, significantly improving DRAM utilization and substantially reducing the overall cost of the PCBA.

[0114] Example 2:

[0115] A consumer electronics manufacturer produces smart terminal products using 4GB DRAM chips as main memory. During FT testing, approximately 15% of a batch of 10,000 DRAM chips were found to have faulty cells. Traditionally, these 1,500 chips would need to be scrapped. To reduce costs and improve DRAM utilization, the manufacturer adopted a DRAM faulty cell repair method based on SOC driver mapping adjustment, as described in this invention.

[0116] Taking one typical chip as an example, the FT test detected 128 failed cell units, occupying approximately 512MB of capacity. The FT machine generated repair mapping data, mapping the failed areas to spare physical addresses, and printed the repair information as a QR code on the chip surface. After the chip was assembled with other components to form a PCBA, the QR code was read by a barcode scanner, and the repair mapping data was stored in NandFlash. During SOC startup, the Vremap driver and Dremap driver simultaneously loaded the repair mapping data, modifying the address mapping tables of the MMU and IOMMU respectively. The system reported the actual available capacity to the operating system as 3.5GB.

[0117] In actual operation, when the CPU accesses data that was originally located in the failed region, the MMU maps the virtual address to a backup physical address. Simultaneously, when the GPU in the product performs graphics rendering as a DMA device, the IOMMU redirects the device address to the backup address according to the synchronously modified mapping table. If only the MMU mapping is modified without modifying the IOMMU mapping, the GPU will access the failed cell, leading to rendering errors. This invention ensures consistency between CPU and GPU access through dual-driver collaborative operation.

[0118] After 72 hours of stability testing, the system operated normally. During the test, the system performed mapping consistency checks every hour. In the 48th hour, an IOMMU mapping configuration anomaly was detected. The system immediately triggered an alarm and automatically reloaded and repaired the data. The entire recovery process took only 2 seconds.

[0119] During production debugging, a PCBA required the replacement of its DRAM chips. Since the repair information was printed on the chip surface in the form of a QR code, maintenance personnel could obtain the repair data simply by scanning the QR code on the new chip, eliminating the need for retesting and reducing the replacement time from 30 minutes to 5 minutes.

[0120] Using the traditional method, all 1,500 defective chips in this batch would be scrapped, resulting in a direct loss of 30,000 yuan based on a cost of 20 yuan per 4GB DRAM chip.

[0121] Using this invention, these 1500 defective memory chips, after being downgraded to 3.5GB, can be used in product lines with lower capacity requirements (such as entry-level devices, which come standard with 3GB or 3.5GB of memory). Based on a market price of 16 yuan per 3.5GB chip, this recovers a value of 24,000 yuan. After deducting the labor costs for QR code printing and scanning (approximately 0.2 yuan per chip), the net cost saving is approximately 23,700 yuan, representing a cost saving rate of 79%.

[0122] Compared to hardware ECC solutions, hardware ECC requires dedicated error correction circuitry, increasing the cost per chip by approximately 2-3 yuan, and can only correct a small number of bit errors, failing to handle large-scale failures. This invention employs a purely software solution, resulting in almost zero cost per chip for repair and a wider range of applications.

[0123] This invention achieves system-level access consistency by simultaneously modifying the address mapping relationship between the MMU and IOMMU at the driver level. Combined with repair information binding to DRAM chips and runtime monitoring mechanisms, previously obsolete DRAM chips can be degraded and used in other product lines, significantly reducing overall costs and demonstrating significant economic and practical value.

[0124] Example 3

[0125] In the third embodiment of the present invention, based on the same inventive concept, the present invention proposes a computer-readable storage medium storing a computer program. When the computer program is executed by a processor, it implements the steps of a DRAM failure cell repair method based on SOC driver mapping adjustment as described in the above embodiment.

[0126] Example 4

[0127] In the fourth embodiment of the present invention, based on the same inventive concept, a computer device is proposed, comprising: a processor and a memory; the processor and the memory communicate with each other; the memory is used to store instructions; the processor is used to execute the instructions in the memory to perform a DRAM failure cell repair method based on SOC driver mapping adjustment according to the above embodiment.

[0128] It should be understood that various parts of the present invention can be implemented in hardware, software, firmware, or a combination thereof. In the above embodiments, multiple steps or methods can be implemented in software or firmware stored in memory and executed by a suitable instruction execution system. For example, if implemented in hardware, as in another embodiment, it can be implemented using any one or a combination of the following techniques known in the art: discrete logic circuits having logic gates for implementing logical functions on data signals, application-specific integrated circuits (ASICs) having suitable combinational logic gates, programmable gate arrays (PGAs), field-programmable gate arrays (FPGAs), etc.

[0129] Finally, it should be noted that the above descriptions are merely preferred embodiments of the present invention and are not intended to limit the present invention. Although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art can still modify the technical solutions described in the foregoing embodiments or make equivalent substitutions for some of the technical features. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the protection scope of the present invention.

Claims

1. A DRAM failed cell repair method based on SOC drive map adjustment, characterized in that, include: S100: Detect the physical address of the failed cell in the DRAM chip, and generate repair mapping data based on the physical address of the failed cell; S200: Record the repair mapping data in a recognizable form on or associated with the DRAM chip, and store the repair mapping data in non-volatile memory; S300: During SOC startup, repair mapping data is loaded from the non-volatile memory to the driver program, specifically including: Perform integrity and validity checks on the repaired mapping data; The repair mapping data is simultaneously loaded into the first driver module used to modify the MMU mapping and the second driver module used to modify the IOMMU mapping. After the driver is loaded, a verification test is performed to confirm that the address mapping table has been correctly loaded into the MMU and IOMMU. S400: By modifying the mapping relationship between virtual addresses and physical addresses in the MMU and the mapping relationship between device addresses and physical addresses in the IOMMU through the driver, access to the failed physical address is redirected to the spare physical address, thereby enabling normal use of the DRAM chip containing the failed CELL cell.

2. The DRAM failure cell repair method based on SOC driver mapping adjustment according to claim 1, characterized in that, The generation of the repair mapping data includes: Establish a mapping relationship between failed physical addresses and backup physical addresses; Generate invalid address masking flags to mark the range of physical addresses that need to be masked; Calculate the effective capacity of the DRAM after repair.

3. The method of claim 1, wherein, The repair mapping data includes: Physical address mapping table of the failed cell unit; Alternate physical address mapping; The unique identifier of a DRAM chip; Data verification code.

4. The DRAM failed cell repair method based on SOC driving mapping adjustment according to claim 1, characterized in that, The modification of the virtual address to physical address mapping relationship in the MMU includes: By modifying the page table entries in the MMU, a mapping from CPU virtual addresses to spare physical addresses is established; Maintain a blacklist of invalid addresses so that any access to an invalid address is remapped to an alternative physical address.

5. The method of claim 1, wherein, Modifying the mapping relationship between device addresses and physical addresses in the IOMMU includes: establishing a mapping between DMA device addresses and backup physical addresses by modifying the device address table in the IOMMU.

6. The DRAM failed cell repair method based on SOC drive mapping adjustment according to claim 1, characterized in that, The implementation of normal use of DRAM chips containing faulty cell units includes: The effective capacity of the repaired DRAM is equal to the original nominal capacity of the DRAM minus the capacity occupied by the failed cell. The system reports the adjusted actual available DRAM capacity to the operating system or upper-layer applications.

7. The method of claim 1, wherein the method is based on a SOC- driven mapping adjustment for DRAM failed cell repair. Also includes: Set a threshold for the number of failed cells; when the number of failed cells exceeds the threshold, the cell is deemed unrepairable. During system operation, address mapping consistency checks between the MMU and IOMMU are performed periodically. When a mapping deviation is detected, an alarm is triggered and the mapping data is reloaded and repaired.

8. A computer device comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, characterized in that, When the processor executes the computer program, it implements a DRAM failure cell repair method based on SOC driver mapping adjustment as described in any one of claims 1 to 7.

9. A readable storage medium, characterized by, The readable storage medium stores a computer program, which, when executed by a processor, implements a DRAM failure cell repair method based on SOC driver mapping adjustment as described in any one of claims 1 to 7.

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