Packaging structure and preparation method thereof

Abstract

The invention provides a packaging structure and a preparation method thereof, and the preparation method comprises the steps: forming a substrate which is provided with a first surface and a second surface which are oppositely arranged, providing at least one chip, bonding the chip to the first surface of the substrate, forming a plurality of supporting rubber columns, and pasting the plurality of supporting rubber columns to the first surface of the substrate, the supporting columns are distributed on the outer side of the chip and are symmetrical about the center of the chip, a heat dissipation layer is formed on the face, away from the substrate, of the chip, a heat dissipation cover is provided and pasted to the first face of the substrate so that the chip can be contained in the heat dissipation cover, and the face, close to the chip, of the heat dissipation cover is bonded with the heat dissipation layer and the supporting rubber columns. According to the preparation method of the packaging structure, the problem of delamination of the heat dissipation layer can be solved, the heat dissipation performance and reliability of a product are improved, and large-scale production is facilitated.

Description

Technical Field

[0001] This invention belongs to the field of semiconductor integrated circuit manufacturing technology, and relates to a packaging structure and its preparation method. Background Technology

[0002] In today's rapidly evolving semiconductor industry, electronic products are constantly evolving towards miniaturization, which places increasingly stringent demands on electronic packaging products. Electronic packaging products must not only protect the chip but also meet the needs of continuous performance improvement, enhanced reliability, improved heat dissipation efficiency, and optimized electromagnetic shielding within a controllable cost range. In the field of flip-chip packaging structures, Ball Grid Array (BGA) and Flip Chip Ball Array (FCBGA) packaging methods have been widely used to improve the signal transmission performance of products by leveraging flip-chip bump technology. In the structural design of FCBGA packaging, to achieve efficient heat dissipation, the following structure is typically adopted: a heat sink is connected to the substrate by insulating adhesive, and thermal adhesive is filled between the heat sink and the chip, forming a targeted heat dissipation path.

[0003] However, during the high-temperature reflow soldering process of FCBGA packaging, the substrate and heat sink can experience inconsistent warping deformation due to thermal stress. This directly leads to delamination of the thermal adhesive around the chip, resulting in insufficient coverage of the thermal adhesive between the chip and the heat sink. This problem not only significantly reduces the thermal conductivity of the thermal adhesive, affecting the overall heat dissipation performance of the product, but may also cause a decrease in chip stability due to localized heat accumulation, seriously impacting product reliability.

[0004] To address the aforementioned issues, existing solutions primarily focus on two aspects: first, increasing the thickness of the thermal adhesive to compensate for the delamination effect by increasing material usage; and second, optimizing the toughness of the thermal adhesive material to reduce the risk of delamination by improving its mechanical properties. However, practice has shown that increasing the thickness of the thermal adhesive leads to increased thermal resistance, which in turn reduces heat dissipation efficiency. Optimizing material toughness often requires the use of high-performance modified materials, which significantly increases material costs and may adversely affect the compatibility and long-term reliability of the packaging structure due to changes in material composition, making it difficult to fundamentally solve the problem.

[0005] Therefore, how to provide a packaging structure and its preparation method to reduce the warping of the substrate and heat sink, solve the problem of heat sink delamination, improve the heat dissipation performance and reliability of the product, and facilitate mass production has become an important problem that needs to be solved by those skilled in the art.

[0006] It should be noted that the above introduction to the technical background is only for the purpose of providing a clear and complete explanation of the technical solutions of this application and facilitating understanding by those skilled in the art. It should not be assumed that these technical solutions are known to those skilled in the art simply because they have been described in the background section of this application. Summary of the Invention

[0007] In view of the shortcomings of the prior art described above, the purpose of this invention is to provide a packaging structure and its preparation method, which solves the problem that the substrate and heat sink are prone to warping after heat treatment, which leads to the delamination of the heat dissipation layer and reduces the heat dissipation performance and reliability of the product.

[0008] To achieve the above and other related objectives, the present invention provides a method for preparing an encapsulation structure, comprising the following steps:

[0009] A substrate is formed, the substrate having a first surface and a second surface disposed opposite to each other;

[0010] Provide at least one chip, and bond the chip to a first side of the substrate;

[0011] Multiple support pillars are formed and the multiple support pillars are adhered to the first surface of the substrate, and the multiple support pillars are distributed on the outside of the chip and symmetrical about the center of the chip;

[0012] A heat dissipation layer is formed on the side of the chip away from the substrate;

[0013] A heat sink is provided and is attached to the first side of the substrate so that the heat sink accommodates the chip, and the side of the heat sink close to the chip is bonded to the heat dissipation layer and the support post.

[0014] Optionally, the second surface of the substrate is provided with a plurality of solder balls, and the plurality of solder balls are arranged in an array.

[0015] Optionally, the support pillars are distributed on the outer edge of the chip diagonal.

[0016] Optionally, each of the epitaxial lines along the diagonal of the chip has a plurality of the supporting adhesive pillars.

[0017] Optionally, the minimum distance between the support post and the chip is 2.5mm to 3.5mm, the diameter of the support post is 2.5mm to 3.5mm, and the height of the support post is 0.9mm to 1.1mm.

[0018] Optionally, the heat sink has spaced bumps on the side near the chip, the height of the bumps ranging from 0.1 mm to 0.2 mm, and the density ranging from 5 bumps / mm. 2 ~20 pieces / mm 2 .

[0019] Optionally, the heat sink has spaced grooves on the side near the chip, the width of the grooves being 0.05mm to 0.2mm and the depth being 0.01mm to 0.1mm.

[0020] The present invention also provides a packaging structure, comprising:

[0021] The substrate has a first surface and a second surface disposed opposite to each other;

[0022] The chip is bonded to the first side of the substrate;

[0023] Multiple support pillars are attached to the first surface of the substrate, and the multiple support pillars are distributed on the outside of the chip and symmetrical about the center of the chip;

[0024] A heat dissipation layer is located on the side of the chip away from the substrate;

[0025] A heat sink is attached to the first side of the substrate and houses the chip. The side of the heat sink close to the chip is bonded to the heat dissipation layer and the support post.

[0026] Optionally, the heat sink has spaced bumps on the side near the chip, the height of the bumps ranging from 0.1 mm to 0.2 mm and the density ranging from 15 bumps / mm. 2 ~20 pieces / mm 2 .

[0027] Optionally, the heat sink has spaced grooves on the side near the chip, the width of the grooves being 0.05mm to 0.2mm and the depth being 0.01mm to 0.1mm.

[0028] As described above, the method for fabricating the packaging structure of the present invention includes the following steps: forming a substrate having a first side and a second side disposed opposite to each other; providing at least one chip; bonding the chip to the first side of the substrate; forming a plurality of support pillars; attaching the plurality of support pillars to the first side of the substrate, wherein the plurality of support pillars are distributed on the outer side of the chip and symmetrical about the chip center; forming a heat dissipation layer on the side of the chip away from the substrate; providing a heat dissipation cap; attaching the heat dissipation cap to the first side of the substrate so that the heat dissipation cap accommodates the chip, and the side of the heat dissipation cap near the chip is bonded to the heat dissipation layer and the support pillars. The method for fabricating the packaging structure of the present invention, by adding support pillars to form a "four-corner support structure," can reduce the warpage of the substrate and the heat dissipation cap, avoid delamination of the heat dissipation layer, thereby improving the heat dissipation performance and reliability of the product, while facilitating mass production. Attached Figure Description

[0029] Figure 1 The diagram shown is a schematic of a heat dissipation packaging structure.

[0030] Figure 2 Displayed as Figure 1 The diagram shows the structure obtained after a high-temperature reflow soldering process.

[0031] Figure 3 The diagram shows a process flow chart of the method for preparing the packaging structure of the present invention.

[0032] Figure 4 The diagram shown is a schematic representation of the substrate formed in the preparation method of the packaging structure of the present invention.

[0033] Figure 5 The diagram shown is a schematic of the structure obtained after bonding the chip in the preparation method of the packaging structure of the present invention.

[0034] Figure 6 The diagram shown is a schematic of the structure obtained after attaching the support adhesive pillars in the preparation method of the encapsulation structure of the present invention.

[0035] Figure 7 Displayed as Figure 6 Top view of the structure shown.

[0036] Figure 8 The diagram shown is a schematic of the structure obtained after forming a heat dissipation layer in the preparation method of the packaging structure of the present invention.

[0037] Figure 9 The diagram shown is a schematic of the structure obtained after attaching the heat sink in the preparation method of the packaging structure of the present invention.

[0038] Figure 10 The diagram shown illustrates another packaging structure of the present invention.

[0039] Figure 11The diagram shown illustrates another packaging structure of the present invention.

[0040] Explanation of reference numerals in the attached figures

[0041] 101, 201 substrate

[0042] 102, 203 chips

[0043] 103 Heatsink

[0044] 104, 205 Heat dissipation layer

[0045] 202 Welding Balls

[0046] 204 Support Column

[0047] 206 Heatsink

[0048] 207 Filler layer

[0049] 208 bumps

[0050] 209 Groove

[0051] L1 Shortest distance between the support post and the chip

[0052] Steps S1 to S5 Detailed Implementation

[0053] Please see Figure 1 The diagram shows a heat dissipation packaging structure, including a substrate 101, a chip 102, and a heat sink 103. The chip 102 is bonded to the upper surface of the substrate 101, and the heat sink 103 is attached to the upper surface of the substrate 101 and accommodates the chip 102. A heat dissipation layer 104 is provided between the chip 102 and the heat sink 103, so that a heat dissipation path is formed between the heat sink 103 and the chip 102.

[0054] However, please see Figure 2 Displayed as Figure 1 The diagram shows the structure obtained after a high-temperature reflow soldering process. During the high-temperature reflow soldering process, due to the difference in material properties between the substrate 101 and the heat sink 103, the substrate 101 and the heat sink 103 will undergo inconsistent warping deformation due to thermal stress during heating. This leads to delamination at the interface between the heat dissipation layer 104 and the surface of the chip 102 and the surface of the heat sink 103, resulting in insufficient coverage of the thermal adhesive between the chip 102 and the heat sink 103. This not only significantly reduces the thermal conductivity of the thermal adhesive, affecting the overall heat dissipation performance of the product, but also reduces the reliability of the product.

[0055] In addressing the above problems, some relevant invention patents have been disclosed in the existing technology:

[0056] (1) CN111477595A discloses a heat dissipation packaging structure and manufacturing method. Its core is to improve the structural strength by attaching a heat dissipation cover to the back of the substrate, use the heat dissipation cover to conduct heat from the substrate to optimize the heat dissipation effect, and reduce the risk of warpage and chip bump microcracks by enhancing the rigidity of the substrate. Although this solution improves the overall rigidity of the substrate through the heat dissipation cover, it still adopts a structural design of filling thermally conductive adhesive between the chip and the connection shielding line. It does not optimize for the difference in thermal stress between the substrate and the heat dissipation cover during high-temperature reflow soldering, and cannot fundamentally solve the problem of local warpage caused by the mismatch of the thermal expansion coefficients of the two. Therefore, there is still a potential risk of delamination between the thermally conductive adhesive and the chip / heat dissipation cover interface due to warpage.

[0057] (2) CN117524885A discloses a method for reducing the stress at the four corners of an FCBGA substrate by adding adhesive dots at the four corners of the substrate and adding thermal adhesive dots at the "X"-shaped extension of the thermal adhesive path on the chip. This reduces the stress at the four corners of the substrate, enhances the tensile strength of the heat sink to improve warping, and increases the coverage of the thermal adhesive. This solution alleviates the warping and coverage problems to some extent through the optimization of adhesive distribution, but it does not involve the improvement of the material matching between the substrate and the heat sink or the design of a thermal stress buffer structure. The shape, size, and distribution of the adhesive dots still rely on empirical adjustments. The adaptability to dynamic warping of substrates and heat sinks with different material combinations at high temperatures is limited, and it is difficult to completely eliminate the risk of interface delamination caused by thermal stress differences.

[0058] Although the above technical solutions have improved the heat dissipation and warping issues from the perspective of structural reinforcement or adhesive distribution, none of them have built a systematic solution for the core cause of the difference in thermal stress between the substrate and the heat sink. They cannot effectively avoid the problem of delamination of the thermal adhesive interface caused by the warping and deformation of the two during high-temperature processes.

[0059] Therefore, this application provides a packaging structure and its preparation method, which can effectively avoid substrate warping, solve the problem of heat dissipation layer delamination, thereby improving the heat dissipation performance and reliability of the product, and at the same time facilitating mass production.

[0060] The following specific examples illustrate the implementation of the present invention. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention.

[0061] It should be emphasized that the term "including / comprises" as used herein refers to the presence of a feature, whole, step, or component, but does not exclude the presence or addition of one or more other features, wholes, steps, or components.

[0062] Features described and / or illustrated for one embodiment may be used in the same or similar manner in one or more other embodiments, combined with features in other embodiments, or substituted for features in other embodiments.

[0063] In the detailed description of embodiments of the present invention, for ease of explanation, the schematic diagrams illustrating the device structure may be partially enlarged without adhering to the general scale, and the schematic diagrams are merely examples and should not limit the scope of protection of the present invention. Furthermore, in actual manufacturing, the three-dimensional spatial dimensions of length, width, and depth should be included.

[0064] For ease of description, spatial relation terms such as “below,” “under,” “lower than,” “below,” “above,” and “upper” may be used herein to describe the relationship between one element or feature shown in the accompanying drawings and other elements or features. It will be understood that these spatial relation terms are intended to include directions other than those depicted in the drawings for devices in use or operation. Furthermore, when a layer is referred to as being “between” two layers, it may be the only layer between the two layers, or there may be one or more layers in between.

[0065] In the context of this application, the structure described above the first feature may include embodiments in which the first and second features are in direct contact, or embodiments in which additional features are formed between the first and second features, such that the first and second features may not be in direct contact.

[0066] It should be noted that the illustrations provided in this embodiment are only schematic representations of the basic concept of the present invention. Therefore, the illustrations only show the components related to the present invention and are not drawn according to the actual number, shape and size of the components in the actual implementation. In the actual implementation, the form, quantity and proportion of each component can be arbitrarily changed, and the layout of the components may also be more complex.

[0067] Please see Figure 3 The diagram shows a process flow chart of the method for preparing the packaging structure of the present invention, which includes the following steps:

[0068] S1: Forming a substrate, the substrate having a first surface and a second surface disposed opposite to each other;

[0069] S2: Provide at least one chip and bond the chip to a first side of the substrate;

[0070] S3: Form multiple support pillars, attach the multiple support pillars to the first surface of the substrate, and the multiple support pillars are distributed on the outside of the chip and symmetrical about the center of the chip;

[0071] S4: Form a heat dissipation layer on the side of the chip away from the substrate;

[0072] S5: Provide a heat dissipation cover, attach the heat dissipation cover to the first side of the substrate so that the heat dissipation cover accommodates the chip, and the side of the heat dissipation cover near the chip is bonded to the heat dissipation layer and the support adhesive pillar.

[0073] The following will combine Figures 4 to 9 The following details each step of the preparation method of the packaging structure of the present invention.

[0074] First, please refer to Figure 4 Step S1: Form a substrate 201, wherein the substrate 201 has a first surface and a second surface disposed opposite to each other.

[0075] As an example, the second surface of the substrate 201 is provided with a plurality of solder balls 202, and the plurality of solder balls 202 are distributed in an array.

[0076] As an example, the substrate 201 is made of epoxy fiberglass laminate (FR4) and metallic copper.

[0077] As an example, the length of the substrate 201 ranges from 40mm to 100mm, such as 40mm, 50mm, 60mm and 80mm, and the width of the substrate 201 ranges from 40mm to 60mm, such as 40mm, 50mm, 60mm and 80mm.

[0078] Please see again Figure 5 Step S2: Provide at least one chip 203 and bond the chip 203 to the first side of the substrate 201.

[0079] As an example, the types of chips 203 include microcontrollers, digital signal processors, and micro sensors.

[0080] As an example, the length of the chip 203 ranges from 10mm to 50mm, such as 10mm, 20mm and 30mm, and the width of the chip 203 ranges from 40mm to 60mm, such as 10mm, 20mm and 30mm.

[0081] As an example, the chip 203 is packaged in a ball grid array (BGA) package.

[0082] As an example, the bonding method of the chip 203 includes flip-chip bonding.

[0083] As an example, the chip 203 is bonded to the central region of the substrate 201.

[0084] Please see again Figure 6 Step S3: Form a plurality of support adhesive pillars 204, attach the plurality of support adhesive pillars 204 to the first surface of the substrate 201, and the plurality of support pillars 204 are distributed on the outer side of the chip 203 and are symmetrical about the center of the chip 203.

[0085] Specifically, the process of attaching the multiple support posts 204 to the first surface of the substrate 201 is a dispensing process. It is worth noting that no additional fixing adhesive is needed when fixing the support posts 204. This design allows operators to flexibly adjust the fixing position of the support posts 204 according to the actual distribution of electronic components on the substrate 201 during the manufacturing process, thereby effectively simplifying the packaging process and reducing overall manufacturing costs. Furthermore, through the structural design of the support posts 204, no changes are needed to existing flip-chip bonding and dispensing equipment; only a four-corner dispensing process is added, resulting in a cost increase of ≤5%. The process is simple, feasible, and easily scalable for mass production.

[0086] For example, please refer to Figure 7 The support pillars 204 are distributed on the outer edge of the diagonal of the chip 203.

[0087] As an example, each of the epitaxial lines along the diagonal of the chip 203 has a plurality of the support posts 204.

[0088] As an example, the minimum distance L1 between the support post and the chip is 2.5mm to 3.5mm, the diameter of the support post 204 is 2mm to 5mm, for example 3mm and 3.5mm, and the height of the support post 204 is 0.5mm to 2.5mm, for example 0.9mm, 1mm and 1.1mm.

[0089] As an example, the support column 204 is made of high-temperature resistant silicone.

[0090] Please see again Figure 8 Step S4: Form a heat dissipation layer 205 on the side of the chip 203 away from the substrate 201.

[0091] As an example, the materials of the heat dissipation layer 205 include polyetheretherketone (PEEK), carbon nanotube thermal grease, and graphene thermal film.

[0092] As an example, the thermal conductivity of the heat dissipation layer 205 is in the range of 100 W / (m·K) to 250 W / (m·K), such as 100 W / (m·K), 180 W / (m·K) and 250 W / (m·K).

[0093] As an example, the heat dissipation layer 205 can be formed by coating.

[0094] As an example, the thickness of the heat dissipation layer 205 ranges from 0.01 mm to 0.1 mm, such as 0.04 mm, 0.06 mm and 0.08 mm.

[0095] Please see again Figure 9 Step S5: Provide a heat dissipation cover 206 and attach the heat dissipation cover 206 to the first side of the substrate 201 so that the heat dissipation cover 206 accommodates the chip 203, and the side of the heat dissipation cover 206 near the chip 203 is bonded to the heat dissipation layer 205 and the support adhesive pillar 204.

[0096] Specifically, the side of the heat sink 206 closest to the chip 203 is bonded to the support post 204, thus forming a rigid connection between the substrate 201, the support post 204, and the heat sink 206. (See also...) Figure 9 Multiple support pillars 204 are centrally symmetrically distributed on the outer sides of the four corners of the chip 203 and located on the outer extension lines of the diagonals of the chip 203, maintaining a preset distance from the chip 203, thus forming a "four-corner support structure". These support pillars 204 can transfer the thermal stress difference between the substrate 201 and the heat sink 206 to the four corner support points. When a thermal stress difference occurs between the substrate 201 and the heat sink 206, the support pillars 204 can absorb this difference through their own elastic deformation, thereby reducing the warping driving force caused by the mismatch in the thermal expansion coefficients of the materials, thus preventing delamination of the heat sink layer 205 and improving the heat dissipation performance of the packaging structure. Furthermore, the rigid connection between the substrate 201, the support pillars 204, and the heat sink 206 also improves the overall structural strength of the product, effectively enhancing its reliability.

[0097] Specifically, there is a positive correlation between the distance between the support pillar 204 and the chip 203 and the difference in thermal stress experienced by the support pillar 204. The smaller the distance, the smaller the difference in thermal stress experienced by the support pillar 204 during the thermal processing. If the distance is too large, the thermal stress generated by the difference in thermal expansion between the substrate 201 and the heat sink 206 will be excessively concentrated on the support pillar 204, potentially causing the support pillar 204 to detach from the substrate 201 or the heat sink 206, leading to delamination of the heat dissipation layer 205. Conversely, if the distance is too small, the support pillar 204 may adversely affect the electrical performance of the chip 203. Therefore, the distance between the support pillar 204 and the chip 203 needs to be within the range of 2.5mm to 3.5mm to balance thermal stress stability and the electrical performance requirements of the chip 203.

[0098] As an example, the heat sink 206 is made of copper, aluminum and silicon carbide.

[0099] As an example, the thermal conductivity of the heat sink 206 is not less than 100 W / (m·K).

[0100] As an example, the thickness of the heat sink 206 ranges from 0.2 mm to 1 mm, such as 0.3 mm, 0.5 mm and 0.8 mm.

[0101] As an example, the length of the heat dissipation cover 206 ranges from 40mm to 80mm, and the width ranges from 40mm to 80mm. It should be noted that the length and width of the heat dissipation cover are smaller than the length and width of the substrate 201.

[0102] As an example, after step S5 is completed, a curing process is also included, wherein the temperature range of the curing process is 100℃~150℃, for example 120℃, 125℃ and 130℃.

[0103] This completes the fabrication of a packaging structure. Please refer to [link / reference]. Figure 8 The packaging structure includes a substrate 201, a chip 203, a plurality of support posts 204, a heat dissipation layer 205, and a heat dissipation cap 206. The substrate 201 has a first side and a second side disposed opposite to each other. The chip 203 is bonded to the first side of the substrate 201. The plurality of support posts 204 are attached to the first side of the substrate 201 and are distributed on the outer side of the chip 203 and are symmetrical about the center of the chip 203. The heat dissipation layer 205 is located on the side of the chip 203 away from the substrate 201. The heat dissipation cap 206 is attached to the first side of the substrate 201 and accommodates the chip 203. The side of the heat dissipation cap 206 close to the chip 203 is bonded to the heat dissipation layer 205 and the support posts 204.

[0104] Specifically, the distance between the support post 204 and the chip 203 is in the range of 2.5mm to 3.5mm.

[0105] For example, please refer to Figure 10 The diagram shows another packaging structure of the present invention. The heat sink 206 has spaced bumps 208 on the side near the chip 203. The height of the bumps 208 ranges from 0.1 mm to 0.2 mm, for example, 0.15 mm, and the density ranges from 5 bumps / mm. 2 ~20 pieces / mm 2 For example, 10 pieces / mm 2 .

[0106] For example, please refer to Figure 11 The diagram shows another packaging structure of the present invention. The heat sink 206 has spaced grooves 209 on the side near the chip 203. The width of the grooves 209 is in the range of 0.05mm to 0.2mm, for example 0.08mm and 0.1mm, and the depth of the grooves 209 is in the range of 0.01mm to 0.1mm, for example 0.04mm and 0.05mm.

[0107] Specifically, the bumps 208 or the grooves 209 can increase the contact area between the heat dissipation layer 205 (using a thermal interface material) and the heat dissipation cover 206 and the chip 203, thereby further improving the heat conduction efficiency and reducing the contact thermal resistance.

[0108] To demonstrate the advantages of the packaging structure fabrication method of the present invention, existing packaging structure products (i.e. Figure 1 The packaging structure shown was compared with the packaging structure of the present invention through experimental testing, including four aspects: delamination rate of the heat dissipation layer, warpage of the substrate, coverage of the heat dissipation layer, and thermal resistance of the packaging structure. The delamination rate of the heat dissipation layer was obtained after subjecting both types of products to rigorous tests, including 456 hours of damp heat testing (temperature 130℃, humidity 85%), 2000 hours of cycling testing (temperature range -55~125℃), and 3000 hours of high-temperature storage (temperature 150℃). The comparison results are shown in Table 1 below:

[0109] Table 1 Performance Comparison Table

[0110] The packaging structure product of the present invention Existing packaging structure products Delamination rate of heat dissipation layer 5％ 90％ substrate warpage ≤10 micrometers ≥50 micrometers heat dissipation layer coverage ≥95％ <70％ thermal resistance <![CDATA[1.0℃·cm 2 / W]]> <![CDATA[2.6℃·cm 2 / W]]>

[0111] As can be seen from Table 1, the delamination rate of the heat dissipation layer, the warpage of the substrate, and the thermal resistance of the packaging structure product of the present invention are much lower than those of existing packaging structure products. On the other hand, the coverage of the heat dissipation layer of the packaging structure product of the present invention is much higher than that of existing packaging structure products. This indicates that the preparation method of the packaging structure of the present invention effectively avoids the delamination of the heat dissipation layer and improves the overall performance, reliability, and heat dissipation efficiency of the product.

[0112] Therefore, through the structural design and packaging process in the above preparation method, uniform coverage of the thermal adhesive on the chip surface is achieved, effectively solving the problem of warping and deformation of the substrate and heat sink caused by thermal stress during high-temperature reflow soldering, and significantly improving the heat dissipation performance and reliability of the product.

[0113] In summary, the method for fabricating the packaging structure of the present invention includes the following steps: forming a substrate having a first side and a second side disposed opposite to each other; providing at least one chip; bonding the chip to the first side of the substrate; forming a plurality of support pillars; attaching the plurality of support pillars to the first side of the substrate, wherein the plurality of support pillars are centrally symmetrically distributed on the outer sides of the four corners of the chip and located on the outer extension line of the chip's diagonal, the distance between the support pillars and the chip is in the range of 2.5mm to 3.5mm; forming a heat dissipation layer on the side of the chip away from the substrate; providing a heat dissipation cap; attaching the heat dissipation cap to the first side of the substrate so that the heat dissipation cap accommodates the chip, and the side of the heat dissipation cap close to the chip is bonded to the heat dissipation layer and the support pillars. The method for fabricating the packaging structure of the present invention can reduce the warpage of the substrate and the heat dissipation cap, avoid delamination of the heat dissipation layer, thereby improving the heat dissipation performance and reliability of the product, while facilitating mass production. Therefore, the present invention effectively overcomes the various shortcomings of the prior art and has high industrial applicability.

[0114] The above embodiments are merely illustrative of the principles and effects of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by those skilled in the art without departing from the spirit and technical concept disclosed in the present invention should still be covered by the claims of the present invention.

Claims

1. A method for preparing a packaging structure, characterized in that, Includes the following steps: A substrate is formed, the substrate having a first surface and a second surface disposed opposite to each other; Provide at least one chip, and bond the chip to a first side of the substrate; Multiple support pillars are formed and the multiple support pillars are adhered to the first surface of the substrate, and the multiple support pillars are distributed on the outside of the chip and symmetrical about the center of the chip; A heat dissipation layer is formed on the side of the chip away from the substrate; A heat sink is provided and is attached to the first side of the substrate so that the heat sink accommodates the chip, and the side of the heat sink close to the chip is bonded to the heat dissipation layer and the support post.

2. The method for preparing the packaging structure according to claim 1, characterized in that: The second side of the substrate is provided with a plurality of solder balls, and the plurality of solder balls are arranged in an array.

3. The method for preparing the packaging structure according to claim 1, characterized in that: The support pillars are distributed on the outer edge of the diagonal of the chip.

4. The method for preparing the packaging structure according to claim 3, characterized in that: Each of the epitaxial lines along the diagonal of the chip has a plurality of the supporting adhesive pillars.

5. The method for preparing the packaging structure according to claim 1, characterized in that: The minimum distance between the support post and the chip is 2.5mm to 3.5mm, the diameter of the support post is 2.5mm to 3.5mm, and the height of the support post is 0.9mm to 1.1mm.

6. The method for preparing the packaging structure according to claim 1, characterized in that: The heat sink has spaced bumps on the side near the chip. The height of the bumps ranges from 0.1 mm to 0.2 mm, and the density ranges from 5 bumps / mm. 2 ~20 pieces / mm 2 .

7. The method for preparing the packaging structure according to claim 1, characterized in that: The heat sink has spaced grooves on the side near the chip. The width of the grooves ranges from 0.05mm to 0.2mm, and the depth ranges from 0.01mm to 0.1mm.

8. A packaging structure, characterized in that, include: The substrate has a first surface and a second surface disposed opposite to each other; The chip is bonded to the first side of the substrate; Multiple support pillars are attached to the first surface of the substrate, and the multiple support pillars are distributed on the outside of the chip and symmetrical about the center of the chip; A heat dissipation layer is located on the side of the chip away from the substrate; A heat sink is attached to the first side of the substrate and houses the chip. The side of the heat sink close to the chip is bonded to the heat dissipation layer and the support post.

9. The packaging structure according to claim 8, characterized in that: The heat sink has spaced bumps on the side near the chip. The height of the bumps ranges from 0.1 mm to 0.2 mm, and the density ranges from 15 bumps / mm. 2 ~20 pieces / mm 2 .

10. The packaging structure according to claim 8, characterized in that: The heat sink has spaced grooves on the side near the chip. The width of the grooves ranges from 0.05mm to 0.2mm, and the depth ranges from 0.01mm to 0.1mm.

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