LED chip assembly and manufacturing method thereof
By generating a roughened layer on the surface of the P-type semiconductor layer of the red MLED chip and embedding a P-type ohmic contact metal layer, combined with oxide layer evaporation and overlay etching technology, the problems of small light-emitting layer area and chip leakage were solved, chip brightness was improved and the process was simplified.
Patent Information
- Application Number
- CN202410905136.0
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-07-08
- Publication Date
- 2026-01-13
AI Technical Summary
Existing red MLED chips have a small light-emitting layer area, and the passivation and reflective layers are easily damaged after etching, leading to leakage current in the chip.
A roughened layer is generated on the surface of the P-type semiconductor layer, and a P-type ohmic contact metal layer is embedded. The ohmic contact is formed by etching and metal evaporation. Combined with the evaporation and overlay etching techniques of the oxide layer, P-type and N-type metal layers are prepared to increase the light-emitting area and protect the chip.
It improves the brightness and overall light-emitting area of the chip, reduces the etching difficulty, avoids chip leakage caused by side etching of the passivation layer, and simplifies the process flow.
Smart Images
Figure CN121335302A_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of LED chip technology, and in particular to an LED chip assembly and its manufacturing method. Background Technology
[0002] MLED stands for Micro LED or Mini LED. Compared to traditional LEDs, its size is reduced from the millimeter level to the micro-nano level. When integrated into high-density, small-sized arrays and applied to the display field, it has advantages such as high brightness, high resolution, high contrast, low energy consumption, and long lifespan. It also has excellent performance in terms of response speed and thermal stability.
[0003] like Figure 1 The above describes the structure of a traditional red MLED chip, and its process steps are as follows: 1. The roughened epitaxial layer is subjected to oxide evaporation and planarization; 2. The substrate is bonded to the epitaxial layer and then removed; 3. After removing the cutoff layer, the pattern is created, and the P-type layer is extracted using dry etching. The yellow light pattern is then created and P-layer metal is formed after evaporation; 4. The N-type layer pattern is created, and N-layer metal is formed after evaporation. Excess GaAs layer is removed to improve light extraction efficiency; 5. The mesa pattern is created to separate the interconnected chips, preparing for subsequent cutting and dicing; 6. After DBR (Distributed Bragg Mirror) evaporation, a passivation layer and a reflective / insulating layer are added to prevent leakage and encapsulate the epitaxial layer of the chip; 7. The N / P metal is extracted through pattern creation, and N / P electrodes are deposited for customer use.
[0004] However, the red MLED chips produced based on the above process have a small light-emitting area in the light-emitting layer, and there is a high probability that the passivation layer and the reflective / insulating layer will be damaged after etching, resulting in chip leakage. Summary of the Invention
[0005] In view of the shortcomings of the prior art, the purpose of this application is to provide an LED chip component and a method for manufacturing the same, which aims to solve at least one of the above problems.
[0006] In a first aspect, this application provides a method for manufacturing an LED chip assembly, comprising: providing an epitaxial wafer, the epitaxial wafer comprising a substrate, a cutoff layer, an N-type ohmic contact layer, an N-type semiconductor layer, a light-emitting layer and a P-type semiconductor layer stacked sequentially;
[0007] A roughening operation is performed on the surface of the P-type semiconductor layer to generate a roughened layer;
[0008] A P-type ohmic contact metal layer is formed on the roughened layer, and the P-type ohmic contact metal layer penetrates the roughened layer and contacts the P-type semiconductor layer;
[0009] An oxide layer is deposited on the surface of the epitaxial wafer on which the P-type ohmic contact metal layer is formed.
[0010] The epitaxial wafer with the oxide layer deposited is transferred to a carrier substrate and the substrate is removed to obtain a new wafer source;
[0011] After removing the cutoff layer on the new source film, the N-type ohmic contact layer is patterned.
[0012] The new wafer source, after patterning the N-type ohmic contact layer, is subjected to Mesa etching to expose at least a portion of the P-type ohmic contact metal layer;
[0013] A passivation layer and a reflective layer are deposited on the new wafer source that exposes at least a portion of the P-type ohmic contact metal layer;
[0014] A P-type metal layer and an N-type metal layer are prepared on the new wafer source on which the passivation layer and the reflective layer are deposited. The P-type metal layer is connected to the P-type ohmic contact metal layer, and the N-type metal layer is located on the N-type ohmic contact layer.
[0015] P-electrodes and N-electrodes are fabricated on the P-type metal layer and the N-type metal layer, respectively.
[0016] In one possible embodiment, generating a P-type ohmic contact metal layer on the roughened layer includes:
[0017] The target pattern is obtained by applying a masking adhesive to the surface of the roughened layer and exposing and developing it.
[0018] Using the target pattern obtained through exposure and development as a mask, a groove is created on the roughened layer by dry etching, and a P-type ohmic contact metal layer is deposited in the groove, wherein the P-type semiconductor layer encapsulates the P-type ohmic contact metal layer.
[0019] In one possible embodiment, the step of patterning the N-type ohmic contact layer after removing the cutoff layer on the new wafer source includes:
[0020] The cutoff layer on the new wafer source is removed using wet etching to expose the N-type ohmic contact layer;
[0021] A protective layer is deposited onto the N-type ohmic contact layer;
[0022] The protective layer is coated with a masking adhesive and then exposed and developed to reveal the target pattern.
[0023] Using the target pattern as a mask, wet etching is used to pattern the protective layer and the N-type ohmic contact layer.
[0024] In one possible embodiment, the fabrication of a P-type metal layer and an N-type metal layer on the new wafer source having the passivation layer and the reflective layer deposited thereon includes:
[0025] A masking adhesive is applied to the surface of the reflective layer and exposed and developed to reveal the first target pattern.
[0026] The oxide layer is etched using the first target pattern obtained through exposure and development as a mask to expose the carrier substrate, and the mask adhesive is removed.
[0027] A masking material is applied to the etched new source film and exposed to develop a second target pattern.
[0028] The second target pattern, obtained through exposure and development, is used as a mask for etching through to the P-type ohmic contact metal layer;
[0029] A P-type metal layer is deposited on the P-type ohmic contact metal layer by vapor deposition, and the masking material is removed;
[0030] The masking material is applied to the new source film on which the P-type metal layer is deposited and then exposed and developed to reveal the third target pattern.
[0031] The third target pattern, obtained through exposure and development, is used as a mask for etching onto the N-type ohmic contact layer;
[0032] An N-type metal layer is deposited on the N-type ohmic contact layer, and the masking material is removed.
[0033] In one possible embodiment, the shape of the P-type ohmic contact metal layer is square, circular, polygonal, U-shaped, or square.
[0034] In one possible embodiment, the N-type metal layer is in the shape of a vertical square, a concave square, a horizontal square, or a combination of these shapes.
[0035] In one possible embodiment, the material of the N-type metal layer or the P-type metal layer includes at least one of Au, Ge, Ni, Cr, Pt, Ti, Al, Cu, Ag, AuBe, and AuGeNi.
[0036] In one possible embodiment, the roughening operation on the surface of the P-type semiconductor layer to generate a roughened layer includes:
[0037] The surface of the P-type semiconductor layer is roughened using a wet etching method to generate a roughened layer.
[0038] Secondly, this application also provides an LED chip assembly, which is prepared using the LED chip assembly manufacturing method described in any one of the first aspects.
[0039] Beneficial effects:
[0040] This application provides an LED chip assembly and its fabrication method. Before chip bonding, a P-type ohmic contact metal layer is embedded into the epitaxial layer using etching and metal evaporation to form an ohmic contact. After transfer, the P-type ohmic contact metal layer is introduced to the chip surface using overlay etching, thereby increasing the light-emitting area of the light-emitting layer and significantly improving the overall chip brightness. Furthermore, due to the evaporation of the oxide layer, the epitaxial wafer and metal are well encapsulated, making ultraplanarization easier. Substrate removal and subsequent fusion indirectly fuse the metal and epitaxial wafer, shortening the process flow. Attached Figure Description
[0041] Figure 1 This is a schematic diagram of the structure of a traditional red MLED chip;
[0042] Figure 2 This is a schematic diagram of an LED chip assembly manufacturing method provided in an embodiment of this application;
[0043] Figure 3 This is a schematic diagram of the epitaxial wafer structure in the LED chip assembly fabrication method provided in the embodiments of this application;
[0044] Figure 4 This is a schematic diagram of the roughened P-type semiconductor layer in the LED chip assembly fabrication method provided in the embodiments of this application;
[0045] Figure 5 This is a schematic diagram of the deposition of a P-type ohmic contact metal layer in an LED chip assembly fabrication method provided in this application embodiment;
[0046] Figure 6-1 This is a schematic diagram of the structure after depositing a P-type ohmic contact metal layer in an LED chip assembly fabrication method provided in this application embodiment;
[0047] Figure 6-2 This is a schematic diagram of another structure after depositing a P-type ohmic contact metal layer in an LED chip assembly fabrication method provided in this application embodiment;
[0048] Figure 6-3 This is another structural schematic diagram of an LED chip assembly fabrication method provided in this application after depositing a P-type ohmic contact metal layer;
[0049] Figure 7-1 This is another structural schematic diagram of an LED chip assembly fabrication method provided in this application after depositing a P-type ohmic contact metal layer;
[0050] Figure 7-2This is another structural schematic diagram of an LED chip assembly fabrication method provided in this application after depositing a P-type ohmic contact metal layer;
[0051] Figure 8 This is a schematic diagram of the structure after the oxide layer is generated in an LED chip assembly fabrication method provided in this application embodiment;
[0052] Figure 9 A schematic diagram illustrating the formation of a new chip source in an LED chip assembly manufacturing method provided in this application embodiment;
[0053] Figure 10 This is a schematic diagram illustrating the patterning of an N-type ohmic contact layer in an LED chip assembly fabrication method provided in this application embodiment.
[0054] Figure 11 This is a schematic diagram of Mesa etching in an LED chip assembly fabrication method provided in an embodiment of this application.
[0055] Figure 12 This is a schematic diagram illustrating the formation of a passivation layer and a reflective layer in an LED chip assembly manufacturing method provided in this application embodiment.
[0056] Figure 13 This is a schematic diagram of the deposition of a P-type metal layer and an N-type metal layer in an LED chip assembly fabrication method provided in an embodiment of this application.
[0057] Figure 14 This is a schematic diagram illustrating the preparation of electrodes in an LED chip assembly fabrication method provided in this application embodiment.
[0058] Explanation of reference numerals in the attached figures:
[0059] 110 - Substrate; 120 - Cut-off layer; 130 - N-type ohmic contact layer; 131 - Protective layer; 133 - N-type metal layer; 135 - N-electrode; 140 - N-type semiconductor layer; 150 - Light-emitting layer; 160 - P-type semiconductor layer; 161 - Trench; 163 - Roughening layer; 170 - P-type ohmic contact metal layer; 171 - P-type metal layer; 173 - P-electrode; 180 - Oxide layer; 190 - Supporting substrate; 200 - Passivation layer; 210 - Reflective layer; 300 - Masking adhesive. Detailed Implementation
[0060] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of the present invention, and not all of them. All other embodiments obtained by those skilled in the art based on the embodiments of the present invention without creative effort are within the scope of protection of the present invention.
[0061] This invention discloses many different embodiments or examples for implementing different structures of the invention. To simplify the disclosure, specific examples of components and arrangements are described herein. These are merely examples and are not intended to limit the invention. Furthermore, reference numerals and / or letters may be repeated in different examples; such repetition is for simplification and clarity and does not in itself indicate a relationship between the various embodiments and / or arrangements discussed. In addition, examples of various specific processes and materials are provided in this invention, but those skilled in the art will recognize the application of other processes and / or the use of other materials.
[0062] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein in the specification of this application is for the purpose of describing particular embodiments only and is not intended to be limiting of the application. Generally, terms can be understood at least in part according to their usage in accordance with the invention. For example, the term "one or more" as used herein, depending at least in part on the invention, can be used to describe any component, structure, or feature in the singular or in the plural form to describe a combination of components, structures, or features. Similarly, terms such as "a," "an," or "the" can also be understood, depending at least in part on the invention, to convey either a singular or a plural usage. Furthermore, the term "based on..." can be understood not necessarily to convey an exclusive set of factors, but rather, depending at least in part on the invention, can alternatively allow for additional factors that do not necessarily have to be explicitly described.
[0063] It should be readily understood that the meanings of “on,” “above,” and “on top of” in this invention should be interpreted in the broadest sense, such that “on” means not only “directly on something,” but also “on something” including the presence of an intermediate component or layer between the two, and “on something” or “above something” means not only “on something” or “above something,” but also “on something” or “above something” where no intermediate component or layer between the two exists.
[0064] Furthermore, for ease of description, spatial relative terms such as "below," "under," "lower," "above," and "upper" may be used in this invention to describe the relationship of one element or component to another element or component shown in the accompanying drawings. In addition to the orientations described in the figures, the spatial relative terms are also intended to cover different orientations of the device during use or operation. The device may be oriented in other ways, rotated 90°, or otherwise oriented, and the spatial relative descriptive terms used in this invention can be interpreted accordingly.
[0065] As used in this invention, the term "layer" refers to a portion of material comprising a region of a certain thickness. A layer may extend over the entire lower or upper layer structure, or may have a extent smaller than that of the lower or upper layer structure. Furthermore, a layer may be a region of a homogeneous or heterogeneous continuous structure with a thickness less than the thickness of the continuous structure. For example, a layer may be located between the top and bottom surfaces of a continuous structure, or between any pair of horizontal planes therebetween. A layer may extend horizontally, vertically, and / or along a tapered surface. A substrate may be a single layer, which may include one or more layers, and / or may have one or more layers on, above, and / or below it. A single layer may include multiple layers. For example, a semiconductor layer may include one or more doped or undoped semiconductor layers, and may have the same or different materials.
[0066] refer to Figure 1 This is a schematic diagram of the structure of a traditional red MLED chip. As shown, it involves sequentially etching the N-type ohmic contact layer 130, the N-type semiconductor layer 140, and the light-emitting layer 150 after removing the cutoff layer to expose the P-type semiconductor layer 160. This facilitates the deposition of the P-type ohmic contact metal layer 170 on the P-type semiconductor layer 160. In other words, during the fabrication of a traditional red MLED chip, part of the light-emitting layer is etched away, resulting in a reduction in the area of the light-emitting layer and consequently, a smaller light-emitting area.
[0067] Therefore, this application aims to provide a solution that can solve the above-mentioned technical problems, the details of which will be described in subsequent embodiments.
[0068] refer to Figure 2 This is a schematic flowchart of an LED chip assembly manufacturing method provided in an embodiment of this application. The method includes:
[0069] Step 101: Provide an epitaxial wafer.
[0070] like Figure 3 As shown, the epitaxial wafer includes a substrate 110, a cutoff layer 120, an N-type ohmic contact layer 130, an N-type semiconductor layer 140, a light-emitting layer 150, and a P-type semiconductor layer 160 stacked sequentially.
[0071] Specifically, the aforementioned light-emitting layer 150 can be a multiple quantum well (MQW) structure. A multiple quantum well structure can include one, two, three, four, five, six, seven, or eight quantum wells (or at least one quantum hole).
[0072] In the embodiments of this application, the substrate 110 may be a growth substrate or a temporary substrate.
[0073] In the embodiments of this application, the epitaxial wafer is a red-light-emitting epitaxial wafer based on the indium gallium aluminum phosphide system.
[0074] Step 102: Perform a roughening operation on the surface of the P-type semiconductor layer to generate a roughened layer.
[0075] As one implementation method, such as Figure 4 As shown, the outer surface of the P-type semiconductor layer 160 is roughened by wet etching to form a roughened layer 163.
[0076] The roughening layer 163 is used to improve chip brightness.
[0077] It is understood that the shape of the roughening layer 163 is not specifically limited in this application. It can be a regular shape or an irregular shape.
[0078] 103: A P-type ohmic contact metal layer is formed on the roughened layer, the P-type ohmic contact metal layer penetrating the roughened layer and contacting the P-type semiconductor layer.
[0079] like Figure 5 As shown, in one possible embodiment, step 103 includes: applying a mask adhesive 300 to the surface of the roughened layer 163 and exposing and developing a target pattern; using the exposed and developed target pattern as a mask, dry etching is used to create a groove 161 on the roughened layer 163, and a P-type ohmic contact metal layer 170 is deposited in the groove 161, wherein the P-type semiconductor layer 160 encapsulates the P-type ohmic contact metal layer 170.
[0080] It is understood that the specific shape of the target graphic is set according to actual needs, and this application does not impose any specific limitations.
[0081] As one implementation method, such as Figures 6-1 to 6-3 As shown, the P-type semiconductor layer 160 wraps the P-type ohmic contact metal layer 170 on one side, and the shape of the P-type ohmic contact metal layer 170 includes, but is not limited to, square, circular, and polygonal shapes.
[0082] As another implementation method, such as Figures 7-1 to 7-2 As shown, the P-type semiconductor layer 160 surrounds the P-type ohmic contact metal layer 170 on its periphery / all sides. The shape of the P-type ohmic contact metal layer 170 includes, but is not limited to, U-shape and square shape.
[0083] It should be noted that after the P-type ohmic contact metal layer 170 is deposited, the unwanted metal is stripped off, and the mask adhesive 300 applied in the current step is removed after each step.
[0084] 104: An oxide layer is deposited on the surface of the epitaxial wafer on which the P-type ohmic contact metal layer is formed.
[0085] like Figure 8 As shown, the oxide layer 180 can be SiO2.
[0086] It should be noted that after the oxide layer 180 is deposited, it needs to be polished to facilitate subsequent bonding processes.
[0087] 105: The epitaxial wafer with the oxide layer deposited is transferred to a carrier substrate and the substrate is removed to obtain a new wafer source.
[0088] Alternatively, the substrate 190 can be sapphire.
[0089] Specifically, such as Figure 9 As shown, the oxide layer 180 is bonded to the carrier substrate 190 to obtain a new wafer source. After removing the substrate 110, annealing is performed to test the bonding ability of the epitaxial layer, release stress, and enable the P-type ohmic contact metal layer 170 to form an ohmic contact for subsequent process operations.
[0090] 106: After removing the cutoff layer on the new source film, the N-type ohmic contact layer is patterned.
[0091] As one implementation method, such as Figure 10 As shown, 106 includes: removing the cutoff layer 120 on the new wafer source using wet etching to expose the N-type ohmic contact layer 130; depositing a protective layer 131 onto the N-type ohmic contact layer 130; applying a masking adhesive 300 onto the protective layer 131 and exposing and developing a target pattern; using the target pattern as a mask, and patterning the protective layer 131 and the N-type ohmic contact layer 130 using wet etching.
[0092] Since the N-type ohmic contact layer 130 absorbs the light emitted by the light-emitting layer 150, but the N-type ohmic contact layer 130 is needed to make ohmic contacts to reduce the chip resistance and thus reduce the chip voltage, the morphology of the N-type ohmic contact layer 130 is modified.
[0093] 107: The new wafer source after patterning the N-type ohmic contact layer is subjected to Mesa etching to expose at least a portion of the P-type ohmic contact metal layer.
[0094] like Figure 11 As shown, the pattern is developed using a mask material 300, and at least a portion of the P-type ohmic contact metal layer 170 is exposed using a metal overlay process (Mesa etching). Since there is no need to consider the epitaxial growth film layer, and the metal and epitaxial etching selectivity are different, the etching difficulty can be reduced to a large extent.
[0095] 108: A passivation layer and a reflective layer are deposited on the new wafer source that exposes at least a portion of the P-type ohmic contact metal layer.
[0096] like Figure 12 As shown, a passivation layer 200 and a reflective layer 210 are deposited onto the surface of the new chip source. The passivation layer 200 protects the chip from leakage, and the reflective layer 210 provides high reflectivity for a specified wavelength, thereby improving light utilization.
[0097] It is understandable that the passivation layer 200 can be obtained by deposition or by vapor deposition; no specific limitation is made here.
[0098] It is understandable that the passivation layer 200 can be made of materials such as SiO2 or SiNx. For example, the passivation layer 200 can also be one or more of Al2O3, AlN, and AlON thin films.
[0099] Among them, the reflective layer 210 is a multi-layered structure, such as using SiO2 and Ti3O5 as different materials for the layers.
[0100] It should be understood that the above are merely examples and not limitations.
[0101] It should be noted that the specific processes for the passivation layer 200 and the reflective layer 210 are described here, but are not specifically limited.
[0102] 109: A P-type metal layer and an N-type metal layer are prepared on the new wafer source on which the passivation layer and the reflective layer are deposited.
[0103] The P-type metal layer is connected to the P-type ohmic contact metal layer, and the N-type metal layer is located on the N-type ohmic contact layer, forming an ohmic contact.
[0104] like Figure 13As shown, a mask adhesive 300 is applied to the surface of the reflective layer 210 and exposed to develop a first target pattern; the first target pattern is used as a mask to etch the oxide layer 180 to expose the substrate 190, and the mask adhesive 300 is removed; the mask adhesive 300 is applied to the etched new wafer source and exposed to develop a second target pattern; the second target pattern is used as a mask to etch to the P-type ohmic contact metal layer 170; a P-type metal layer 171 is deposited on the P-type ohmic contact metal layer 170, and the mask adhesive 300 is removed; the mask adhesive 300 is applied to the new wafer source with the P-type metal layer 171 deposited, and exposed to develop a third target pattern; the third target pattern is used as a mask to etch to the N-type ohmic contact layer 130; an N-type metal layer 133 is deposited on the N-type ohmic contact layer 130, and the mask adhesive 300 is removed.
[0105] It should be noted that when the third target pattern obtained by exposure and development is used as a mask to etch onto the N-type ohmic contact layer 130, the protective layer 131 on the N-type ohmic contact layer 130 is etched through to expose the N-type ohmic contact layer 130, so that the vapor-deposited N-type metal layer 133 directly contacts the N-type ohmic contact layer 130, and the N-type metal layer 133 and the N-type ohmic contact layer 130 form an ohmic contact through the annealing process.
[0106] Optionally, the N-type metal layer 133 may be in the shape of a vertical square, a concave square, a horizontal square, or a combination of these shapes.
[0107] Optionally, the material of the N-type metal layer 133 or the P-type metal layer 171 includes at least one of Au, Ge, Ni, Cr, Pt, Ti, Al, Cu, Ag, AuBe, and AuGeNi.
[0108] 110: A P-electrode and an N-electrode are respectively fabricated on the P-type metal layer and the N-type metal layer.
[0109] like Figure 14 As shown, by using a mask adhesive 300 for multiple exposures and developments, a P electrode 173 is deposited on a P-type metal layer 171, and an N electrode 135 is deposited on an N-type metal layer 133.
[0110] Optionally, the masking adhesive 300 can be a photoresist.
[0111] Based on the same inventive concept, this embodiment also provides an LED chip assembly, which is prepared using the LED chip assembly manufacturing method described above.
[0112] In summary, the LED chip assembly and its fabrication method provided in this embodiment embed a P-type ohmic contact metal layer into the epitaxial layer using etching and metal evaporation before chip bonding to form an ohmic contact. After transfer, the P-type ohmic contact metal layer is introduced into the chip surface using overlay etching, thereby increasing the light-emitting area of the light-emitting layer and significantly improving the overall chip brightness. Furthermore, due to the oxide layer evaporation, the epitaxial wafer and metal are well encapsulated, making ultraplanarization easier. Substrate removal and subsequent fusion indirectly fuse the metal and epitaxial wafer, shortening the process flow. Secondly, compared to conventional LEDs, the LED chip assembly fabricated in this embodiment has a relatively simple chip structure and reduces the difficulty of the dry etching process, avoiding the technical problem of chip leakage caused by passivation layer side etching.
[0113] It should be understood that the application of the present invention is not limited to the examples above. Those skilled in the art can make improvements or modifications based on the above description, and all such improvements and modifications should fall within the protection scope of the appended claims.
Claims
1. A method for manufacturing an LED chip assembly, characterized in that, include: An epitaxial wafer is provided, the epitaxial wafer comprising a substrate, a cutoff layer, an N-type ohmic contact layer, an N-type semiconductor layer, a light-emitting layer and a P-type semiconductor layer stacked sequentially; A roughening operation is performed on the surface of the P-type semiconductor layer to generate a roughened layer; A P-type ohmic contact metal layer is formed on the roughened layer, and the P-type ohmic contact metal layer penetrates the roughened layer and contacts the P-type semiconductor layer; An oxide layer is deposited on the surface of the epitaxial wafer on which the P-type ohmic contact metal layer is formed. The epitaxial wafer with the oxide layer deposited is transferred to a carrier substrate and the substrate is removed to obtain a new wafer source; After removing the cutoff layer on the new source film, the N-type ohmic contact layer is patterned. The new wafer source, after patterning the N-type ohmic contact layer, is subjected to Mesa etching to expose at least a portion of the P-type ohmic contact metal layer; A passivation layer and a reflective layer are deposited on the new wafer source that exposes at least a portion of the P-type ohmic contact metal layer; A P-type metal layer and an N-type metal layer are prepared on the new wafer source on which the passivation layer and the reflective layer are deposited. The P-type metal layer is connected to the P-type ohmic contact metal layer, and the N-type metal layer is located on the N-type ohmic contact layer. P-electrodes and N-electrodes are fabricated on the P-type metal layer and the N-type metal layer, respectively.
2. The method for manufacturing an LED chip assembly as described in claim 1, characterized in that, The process of forming a P-type ohmic contact metal layer on the roughened layer includes: The target pattern is obtained by applying a masking adhesive to the surface of the roughened layer and exposing and developing it. Using the target pattern obtained through exposure and development as a mask, a groove is created on the roughened layer by dry etching, and a P-type ohmic contact metal layer is deposited in the groove, wherein the P-type semiconductor layer encapsulates the P-type ohmic contact metal layer.
3. The method for manufacturing an LED chip assembly as described in claim 1, characterized in that, The step of patterning the N-type ohmic contact layer after removing the cutoff layer on the new film source includes: The cutoff layer on the new wafer source is removed using wet etching to expose the N-type ohmic contact layer; A protective layer is deposited onto the N-type ohmic contact layer; The protective layer is coated with a masking adhesive and then exposed and developed to reveal the target pattern. Using the target pattern as a mask, wet etching is used to pattern the protective layer and the N-type ohmic contact layer.
4. The method for manufacturing an LED chip assembly as described in claim 1, characterized in that, The process of fabricating a P-type metal layer and an N-type metal layer on the new wafer source having the passivation layer and the reflective layer deposited thereon includes: A masking adhesive is applied to the surface of the reflective layer and exposed and developed to reveal the first target pattern. The oxide layer is etched using the first target pattern obtained through exposure and development as a mask to expose the carrier substrate, and the mask adhesive is removed. A masking material is applied to the etched new source film and exposed to develop a second target pattern. The second target pattern, obtained through exposure and development, is used as a mask for etching onto the P-type ohmic contact metal layer; A P-type metal layer is deposited on the P-type ohmic contact metal layer by vapor deposition, and the masking material is removed; The masking material is applied to the new source film on which the P-type metal layer is deposited and then exposed and developed to reveal the third target pattern. The third target pattern, obtained through exposure and development, is used as a mask for etching onto the N-type ohmic contact layer; An N-type metal layer is deposited on the N-type ohmic contact layer, and the masking material is removed.
5. The method for manufacturing an LED chip assembly as described in any one of claims 1-4, characterized in that, The shape of the P-type ohmic contact metal layer is square, circular, polygonal, U-shaped, or square.
6. The method for manufacturing an LED chip assembly as described in any one of claims 1-4, characterized in that, The N-type metal layer can be a vertical square, a concave square, a horizontal square, or a combination of these shapes.
7. The method for manufacturing an LED chip assembly as described in any one of claims 1-4, characterized in that, The material of the N-type metal layer or the P-type metal layer includes at least one of Au, Ge, Ni, Cr, Pt, Ti, Al, Cu, Ag, AuBe, and AuGeNi.
8. The method for manufacturing an LED chip assembly as described in claim 1, characterized in that, The roughening operation on the surface of the P-type semiconductor layer to generate a roughened layer includes: The surface of the P-type semiconductor layer is roughened using a wet etching method to generate a roughened layer.
9. An LED chip assembly, characterized in that, Prepared using the LED chip assembly fabrication method as described in any one of claims 1-8.