Semiconductor device and method of forming the same
By forming multiple vias and trenches in a three-dimensional integrated circuit and filling the dielectric layer with different conductive materials, the problems of stress concentration and poor contact during TSV formation are solved, thereby improving connection reliability and mechanical stability.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- Filing Date
- 2025-11-06
- Publication Date
- 2026-03-20
AI Technical Summary
In three-dimensional integrated circuits, stress concentration and poor contact are prone to occur during the formation of through silicon vias (TSVs), which leads to reduced connection reliability and affects chip performance.
By forming multiple vias and trenches in the dielectric layer and filling these structures with connection structures made of different conductive materials, a third connection structure penetrating the substrate is formed, which increases the contact area to disperse stress and improves mechanical stability.
It improves the reliability and mechanical stability of TSV connections, reduces defects on the contact surface, and enhances the reliability of the circuit structure leading out from the back.
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Figure CN121096960B_ABST
Abstract
Description
TECHNICAL FIELD
[0001] The present disclosure relates to the technical field of semiconductor, and particularly relates to a semiconductor device and a forming method thereof. BACKGROUND
[0002] In a three-dimensional integrated circuit (3D IC), a through silicon via (TSV) for leading an internal circuit structure of a chip from a back surface of the chip is usually formed in a back-end process, that is, the TSV is formed from the back surface of the chip after the internal circuit structure of the chip is formed. However, in the process of forming the TSV, stress concentration and poor contact between the TSV and other layer metals are prone to occur, which reduces the reliability of the TSV connection and degrades the performance of the chip. Therefore, how to optimize the forming process of the TSV has become a problem to be solved at present. SUMMARY
[0003] In view of the above, the present disclosure provides a semiconductor device and a forming method thereof.
[0004] To achieve the above object, the technical scheme of the present disclosure is as follows:
[0005] In a first aspect, the present disclosure provides a forming method of a semiconductor device, comprising:
[0006] providing a substrate; the substrate comprises a substrate and a dielectric layer located on a first side of the substrate along a first direction opposite to the other side;
[0007] forming a plurality of first vias and a first trench in the dielectric layer; the first trench extends into the dielectric layer from a top surface of the substrate along the first direction; the plurality of first vias are each extended into the dielectric layer from a bottom surface of the first trench along the first direction, and are located between the first trench and the substrate;
[0008] forming a plurality of first connection structures in the plurality of first vias, and forming a second connection structure in the first trench; the plurality of first connection structures are each connected with the second connection structure at a first end of two ends opposite to each other along the first direction;
[0009] forming a second trench from a second side of the substrate along the first direction opposite to the other side, the second trench penetrating through the substrate along the first direction, extending into the dielectric layer and exposing the plurality of first connection structures; the second trench exposes at least a second end of two ends opposite to each other along the first direction of the plurality of first connection structures and part of a sidewall;
[0010] forming a third connection structure in the second trench.
[0011] In an alternative embodiment, the second trench exposes the entire sidewall of the plurality of first connection structures and the second connection structure; after the third connection structure is formed in the second trench, the plurality of first connection structures and the second connection structure are both connected with the third connection structure.
[0012] In an alternative embodiment, the substrate includes a core region and a peripheral region arranged along a direction perpendicular to the first direction; the third connection structure is formed in the peripheral region; the substrate further includes an interconnect line in the dielectric layer; the interconnect line extends along a direction perpendicular to the first direction and is coupled with a circuit structure in the core region; the forming method further includes:
[0013] forming a plurality of second vias in the dielectric layer while forming the plurality of first vias, the plurality of second vias each extending from the bottom surface of the first trench along the first direction to expose the interconnect line;
[0014] forming a plurality of fourth connection structures in the plurality of second vias; after the second connection structure is formed, the plurality of fourth connection structures are each connected with the second connection structure; after the third connection structure is formed, the third connection structure is coupled with the interconnect line through the plurality of first connection structures, the second connection structure and the plurality of fourth connection structures.
[0015] In an alternative embodiment, forming the plurality of first vias, the plurality of second vias and the first trench in the dielectric layer includes:
[0016] etching the dielectric layer away from the substrate along a side of the dielectric layer on a side of the interconnect layer opposite to the substrate along the first direction to form a plurality of first initial vias extending into the dielectric layer along the first direction and a plurality of second initial vias extending into the dielectric layer along the first direction; the plurality of second initial vias are on a side of the interconnect line opposite to the substrate along the first direction;
[0017] etching the dielectric layer along the first direction to form the first trench through the plurality of first initial vias and the plurality of second initial vias; the plurality of first initial vias and the plurality of second initial vias are each in communication with the first trench;
[0018] removing the portion of the dielectric layer between the bottom of the plurality of first initial vias and the substrate to form the plurality of first vias, and simultaneously removing the portion of the dielectric layer between the bottom of the plurality of second initial vias and the interconnect line to form the plurality of second vias.
[0019] In one optional embodiment, the forming method further includes:
[0020] Before forming the second trench, a mask layer is formed covering the second side of the substrate;
[0021] Using the mask layer as a mask, the substrate and a portion of the dielectric layer located between the plurality of first connection structures and the substrate are etched along the first direction to form a third trench that penetrates the substrate and extends into the dielectric layer along the first direction.
[0022] An initial insulating layer is formed covering the inner wall of the third trench and the mask layer;
[0023] The initial insulating layer located at the bottom of the third trench and the dielectric layer located between the bottom of the third trench and the second connection structure are etched along the first direction to form the second trench; the remaining initial insulating layer constitutes an insulating layer, which is located at least between the second trench and the substrate.
[0024] In one optional embodiment, forming a plurality of first connection structures in the plurality of first through holes includes: filling the plurality of first through holes with a first conductive material to form the plurality of first connection structures;
[0025] The step of forming a second connection structure in the first trench includes: filling the first trench with a second conductive material to form the second connection structure; the second conductive material is different from the first conductive material.
[0026] In one alternative implementation, forming the third connection structure in the second trench includes:
[0027] A third conductive material is filled into the second trench to form the third connection structure; the third conductive material is different from the first conductive material.
[0028] In a second aspect, this disclosure provides a semiconductor device, comprising:
[0029] Substrate;
[0030] A dielectric layer located on a first side of two opposing sides of the substrate along a first direction;
[0031] A plurality of first connection structures and second connection structures are located in the dielectric layer; the plurality of first connection structures all extend along the first direction and are located between the substrate and the second connection structure; the first end of each of the two opposite ends of the plurality of first connection structures along the first direction is connected to the second connection structure;
[0032] A third connection structure extending through the substrate along the first direction; the third connection structure extending into the dielectric layer along the first direction, and the third connection structure being connected to at least the second end of one of the two ends of the plurality of first connection structures opposite each other along the first direction and a portion of the sidewalls of the plurality of first connection structures.
[0033] In one alternative implementation, the entire sidewall of the plurality of first connecting structures and the second connecting structure are connected to the third connecting structure.
[0034] In one optional implementation, the plurality of first connection structures are arranged in an array along a second direction and a third direction; the second direction intersects with the third direction and is perpendicular to the first direction.
[0035] In one optional embodiment, the semiconductor device includes a core region and a peripheral region arranged in a direction perpendicular to the first direction; the third connection structure is located in the peripheral region; the semiconductor device further includes:
[0036] Interconnects located in the dielectric layer; the interconnects extend in a direction perpendicular to the first direction and are coupled to the circuit structure in the core region;
[0037] A plurality of fourth connection structures are located in the dielectric layer; the plurality of fourth connection structures are located between the second connection structure and the interconnect in the first direction; the plurality of fourth connection structures all extend along the first direction and are all connected to the second connection structure; the third connection structure is coupled to the interconnect through the plurality of first connection structures, the second connection structure and the plurality of fourth connection structures.
[0038] In one optional embodiment, the semiconductor device further includes:
[0039] An insulating layer is located at least between the substrate and the third connection structure; the portion of the third connection structure that connects to the plurality of first connection structures protrudes relative to the insulating layer in the first direction.
[0040] In one alternative embodiment, the plurality of first connection structures include a first conductive material; the second connection structure includes a second conductive material; the second conductive material is different from the first conductive material.
[0041] In one alternative embodiment, the third connection structure includes a third conductive material; the third conductive material is different from the first conductive material.
[0042] In one optional embodiment, the first conductive material includes titanium or tungsten, the second conductive material includes one of copper, nickel, aluminum, and gold, and the third conductive material includes copper or tungsten.
[0043] In the technical solution provided in this disclosure, the third connection structure penetrating the substrate along the first direction is connected to at least the second end of one of the two ends of the plurality of first connection structures opposite to each other along the first direction and a portion of the sidewall. Thus, the third connection structure and the plurality of first connection structures can have a large contact area, and the contact surface includes not only the portion perpendicular to the first direction but also the portion parallel to the first direction. This can disperse the stress on the contact surface, improve the mechanical stability of the contact, and reduce the possibility of defects such as cracks on the contact surface. In this way, the reliability of bringing out the internal circuit structure of the semiconductor device from the back side through the third connection structure can be improved. Attached Figure Description
[0044] Figure 1 A schematic flowchart illustrating a method for forming a semiconductor device according to an embodiment of this disclosure;
[0045] Figure 2 A schematic diagram of the semiconductor device formation process provided in the embodiments of this disclosure. Figure 1 ;
[0046] Figure 3 A schematic diagram of the semiconductor device formation process provided in the embodiments of this disclosure. Figure 2 ;
[0047] Figure 4 A schematic diagram of the semiconductor device formation process provided in the embodiments of this disclosure. Figure 3 ;
[0048] Figure 4 A schematic diagram of the semiconductor device formation process provided in the embodiments of this disclosure. Figure 6 ;
[0049] Figure 5 A schematic diagram of the semiconductor device formation process provided in the embodiments of this disclosure. Figure 7 ;
[0050] Figure 6 A schematic diagram of the semiconductor device formation process provided in the embodiments of this disclosure. Figure 8 ;
[0051] Figure 7 A schematic diagram of the semiconductor device formation process provided in the embodiments of this disclosure. Figure 9 ;
[0052] Figure 8 A schematic diagram of the semiconductor device formation process provided in the embodiments of this disclosure.Figure 10 ;
[0053] Figure 9 A schematic diagram of the semiconductor device formation process provided in the embodiments of this disclosure. Figure 11 ;
[0054] Figure 1 Schematic diagram of the structure of the semiconductor device provided in the embodiments of this disclosure Figure 12 ;
[0055] Figure 11 for Figure 13 Cross-sectional view along line AA';
[0056] Figure 1 A three-dimensional structural diagram of the semiconductor device provided in the embodiments of this disclosure. Figure 14 ;
[0057] Figure 2 Schematic diagram of the structure of the semiconductor device provided in the embodiments of this disclosure Figure 15 ;
[0058] Figure 10 A schematic diagram of the semiconductor device formation process provided in the embodiments of this disclosure. Figure 16 ;
[0059] Figure 3 Schematic diagram of the structure of the semiconductor device provided in the embodiments of this disclosure Figure 2 ;
[0060] Figure 1 A three-dimensional structural diagram of the semiconductor device provided in the embodiments of this disclosure. Figure 1 . Detailed Implementation
[0061] Exemplary embodiments of the present disclosure will now be described in more detail with reference to the accompanying drawings. While exemplary embodiments of the present disclosure are shown in the drawings, it should be understood that the present disclosure may be implemented in various forms and should not be limited to the specific embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the disclosure to those skilled in the art.
[0062] In the following description, numerous specific details are set forth in order to provide a more thorough understanding of this disclosure. However, it will be apparent to those skilled in the art that this disclosure may be practiced without one or more of these details. In other instances, to avoid confusion with this disclosure, certain technical features well-known in the art have not been described; that is, not all features of actual embodiments are described herein, nor are well-known functions and structures described in detail.
[0063] In the accompanying drawings, the same reference numerals denote the same elements throughout.
[0064] It should be understood that spatial relation terms such as “below,” “under,” “below,” “below,” “above,” “above,” etc., are used herein for convenience of description to describe the relationship between one element or feature shown in the figure and other elements or features. It should be understood that, in addition to the orientation shown in the figure, spatial relation terms are intended to also include different orientations of the device in use and operation. For example, if the device in the figure is flipped, then the element or feature described as “below” or “below” other elements or features will be oriented “above” other elements or features. Therefore, the exemplary terms “below” and “below” can include both above and below orientations. The device may be otherwise oriented (rotated 90 degrees or otherwise) and the spatial descriptive terms used herein will be interpreted accordingly.
[0065] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit this disclosure. When used herein, the singular forms “a,” “an,” and “the” are also intended to include the plural forms unless the context clearly indicates otherwise. It should also be understood that the terms “comprise” and / or “comprising,” when used in this specification, identify the presence of the stated features, integers, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups. When used herein, the term “and / or” includes any and all combinations of the associated listed items.
[0066] In 3D ICs, vias (Through-Videos) used to expose the internal circuitry of a chip from the back of the chip are typically formed in back-end processes. This means that the internal circuitry is formed first, followed by the formation of vias from the back of the chip. However, the formation of TSVs can easily lead to stress concentration and poor contact between the TSV and other metal layers. Specifically, on the one hand, the TSV formation process involves etching the substrate to create high aspect ratio vias and filling them with metal material. During this process, mechanical stress may be introduced, causing microcracks or delamination at the interface between the TSV and other metal layers. On the other hand, the thermal and / or mechanical stress generated during etching may damage the landing metal layer, potentially preventing the formation of a continuous contact interface between the TSV and the landing metal layer due to grain boundary stress or voids when filling the vias. Furthermore, due to the high aspect ratio of the required vias, the vias may not fully expose the landing metal layer, leading to a significant increase in contact resistance between the TSV and the landing metal layer, and potentially even the formation of an open circuit. The aforementioned issues can reduce the reliability of the connection between the TSV and the landing metal layer, and may further degrade the performance of the 3D IC. Therefore, optimizing the TSV fabrication process has become an urgent problem to be solved.
[0067] The present disclosure provides the following implementation methods.
[0068] This disclosure provides a method for forming a semiconductor device. Figure 2 This is a schematic flowchart of a method for forming a semiconductor device according to an embodiment of the present disclosure, as shown below. Figure 2 As shown, the method for forming a semiconductor device includes the following steps:
[0069] Step S1: Provide a substrate; the substrate includes a substrate and a dielectric layer located on a first side of two opposite sides of the substrate along a first direction;
[0070] Step S2: A plurality of first vias and first trenches are formed in the dielectric layer; the first trenches extend from the top surface of the substrate along the first direction into the dielectric layer; the plurality of first vias all extend from the bottom surface of the first trenches along the first direction into the dielectric layer and are located between the first trenches and the substrate;
[0071] Step S3: A plurality of first connecting structures are formed in the plurality of first through holes, and a second connecting structure is formed in the first trench; the first end of each of the two opposite ends of the plurality of first connecting structures along the first direction is connected to the second connecting structure;
[0072] Step S4: Form a second trench from the second side of the two opposite sides of the substrate along the first direction, extending through the substrate along the first direction, into the dielectric layer, and exposing the plurality of first connection structures; the second trench exposes at least the second end of the two opposite ends of the plurality of first connection structures along the first direction and a portion of the sidewalls;
[0073] Step S5: Form a third connection structure in the second trench.
[0074] The method for forming a semiconductor device provided in this disclosure will now be described in detail with reference to specific examples.
[0075] Reference Figure 4 Step S1 is performed, providing a substrate 10, which includes a substrate 100 and a dielectric layer 101 located on a first side of two opposite sides of the substrate 100 along a first direction. In this embodiment of the disclosure, the first direction may be the Z direction.
[0076] In some specific examples, substrate 100 is a semiconductor substrate. Specifically, substrate 100 may include at least one of elemental semiconductor substrates (e.g., silicon substrates and germanium substrates), compound semiconductor substrates (e.g., gallium arsenide substrates, gallium nitride substrates, silicon carbide substrates), silicon-on-insulator (SOI) substrates, and germanium-on-insulator (GOI) substrates.
[0077] In some specific examples, the dielectric layer 101 may include at least one of dielectric materials such as silicon oxide, silicon nitride, and silicon oxynitride.
[0078] In some embodiments, the substrate 10 may include a core region and a peripheral region arranged in a direction perpendicular to the first direction; the substrate 10 also includes interconnects 102 located in the dielectric layer 101; the interconnects 102 may extend in a direction perpendicular to the first direction and be coupled to the circuit structure in the core region. Here, the core region is the area where the circuit structure is disposed in the semiconductor device, and the circuit structure may be, for example, a memory array including multiple memory cells, a peripheral circuit formed by CMOS process, or other circuit structure, which is not specifically limited in this disclosure. The peripheral region may include Figure 4 The area shown can be used as a setting area for various connection structures, including the third connection structure.
[0079] In some embodiments, in conjunction with reference Figure 2 and Figure 3Step S2 is executed: a plurality of first vias 105 and a first trench 107 are formed in the dielectric layer 101; the first trench 107 extends from the top surface of the substrate 10 along the first direction into the dielectric layer 101; the plurality of first vias 105 extend from the bottom surface of the first trench 107 along the first direction into the dielectric layer 101 and are located between the first trench 107 and the substrate 100.
[0080] In some embodiments, in conjunction with reference Figure 3 and Figure 4 The method for forming a semiconductor device further includes: while forming a plurality of first vias 105, forming a plurality of second vias 106, wherein the plurality of second vias 106 extend from the bottom surface of the first trench 107 along a first direction to expose the interconnect line 102.
[0081] In some embodiments, in conjunction with reference Figure 4 and Figure 5 The dielectric layer 101 is formed with a plurality of first vias 105, a plurality of second vias 106, and a first trench 107. This includes etching the dielectric layer 101 along a first direction on the side of the interconnect layer containing the interconnect 102 that is opposite to the substrate 100 along the first direction, to form a plurality of first initial vias 103 and a plurality of second initial vias 104 extending into the dielectric layer 101 along the first direction. The plurality of second initial vias 104 are located on the side of the interconnect 102 opposite to the substrate 100 along the first direction. Here, the plurality of first initial vias 103 are formed in the region where a third connection structure will subsequently be formed.
[0082] In some embodiments, in conjunction with reference Figure 4 and Figure 5 The method further includes forming a plurality of first vias 105, a plurality of second vias 106, and a first trench 107 in the dielectric layer 101, and etching portions of the dielectric layer 101 penetrated by the plurality of first initial vias 103 and the plurality of second initial vias 104 along a first direction to form the first trench 107; the plurality of first initial vias 103 and the plurality of second initial vias 104 are all connected to the first trench 107; removing a portion of the dielectric layer between the bottom of the plurality of first initial vias 103 and the substrate 100 to form the plurality of first vias 105, and simultaneously removing the dielectric layer between the bottom of the plurality of second initial vias 104 and the interconnect 102 to form the plurality of second vias 106. Here, the plurality of first vias 105 do not expose the substrate 100, and the plurality of second vias 106 expose the interconnect 102.
[0083] In some embodiments, in conjunction with reference Figure 5 and Figure 6Step S3 is executed: a plurality of first connecting structures 108 are formed in a plurality of first through holes 105, and a second connecting structure 110 is formed in a first groove 107; the first end of each of the two opposite ends of the plurality of first connecting structures 108 along the first direction is connected to the second connecting structure 110.
[0084] In some embodiments, in conjunction with reference Figure 6 to Figure 10 and Figure 6 The method for forming a semiconductor device further includes: forming a plurality of fourth connection structures 109 in a plurality of second vias 106; after forming a second connection structure 110, the plurality of fourth connection structures 109 are all connected to the second connection structure 110.
[0085] In some specific examples, the multiple first connection structures 108, the multiple fourth connection structures 109, and the second connection structure 110 may include the same conductive material. In this case, the conductive material can be filled into the multiple first through holes 105, the multiple second through holes 106, and the first trench 107 simultaneously to form the multiple first connection structures 108, the multiple fourth connection structures 109, and the second connection structure 110.
[0086] In other specific examples, forming a plurality of first connection structures 108 in a plurality of first through holes 105 includes: filling the plurality of first through holes 105 with a first conductive material to form a plurality of first connection structures 108; forming a second connection structure 110 in a first trench 107 includes: filling the first trench 107 with a second conductive material to form a second connection structure 110; the second conductive material is different from the first conductive material. Here, the plurality of first connection structures 108 and the second connection structure 110 may each include different conductive materials.
[0087] In some specific examples, the first conductive material may include titanium or tungsten, and the second conductive material may include one of copper, nickel, aluminum, or gold.
[0088] In some embodiments, in conjunction with reference Figure 7 and Figure 7 After performing step S3, a semiconductor structure 200 can be formed on the substrate 10. Here, the semiconductor structure 200 may include multiple layer structures, such as an interconnect layer formed on the substrate or another chip bonded to the substrate. If the core region in the substrate includes a memory array, the other chip may include peripheral circuitry coupled to the memory array. If the core region in the substrate includes peripheral circuitry, the other chip may include a memory array coupled to the peripheral circuitry. This disclosure does not impose any specific limitations in this regard.
[0089] In some embodiments, in conjunction with reference Figure 8Step S4 is executed: a second trench 305 is formed from the second side of the two opposite sides of the substrate 100 along the first direction, extending through the substrate 100 along the first direction, into the dielectric layer 101, and exposing a plurality of first connection structures 108; the second trench 305 exposes at least the second end of the two opposite ends of the plurality of first connection structures 108 along the first direction and part of the sidewalls.
[0090] In some embodiments, in conjunction with reference Figure 8 and Figure 9 The method for forming a semiconductor device further includes forming a mask layer 301 covering a second side of the substrate 100 before forming the second trench 305. Here, the substrate 100 can be thinned first, and then the mask layer 301 can be formed on the thinned substrate 100.
[0091] In some embodiments, in conjunction with reference Figure 9 and Figure 10 Using the mask layer 301 as a mask, the substrate 100 and a portion of the dielectric layer 101 located between the plurality of first connection structures 108 and the substrate 100 are etched along the first direction to form a third trench 302 that penetrates the substrate 100 and extends into the dielectric layer 101 along the first direction.
[0092] In some specific examples, a third trench 302 with a high aspect ratio can be formed by a deep reactive ion etching (DRIE) process, such as the Bosch etching process.
[0093] In some embodiments, in conjunction with reference Figure 10 and Figure 11 The method for forming a semiconductor device further includes forming an initial insulating layer 303 covering the inner wall of the third trench 302 and the mask layer 301. Here, the material of the initial insulating layer 303 may include, but is not limited to, insulating dielectric materials such as silicon oxide, silicon nitride, and silicon oxynitride.
[0094] In some embodiments, in conjunction with reference Figure 12 and Figure 11The method for forming a semiconductor device further includes: etching an initial insulating layer 303 located at the bottom of a third trench 302 and a dielectric layer 101 located between the bottom of the third trench 302 and the second interconnect structure 110 along a first direction to form a second trench 305; the remaining initial insulating layer 303 constitutes an insulating layer 304, which is located at least between the second trench 305 and the substrate 100. Here, during the further etching of the initial insulating layer 303 and the dielectric layer 101 from the bottom of the third trench 302, the initial insulating layer 303 covering the sidewalls of the third trench 302 can serve as a protective layer to reduce the damage to the trench sidewalls caused by the etching process. Furthermore, the insulating layer 304 can serve as an isolation layer between the subsequently formed third interconnect structure and the substrate 100, so that the third interconnect structure and the substrate 100 can achieve insulation isolation.
[0095] In some embodiments, in conjunction with reference Figure 12 and Figure 13 Step S5: Forming a third connection structure 306 in the second trench 305. In some specific examples, forming the third connection structure 306 in the second trench 305 includes filling the second trench 305 with a third conductive material to form the third connection structure 306.
[0096] In some specific examples, the third conductive material included in the third connection structure 306 may be the same as or different from the first conductive material included in the plurality of first connection structures 108.
[0097] In some specific examples, the first conductive material includes titanium or tungsten, the second conductive material includes one of copper, nickel, aluminum, and gold, and the third conductive material includes copper or tungsten.
[0098] In this embodiment, after the second trench 305 is formed, the plurality of first connection structures 108 are re-exposed. When the plurality of first connection structures 108 include titanium or tungsten, they can have high strength and are not easily deformed, that is, they can still maintain their shape after being exposed. This is beneficial for forming a more regular contact surface with the third connection structure 306 formed in the second trench 305, thereby improving the performance consistency between different batches of semiconductor devices. In addition, the third conductive material may include copper or tungsten, which has good filling properties, which is beneficial for forming a more complete filling between the plurality of first connection structures 108 exposed by the second trench 305.
[0099] In some specific examples, Figure 11 for Figure 12 A cross-sectional view along line AA' and perpendicular to the Z direction, refer to... Figure 13Multiple first connection structures 108 can be arranged in an array along a second direction and a third direction, and both the second direction and the third direction are perpendicular to the first direction. Here, the second direction can be, for example, the Y direction, and the angle between the second direction and the third direction can be, for example, 60 degrees. A third connection structure 306 can surround multiple first connection structures 108.
[0100] In some specific examples, Figure 12 This is a three-dimensional structural diagram of a semiconductor device provided in an embodiment of this disclosure. For ease of observation, only the third connection structure 306, the second connection structure 110, the plurality of first connection structures 108, the dielectric layer 101, and the substrate 100 are shown in the three-dimensional structural diagram, and these structures are all perspective views. (Refer to reference...) Figure 13 , Figure 12 and Figure 14 The third connecting structure 306 is connected to at least the second end of one of the two ends of the plurality of first connecting structures 108 that are opposite each other in the first direction, as well as part of the sidewall. That is, the bottom of the third connecting structure 306 can surround a part of the plurality of first connecting structures 108, thereby allowing the third connecting structure 306 and the plurality of first connecting structures 108 to have a large contact area.
[0101] It should be noted that, Figure 9 and Figure 15 Taking the circular cross-sectional shape of the first connecting structure 108 and the third connecting structure 306 as an example, this disclosure is not limited to this. In other embodiments, the cross-sections of the first connecting structure 108 and the third connecting structure 306 can also be rectangular, elliptical, or other shapes. Furthermore, Figure 15 The number and specific arrangement of the first connection structures 108 shown are merely examples. Under the condition that they are arranged in a second direction and a third direction perpendicular to the first direction, this disclosure does not limit the number and arrangement of the multiple first connection structures 108.
[0102] In this embodiment of the present disclosure, a plurality of first connection structures 108 and second connection structures 110 can be formed in the preceding process. The connection between the plurality of first connection structures 108 and second connection structures 110 has high reliability. Furthermore, a second trench 305 penetrating the substrate 100 can be formed from the back side of the semiconductor device in the subsequent process. Since a plurality of first connection structures 108 are formed in advance, the size of the formed second trench 305 in the first direction can be relatively small. As a result, the process window of the etching process can be increased, the time required for the etching process can be shortened, and the thermal and mechanical stress generated by the etching process can be reduced. Furthermore, a third connection structure 306 can be formed in the second trench 305 exposing the plurality of first connection structures 108. The third connection structure 306 is connected to at least the second end and part of the sidewall of the two ends of the plurality of first connection structures 108 opposite to each other along the first direction. Thus, the third connection structure 306 and the plurality of first connection structures 108 can have a large contact area, and the contact surface includes not only the part perpendicular to the first direction, but also the part parallel to the first direction. This can disperse the stress on the contact surface, improve the mechanical stability of the contact, and reduce the possibility of defects such as cracks on the contact surface. This can improve the reliability of bringing out the internal circuit structure of the semiconductor device from the back side through the third connection structure 306.
[0103] In some embodiments, refer to Figure 16 The method for forming a semiconductor device may further include: forming a pad lead-out layer 307, wherein the pad lead-out layer 307 may include lead-out pads for external connection with the semiconductor device, and the lead-out pads may be coupled to a third connection structure 306. Thus, the internal circuit structure of the semiconductor device may be coupled to the outside in sequence through interconnects 102, multiple fourth connection structures 109, a second connection structure 110, multiple first connection structures 108, a third connection structure 306, and the lead-out pads. Here, the lead-out pads may be further connected to data lines or power lines outside the semiconductor device, so that power signals or data signals may be transmitted to the inside of the semiconductor device in sequence through the lead-out pads, the third connection structure 306, multiple first connection structures 108, a second connection structure 110, multiple fourth connection structures 109, and interconnects 102. In this transmission path, since the reliability of the connection between the third connection structure 306 and the second connection structure 110 can be improved by the multiple first connection structures 108, the transmission rate and reliability of power signals or data signals can be further improved.
[0104] The above embodiment takes the connection between the formed third connecting structure and the second end and part of the sidewall of the plurality of first connecting structures as an example. In other embodiments, the third connecting structure may also be connected to the entire sidewall of the plurality of first connecting structures.
[0105] Combined with referenceFigure 11 and Figure 11 After forming the initial insulating layer 303, the initial insulating layer 303 at the bottom of the third trench 302 and all the dielectric layer 101 between the bottom of the third trench 302 and the second connection structure 110 can be further removed by etching to form the second trench 305'. The second trench 305' can then expose the second end of one of the two opposite ends of the plurality of first connection structures 108 along the first direction and the entire sidewall. Here, since a plurality of first connection structures 108 are formed in the dielectric layer 101 between the bottom of the third trench 302 and the second connection structure 110, the volume of dielectric material to be removed by etching is smaller than that in the case where no plurality of first connection structures 108 are formed. Therefore, the process window of the etching process can be increased, and the residual dielectric material between the bottom of the formed second trench 305' and the second connection structure 110 can be reduced.
[0106] Furthermore, in conjunction with reference Figure 12 and Figure 11 A third connection structure 306' is formed in the second groove 305'. The third connection structure 306' can be connected to the second end of the two opposite ends of the plurality of first connection structures 108 along the first direction and the entire sidewall. This can further increase the contact area between the plurality of first connection structures 108 and the third connection structure 306', and the third connection structure 306' can also contact the second connection structure 110, thereby further reducing the contact resistance and improving the reliability of the connection.
[0107] Based on a concept similar to the semiconductor device formation method described above, this disclosure also provides a semiconductor device that can be obtained by the semiconductor device formation method provided in any of the above embodiments.
[0108] In some embodiments, refer to Figure 13 The semiconductor device includes: a substrate 100; a dielectric layer 101 located on a first side of two opposite sides of the substrate 100 along a first direction; a plurality of first connection structures 108 and a second connection structure 110 located in the dielectric layer 101; the plurality of first connection structures 108 extending along the first direction and located between the substrate 100 and the second connection structure 110; a first end of each of the two opposite ends of the plurality of first connection structures 108 along the first direction being connected to the second connection structure 110; and a third connection structure 306 penetrating the substrate 100 along the first direction; the third connection structure 306 extending along the first direction into the dielectric layer 101, and the third connection structure 306 being connected to at least a second end of one of the two opposite ends of the plurality of first connection structures 108 along the first direction and a portion of the sidewalls of the plurality of first connection structures 108. Here, the first direction can be the Z direction.
[0109] In some specific examples, substrate 100 is a semiconductor substrate. Specifically, substrate 100 may include at least one of elemental semiconductor substrates (e.g., silicon substrates and germanium substrates), compound semiconductor substrates (e.g., gallium arsenide substrates, gallium nitride substrates, silicon carbide substrates), silicon-on-insulator (SOI) substrates, and germanium-on-insulator (GOI) substrates.
[0110] In some specific examples, the dielectric layer 101 may include at least one of dielectric materials such as silicon oxide, silicon nitride, and silicon oxynitride.
[0111] In some embodiments, the semiconductor device includes a core region and a peripheral region arranged along a direction perpendicular to a first direction; a third connection structure 306 is located in the peripheral region; here, the core region is the area where the circuit structure is disposed in the semiconductor device, and the circuit structure may be, for example, a memory array including multiple memory cells, a peripheral circuit formed by CMOS technology, or other circuit structures, which are not specifically limited in this disclosure. The peripheral region may include Figure 12 The area shown can be used as a setting area for various connection structures, including the third connection structure.
[0112] In some embodiments, the semiconductor device further includes: an interconnect 102 located in a dielectric layer 101; the interconnect 102 extending in a direction perpendicular to a first direction and coupled to a circuit structure in a core region; a plurality of fourth connection structures 109 located in the dielectric layer 101; the plurality of fourth connection structures 109 located in a first direction between a second connection structure 110 and the interconnect 102; the plurality of fourth connection structures 109 all extending in a first direction and all connected to the second connection structure 110; and a third connection structure 306 coupled to the interconnect 102 through a plurality of first connection structures 108, a second connection structure 110 and a plurality of fourth connection structures 109.
[0113] In this embodiment of the present disclosure, the third connection structure 306 penetrating the substrate 100 is connected to at least the second end of one of the two ends of the plurality of first connection structures 108 opposite to each other along the first direction and a portion of the sidewall. Thus, the third connection structure 306 and the plurality of first connection structures 108 can have a large contact area, and the contact surface includes not only the portion perpendicular to the first direction but also the portion parallel to the first direction. This can disperse the stress on the contact surface, improve the mechanical stability of the contact, and reduce the possibility of defects such as cracks on the contact surface. In this way, the reliability of bringing out the internal circuit structure of the semiconductor device from the back side through the third connection structure 306 can be improved.
[0114] In some specific examples, Figure 13 for Figure 14 A cross-sectional view along line AA' and perpendicular to the Z direction. Figure 16This is a three-dimensional structural schematic diagram of a semiconductor device provided in an embodiment of this disclosure, in conjunction with reference to... Figure 17 and Figure 16 Multiple first connecting structures 108 can be arranged in an array along a second direction and a third direction, both of which are perpendicular to the first direction. Here, the second direction can be, for example, the Y direction, and the angle between the second direction and the third direction can be, for example, 60 degrees. A third connecting structure 306 can surround the multiple arrayed first connecting structures 108. The stress on the contact surface between the third connecting structure 306 and the multiple first connecting structures 108 can be dispersed in various directions perpendicular to the first direction. This can further improve the mechanical stability of the contact between the third connecting structure 306 and the multiple first connecting structures 108 and reduce the possibility of defects such as cracks on the contact surface.
[0115] In some embodiments, a plurality of first connection structures 108 include a first conductive material; a second connection structure 110 includes a second conductive material; the second conductive material is different from the first conductive material.
[0116] In some embodiments, the third connection structure 306 includes a third conductive material; the third conductive material is different from the first conductive material.
[0117] In some specific examples, the first conductive material includes titanium or tungsten, the second conductive material includes one of copper, nickel, aluminum, and gold, and the third conductive material includes copper or tungsten.
[0118] In this embodiment, the plurality of first connecting structures 108 include titanium or tungsten, which have high strength and are not easily deformed, thus facilitating the maintenance of a reliable connection between the second connecting structure 110 and the third connecting structure 306.
[0119] In some embodiments, the semiconductor device further includes: an insulating layer 304 located at least between the substrate 100 and the third connection structure 306; a portion of the third connection structure 306 connected to a plurality of first connection structures 108 protrudes relative to the insulating layer 304 in a first direction. Here, the insulating layer 304 can provide insulation between the third connection structure 306 and the substrate 100 to prevent leakage current from occurring between the substrate 100 and the third connection structure 306.
[0120] In some embodiments, refer to Figure 17 The semiconductor device may also include: a semiconductor structure 200 and a pad lead-out layer 307.
[0121] In some specific examples, the semiconductor structure 200 may include multiple layer structures, such as interconnect layers formed on a substrate or another chip bonded to the substrate. If the core region in the substrate includes a memory array, the other chip may include peripheral circuitry coupled to the memory array. This disclosure does not impose any specific limitations on this.
[0122] In some specific examples, the pad lead-out layer 307 may include lead-out pads for external connection to the semiconductor device. These lead-out pads may be coupled to the third connection structure 306. Thus, the internal circuitry of the semiconductor device can be coupled to the external environment sequentially via interconnect 102, multiple fourth connection structures 109, second connection structure 110, multiple first connection structures 108, third connection structure 306, and the lead-out pads. Here, the lead-out pads may be further connected to external data lines or power lines of the semiconductor device. Power signals or data signals can then be transmitted to the interior of the semiconductor device sequentially via the lead-out pads, third connection structure 306, multiple first connection structures 108, second connection structure 110, multiple fourth connection structures 109, and interconnect 102. In this transmission path, since the reliability of the connection between the third connection structure 306 and the second connection structure 110 can be improved by the multiple first connection structures 108, the transmission rate and reliability of power signals or data signals can be further improved.
[0123] In other embodiments, This is a schematic diagram of the structure of a semiconductor device provided in an embodiment of this disclosure. This is a three-dimensional structural schematic diagram of a semiconductor device provided in an embodiment of this disclosure, in conjunction with reference to... and The entire sidewalls of the multiple first connecting structures 108 and the second connecting structure 110 are connected to the third connecting structure 306. Here, the contact area between the multiple first connecting structures 108 and the third connecting structure 306' can be further increased, and the third connecting structure 306' can also contact the second connecting structure 110, thereby further reducing the contact resistance and improving the reliability of the connection.
[0124] The methods disclosed in the several method embodiments provided in this disclosure can be arbitrarily combined without conflict to obtain new method embodiments.
[0125] The features disclosed in the several device embodiments provided in this disclosure can be arbitrarily combined without conflict to obtain new device embodiments.
[0126] The above description is merely a specific embodiment of this disclosure, but the scope of protection of this disclosure is not limited thereto. Any changes or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this disclosure should be included within the scope of protection of this disclosure.
Claims
1. A method for forming a semiconductor device, characterized in that, include: Provide a base; The substrate includes a substrate and a dielectric layer located on a first side of the substrate along a first direction; The first direction is perpendicular to the substrate; A plurality of first through holes and first trenches are formed in the dielectric layer; the first trenches extend from the top surface of the substrate in the opposite direction to the first direction into the dielectric layer; The plurality of first vias extend from the bottom surface of the first trench in the opposite direction to the first direction into the dielectric layer and are located between the first trench and the substrate. A plurality of first connecting structures are formed in the plurality of first through holes, and a second connecting structure is formed in the first groove; the first ends of the plurality of first connecting structures along the first direction are all connected to the second connecting structure. A second trench is formed from a second side of the substrate in the opposite direction to the first direction, extending through the substrate in the first direction, into the dielectric layer, and exposing the plurality of first connection structures; The second trench exposes the second ends of the plurality of first connecting structures in the opposite direction to the first direction and the entire sidewall, and the second trench exposes the second connecting structure; A third connection structure is formed in the second trench; the plurality of first connection structures and the second connection structure are all connected to the third connection structure.
2. The method for forming a semiconductor device according to claim 1, characterized in that, The substrate includes a core region and a peripheral region arranged in a direction perpendicular to the first direction; the third connection structure is formed in the peripheral region; the substrate also includes interconnects located in the dielectric layer; The interconnect extends along a direction perpendicular to the first direction and is coupled to the circuit structure in the core region; the forming method further includes: While forming the plurality of first vias, a plurality of second vias are formed in the dielectric layer, and the plurality of second vias extend from the bottom surface of the first trench in the opposite direction to the first direction to expose the interconnects; A plurality of fourth connection structures are formed in the plurality of second through holes; after the second connection structure is formed, the plurality of fourth connection structures are all connected to the second connection structure; after the third connection structure is formed, the third connection structure is coupled to the interconnect line through the plurality of first connection structures, the second connection structure and the plurality of fourth connection structures.
3. The method for forming a semiconductor device according to claim 2, characterized in that, Forming the plurality of first through-holes, the plurality of second through-holes, and the first trench in the dielectric layer includes: The dielectric layer located on the side of the interconnect layer away from the substrate along the first direction is etched in the opposite direction of the first direction to form a plurality of first initial vias extending into the dielectric layer in the opposite direction of the first direction and a plurality of second initial vias extending into the dielectric layer in the opposite direction of the first direction; the plurality of second initial vias are located on the side of the interconnect away from the substrate along the first direction. The portion of the dielectric layer penetrated by the plurality of first initial vias and the plurality of second initial vias is etched in the opposite direction to the first direction to form the first trench; the plurality of first initial vias and the plurality of second initial vias are all connected to the first trench; A portion of the dielectric layer between the bottom of the plurality of first initial vias and the substrate is removed to form the plurality of first vias. Simultaneously, the dielectric layer between the bottom of the plurality of second initial vias and the interconnect is removed to form the plurality of second vias.
4. The method for forming a semiconductor device according to claim 1, characterized in that, The forming method further includes: Before forming the second trench, a mask layer is formed covering the second side of the substrate; Using the mask layer as a mask, the substrate and a portion of the dielectric layer located between the plurality of first connection structures and the substrate are etched along the first direction to form a third trench that penetrates the substrate and extends into the dielectric layer along the first direction. An initial insulating layer is formed covering the inner wall of the third trench and the mask layer; The initial insulating layer located at the bottom of the third trench and the dielectric layer located between the bottom of the third trench and the second connection structure are etched along the first direction to form the second trench; the remaining initial insulating layer constitutes an insulating layer, which is located at least between the second trench and the substrate.
5. The method for forming a semiconductor device according to claim 1, characterized in that, The step of forming a plurality of first connection structures in the plurality of first through holes includes: filling the plurality of first through holes with a first conductive material to form the plurality of first connection structures; The step of forming a second connection structure in the first trench includes: filling the first trench with a second conductive material to form the second connection structure; the second conductive material is different from the first conductive material.
6. The method for forming a semiconductor device according to claim 5, characterized in that, The formation of the third connection structure in the second trench includes: A third conductive material is filled into the second trench to form the third connection structure; the third conductive material is different from the first conductive material.
7. A semiconductor device, characterized in that, include: Substrate; A dielectric layer located on a first side of the substrate along a first direction; The first direction is perpendicular to the substrate; A plurality of first connection structures and second connection structures are located in the dielectric layer; the plurality of first connection structures all extend along the first direction and are located between the substrate and the second connection structure; the first ends of the plurality of first connection structures along the first direction are all connected to the second connection structure; A third connection structure extending through the substrate along the first direction; the third connection structure extending into the dielectric layer along the first direction, and the third connection structure being connected to the second end of the plurality of first connection structures in the opposite direction of the first direction and the entire sidewall of the plurality of first connection structures, and the third connection structure being connected to the second connection structure.
8. The semiconductor device according to claim 7, characterized in that, The plurality of first connection structures are arranged in an array along a second direction and a third direction; the second direction intersects with the third direction and is perpendicular to the first direction.
9. The semiconductor device according to claim 7, characterized in that, The semiconductor device includes a core region and a peripheral region arranged along a direction perpendicular to the first direction; The third connection structure is located in the peripheral region; The semiconductor device further includes: Interconnects located in the dielectric layer; the interconnects extend in a direction perpendicular to the first direction and are coupled to the circuit structure in the core region; A plurality of fourth connection structures are located in the dielectric layer; the plurality of fourth connection structures are located between the second connection structure and the interconnect in the first direction; the plurality of fourth connection structures all extend along the first direction and are all connected to the second connection structure; the third connection structure is coupled to the interconnect through the plurality of first connection structures, the second connection structure and the plurality of fourth connection structures.
10. The semiconductor device according to claim 8, characterized in that, The semiconductor device further includes: An insulating layer is located at least between the substrate and the third connection structure; the portion of the third connection structure that connects to the plurality of first connection structures protrudes relative to the insulating layer in the first direction.
11. The semiconductor device according to claim 7, characterized in that, The plurality of first connection structures include a first conductive material; the second connection structure includes a second conductive material; the second conductive material is different from the first conductive material.
12. The semiconductor device according to claim 11, characterized in that, The third connection structure includes a third conductive material; the third conductive material is different from the first conductive material.
13. The semiconductor device according to claim 12, characterized in that, The first conductive material includes titanium or tungsten, the second conductive material includes one of copper, nickel, aluminum, and gold, and the third conductive material includes copper or tungsten.
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