Multistage crossbar switch system, chip and data transmission method thereof
By employing a hierarchical design of a multi-level cross switch system and a hybrid decoder arbitrator strategy, the complexity and scalability issues of traditional full cross switches in large-scale on-chip interconnect networks are resolved, achieving efficient data transmission and protocol compliance while reducing latency and power consumption.
Patent Information
- Application Number
- CN202511273575.5
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-09-08
- Publication Date
- 2025-12-09
AI Technical Summary
Traditional full-crossover switch architectures face challenges in large-scale on-chip interconnect networks, including complexity, area overhead, and critical path timing degradation. Interconnect latency and power consumption are particularly prominent in high-frequency design scenarios, limiting scalability.
A multi-level cross switch system is adopted, which is decomposed into multiple small cross switch units. A hierarchical interconnection design is used, and static and dynamic decoder and arbitrator strategies are combined to achieve a balance between high throughput and complexity. Data transmission order is ensured through remapping mechanism and deadlock avoidance mechanism.
It significantly reduces interconnect complexity and area overhead, optimizes system scalability, improves data transmission efficiency, is compatible with traditional algorithms and adapts to traffic patterns, and meets AXI protocol requirements.
Smart Images
Figure CN121098296A_ABST
Abstract
Description
Technical Field
[0001] This invention belongs to the field of on-chip interconnect network technology, and relates to a multi-level cross switch system, chip and its data transmission method. Background Technology
[0002] As the core data path of routers in on-chip interconnect networks, the crossbar switch's essential function is to enable efficient transmission of data bits from input ports to output ports. Current mainstream technologies employ a full crossbar switch architecture, with a typical structure shown in the attached figure. Figure 1 As shown, the left side has N slave ports connected to N external hosts, and the right side has M host ports connected to M external slaves. A default slave is also typically integrated to handle invalid address requests and generate responses. In this architecture, a standard NM AXI interconnect is usually implemented using N-(M+1) full crossover switches.
[0003] The core components of a crossbar switch include two main functional modules: a decoder and an arbitrator. The decoder is typically deployed at the source of the data stream, accurately determining the destination of the data transmission by parsing the address field in the request information. The arbitrator, located at the destination of the data stream, selects the optimal request from multiple concurrent requests based on a pre-defined arbitration algorithm to ensure the orderly transmission of data.
[0004] Modern advanced solutions generally adopt a Multiple Address Multiple Data (MAMD) architecture design, in which each physical port fully implements the five independent channels specified by the AXI protocol: AR (Read Address), R (Read Data), AW (Write Address), W (Write Data), and B (Write Response). This architecture, in addition to satisfying the channel dependency requirements of the AXI protocol itself, also achieves physical isolation and parallel operation of the five subnets, ensuring that each subnet does not interfere with the others, significantly improving system throughput.
[0005] Full-cross switches exhibit significant advantages in small-scale on-chip interconnect scenarios, enabling efficient data transmission through their rich interconnect paths. However, with the continuous expansion of on-chip network scale and the increasing number of host devices, the interconnect paths of full-cross switches become exceptionally complex. This complexity directly leads to a sharp increase in area overhead and severe deterioration of critical path timing, posing a serious challenge to the scalability of traditional architectures. Especially in high-frequency design scenarios, interconnect latency and power consumption issues become more prominent, urgently requiring innovative breakthroughs in new architectures. Summary of the Invention
[0006] To address the problems existing in the background art, the present invention provides a multi-level cross switch system, chip, and data transmission method thereof.
[0007] The technical solution adopted in this invention is:
[0008] The present invention includes N input ports, M output ports, R primary cross switches and one secondary cross switch. Each primary cross switch includes S first input ports and T first output ports, and the S first input ports and T first output ports are in a fully cross structure. The secondary cross switch includes Q second input ports and M second output ports, and the Q second input ports and M second output ports are in a fully cross structure.
[0009] The first input ports of the R primary cross switches are connected one-to-one with the N input ports of the multi-level cross switch system, the first output ports of the R primary cross switches are connected one-to-one with the Q second input ports of the secondary cross switches, and the M second output ports of the secondary cross switches are connected one-to-one with the M output ports of the multi-level cross switch system, where N = R * S and Q = R * T.
[0010] When a multi-level crossbar switch system is applied to a request network, each first-level crossbar switch includes S first input ports, T first output ports, S first-level decoders, and T first-level arbitrators. The S first-level decoders and the S first input ports are connected one-to-one, the T first-level arbitrators and the T first output ports are connected one-to-one, any one-level decoder is connected to the T first-level arbitrators, and any one-level arbitrator is connected to the S first-level decoders.
[0011] The secondary cross switch includes Q second input ports, M second output ports, Q secondary decoders, and M secondary arbitrators. The Q secondary decoders are connected one-to-one with the Q second input ports, the M secondary arbitrators are connected one-to-one with the M second output ports, any secondary decoder is connected to all M secondary arbitrators, and any secondary arbitrator is connected to all Q secondary decoders.
[0012] The first-level decoder is a dynamic path selection decoder, and the second-level decoder is an address decoder.
[0013] When a multi-level cross switch system is applied to a response network, each first-level cross switch includes S first input ports, T first output ports, T first-level decoders, and S first-level arbitrators. The T first-level decoders and the T first output ports are connected one-to-one, the S first-level arbitrators and the S first input ports are connected one-to-one, any one-level decoder is connected to each of the S first-level arbitrators, and any one-level arbitrator is connected to each of the T first-level decoders.
[0014] The two-level crossbar switch includes Q second input ports, M second output ports, M second-level decoders, and Q second-level arbitrators. The M second-level decoders and the M second output ports are connected one-to-one, the Q second-level arbitrators and the Q second input ports are connected one-to-one, any one of the two-level decoders is connected to each of the Q second-level arbitrators, and any one of the two-level arbitrators is connected to each of the M second-level decoders.
[0015] The first-level decoder is an address decoder, and the second-level decoder is a dynamic path selection decoder.
[0016] The dynamic path selection decoder selects an output port for data forwarding according to a preset path selection strategy, which is one of the following three strategies:
[0017] (1) Static allocation strategy: The correspondence between input ports and output ports is established by looking up a table according to predefined mapping rules, and then the output port is selected according to the correspondence between input ports and output ports;
[0018] (2) Polling allocation strategy: Select output ports sequentially according to the preset output port order;
[0019] (3) Dynamic allocation strategy: Set the output port priority according to the size of the free space in the output port buffer, and then select the output port according to the output port priority.
[0020] Both the primary and secondary arbitrators transmit the output data of the primary and secondary decoders to the first and second output ports selected by the corresponding decoders, respectively, according to a preset arbitration strategy.
[0021] A data transmission method using a multi-level cross switch system includes the following steps:
[0022] S1. Request Phase: Receive a data transmission request from the input port of the multi-level cross switch system. The data transmission request includes a transaction ID.
[0023] S2. The data transmission request enters the first-level crossbar switch and the second-level crossbar switch in sequence, and the sequence information of the first and second input ports are respectively appended to the transaction ID in the data transmission request to obtain a data transmission request with a second appended ID.
[0024] S3. Subsequently, the secondary cross switch performs ID compression processing on the secondary additional ID data transmission request according to the preset ID remapping table to obtain the ID compressed data transmission request.
[0025] S4. Recovery Phase: Based on the ID remapping table, the data transmission request with compressed ID is used to recover the ID and obtain the data transmission request with the recovered ID. Then, based on the transaction ID of the data transmission request with the recovered ID, the path is identified to realize data recovery.
[0026] A chip that includes a multi-stage cross switch system.
[0027] The beneficial effects of this invention are:
[0028] The multi-level cross-connector architecture proposed in this invention offers significant technical advantages over traditional full-cross-connector networks. In terms of architecture design, by decomposing the traditional large-scale full-cross-connector network into multiple optimized small cross-connector units, a hierarchical reconstruction of the network topology is achieved. By employing a layered interconnection scheme, the first-level cross-connectors select appropriate paths, and the second-level cross-connectors achieve global interconnection, achieving a balance between high throughput and the complexity of full-cross-connector networks. This innovative architecture not only significantly reduces interconnection complexity but also optimizes area. First, the hierarchical network topology significantly reduces overall area overhead; second, the distributed arbitration mechanism effectively improves the timing of critical paths; and finally, modular design enhances the system's scalability and flexibility.
[0029] This invention provides a variety of decoder and arbitrator strategies that combine static and dynamic approaches. The static strategy ensures transmission determinism through predefined mapping rules, while the dynamic strategy implements intelligent routing based on real-time network conditions. This hybrid design is compatible with traditional fixed algorithms and can automatically adjust according to current traffic patterns, achieving optimal bandwidth balance and adaptive routing.
[0030] Regarding data transmission, this invention incorporates a remapping mechanism and a deadlock avoidance mechanism. Through dynamic ID expansion / compression technology and a request tracing system, it effectively solves the sequential problem of same-origin, same-ID transmissions while ensuring protocol compliance. Attached Figure Description
[0031] Figure 1 This is a schematic diagram of a traditional full-cross switch NM interconnect architecture;
[0032] Figure 2 This is a schematic diagram of the two-stage cross switch NM interconnect architecture of the present invention;
[0033] Figure 3 This is a schematic diagram of the 12-2 interconnect decoder for the two-stage cross switch of the present invention;
[0034] Figure 4 This is a schematic diagram of the 12-2 interconnected arbitrator for the second-level cross-connection of the present invention;
[0035] Figure 5 This is a schematic diagram of the interconnection ID processing element of the secondary cross switch 12-2 of the present invention. Detailed Implementation
[0036] The present invention will be further described below with reference to the accompanying drawings and embodiments. The embodiments of the present invention include, but are not limited to, the following embodiments.
[0037] This embodiment includes N input ports, M output ports, R primary cross switches, and one secondary cross switch. Each primary cross switch includes S first input ports and T first output ports, with a full cross structure between the S first input ports and T first output ports, used for path selection and data forwarding of data transmission requests input from the input terminals. The secondary cross switch includes Q second input ports and M second output ports, also with a full cross structure between the Q second input ports and M second output ports, used for data forwarding of data output from all primary cross switches based on the target address information carried in the data.
[0038] The first input ports of R primary cross switches (a total of R*S) are connected one-to-one with the N input ports of the multi-stage cross switch system. The first output ports of R primary cross switches are connected one-to-one with the second input ports of secondary cross switches. The second output ports of secondary cross switches are connected one-to-one with the M output ports of the multi-stage cross switch system. Where N = R*S and Q = R*T.
[0039] A full crossover structure means that any one of the input ports can establish a data transmission path with any one of the output ports, achieving complete interconnection between inputs and outputs.
[0040] Specifically, each primary cross switch establishes S*T routing paths between S first input ports and T first output ports, and the secondary cross switch establishes R*T*M routing paths between R*T second input ports and M second output ports.
[0041] The multi-level cross switch system provided by this invention can be applied to different network structures. When the multi-level cross switch system is applied to a request network, each first-level cross switch includes S first input ports, T first output ports, S first-level decoders and T first-level arbitrators. The S first-level decoders are connected one-to-one with the S first input ports, the T first-level arbitrators are connected one-to-one with the T first output ports, any one first-level decoder is connected to each of the T first-level arbitrators, and any one first-level arbitrator is connected to each of the S first-level decoders.
[0042] The two-level crossbar switch includes Q second input ports, M second output ports, Q second-level decoders, and M second-level arbitrators. The Q second-level decoders are connected one-to-one with the Q second input ports, the M second-level arbitrators are connected one-to-one with the M second output ports, any one of the second-level decoders is connected to each of the M second-level arbitrators, and any one of the second-level arbitrators is connected to each of the Q second-level decoders.
[0043] When a multi-level crossbar switch system is applied to a request network, it means that the multi-level crossbar switch system is used in a network structure that processes request data. The data flow direction is: from the input port to the first-level crossbar switch, to the second-level crossbar switch, and to the output port.
[0044] When processing request data, the request data enters the first-level crossbar switch from the system's input port, enters the second-level crossbar switch after dynamic path selection by the first-level decoder, is then parsed by the second-level decoder to resolve the target address, selects the output port through the second-level arbitrator, and is finally output from the system's output port.
[0045] When a multi-level cross switch system is applied to a response network, each first-level cross switch includes S first input ports, T first output ports, T first-level decoders, and S first-level arbitrators. The T first-level decoders and the T first output ports are connected one-to-one, the S first-level arbitrators and the S first input ports are connected one-to-one, any one-level decoder is connected to each of the S first-level arbitrators, and any one-level arbitrator is connected to each of the T first-level decoders.
[0046] The two-level crossbar switch includes Q second input ports, M second output ports, M second-level decoders, and Q second-level arbitrators. The M second-level decoders and M second output ports are connected one-to-one, the Q second-level arbitrators and Q second input ports are connected one-to-one, any one of the two-level decoders is connected to each of the Q second-level arbitrators, and any one of the two-level arbitrators is connected to each of the M second-level decoders.
[0047] When a multi-stage crossbar switch system is applied to a response network, it means that the multi-stage crossbar switch system is used in the network structure for processing response data, and the data flow direction is: from the output port to the second-stage crossbar switch, to the first-stage crossbar switch, and to the input port.
[0048] When processing the response data, the response data enters the secondary crossbar switch from the system's output port, undergoes dynamic path selection by the secondary decoder, enters the primary crossbar switch, is then parsed by the primary decoder to resolve the target address, selects the input port through the primary arbitrator, and is finally output from the system's input port.
[0049] In this embodiment, the decoder is located at the source of the data stream and is responsible for selecting the appropriate output. The multi-level crossbar switch architecture of this invention contains two types of decoders. The first type is the address decoder: similar to the decoder in a traditional full-crossbar network, it directly determines the target port by resolving the address / ID, as shown in the attached diagram. Figure 3 The yellow blocks indicate the secondary crossbar switches in the request network and the primary crossbar switches in the response network. The second type of dynamic path selection decoder, taking advantage of the flexibility of multi-level crossbar switches, uses an algorithm to select a specified path from multiple candidate ports, as shown in the attached diagram. Figure 3 The green blocks in the diagram represent the first-level crossbar switches in the request network and the second-level crossbar switches in the response network.
[0050] The configuration of the first-level decoder and the second-level decoder is determined according to the data flow type. When the multi-level crossbar system is applied to the request network, the first-level decoder is a dynamic path selection decoder and the second-level decoder is an address decoder. When the multi-level crossbar system is applied to the response network, the first-level decoder is an address decoder and the second-level decoder is a dynamic path selection decoder.
[0051] In the request network, data enters the first-level cross switch from the first input port, selects the appropriate output port through the dynamic path selection decoder, and then is sent to the second-level cross switch. The address decoder resolves the target address and completes the final output through the second-level arbitrator, realizing the orderly transmission of the request data stream from the source to the target.
[0052] In the response network, the data transmission direction is opposite to that of the request network. The data enters the secondary cross switch from the second output port, and the dynamic path selection decoder selects a suitable output port from the preset output ports. Then it is sent to the primary cross switch, and the address decoder performs the final port selection based on the source address.
[0053] The dynamic path selection decoder selects the output port for data forwarding according to a preset path selection strategy. The path selection strategy is one of the following three strategies:
[0054] (1) Static allocation strategy: The correspondence between input ports and output ports is established by looking up a table according to predefined mapping rules, and then the output port is selected according to the correspondence between input ports and output ports;
[0055] (2) Polling allocation strategy: The output ports are selected sequentially according to the preset output port order. This strategy adopts a simple polling selection mechanism. Each input port is selected in a loop among several output ports. It does not require maintaining a complex lookup table or real-time monitoring of the channel status, and the computational overhead is small.
[0056] (3) Dynamic allocation strategy: Set the output port priority according to the size of the free space of the output port buffer (i.e. the size of the remaining space), and then select the output port according to the output port priority.
[0057] The dynamic allocation strategy works as follows: each output port is equipped with a buffer for temporary storage of data to be transmitted. The remaining buffer space of each output channel is monitored in real time. During each allocation, the output port with the largest remaining space becomes the candidate port. If the output port with the largest remaining space is not unique, one is selected based on the modulo operation of the input port number. This strategy has the advantage of adapting to changes in traffic flow and can also effectively avoid instantaneous congestion through the bias mechanism of the modulo operation.
[0058] The dynamic path selection decoder is specifically used to select the optimal output port from multiple candidate output ports to complete data routing, based on a preset priority strategy, port idle status, or path load.
[0059] Specifically, the address decoder parses the target address information carried in the input request and determines the corresponding target output port based on the address mapping relationship to complete data routing.
[0060] The arbitrator, located at the destination of the data stream, is responsible for selecting the appropriate source for authorization, as shown in the attached diagram. Figure 4 As shown.
[0061] Both the primary and secondary arbitrators transmit the output data of the primary and secondary decoders to the first and second output ports selected by the corresponding decoders, respectively, according to a preset arbitration strategy. The arbitration strategy is one of the following three strategies:
[0062] (1) Fixed priority arbitration: Set the data priority of the input port according to the sequence information of the input port, and then grant access permissions according to the data priority of the input port;
[0063] (2) Signal priority arbitration: Priority is determined based on the QoS signal of the read / write address channel in the AXI protocol. The source with the highest priority is granted authorization. When multiple sources have the same priority, a round-robin mechanism is used.
[0064] (3) Adaptive priority arbitration: Decisions are made by tracking the waiting time of each transmission. The port waiting time is calculated during the first arbitration, and the total delay from the external port is calculated during the second arbitration. The source with the longest waiting time will be given priority.
[0065] The core design concept of this embodiment is as follows: Figure 2As shown, an innovative multi-level crossbar switch architecture is proposed, employing a hierarchical interconnection scheme to significantly improve system scalability. Regarding port configuration, the N slave ports on the left adopt a grouped design, with each group of ports interconnected locally via an independent first-level crossbar switch. This design not only optimizes cabling resource allocation but also significantly reduces signal transmission latency. The M master ports on the right employ centralized management, achieving global interconnection through a second-level crossbar switch to ensure efficient data transmission.
[0066] The hierarchical interconnection structure is the core feature of this solution. The system intelligently divides N slave ports into R logical groups, each containing S (S = N / R) external host connections. Each first-level crossbar switch adopts an ST full-crossbar architecture, responsible for data exchange within the group. The second-level crossbar switch adopts an (R×T)-M full-crossbar design to achieve cross-group data routing. This hierarchical design retains the high throughput characteristics of full-crossbar switches while avoiding the scalability bottleneck of traditional architectures.
[0067] By dynamically configuring the R (number of groups) and T (first-level cross-output) parameters, the topology can be adjusted and optimized according to the actual interconnect scale, achieving an optimal balance between performance and area overhead through appropriate grouping strategies. This adaptive capability enables the architecture to adapt to various application scenarios from small to large scale, achieving a balance between high throughput and full cross-connect switching complexity.
[0068] This embodiment adopts the AXI protocol, which specifies five independent channels: AR read address channel, R read data channel, AW write address channel, W write data channel, and B write response channel. Each channel corresponds to a multi-level cross switch system.
[0069] For write data transmission, the same port allocation scheme as the corresponding write address transmission must be strictly maintained. This means the path selection of the multi-level crossbar switch system for the write data channel must be consistent with that of the multi-level crossbar switch system for the write address channel. Furthermore, the remaining buffer space of the write data channel must be considered during dynamic allocation to prevent traffic imbalance in the write data channel while traffic in the write address channel remains balanced. For both write data transmission and write address transmission, it is essential to ensure that all data units in a single burst transmission are transmitted through the same path to avoid out-of-order data transmission. These mechanisms collectively ensure that while improving system throughput, the timing and ordering requirements of the AXI protocol are strictly met.
[0070] This embodiment features a special design for the AXI protocol, which uses the RID / WID fields of the read / write address channel as identifiers to distinguish different transmissions: Firstly, it includes ID appending and ID remapping, as shown in the appendix... Figure 5As shown. During the network transmission request process, each crossbar switch appends the current port number to the transmission ID upon receiving a new transmission, clearly identifying the origin of the transmission. When the transmission reaches the output port of the secondary crossbar switch, the bit width is expanded because the ID has already been appended with the port number twice. The system performs ID compression by maintaining a remapping table, effectively reducing bus resource consumption. On the reply path, the input port of the secondary crossbar switch queries the ID remapping table to restore the compressed ID to its original format, and then accurately routes the reply data to the corresponding source device based on the appended two port number information.
[0071] Secondly, there is a built-in out-of-order deadlock avoidance mechanism, as shown in the appendix. Figure 5 As shown. To strictly meet the AXI protocol's requirement for sequential transmission of the same source and ID, this invention implements an out-of-order control mechanism at the input port of the first-level crossbar switch. This mechanism monitors the status of incomplete requests at each input port. When a new arrival transmission is detected to conflict with an incomplete preceding transmission of the same ID, the transmission of the new transmission is automatically suspended until the preceding transmission is completed. This design strictly guarantees that the order in which the host receives responses is completely consistent with the order in which it sends requests, fundamentally avoiding the risk of deadlock at the protocol level.
[0072] A data transmission method using a multi-level cross switch system includes the following steps:
[0073] S1, Request Phase: Receive data transmission requests from the N input ports of the multi-level crossbar switch system. The data transmission request includes the target address information and the transaction ID.
[0074] S2. The data transmission request enters the first-level crossbar switch and the second-level crossbar switch in sequence, and the sequence information of the first and second input ports are respectively appended to the transaction ID in the data transmission request to obtain a data transmission request with a second appended ID.
[0075] S3. Subsequently, the secondary cross switch performs ID compression processing on the secondary additional ID data transmission request according to the preset ID remapping table to obtain the ID compressed data transmission request.
[0076] S4. Response Phase: The secondary cross switch of the corresponding channel responds by performing ID recovery on the data transmission request of the ID compression according to the ID remapping table to obtain the data transmission request of the recovered ID. Then, the path is identified according to the transaction ID of the data transmission request of the recovered ID to realize data recovery.
[0077] The present invention and its embodiments have been described above. This description is not restrictive, and the accompanying drawings are only one embodiment of the present invention; the actual structure is not limited thereto. In conclusion, if those skilled in the art are inspired by this description and design similar structures and embodiments without departing from the spirit of the invention, such designs should fall within the protection scope of the present invention.
Claims
1. A multi-stage cross switch system, characterized in that: It includes N input ports, M output ports, R primary cross switches and one secondary cross switch. Each primary cross switch includes S first input ports and T first output ports, and the S first input ports and T first output ports are in a fully cross structure. The secondary cross switch includes Q second input ports and M second output ports, and the Q second input ports and M second output ports are in a fully cross structure. The first input ports of the R primary cross switches are connected one-to-one with the N input ports of the multi-level cross switch system, the first output ports of the R primary cross switches are connected one-to-one with the Q second input ports of the secondary cross switches, and the M second output ports of the secondary cross switches are connected one-to-one with the M output ports of the multi-level cross switch system, where N = R * S and Q = R * T.
2. The multi-level cross switch system according to claim 1, characterized in that: When a multi-level crossbar switch system is applied to a request network, each first-level crossbar switch includes S first input ports, T first output ports, S first-level decoders, and T first-level arbitrators. The S first-level decoders and the S first input ports are connected one-to-one, the T first-level arbitrators and the T first output ports are connected one-to-one, any one-level decoder is connected to the T first-level arbitrators, and any one-level arbitrator is connected to the S first-level decoders. The secondary cross switch includes Q second input ports, M second output ports, Q secondary decoders, and M secondary arbitrators. The Q secondary decoders and Q second input ports are connected one-to-one, the M secondary arbitrators and M second output ports are connected one-to-one, any secondary decoder is connected to all M secondary arbitrators, and any secondary arbitrator is connected to all Q secondary decoders. The first-level decoder is a dynamic path selection decoder, and the second-level decoder is an address decoder.
3. The multi-level cross switch system according to claim 1, characterized in that: When a multi-level cross switch system is applied to a response network, each first-level cross switch includes S first input ports, T first output ports, T first-level decoders, and S first-level arbitrators. The T first-level decoders and the T first output ports are connected one-to-one, the S first-level arbitrators and the S first input ports are connected one-to-one, any one-level decoder is connected to each of the S first-level arbitrators, and any one-level arbitrator is connected to each of the T first-level decoders. The two-level crossbar switch includes Q second input ports, M second output ports, M second-level decoders, and Q second-level arbitrators. The M second-level decoders and the M second output ports are connected one-to-one, the Q second-level arbitrators and the Q second input ports are connected one-to-one, any one of the two-level decoders is connected to each of the Q second-level arbitrators, and any one of the two-level arbitrators is connected to each of the M second-level decoders. The first-level decoder is an address decoder, and the second-level decoder is a dynamic path selection decoder.
4. A multi-level cross switch system according to claim 2, characterized in that: The dynamic path selection decoder selects an output port for data forwarding according to a preset path selection strategy, which is one of the following three strategies: (1) Static allocation strategy: The correspondence between input ports and output ports is established by looking up a table according to predefined mapping rules, and then the output port is selected according to the correspondence between input ports and output ports; (2) Polling allocation strategy: Select output ports sequentially according to the preset output port order; (3) Dynamic allocation strategy: Set the output port priority according to the size of the free space in the output port buffer, and then select the output port according to the output port priority.
5. A multi-level cross switch system according to claim 2, characterized in that: Both the primary and secondary arbitrators transmit the output data of the primary and secondary decoders to the first and second output ports selected by the corresponding decoders, respectively, according to a preset arbitration strategy.
6. A data transmission method using a multi-level cross switch system as described in any one of claims 1-5, characterized in that, The method includes the following steps: S1. Request Phase: Receive a data transmission request from the input port of the multi-level cross switch system. The data transmission request includes a transaction ID. S2. The data transmission request enters the first-level crossbar switch and the second-level crossbar switch in sequence, and the sequence information of the first and second input ports are respectively appended to the transaction ID in the data transmission request to obtain a data transmission request with a second appended ID. S3. Subsequently, the secondary cross switch performs ID compression processing on the secondary additional ID data transmission request according to the preset ID remapping table to obtain the ID compressed data transmission request. S4. Recovery Phase: Based on the ID remapping table, the data transmission request with compressed ID is used to recover the ID and obtain the data transmission request with the recovered ID. Then, based on the transaction ID of the data transmission request with the recovered ID, the path is identified to realize data recovery.
7. A chip, characterized in that, The chip includes the multi-level cross switch system according to any one of claims 1-5.