Intermittent output device with frequency hopping

Abstract

The invention relates to the technical field of frequency hopping detection, in particular to a frequency hopping intermittent output device. Automatic or manual switching and intermittent output of the three frequencies of 360 Hz, 400 Hz and 800 Hz are achieved through a pure hardware circuit structure, dependence on a microprocessor or software programming is not needed, the system complexity and development cost are remarkably reduced, meanwhile, the tedious process of software reliability authentication is avoided, the detection efficiency and equipment adaptability are improved, and the detection cost is reduced. An oscillation frequency dividing circuit is combined with a delay resistor array and a frequency dividing counter, stable and adjustable square wave signals are generated through an accurate resistance-capacitance matching relation, 24 frequency division and logic control are achieved through a gate circuit, and accurate control and intermittent output of frequency signals are achieved. The technical problems that in the existing production process, detection equipment is insufficient and efficiency is not high when tested equipment alternately works and intermittently works at the frequency of 360 Hz, 400 Hz and 800 Hz are solved.

Description

Technical Field

[0001] This invention relates to the field of frequency jump detection technology, and more particularly to an intermittent output device for frequency jumps. Background Technology

[0002] The AC main power supply frequency of commercial aircraft is typically 400Hz. However, during takeoff and engine shutdown, the frequency variation caused by the rapid changes in engine speed can reach as high as 200Hz / s. Therefore, the system often requires testing the equipment under test (UTT) at alternating frequencies of 360Hz, 400Hz, and 800Hz. This is especially true for power monitoring UTTs, which often require assessment of their operation during power outages, i.e., intermittent input signals to power monitoring UTTs. Testing of such UTTs is usually done using dedicated equipment and manual setup. However, dedicated equipment is expensive, and bulk purchases would increase production costs. Generating intermittent output test signals at different frequencies using a microprocessor is one technical approach to solve this problem. However, microprocessors involve software programming, and in special applications, the complex software evaluation resulting from microprocessor software programming significantly increases the development cycle and cost. Summary of the Invention

[0003] To address the shortcomings of existing technologies, this invention provides a frequency-hopping intermittent output device, which solves the technical problems of insufficient and inefficient testing equipment in existing production processes when the tested equipment operates alternately or intermittently at frequencies of 360Hz, 400Hz, and 800Hz.

[0004] To solve the above-mentioned technical problems, the present invention provides the following technical solution: an intermittent output device with frequency hopping, the output device comprising:

[0005] An oscillation frequency divider circuit is used to generate a square wave signal and a 24-division frequency signal after power-on, and to AND the square wave signal and the 24-division frequency signal through an AND gate to intermittently output a first output signal with frequencies of 360Hz, 400Hz and 800Hz.

[0006] An output driving circuit is provided, which receives a first output signal and outputs a second output signal that is intermittent and frequency-hopping.

[0007] The control module includes a first control module for controlling the frequency of the square wave signal output by the oscillation frequency divider circuit, and a reset circuit for controlling the reset of the square wave signal and the 24-division signal output by the oscillation frequency divider circuit.

[0008] Preferably, the oscillation frequency divider circuit includes a frequency divider counter D1 with an oscillator structure. A delay resistor array and a resistor R4 are connected in series between pins 10 and 11 of the frequency divider counter D1. A capacitor C1 is connected between the connection line between the delay resistor array and the resistor R4 and pin 9 of the frequency divider counter D1.

[0009] Preferably, the delay resistor array consists of resistors R1, R2, and R3 connected in series between resistor R4 and pin 10 of the frequency divider counter D1.

[0010] Preferably, the resistance values ​​of resistors R1, R2, and R3 satisfy the following relationship:

[0011]

[0012] In the above formula, The frequencies of the square wave signals are 360Hz, 400Hz, and 800Hz, respectively. R1, R2, and R3 represent the resistance values ​​of resistors R1, R2, and R3, respectively, and C1 represents the capacitance value of capacitor C1.

[0013] Preferably, the first control module includes analog switch D2 and analog switch D3. A switch K1 is connected in series between the ENB pin of analog switch D2 and the ENB pin of analog switch D3. The A1 pin and B pin of analog switch D2 are respectively connected to both ends of resistor R1, and the A1 pin of analog switch D2 is connected between resistor R1 and resistor R2. The A1 pin of analog switch D3 is connected to the B pin of analog switch D2, and the B pin of analog switch D3 is connected between resistor R2 and resistor R3.

[0014] Preferably, the first control module further includes a switch K2 connected in series between pins A1 and B of analog switch D2, and a switch K3 connected in series between pins B of analog switch D2 and pin B of analog switch D3.

[0015] Preferably, the reset circuit includes a capacitor C12 and an AND gate D4B connected in series on pin 12 of the frequency divider counter D1. A grounded resistor R5 is also connected to pin 12 of the frequency divider counter D1. Pins 3 and 4 of the AND gate D4B are connected to pin Q4 of the frequency divider counter D1, and pin 5 of the AND gate D4B is connected to pin Q5 of the frequency divider counter D1.

[0016] Preferably, the output drive circuit includes a resistor R7 connected to the output terminal of an AND gate, a transistor V1 connected to resistor R7, the base of transistor V1 connected to resistor R7, resistors R9 and R8 connected in sequence between the collector of transistor V1 and the power supply VDD, a MOSFET V2 connected on the line between resistors R9 and R8, the gate of MOSFET V2 connected to the line between resistors R9 and R8, the source of MOSFET V2 connected to the power supply VDD, and a diode connected between the source and drain of MOSFET V2.

[0017] By employing the above technical solution, the present invention provides an intermittent output device with frequency hopping, which has at least the following beneficial effects:

[0018] 1. This invention provides a frequency-hopping intermittent output device that achieves automatic or manual switching and intermittent output of three frequencies: 360Hz, 400Hz, and 800Hz through a pure hardware circuit structure. It does not rely on a microprocessor or software programming, which significantly reduces system complexity and development costs. At the same time, it avoids the cumbersome process of software reliability certification. It is suitable for high reliability testing scenarios of aviation power monitoring equipment, improves testing efficiency and equipment adaptability, and has strong engineering practicality and economy.

[0019] 2. This device uses an oscillation frequency divider circuit combined with a delay resistor array and a frequency divider counter. It generates a stable and adjustable square wave signal through precise resistor-capacitor matching. Then, it achieves 24-fold frequency division and logic control through gate circuits, realizing precise control and intermittent output of frequency signals. It has a simple structure, fast response speed, and strong anti-interference ability. It is suitable for simulation test environments with high dynamic frequency changes, improving the accuracy and repeatability of test signals.

[0020] 3. This invention achieves manual and automatic dual-mode operation of frequency switching through a control module that combines analog and mechanical switches. Users can flexibly select the working mode according to the test requirements. In the automatic mode, the system can automatically switch between three frequencies in a preset sequence and cooperate with intermittent output, which greatly reduces manual intervention and improves the consistency and efficiency of testing. It is especially suitable for rapid testing applications in mass production.

[0021] 4. The output drive circuit of this invention adopts a drive structure combining transistors and MOSFETs, which has strong load-carrying capacity and signal isolation function. It can effectively drive various power monitoring equipment. At the same time, the diode protection circuit enhances the system's anti-reverse voltage and anti-impact capabilities, ensuring the stability of the output signal and the safety of the equipment, extending the service life of the device, and is suitable for various industrial and aerospace electronic testing occasions. Attached Figure Description

[0022] The accompanying drawings, which are included to provide a further understanding of this application and form part of this application, illustrate exemplary embodiments and are used to explain this application, but do not constitute an undue limitation of this application. In the drawings:

[0023] Figure 1 This is a structural block diagram of the frequency-hopping intermittent output device of the present invention;

[0024] Figure 2 This is a circuit diagram of the oscillation frequency divider circuit of the present invention;

[0025] Figure 3 This is the circuit diagram of gate one of the present invention;

[0026] Figure 4 This is a timing diagram of the output signal of AND gate 1 in this invention;

[0027] Figure 5 This is a circuit diagram of the control module of the present invention;

[0028] Figure 6 This is a control timing diagram of the control module of the present invention;

[0029] Figure 7 This is a circuit diagram of the reset circuit of the present invention.

[0030] In the diagram: 1. Oscillation frequency divider circuit; 2. Output drive circuit; 3. Control module; 4. First control module; 5. Reset circuit. Detailed Implementation

[0031] To make the above-mentioned objects, features, and advantages of the present invention more apparent and understandable, the present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments. This will allow for a full understanding of how the present application uses technical means to solve technical problems and achieve technical effects, and to facilitate its implementation.

[0032] To address the problems of insufficient and inefficient testing equipment in existing production processes for testing equipment operating at alternating frequencies of 360Hz, 400Hz, and 800Hz, as well as intermittent operation, this invention provides an intermittent output device with frequency jumps, such as... Figure 1 As shown, the system includes an oscillation frequency divider circuit 1 for generating a square wave signal and a 24-division frequency signal after power-on, and an output drive circuit 2 for receiving the first output signal and outputting a second output signal with intermittent frequencies of 360Hz, 400Hz and 800Hz by ANDing the square wave signal and the 24-division frequency signal through an AND gate; a control module 3 for receiving the first output signal and outputting a second output signal with intermittent frequency jumps; and a control module 3 including a first control module 4 for controlling the frequency of the square wave signal output by the oscillation frequency divider circuit 1, and a reset circuit 5 for controlling the reset of the square wave signal and the 24-division frequency signal output by the oscillation frequency divider circuit 1.

[0033] like Figure 2 As shown, the oscillation frequency divider circuit 1 includes a frequency divider counter D1 with an oscillator structure. A delay resistor array and a resistor R4 are connected in series between pins 10 and 11 of the frequency divider counter D1. A capacitor C1 is connected between the connection line between the delay resistor array and the resistor R4 and pin 9 of the frequency divider counter D1. A grounded resistor R5 is connected to pin 12 of the frequency divider counter D1. The delay resistor array is composed of resistors R1, R2, and R3 connected in series. When the circuit is powered on, the oscillation frequency divider circuit 1 starts to work and generates a square wave signal. The frequency f of the square wave signal satisfies the following formula:

[0034]

[0035] By calculating, the resistance values ​​of resistors R1, R2, and R3, as well as the capacitance value of capacitor C1, can be set so that the frequencies of the square wave signal are f1=360Hz, f2=400Hz (R1=0), and f3=800Hz (R1=R2=0). The square wave signal is output through OUT0 of the frequency divider counter D1, and the frequency divider counter D1 outputs a 24-division signal through OUT4.

[0036] like Figure 3 and Figure 4 As shown, the square wave signal output from OUT0 of frequency divider counter D1 and the 24-division signal output from OUT4 are ANDed by AND gate D4A. When the square wave signal output from OUT0 has not reached 8, the Q4 terminal of frequency divider counter D1 outputs a low level, and the 9th pin of AND gate D4A outputs a low level. When the square wave signal output from OUT0 reaches 8 but less than 16, the Q4 terminal of frequency divider counter D1 outputs a high level, and the 9th pin of AND gate D4A outputs the OUT0 signal. The following steps are the same, thus realizing the intermittent output signal.

[0037] like Figure 5 and Figure 6 As shown, the first control module 4 includes analog switches D2 and D3. A switch K1 is connected in series between the ENB pins of analog switches D2 and D3. The A1 and B pins of analog switches D2 are respectively connected to both ends of resistor R1, and the A1 pin of analog switches D2 is connected between resistor R1 and resistor R2. The A1 pin of analog switches D3 is connected to the B pin of analog switches D2, and the B pin of analog switches D3 is connected between resistor R2 and resistor R3. Thus, automatic control is achieved through analog switches D2 and D3. In addition, to enrich the control methods of this device, the first control module 4 also includes a switch K2 connected in series between the A1 and B pins of analog switches D2, and a switch K3 connected in series between the B pins of analog switches D2 and D3.

[0038] When K1, K2, and K3 are all open, resistors R1, R2, and R3 all participate in the oscillation, and pin 9 of AND gate D4A outputs a 360Hz intermittent control signal. When K2 is closed, resistor R1 is short-circuited and does not participate in the oscillation, and pin 9 of AND gate D4A outputs a 400Hz intermittent control signal. When K3 is closed, resistors R1 and R2 are short-circuited and do not participate in the oscillation, and pin 9 of AND gate D4A outputs an 800Hz intermittent control signal.

[0039] When switch K1 is closed and switches K2 and K3 are both open, the system switches to automatic mode. The Q5 terminal of frequency divider counter D1 divides the Q4 terminal by 2, and the Q6 terminal of frequency divider counter D1 divides the Q5 terminal by 2. The Q5 port receives the control signal from analog switch D3, and the Q6 port receives the control signal from analog switch D2. When the device is powered on, Q4, Q5, and Q6 of frequency divider counter D1 all output a low level, and pin 9 of AND gate D4A outputs a low level for the first time. When the square wave signal output from OUT0 reaches 8, the Q4 port becomes high, and pin 9 of AND gate D4A outputs the first group of 360Hz square wave signals. When the square wave signal output from OUT0 reaches 16, Q4 of frequency divider counter D1 becomes low, Q5 becomes high, and pin 9 of AND gate D4A outputs a low level for the second time. After Q5 becomes high, the B port of analog switch D3 is connected to A1, R1 is shorted, and the oscillation frequency becomes 400Hz. When the square wave signal output from OUT0 reaches 24, Q4 goes high, and pin 9 of AND gate D4A outputs a second group of 400Hz square wave signals. When the square wave signal output from OUT0 reaches 32, Q4 and Q5 go low, and Q6 goes high, and pin 9 of AND gate D4A outputs a third low level. After Q6 goes high, analog switch D2's B and A1 are connected, R1 and R2 are shorted, and the oscillation frequency becomes 800Hz. When the square wave signal output from OUT0 reaches 40, Q4 goes high, and pin 9 of AND gate D4A outputs a third group of 800Hz square wave signals. When the square wave signal output from OUT0 reaches 48, Q4 goes low, and Q5 goes high. Since Q5 and Q6 go high simultaneously, pin 6 of AND gate D4B outputs a high level.

[0040] The reset circuit 5 includes a capacitor C12 and an AND gate D4B connected in series on pin 12 of the frequency divider counter D1. A grounded resistor R5 is also connected to pin 12 of the frequency divider counter D1. Pins 3 and 4 of the AND gate D4B are connected to pin Q4 of the frequency divider counter D1, and pin 5 of the AND gate D4B is connected to pin Q5 of the frequency divider counter D1. When pin 6 of the AND gate D4B outputs a high level, a high-level reset pulse signal will appear at pin 12 of the frequency divider counter D1, causing all outputs of the frequency divider counter D1 to output a low level, and the oscillator stops oscillating. After the reset is completed, the oscillator starts working again and repeats the above process, realizing the intermittent output with automatic frequency switching.

[0041] like Figure 5 As shown, the output drive circuit 2 includes a resistor R7 connected to the output terminal of the AND gate. A transistor V1 is connected to the resistor R7. The base of the transistor V1 is connected to the resistor R7. Resistors R9 and R8 are connected in sequence between the collector of the transistor V1 and the power supply VDD. A MOSFET V2 is connected on the line between resistors R9 and R8. The gate of the MOSFET V2 is connected to the line between resistors R9 and R8. The source of the MOSFET V2 is connected to the power supply VDD. A diode is connected between the source and drain of the MOSFET V2. The output signal of pin 9 of D4A is applied to R7. The transistor controls the MOSFET V2 to realize the transmission of intermittent and manual / automatic frequency switching of VDD.

[0042] Those skilled in the art will understand that all or part of the steps in the methods of the above embodiments can be implemented by a program instructing related hardware. Therefore, this application can take the form of a completely hardware embodiment, a completely software embodiment, or an embodiment combining software and hardware aspects. Moreover, this application can take the form of a computer program product implemented on one or more computer-usable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) containing computer-usable program code.

[0043] The various embodiments in this specification are described in a progressive manner, with each embodiment focusing on its differences from other embodiments. Similar or identical parts between embodiments can be referred to interchangeably. Since the above embodiments are substantially similar to the method embodiments, their descriptions are relatively simple; relevant parts can be referred to the descriptions of the method embodiments.

[0044] The above embodiments provide a detailed description of the present invention. Specific examples have been used to illustrate the principles and implementation methods of the present invention. The descriptions of the above embodiments are only for the purpose of helping to understand the method and core ideas of the present invention. At the same time, for those skilled in the art, there will be changes in the specific implementation methods and application scope based on the ideas of the present invention. Therefore, the content of this specification should not be construed as a limitation of the present invention.

Claims

1. A frequency-hopping intermittent output device, characterized in that, The detection device includes: The oscillation frequency divider circuit (1) is used to generate a square wave signal and a 24-division frequency signal after power-on, and to AND the square wave signal and the 24-division frequency signal through AND gate 1 to intermittently output a first output signal with frequencies of 360Hz, 400Hz and 800Hz. Output driving circuit (2), the output driving circuit (2) is used to receive the first output signal and output the second output signal with intermittent and frequency jump; The control module (3) includes a first control module for controlling the frequency of the square wave signal output by the oscillation frequency divider circuit (1), and a reset circuit (5) for controlling the reset of the square wave signal and the 24-division signal output by the oscillation frequency divider circuit (1).

2. The intermittent output device according to claim 1, characterized in that, The oscillation frequency divider circuit (1) includes a frequency divider counter D1 with an oscillator structure. A delay resistor array and a resistor R4 are connected in series between pins 10 and 11 of the frequency divider counter D1. A capacitor C1 is connected between the connection line between the delay resistor array and the resistor R4 and pin 9 of the frequency divider counter D1.

3. The intermittent output device according to claim 3, characterized in that, The delay resistor array consists of resistors R1, R2, and R3 connected in series between resistor R4 and pin 10 of the frequency divider counter D1.

4. The intermittent output device according to claim 3, characterized in that, The resistance values ​​of resistors R1, R2, and R3 satisfy the following relationship: In the above formula, The frequencies of the square wave signals are 360Hz, 400Hz, and 800Hz, respectively. R1, R2, and R3 represent the resistance values ​​of resistors R1, R2, and R3, respectively, and C1 represents the capacitance value of capacitor C1.

5. The intermittent output device according to claim 1, characterized in that, The first control module includes analog switches D2 and D3. A switch K1 is connected in series between the ENB pins of analog switches D2 and D3. The A1 and B pins of analog switches D2 are respectively connected to the two ends of resistor R1, and the A1 pin of analog switches D2 is connected between resistor R1 and resistor R2. The A1 pin of analog switches D3 is connected to the B pin of analog switches D2, and the B pin of analog switches D3 is connected between resistor R2 and resistor R3.

6. The intermittent output device according to claim 5, characterized in that, The first control module also includes a switch K2 connected in series between pins A1 and B of analog switch D2, and a switch K3 connected in series between pin B of analog switch D2 and pin B of analog switch D3.

7. The intermittent output device according to claim 1, characterized in that, The reset circuit (5) includes a capacitor C12 and an AND gate D4B connected in series on pin 12 of the frequency divider counter D1. A grounded resistor R5 is also connected to pin 12 of the frequency divider counter D1. Pins 3 and 4 of the AND gate D4B are connected to pin Q4 of the frequency divider counter D1, and pin 5 of the AND gate D4B is connected to pin Q5 of the frequency divider counter D1.

8. The intermittent output device according to claim 1, characterized in that, The output drive circuit (2) includes a resistor R7 connected to the output terminal of the AND gate, a transistor V1 connected to the resistor R7, the base of the transistor V1 connected to the resistor R7, a resistor R9 and a resistor R8 connected in sequence between the collector of the transistor V1 and the power supply VDD, a MOS transistor V2 connected on the line between the resistor R9 and the resistor R8, the gate of the MOS transistor V2 connected to the line between the resistor R9 and the resistor R8, the source of the MOS transistor V2 connected to the power supply VDD, and a diode connected between the source and the drain of the MOS transistor V2.

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