True rail-to-rail input / output reference voltage buffer circuit suitable for high precision adc

Abstract

The application provides a true rail-to-rail input and output reference voltage buffer circuit suitable for high-precision ADC, which alternately performs a sampling phase F1 and a holding phase F2 during operation; the circuit comprises a sampling capacitor C s During the sampling phase F1, the bottom plate tracks the input reference voltage, and the top plate is reset to the ground; a level shift capacitor C LVL During the sampling phase F1, the difference between the input reference voltage and the output common-mode voltage of a transconductance operational amplifier (OTA) is synchronously sampled, and during the holding phase F2, the output voltage is connected to the output end of the transconductance operational amplifier (OTA), so as to realize the expansion of the true rail-to-rail range of the output voltage; a feedback capacitor C f During the sampling phase F1, the charge is not cleared, and during the holding phase F2, the sampling capacitor C s is connected in parallel, and the output voltage is established through charge averaging; the switch network is used for controlling the connection state of the capacitors in the sampling phase F1 and the holding phase F2. The application embodiment can realize true rail-to-rail input and output and high effective input impedance.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of integrated circuit design, in particular to a true rail-to-rail input and output reference voltage buffer circuit suitable for high-precision ADC. BACKGROUND

[0002] High-precision ADC is a core component in precision instruments, power management and medical electronic devices, etc. applications, responsible for weak signal detection in the system. High-precision ADC usually adopts two kinds of switched capacitor structures of sigma-delta type ADC and SAR type ADC, and its working principle is as follows: in the sampling phase of ADC, the input signal is tracked by the sampling capacitor inside the ADC, and the input signal is sampled at the falling edge. In the conversion phase (i.e. holding phase) of ADC, the internal D / A capacitor array of ADC is connected to the reference voltage, and the input signal sampled in the sampling phase is converted. For Sigma-Delta type ADC, the first stage integrator also needs to integrate the residual signal in the holding phase, and the integrated voltage is sampled by the rear integrator at the falling edge of the holding phase. In order to avoid the disturbance of the reference voltage caused by the D / A capacitor array in the holding phase, the ADC chip usually has an on-chip reference voltage buffer to isolate the D / A capacitor of the ADC from the input reference voltage. The reference voltage buffer needs to have the characteristics of high precision, low noise and sufficient driving ability, and its equivalent input impedance and input voltage range determine the flexibility of the design of the input reference voltage of the ADC chip.

[0003] In the traditional technical solution, due to the limitation of the structure of the operational amplifier, the lowest output voltage of the operational amplifier needs to be at least one NMOS saturation voltage higher than the ground voltage, and the highest output voltage needs to be at least one PMOS saturation voltage lower than the analog power supply voltage, which limits the input voltage range and cannot cover the complete power rail to ground rail range. In order to eliminate the operational amplifier imbalance and imbalance temperature drift, the chopping technology is introduced to modulate the imbalance to the chopping frequency, resulting in periodic ripple of the output reference voltage; for SAR type ADC, a large number of off-chip decoupling capacitors need to be additionally introduced to reduce the ripple amplitude to within 1 least significant bit (LSB), which increases the complexity and cost of circuit design. SUMMARY

[0004] The purpose of the present application is to provide a true rail-to-rail input and output reference voltage buffer circuit suitable for high-precision ADC, which solves the problem that the traditional reference voltage buffer cannot realize true rail-to-rail input and output and low input impedance, and provides a more flexible and efficient solution for high-precision ADC design.

[0005] To solve the above technical problems, the embodiment of the present application provides a true rail-to-rail input and output reference voltage buffer circuit suitable for high-precision ADC, which alternately performs a sampling phase F1 and a holding phase F2 during operation; the circuit comprises: a sampling capacitor module, a level shift capacitor module, a feedback capacitor module, a transconductance operational amplifier (OTA) and a switch network; the sampling capacitor module comprises at least one pair of sampling capacitors C s , the level shift capacitor module comprises at least one pair of level shift capacitors C LVL , and the feedback capacitor module comprises at least one pair of feedback capacitors C f .

[0006] The sampling capacitor C s tracks the input reference voltage at the bottom plate in the sampling phase F1 and is reset to the ground at the top plate, and is used for sampling the input signal.

[0007] The level shift capacitor C LVL synchronously samples the difference between the input reference voltage and the common-mode voltage of the output of the transconductance operational amplifier (OTA) in the sampling phase F1, and is connected to the output end of the transconductance operational amplifier (OTA) in the holding phase F2, so as to realize the range expansion of the output voltage in the true rail-to-rail range.

[0008] The feedback capacitor C f does not clear the charge in the sampling phase F1, and is connected in parallel with the sampling capacitor C s in the holding phase F2, so as to realize the establishment of the output voltage through charge averaging.

[0009] The switch network is used for controlling the connection state of the capacitors in the sampling phase F1 and the holding phase F2.

[0010] Optionally, the level shift capacitor C LVL is connected to the input reference voltage at the top plate and is connected to the common-mode voltage of the output of the transconductance operational amplifier (OTA) at the bottom plate in the sampling phase F1; and is connected to the output end of the transconductance operational amplifier (OTA) at the top plate and is connected to the output reference voltage at the bottom plate in the holding phase F2, so that the voltage at the output end of the transconductance operational amplifier (OTA) is shifted to the output common-mode voltage.

[0011] Optionally, the feedback capacitor C f maintains a floating state in the sampling phase F1, and the charge stored thereon is not reset, so as to reduce the charge extraction of the input reference voltage, thereby improving the equivalent input impedance.

[0012] Optionally, the feedback capacitor C f does not clear the charge in the sampling phase F1, and the charge stored at both ends of the feedback capacitor C f remains unchanged in the sampling phase F1.

[0013] Optionally, the OTA performs self-zeroing operation in the sampling phase F1, and the self-zeroing capacitor C AZ The operational amplifier stores the offset voltage to eliminate the offset error.

[0014] Optionally, the timing control of the switch network satisfies:

[0015] In the sampling phase F1, the switches SW1, SW2, SW4, SW8, and SW9 are closed, and the switches SW3, SW5, SW6, and SW7 are opened.

[0016] In the holding phase F2, the switches SW3, SW5, SW6, and SW7 are closed, and the switches SW1, SW2, SW4, SW8, and SW9 are opened.

[0017] Optionally, the switch device includes a switch pair, and the switch pairs are symmetrically arranged.

[0018] Optionally, the high-precision ADC includes a feedforward structure sigma-delta ADC or a synchronous SAR ADC.

[0019] Optionally, the circuit has a low-pass filtering effect on the noise introduced in the sampling process, and the output noise power The following relationship is satisfied:

[0020] Wherein, k is the Boltzmann constant, and T is the absolute temperature.

[0021] Optionally, the true rail-to-rail input and output specifically refer to that the range of the input reference voltage covers the analog power voltage to the analog ground voltage, and the range of the output reference voltage synchronously covers the analog power voltage to the analog ground voltage.

[0022] Compared with the prior art, the embodiment of the present application introduces another pair of level shift capacitors to sample the input reference voltage synchronously while the sampling capacitors sample the input reference voltage. Then, in the holding phase, the level shift capacitors are connected between the operational amplifier output and the output reference voltage, so that the operational amplifier output voltage works within a reasonable output range, realizing true rail-to-rail output of the reference voltage. In addition, the original sampling and holding process is replaced by a sampling and integration process in the embodiment of the present application, and the charge on the feedback capacitor is not emptied in the sampling phase, thereby reducing the charge extraction amount of the input reference voltage and improving the equivalent input impedance. Compared with the traditional sampling and holding reference voltage buffer circuit, the embodiment of the present application realizes the advantages of true rail-to-rail input and output of the reference voltage and high equivalent input impedance by introducing the level shift capacitors and the mechanism of not emptying the feedback capacitor. BRIEF DESCRIPTION OF DRAWINGS

[0023] One or more embodiments are illustrated by way of example in the drawings and specification hereof, which are not intended to limit the scope of the embodiments, the same being comprised only by the appended claims as limited by the patent laws of the jurisdiction to which this application is submitted, and the elements of the drawings being not necessarily to scale as set forth herein.

[0024] Figure 1 is a true rail-to-rail input-output reference voltage buffer circuit diagram for high-precision ADC according to one embodiment of the present application;

[0025] Figure 2 is a circuit diagram of the true rail-to-rail input-output reference voltage buffer at the sampling phase F1 according to one embodiment of the present application;

[0026] Figure 3 is a circuit diagram of the true rail-to-rail input-output reference voltage buffer at the holding phase F2 according to one embodiment of the present application. DETAILED DESCRIPTION

[0027] The foregoing disclosure of embodiments of the present application has been presented for the purposes of illustration and description. It is not intended to be exhaustive or to limit the present application to the precise forms disclosed. Many variations and modifications are possible in light of this disclosure. Any and all variations and modifications are within the scope of the present application. The described embodiments were chosen in order to provide a clear understanding of the principles of the present application and its practical application. The scope of the application is defined only by the claims.

[0028] It is noted that various aspects of the embodiments described below are described within the scope of the appended claims. It should be apparent that the aspects described herein can be embodied in a wide variety of forms and that any specific structure and / or function described herein is merely illustrative. Based on the teachings herein one skilled in the art should appreciate that an aspect described herein can be implemented independently of any other aspects and that an aspect described herein can be implemented both as any number of software and / or hardware structures and as any number of combinations of software and / or hardware structures. Examples of software can include, but are not limited to, firmware, resident software, microcode, etc. Furthermore, any

[0029] It is also necessary to note that the drawings provided in the following embodiments only illustrate the basic concepts of the present application in a schematic manner, and only show the components related to the present application in the drawings, not drawn according to the number, shape and size of the components in actual implementation. The actual implementation of each component may be a random change, and the component layout pattern may be more complex.

[0030] In addition, in the following description, specific details are provided in order to facilitate a thorough understanding of the examples. However, those skilled in the art will understand that the examples can be practiced without these specific details.

[0031] In order to solve the problem that the reference voltage buffer in the prior art cannot realize true rail-to-rail input and output and low input impedance, the embodiments of the present application provide a true rail-to-rail input and output reference voltage buffer circuit suitable for high-precision ADC, as shown in Figure 1 The circuit includes a sampling capacitor module, a level shift capacitor module, a feedback capacitor module, a transconductance operational amplifier (OTA) and a switch network. s The level shift capacitor module includes at least one pair of level shift capacitors C LVL The feedback capacitor module includes at least one pair of feedback capacitors C f

[0032] The circuit alternately performs a sampling phase F1 and a holding phase F2 during operation.

[0033] The sampling capacitor C s tracks the input reference voltage VRPI and VRNI at the bottom plate in the sampling phase F1, and the top plate is reset to ground, for sampling the input signal.

[0034] The level shift capacitor C LVL synchronously samples the difference between the input reference voltage VRPI and VRNI and the common-mode voltage VCMO of the output of the transconductance operational amplifier (OTA) in the sampling phase F1, and is connected to the output end of the transconductance operational amplifier (OTA) in the holding phase F2, to realize true rail-to-rail range expansion of the output voltage.

[0035] The feedback capacitor C f is not cleared in the sampling phase F1, and is connected in parallel with the sampling capacitor C s in the holding phase F2, to realize output voltage establishment through charge averaging. In the embodiments, the feedback capacitor C f is connected in parallel with the sampling capacitor C s , and the charges of the two are evenly distributed to establish the output voltage. After alternately performing the sampling phase F1 and the holding phase F2 for several cycles, the feedback capacitor C f ​The differential output voltage will be fully established to the input reference voltages VRPI and VRNI. After that, the output reference voltages of the phase output buffer F2 are VRPO=VRPI and VRNO=VRNI.

[0036] The switching network (such as SW1-SW9) is used to control the capacitor connection state of sampling phase F1 and holding phase F2.

[0037] In this embodiment of the application, the true rail-to-rail input and output specifically means that the range of the input reference voltage covers the analog power supply voltage to the analog ground voltage, and the range of the output reference voltage simultaneously covers the analog power supply voltage to the analog ground voltage.

[0038] In an optional embodiment, the level shifting capacitor C LVL The top plate of sampling phase F1 is connected to the input reference voltages VRPI and VRNI, and the bottom plate is connected to the output common-mode voltage VCMO of the transconductance operational amplifier OTA. The top plate of holding phase F2 is connected to the output terminal of the transconductance operational amplifier OTA, and the bottom plate is connected to the output reference voltages VRPO and VRNO. This shifts the output voltage of the transconductance operational amplifier OTA to the output common-mode voltage VCMO, while the output reference voltages VRPO and VRNO achieve rail-to-rail range.

[0039] The feedback capacitor C f During sampling phase F1, the base plate remains floating, and the stored charge on it is not reset, reducing charge draw from the input reference voltage and thus improving the equivalent input impedance. Specifically, the feedback capacitor C... f The two ends of the capacitor C are not connected to a reset voltage, so that the feedback capacitor C... f The base plate is floating, so the charge cannot be discharged and is not cleared to zero; the charge is retained. Other switches (such as SW3 and SW5) are also disconnected to ensure the feedback capacitor C... f Isolated from the output of the transconductance operational amplifier OTA, the charge stored on it remains unchanged during the sampling phase F1.

[0040] The transconductance operational amplifier OTA performs a self-zeroing operation at sampling phase F1, through the self-zeroing capacitor C. AZ The op-amp offset voltage is stored to eliminate offset error. At the falling edge of F1D, the sampling capacitor C... s Level shifting capacitor C LVL Complete the sampling of the input reference voltage.

[0041] In an alternative embodiment, such as Figure 1 As shown, the switch network includes several switching devices, such as SW1-SW9. Each switching device includes switch pairs; for example, switch device SW1 includes switch pairs SW1a and SW1b, switch device SW2 includes switch pairs SW2a and SW2b, and so on. All switch pairs are arranged symmetrically.

[0042] The timing control of the switch network satisfies:

[0043] In the sampling phase F1, as shown in Figure 2 , switches SW1 (SW1a, SW1b), SW2 (SW2a, SW2b), SW4 (SW4a, SW4b), SW8 (SW8a, SW8b), SW9 (SW9a, SW9b) are closed, and SW3 (SW3a, SW3b), SW5 (SW5a, SW5b), SW6 (SW6a, SW6b), SW7 (SW7a, SW7b) are open.

[0044] In the holding phase F2, as shown in Figure 3 , switches SW3 (SW3a, SW3b), SW5 (SW5a, SW5b), SW6 (SW6a, SW6b), SW7 (SW7a, SW7b) are closed, and SW1 (SW1a, SW1b), SW2 (SW2a, SW2b), SW4 (SW4a, SW4b), SW8 (SW8a, SW8b), SW9 (SW9a, SW9b) are open.

[0045] Specifically, in the sampling phase F1 stage of the embodiment: the input reference voltages VRPI, VRNI are connected to the bottom plate of the sampling capacitor C s through switches SW9a, SW9b, the top plate of the sampling capacitor C s is connected to the common node through SW1a, SW1b, the bottom plate of the self-zeroing capacitor C AZ is connected to the input end of the transconductance operational amplifier OTA through SW2a, SW2b to store the operational amplifier offset voltage, the top plate of the level shift capacitor C LVL is connected to the input reference voltages VRPI, VRNI through SW8a, SW8b, the bottom plate of the level shift capacitor C LVL is connected to the common mode voltage VCMO through SW4a, SW4b, and the bottom plate of the feedback capacitor C f is disconnected and in a floating state through SW5b, SW5a, SW6b, SW6a, SW7b, SW7a, and the historical charge is retained (not cleared).

[0046] In the holding phase F2 stage: the bottom plate of the feedback capacitor C f is connected to the output reference voltages VRPO, VRNO through SW6b, SW6a, the bottom plate of the sampling capacitor C s is connected to the output reference voltages VRPO, VRNO through SW7b, SW7a, SW6b, SW6a, the feedback capacitor C f is connected in parallel with the sampling capacitor C s to achieve charge averaging, and the top plate of the level shift capacitor C LVLbottom plate of the capacitor C LVL top plate of the capacitor C VCMO” voltage difference, shifts the output of the transconductance operational amplifier OTA to the range of the common-mode voltage VCMO, and finally makes the output reference voltages VRPO and VRNO track the input reference voltages VRPI and VRNI to realize true rail-to-rail output; meanwhile, the self-resetting capacitor C AZ continuously offsets the transconductance operational amplifier OTA, and the feedback capacitor C f eliminates the non-zero mechanism to improve the equivalent input impedance.

[0047] Therefore, in the embodiment of the present application, in the sampling phase F1: the input voltage is sampled, the operational amplifier offset is stored, and the level shift difference value is recorded, to prepare for the holding phase F2;

[0048] In the holding phase F2: the charge is averaged through the capacitor parallel connection, the level shift breaks through the output range limitation of the operational amplifier, and finally the reference voltage of true rail-to-rail is output.

[0049] The high-precision ADC in the embodiment of the present application includes a feedforward structure sigma-delta ADC or a synchronous SAR ADC.

[0050] The reference voltage buffer proposed in the embodiment of the present application has the following two points. LVL The true rail-to-rail reference voltage output is realized. Specifically, assuming that the input reference voltages VRPI and VRNI are completely rail-to-rail, i.e., VRPI = AVDD (positive power voltage) and VRNI = AVSS (negative power voltage, usually ground). In the F1 phase, the stored voltage of the level shift capacitor C LVL connected to the output reference voltage VRPO is AVDD-VCMO, and the stored voltage of the level shift capacitor C LVL connected to the output reference voltage VRNO is AVSS-VCMO. When the holding phase F2 arrives, the level shift capacitor C LVL shifts the negative output end of the transconductance operational amplifier to AVSS-(AVSS-VCMO) = VCMO, and the positive output end to AVDD-(AVDD-VCMO) = VCMO. It can be seen that in the F2 phase, although the output voltage of the reference voltage buffer is the power ground rail, the positive and negative output ends of the transconductance operational amplifier OTA are both at the output common-mode voltage of the transconductance operational amplifier OTA, thereby ensuring the normal operation of the transconductance operational amplifier OTA.

[0051] The second point is the feedback capacitor C fThe non-reset operation increases the equivalent input resistance. When the feedback capacitor C f After the voltage is established to the input reference voltages VRPI and VRNI, each sampling phase starts at F1, and the sampling capacitor C... s Both are connected to the input reference voltage in a fully charged state, which eliminates the need to adjust the sampling capacitor C during each cycle. s The circuit can be charged and discharged by only charging and discharging a portion of the parasitic capacitance in the circuit. This reduces the amount of input reference voltage drawn, thereby greatly improving the equivalent input impedance of the reference buffer.

[0052] Furthermore, the reference voltage buffer circuit in this embodiment of the application has a low-pass filtering effect on the kT / C noise introduced by the sampling capacitor Cs in the sampling phase F1 during the sampling of the input reference voltage VRPI / VRNI. This allows the capacitance of Cs to be smaller than the capacitance required by a conventional sample-and-hold reference voltage buffer, under the same sampling noise budget. The following is an explanation of the principle of the noise filtering effect: Assume the input differential voltage VRPI-VRNI signal is... The output differential voltage signal VRPO-VRNO is Vo. Therefore, for the (n+1)th cycle, due to charge conservation, we have:

[0053]

[0054] After Z-transformation and simplification, we get:

[0055]

[0056] z represents the complex variable in the z-transform. This represents the expression for the output differential voltage Vo(VRPO-VRNO) in the z-domain. Indicates input differential voltage The expression of (VRPI-VRNI) in the z-domain.

[0057] The transfer function is:

[0058]

[0059] The amplitude-frequency response of this function is a low-pass function, with an amplitude of 1 at DC. The power of the kT / C noise is kT / Cs, and the one-sided noise density is kT / ( Cs), the noise power after the noise is transmitted to VRPO-VRNO for:

[0060]

[0061] Solving the above definite integral yields:

[0062]

[0063] where k is the Boltzmann constant and T is the absolute temperature.

[0064] From the above equation, it can be seen that the kT / C noise introduced by the VRPI-VRNI sampling is attenuated by the feedback capacitor , and under the same kT / C noise budget, the sampling capacitor can be reduced by increasing the feedback capacitor .

[0065] In the embodiments of the present application, since the charge of the feedback capacitor C f is not reset, the charging process of the sampling capacitor Cs to Cf can be regarded as an integration process, and since the integration has an averaging effect on the sampling noise, the capacitance of the sampling capacitor C s can be smaller than the capacitance required by the conventional sample-and-hold reference voltage buffer, and the noise effect is reduced by the averaging effect of the sampling integration process.

[0066] Compared with the prior art, in the embodiments of the present application, another pair of level shift capacitors is introduced to sample the input reference voltage at the same time when the sampling capacitor samples the input reference voltage. Then, in the hold phase, the level shift capacitors are connected between the output of the operational amplifier and the output reference voltage, so that the output voltage of the operational amplifier works in a reasonable output range, and the true rail-to-rail output of the reference voltage is realized. In addition, the original sampling establishment process is replaced by a sampling integration process in the embodiments of the present application, and the charge on the feedback capacitor is not cleared in the sampling phase, so that the amount of charge drawn from the input reference voltage is reduced, and the equivalent input impedance is improved. Compared with the conventional sample-and-hold reference voltage buffer circuit, the embodiments of the present application realize the advantages of true rail-to-rail input and output capability of the reference voltage and high equivalent input impedance by introducing the mechanism of the level shift capacitors and the non-zeroing of the feedback capacitor.

[0067] The technical features of the above-described embodiments can be combined in any manner. To make the description concise, not all possible combinations of the technical features in the above-described embodiments are described, but it should be considered that any combination of the technical features is within the scope of the present disclosure as long as the combination does not contradict.

[0068] The above-described embodiments only express several implementation manners of the present application, and the description is relatively specific and detailed, but it should not be understood as a limitation on the patent scope of the application. It should be noted that for ordinary skilled persons in the art, some modifications and improvements can be made without departing from the concept of the present application, and these are within the protection scope of the present application. Therefore, the patent protection scope of the present application should be subject to the appended claims.

[0069] Those skilled in the art can understand that the above-mentioned embodiments are specific embodiments for implementing the present application, and various changes can be made in form and details in practical application without departing from the spirit and scope of the present application.

Claims

1. A true rail-to-rail input / output reference voltage buffer circuit suitable for high-precision ADCs, characterized in that, The circuit alternately executes sampling phase F1 and holding phase F2 during operation; the circuit includes: a sampling capacitor module, a level shifting capacitor module, a feedback capacitor module, a transconductance operational amplifier (OTA), and a switching network; the sampling capacitor module includes at least one pair of sampling capacitors C. s The level shifting capacitor module includes at least one pair of level shifting capacitors C. LVL The feedback capacitor module includes at least one pair of feedback capacitors C. f ; Sampling capacitor C s The bottom plate tracks the input reference voltage in sampling phase F1, and the top plate is reset to ground for sampling the input signal; Level shift capacitor C LVL The difference between the input reference voltage and the output common-mode voltage of the transconductance operational amplifier OTA is synchronously sampled in sampling phase F1, and connected to the output terminal of the transconductance operational amplifier OTA in holding phase F2 to achieve true rail-to-rail range extension of the output voltage. The level shifting capacitor C LVL The top plate is connected to the input reference voltage and to the output reference voltage through switches SW5 and SW6 of the switch network. The bottom plate is connected to the output common-mode voltage of the transconductance operational amplifier OTA through switch SW4 of the switch network and to the output terminal of the transconductance operational amplifier OTA through switch SW3 of the switch network. Feedback capacitor C f The charge is not cleared in sampling phase F1, while maintaining the relationship between phase F2 and sampling capacitor C. s The parallel connection achieves the establishment of the output voltage through charge averaging, wherein the feedback capacitor C f By maintaining the floating state of switches SW5 and SW6 during sampling phase F1, the stored charge is not reset, reducing charge draw from the input reference voltage and increasing the equivalent input impedance. The feedback capacitor C... f The specific operation of not clearing the charge in sampling phase F1 is as follows: the feedback capacitor C f The two ends of the device are not connected to a reset voltage, and the charge stored on it remains unchanged during the sampling phase F1; The switching network is used to control the capacitor connection state of sampling phase F1 and holding phase F2.

2. The circuit according to claim 1, characterized in that, The level shifting capacitor C LVL The input reference voltage is connected to the top plate of the sampling phase F1, and the common-mode voltage of the transconductance operational amplifier OTA is connected to the bottom plate; the output terminal of the transconductance operational amplifier OTA is connected to the top plate of the holding phase F2, and the output reference voltage is connected to the bottom plate, so that the output voltage of the transconductance operational amplifier OTA is shifted to the output common-mode voltage.

3. The circuit according to claim 1, characterized in that, The transconductance operational amplifier OTA performs a self-zeroing operation at sampling phase F1 through the self-zeroing capacitor C. AZ Store the op-amp offset voltage to eliminate offset error.

4. The circuit according to any one of claims 1-3, characterized in that, The switching network includes several switching devices, wherein switch SW1 is connected at one end to the top plate of sampling capacitor Cs and at the other end to the common ground node; switch SW2 is connected across the bottom plate of self-zeroing capacitor CAZ and the input terminal of transconductance operational amplifier OTA; switch SW7 is connected at one end to the bottom plate of sampling capacitor Cs and at the other end to switch SW6; switch SW8 is connected at one end to the top plate of level shift capacitor CLVL and at the other end to the input reference voltage; and switch SW9 is connected at one end to the input reference voltage and at the other end to the bottom plate of sampling capacitor Cs. The timing control of the switching network satisfies: During sampling phase F1, switches SW1, SW2, SW4, SW8, and SW9 are closed, while switches SW3, SW5, SW6, and SW7 are open. While maintaining phase F2, switches SW3, SW5, SW6, and SW7 are closed, while switches SW1, SW2, SW4, SW8, and SW9 are open.

5. The circuit according to claim 4, characterized in that, The switching device includes a pair of switches, all of which are symmetrically arranged.

6. The circuit according to claim 1, characterized in that, The high-precision ADC includes a feedforward sigma-delta ADC or a synchronous SAR ADC.

7. The circuit according to claim 1, characterized in that: The circuit described above provides low-pass filtering for noise introduced during the sampling process, and its output noise power... The following relationship must be satisfied: Where k is the Boltzmann constant and T is the absolute temperature.

8. The circuit according to claim 1, characterized in that, The true rail-to-rail input and output are specifically defined as follows: the range of the input reference voltage covers the analog power supply voltage to the analog ground voltage, and the range of the output reference voltage simultaneously covers the analog power supply voltage to the analog ground voltage.

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