Semiconductor structure and forming method thereof
By forming multiple grooves on the substrate and filling them with a dielectric layer, the problems of stacking structure peeling and leakage in 3D DRAM are solved, and the electrical performance of the memory cell is improved.
Patent Information
- Application Number
- CN202410740575.0
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-06-07
- Publication Date
- 2025-12-09
AI Technical Summary
During the fabrication of 3D DRAM, the stacked structure is prone to peeling off from the substrate or leakage, which affects the electrical performance of the memory cells.
Multiple grooves are formed in different regions of the substrate, and dielectric layers are filled in the sidewalls and bottom of the grooves to form a connected dielectric layer structure to protect the substrate from etching and ion implantation.
It effectively prevents the peeling of the stacked structure and substrate leakage, thus improving the electrical performance of the memory cell.
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Figure CN121099604A_ABST
Abstract
Description
TECHNICAL FIELD
[0001] Embodiments of the present disclosure relate to the technical field of semiconductor technology, and particularly relate to a preparation method of a semiconductor structure and the semiconductor structure. BACKGROUND
[0002] With the development of the integration density of dynamic memory towards higher direction, higher requirements are generated for the arrangement mode of transistors and the size of transistors in the structure of a dynamic memory array. However, due to the limitation of manufacturing factors such as photolithography machines and various electrical parasitic effects, there is a limit to the reduction of the critical dimension, and therefore, how to make a chip with higher storage density on a wafer is the research direction of many researchers and semiconductor practitioners.
[0003] The emergence of three-dimensional dynamic random memory (3D DRAM), especially 3D DRAM including multilayer horizontal cells (MHC), generally includes a plurality of transistors stacked on a substrate, which meets the above requirements. To form the stacked multilayer horizontal cells, an initial stack structure needs to be formed on the substrate, and then etching, ion implantation, deposition and other processes are performed on the stack structure. In this process, the substrate is easily etched or ion implanted, which causes the stack structure to be peeled off from the substrate or the substrate to have a leakage phenomenon, affecting the electrical performance of the finally formed storage unit. SUMMARY
[0004] Embodiments of the present disclosure provide a preparation method of a semiconductor structure and the semiconductor structure, which at least helps to prevent etching of the substrate, helps to reduce the risk of peeling off the stack structure from the substrate, improves the leakage phenomenon of the storage unit, and improves the overall electrical performance of the storage unit.
[0005] In an aspect, the present disclosure provides a preparation method of a semiconductor structure, comprising:
[0006] providing a substrate; the substrate includes a first region and a second region distributed along a first direction, and forming a stack structure on the substrate;
[0007] forming a plurality of first grooves, the plurality of first grooves being located in the first region of the substrate, and the plurality of first grooves being located in the substrate, the first grooves extending along a first direction, and a plurality of the first grooves being arranged at intervals along a second direction; a plane determined by the first direction and the second direction is parallel to the surface of the substrate;
[0008] forming a first dielectric layer on the sidewall of the first groove;
[0009] etching the substrate along the bottom of the first groove to form a second groove inside the substrate, adjacent first grooves being connected to each other by the second groove along the second direction;
[0010] filling the second groove with a second dielectric layer.
[0011] In some embodiments, further comprising:
[0012] forming a third groove in the second region of the substrate and extending along the second direction, and the third groove being inside the substrate;
[0013] forming a third dielectric layer on the sidewall of the third groove;
[0014] etching the substrate along the bottom of the third groove to form a fourth groove inside the substrate, the fourth groove exposing the side of the second dielectric layer along the first direction;
[0015] filling the fourth groove with a fourth dielectric layer;
[0016] the fourth dielectric layer inside the substrate being connected to the second dielectric layer inside the substrate.
[0017] In some embodiments, before forming the plurality of first grooves, further comprising: patterning the stack structure to form an initial layer stack structure, the initial layer stack structure comprising a plurality of first portions in the first region and a second portion in the second region; the plurality of first portions extending along the first direction, and the second portion extending along the second direction;
[0018] the plurality of first portions being spaced apart along the second direction, and a first trench isolation structure being formed between adjacent first portions;
[0019] etching the substrate along the bottom of the first trench isolation structure to form the first groove;
[0020] the first groove being connected to the first trench isolation structure.
[0021] In some embodiments, before forming the third groove, further comprising: patterning the second portion of the second region to form a second trench isolation structure, the second trench isolation structure extending along the second direction, and etching the substrate along the bottom of the second trench isolation structure to form the third groove;
[0022] the third groove being connected to the second trench isolation structure.
[0023] In some embodiments, the second recess separates the substrate in the first region into a first substrate under the second recess and a second substrate over the second recess, the fourth recess separates the substrate in the second region into a third substrate under the fourth recess and a fourth substrate over the fourth recess, the first substrate and the third substrate are connected to each other, and the second substrate and the fourth substrate are connected to each other.
[0024] In some embodiments, further comprising: filling a first sacrificial dielectric layer in the first trench isolation structure, and filling a second sacrificial dielectric layer in the second trench isolation structure, the first sacrificial dielectric layer and / or the second sacrificial dielectric layer is polysilicon or low-k dielectric material.
[0025] In some embodiments, the first sacrificial dielectric layer and / or the second sacrificial dielectric layer is in contact with the substrate, or a second dielectric layer or a fourth dielectric layer is disposed between the first sacrificial dielectric layer and / or the second sacrificial dielectric layer and the substrate.
[0026] In some embodiments, the stack structure comprises a first semiconductor layer and a second semiconductor layer stacked in sequence, the first semiconductor layer is germanium-silicon, and the second semiconductor layer is silicon.
[0027] In some embodiments, the first dielectric layer, the second dielectric layer, the third dielectric layer, or the fourth dielectric layer is one or more of silicon oxide, silicon nitride, silicon oxynitride, and low-k dielectric material.
[0028] In some embodiments, along a third direction, a depth of the fourth recess is greater than or equal to a depth of the second recess, the third direction intersects a plane determined by the first direction and the second direction.
[0029] In some embodiments, along the third direction, a thickness of the fourth dielectric layer is greater than a thickness of the second dielectric layer.
[0030] Another aspect of the embodiments of the present disclosure further provides a semiconductor structure, comprising:
[0031] a substrate, the substrate comprising a first region and a second region distributed along a first direction;
[0032] a stack device layer on an upper surface of the substrate;
[0033] The substrate comprises a first substrate and a second substrate in the first region, and a third substrate and a fourth substrate in the second region; the first substrate and the second substrate are spaced apart along a third direction, and the third substrate and the fourth substrate are spaced apart along the third direction; the first direction is parallel to the surface of the substrate, and the third direction intersects the surface of the substrate;
[0034] A second dielectric layer is located between the first substrate and the second substrate;
[0035] A fourth dielectric layer is located between the third substrate and the fourth substrate;
[0036] The second dielectric layer and the fourth dielectric layer are connected to each other.
[0037] In the third direction, the thickness of the fourth dielectric layer is greater than the thickness of the second dielectric layer.
[0038] In some embodiments, in the first direction, the interface between the fourth dielectric layer and the third substrate and / or the fourth substrate is curved.
[0039] In some embodiments, in the second direction, the interface between the second dielectric layer and the first substrate and / or the second substrate is curved, and the plane determined by the first direction and the second direction is parallel to the surface of the substrate.
[0040] In some embodiments, the stacked device layer comprises a plurality of transistor structures and / or a plurality of capacitor structures stacked in the third direction.
[0041] The technical solutions provided by the embodiments of the present disclosure have at least the following advantages: a substrate is provided, a plurality of first grooves are formed in a first region of the substrate, a first dielectric layer is formed on the sidewalls of the first grooves, the substrate is etched along the bottom of the first grooves to form second grooves inside the substrate, and a second dielectric layer is filled in the second grooves; a third groove is formed in a second region of the substrate, a third dielectric layer is formed on the sidewalls of the third groove; the substrate is etched along the bottom of the third groove to form a fourth groove inside the substrate, the fourth groove exposes the side surface of the second dielectric layer in the first direction; a fourth dielectric layer is filled in the fourth groove; and the fourth dielectric layer inside the substrate is connected to the second dielectric layer inside the substrate. The dielectric layer formed by the embodiments of the present disclosure can protect the substrate, prevent the peeling of the stacked structure and the leakage of the substrate, and improve the electrical performance of the stacked device. BRIEF DESCRIPTION OF DRAWINGS
[0042] One or more embodiments are illustrated by way of example in the drawings and specification hereof, which are not intended to limit the embodiments to the specific embodiments pictured and described. Wherever possible, specific terminology used in here has been used for the sake of clarity. It is not intended that the disclosure be limited to the specific embodiments described.
[0043] Figure 1 A flow chart of a method for manufacturing a semiconductor structure according to an embodiment of the present disclosure is provided.
[0044] Figures 2-20 A cross-sectional view corresponding to each step of a method for manufacturing a semiconductor structure according to an embodiment of the present disclosure is provided.
[0045] Figures 21-23 A schematic view of a partial cross-section of a semiconductor structure according to an embodiment of the present disclosure is provided.
[0046] Legend of reference signs:
[0047] I: first region; II: second region; 201: substrate; 2011: first substrate; 2012: second substrate; 2013: third substrate; 2014: fourth substrate; 200: stacked structure; 202: first semiconductor layer; 203: second semiconductor layer; 300: initial layer stack; 301: first portion; 302: second portion; 204: first trench isolation structure; 208: second trench isolation structure; 206: first gap; 210: second gap; 205: first recess; 207: second recess; 209: third recess; 211: fourth recess; 400: stacked device layer; 401: first dielectric layer; 501: second dielectric layer; 601: first sacrificial dielectric layer; 701: third dielectric layer; 801: fourth dielectric layer; 901: second sacrificial dielectric layer. DETAILED DESCRIPTION
[0048] The technical solutions of the present disclosure will be described in further detail below with reference to the drawings and embodiments. Although the exemplary implementation methods of the present disclosure are shown in the drawings, it should be understood that the present disclosure can be implemented in various forms and should not be limited by the implementation described here. On the contrary, these implementations are provided to enable a more thorough understanding of the present disclosure and to fully convey the scope of the present disclosure to those skilled in the art.
[0049] The present disclosure is described more by way of example with reference to the following paragraphs and accompanying drawings. The advantages and features of the disclosure will become more fully apparent in light of the following description and claims, appended hereto. It should be understood that the drawings are not to scale, and are merely intended for use in illustrating the embodiments of the disclosure; and where used, like reference characters designate like elements throughout the several views.
[0050] It is to be understood that the terms "on", "over", and "above" in the present disclosure are to be interpreted in the broadest possible way, such that "on" not only means "on" something without intervening intermediate features or layers (i.e., directly on something), but also includes "on" something with intervening intermediate features or layers.
[0051] In the embodiments of the present disclosure, the terms "first", "second", "third", etc. are used to distinguish similar objects, and do not necessarily have to describe a specific order or sequence.
[0052] In the embodiments of the present disclosure, the term "layer" refers to a portion of material that includes a region having a thickness. The layer can extend over the entirety of an underlying or overlying structure, or can have a scope that is less than the scope of an underlying or overlying structure. Further, a layer can be a region of a homogeneous or inhomogeneous continuous structure that has a thickness that is less than the thickness of the continuous structure. For example, a layer can be located between a top surface and a bottom surface of a continuous structure, or the layer can be between any pair of horizontal planes at the top surface and the bottom surface of the continuous structure. A layer can extend horizontally, vertically, and / or along an inclined surface. A layer can include multiple sub-layers.
[0053] It should be noted that the technical solutions described in the embodiments of the present disclosure can be combined arbitrarily without conflict.
[0054] As can be known from the background art, in the preparation process of the 3D DRAM, a stack structure is usually formed on the substrate first, and then the transistors, bit lines, word lines and capacitors of the memory cells are formed by etching or ion implantation on the stack structure. The number of the stack structure directly determines the storage density of the memory cells. Therefore, the formation process of the stack structure is crucial to the final performance and storage density of the 3D DRAM. The current stack structure is usually divided into two types: one is a non-epitaxial structure (Non-EPI) stack formed by a deposition process, which is a non-epitaxial structure of a dielectric layer and a dielectric layer (ONON) or a dielectric layer and a semiconductor layer (OPOP); and the other is an epitaxial structure (EPI) stack formed by an epitaxial process, which is usually a Si-SiGe epitaxial structure. Since the stack structure formed by the epitaxial structure is usually consistent with the lattice structure of the substrate, the stack structure formed has better lattice consistency, and the electrical properties of the formed memory cells tend to be consistent. Therefore, the stack structure formed based on the EPI process is the main process method for forming the 3D DRAM. The EPI process needs to use the substrate as an epitaxial substrate for epitaxial process. Therefore, the etching stop layer cannot be formed on the surface of the substrate. In the etching process, due to the limitation of the etching selectivity, the substrate used to form the stack structure will also be etched, which causes the substrate to be unable to be effectively protected and easily be etched or ion implanted multiple times, resulting in a risk of peeling of the stack structure on the substrate. In addition, due to the ion implantation of the substrate, the substrate may have a risk of electric leakage, which seriously causes the memory cells to be unable to work normally, reduces the electrical properties of the memory cells, and affects the device yield of the finally formed 3D DRAM.
[0055] The present disclosure provides a preparation method of a semiconductor structure, which comprises: providing a substrate, forming a plurality of first grooves in a first region of the substrate, and forming a first dielectric layer on the sidewalls of the first grooves; etching the substrate along the bottom of the first grooves to form a second groove inside the substrate, and filling a second dielectric layer in the second groove; forming a third groove in a second region of the substrate, and forming a third dielectric layer on the sidewalls of the third groove; etching the substrate along the bottom of the third groove to form a fourth groove inside the substrate, and the fourth groove exposes the side surface of the second dielectric layer in the first direction; filling a fourth dielectric layer in the fourth groove; and the fourth dielectric layer inside the substrate and the second dielectric layer inside the substrate are connected to each other. The dielectric layer formed in the present disclosure can protect the substrate, prevent the peeling of the stack structure and the electric leakage of the substrate, and improve the electrical properties of the stack device. In the following, the embodiments of the present disclosure will be described in detail with reference to the accompanying drawings. However, those skilled in the art can understand that in the embodiments of the present disclosure, many technical details are proposed in order to enable the readers to better understand the embodiments of the present disclosure. However, the technical solutions claimed by the embodiments of the present disclosure can be realized even without these technical details and various changes and modifications based on the following embodiments.
[0056] An embodiment of the present disclosure provides a method for preparing a semiconductor structure, which will be described in detail below in combination with the accompanying drawings. Figure 1 A flowchart of the method for preparing a semiconductor structure provided by an embodiment of the present disclosure.
[0057] Reference Figure 1 The method for preparing a semiconductor structure specifically comprises the following steps:
[0058] S01: providing a substrate; the substrate comprises a first region and a second region distributed along a first direction, and a stack structure is formed on the substrate;
[0059] S02: forming a plurality of first grooves, the plurality of first grooves being located in the first region of the substrate, and the plurality of first grooves being located in the substrate, the first grooves extending along a first direction, and the plurality of first grooves being arranged at intervals along a second direction; a plane determined by the first direction and the second direction is parallel to the surface of the substrate;
[0060] S03: forming a first dielectric layer on the sidewall of the first groove; etching the substrate along the bottom of the first groove to form a second groove located inside the substrate, along the second direction, adjacent first grooves being connected to each other through the second groove, and filling a second dielectric layer in the second groove;
[0061] S04: forming a third groove, the third groove being located in the second region of the substrate and extending along the second direction, and the third groove being located in the substrate;
[0062] S05: forming a third dielectric layer on the sidewall of the third groove; etching the substrate along the bottom of the third groove to form a fourth groove located inside the substrate, the fourth groove exposing the side surface of the second dielectric layer along the first direction; filling a fourth dielectric layer in the fourth groove; the fourth dielectric layer located inside the substrate and the second dielectric layer located inside the substrate are connected to each other.
[0063] Figures 2-20 The local schematic diagrams corresponding to each step in the method for preparing a semiconductor structure provided by an embodiment of the present disclosure are shown below, and the method for preparing a semiconductor structure provided by an embodiment of the present disclosure will be described in detail below in combination with Figures 2-20 The method for preparing a semiconductor structure provided by an embodiment of the present disclosure will be described in detail below.
[0064] Step S01: providing a substrate; the substrate comprises a first region and a second region distributed along a first direction X, and a stack structure is formed on the substrate; specifically comprising the following steps, as shown in Figure 2As shown, a substrate 201 is provided, which includes a first region I and a second region II distributed along a first direction X according to the dashed line shown in the figure, wherein the substrate material includes monocrystalline silicon, polycrystalline silicon, amorphous silicon, germanium, silicon carbide, silicon germanium, germanium on insulator (GOI) or silicon on insulator (SOI), etc. In the embodiments of the present disclosure, in order to form a silicon-germanium silicon stack structure on the substrate by using an epitaxial process, the substrate material is selected as a monocrystalline silicon material, and in some embodiments, an N-type or P-type substrate 201 can be formed by performing an N-type or P-type doping treatment and an annealing treatment on the monocrystalline silicon material, and the N-type element can be a group V element such as phosphorus (P) element, bismuth (Bi) element, antimony (Sb) element or arsenic (As) element. The P-type element can be a group III element such as boron (B) element, aluminum (Al) element, gallium (Ga) element or indium (In) element. In some embodiments, only the upper surface of the substrate can be subjected to the doping treatment to form an N-type doped layer or a P-type doped layer on the substrate surface, or the entire substrate can be subjected to the doping treatment to form an N-type substrate 201 or a P-type substrate 201. In the embodiments of the present disclosure, before the epitaxial formation of the stack structure on the substrate 201, the surface of the substrate 201 can be pretreated to remove impurities or natural oxide layers on the surface. For example, Figure 2 As shown, a multi-layer stack structure 200 is formed on the substrate 201 and stacked along a third direction Z, and along the third direction, the stack structure 200 includes a first semiconductor layer 202 and a second semiconductor layer 203 stacked in sequence. The first semiconductor layer 202 can be formed of or include at least one of, for example, silicon germanium, silicon oxide, silicon nitride and silicon oxynitride. In some embodiments, the first semiconductor layer 202 can be formed by an epitaxial growth method and can be, for example, a silicon germanium layer. The second semiconductor layer 203 can be formed of or include at least one of, for example, silicon, germanium, silicon germanium and indium gallium zinc oxide (IGZO). In some embodiments, the second semiconductor layer 203 can be formed of or include the same semiconductor material as the substrate 201. For example, the second semiconductor layer 203 can be formed by an epitaxial growth method and can be a monocrystalline silicon layer. In the embodiments of the present disclosure, a germanium silicon layer and a silicon layer formed by epitaxial growth are taken as examples for illustration, and the formed stack structure has a crystal structure similar to a superlattice. Since the crystal lattice structures of the germanium silicon layer and the silicon layer are the same, the stack structure can be formed by epitaxial growth, which reduces the generation of defects in the stack structure and is beneficial to improve the electrical performance of the formed semiconductor structure. The embodiments of the present disclosure take the formation of a five-layer stack structure as an example for illustration, and in actual processes, this is not limited thereto, and the number of stack layers can be selected according to actual stack requirements.
[0065] Step S02: forming a plurality of first grooves in the first region of the substrate, and the plurality of first grooves are formed in the substrate, the first grooves extend along a first direction, and the plurality of first grooves are arranged at intervals along a second direction; the plane determined by the first direction and the second direction is parallel to the surface of the substrate; specifically including the following steps, such as Figure 3 As shown in FIG. 2, a mask layer (not shown) is formed above the stack structure 200, and the stack structure 200 is subjected to a patterning process, which includes dry etching, wet etching, or a combination of the two. After the patterning process, the stack structure 200 forms an initial layer stack structure 300, which includes a plurality of first portions 301 in the first region I and a second portion 302 in the second region II. The plurality of first portions 301 extend along a first direction X, and the second portion 302 extends along a second direction Y. The plurality of first portions are arranged at intervals along the second direction, and a first trench isolation structure 204 is formed between adjacent first portions along the second direction. The first trench isolation structure 204 exposes part of the surface of the substrate 201. Through the exposed part of the surface, the substrate 201 is subjected to dry or wet etching to form a plurality of first grooves 205 in the first region I of the substrate, Figure 4a and 4b respectively Figure 3 After etching the substrate 201 along A-A' and B-B', the cross-sectional views are shown in FIGS. 3 and 4, respectively, with reference to Figure 3 and Figure 4a and 4b As shown in FIG. 5, by forming a mask layer (not shown) on the initial layer stack structure 300, the substrate 201 exposed by the first trench isolation structure 204 is etched to form a plurality of first grooves 205 extending into the substrate 201 along a third direction Z. The plurality of first grooves 205 extend along the first direction, and the plurality of first grooves 205 are arranged at intervals along the second direction Y, as shown in FIG. 6. Figure 4a As can be seen, the plurality of first grooves 205 are formed by etching the substrate exposed by the plurality of first trench isolation structures 204, and therefore the plurality of first grooves 205 and the corresponding plurality of first trench isolation structures 204 are in communication with each other. In some embodiments, the first grooves 205 and the first trench isolation structures 204 can be formed in the same step, that is, while the stack structure 200 is subjected to the patterning process to form the initial layer stack structure 300, the substrate 201 is also subjected to the patterning process to form the plurality of first grooves 205 in the substrate 201, and the present disclosure does not make specific limitations thereto.
[0066] Step S03: forming a first dielectric layer on the sidewall of the first groove; etching the substrate along the bottom of the first groove to form a second groove inside the substrate, along the second direction, adjacent first grooves are connected to each other through the second groove, and filling the second groove with a second dielectric layer; specifically including the following steps, as shown in Figure 5a and 5b As shown in FIG. 4B, the first semiconductor layer 202 in the first part 301 is removed by selective etching of the initial layer stack 300 through the first trench isolation structure 204. In some embodiments, a wet etching process can be used to remove the first semiconductor layer 202. By using an etching selectivity ratio (e.g., greater than 10:1) between the first semiconductor layer 202 and the second semiconductor layer 203, the first semiconductor layer 202 on the first region I is removed, while the second semiconductor layer 203 is not etched or is etched in a small amount, thereby forming a plurality of first gaps 206 between the second semiconductor layer 203, which are in communication with the first trench isolation structure 204. Figure 6a and 6b As shown in FIG. 4C, a first dielectric layer 401 is deposited by a process such as chemical vapor deposition (CVD), physical vapor deposition (PVD), or atomic layer deposition (ALD), etc. The first dielectric layer 401 fills the first gap 206, the sidewall of the first trench isolation structure 204, the sidewall and the bottom of the first groove 205. In some embodiments, after the first dielectric layer 401 is deposited, a chemical mechanical polishing (CMP) process can be used to remove the top portion of the first dielectric layer, so that the top of the first dielectric layer 401 after polishing is flush with the top surface of the second semiconductor layer 203 or the mask layer on the uppermost layer. In some embodiments, the material of the deposited first dielectric layer includes one or a combination of silicon oxide (SiO2), silicon nitride (SiN), silicon oxynitride (SiON), and low-k dielectric material. The low-k dielectric material refers to a material with a dielectric constant less than 3, for example, the low-k dielectric constant material can be but is not limited to one or a combination of two or more of SiOH, SiOCH, FSG (fluorosilicate glass), BSG (borosilicate glass), PSG (phosphosilicate glass), and BPSG (borophosphosilicate glass). As shown in Figure 7a and 7bAs shown, the first dielectric layer 401 at the bottom of the first recess 205 is etched to remove the first dielectric layer at the bottom and retain the first dielectric layer 401 at the sidewall of the first recess 205. In some embodiments, a dry etching process can be used to etch the first dielectric layer 401 at the bottom of the first recess 205. Specifically, a plasma etching process can be used to perform an anisotropic etching process on the first dielectric layer 401 to remove the first dielectric layer at the bottom of the first recess 205, while the first dielectric layer 401 at the sidewall of the first recess 205 and the first trench isolation structure 204 is not etched or etched by a small amount. By removing the first dielectric layer 401 at the bottom of the first recess 205, part of the surface of the substrate 201 is exposed. As shown in Figure 8a and 8b As shown, the first dielectric layer 401 at the bottom of the first recess 205 is etched to remove the first dielectric layer at the bottom and retain the first dielectric layer 401 at the sidewall of the first recess 205. In some embodiments, a dry etching process can be used to etch the first dielectric layer 401 at the bottom of the first recess 205. Specifically, a plasma etching process can be used to perform an anisotropic etching process on the first dielectric layer 401 to remove the first dielectric layer at the bottom of the first recess 205, while the first dielectric layer 401 at the sidewall of the first recess 205 and the first trench isolation structure 204 is not etched or etched by a small amount. By removing the first dielectric layer 401 at the bottom of the first recess 205, part of the surface of the substrate 201 is exposed. As shown in Figure 7a and 8a As shown, the first dielectric layer 401 at the bottom of the first recess 205 is etched to remove the first dielectric layer at the bottom and retain the first dielectric layer 401 at the sidewall of the first recess 205. In some embodiments, a dry etching process can be used to etch the first dielectric layer 401 at the bottom of the first recess 205. Specifically, a plasma etching process can be used to perform an anisotropic etching process on the first dielectric layer 401 to remove the first dielectric layer at the bottom of the first recess 205, while the first dielectric layer 401 at the sidewall of the first recess 205 and the first trench isolation structure 204 is not etched or etched by a small amount. By removing the first dielectric layer 401 at the bottom of the first recess 205, part of the surface of the substrate 201 is exposed. As shown in Figure 9a and 9b As shown, a second dielectric layer 501 is deposited by a process such as chemical vapor deposition (CVD), physical vapor deposition (PVD), or atomic layer deposition (ALD), etc. The second dielectric layer 501 fills the second recess 207 and covers the sidewall of the first dielectric layer 401. In some embodiments, the material of the deposited second dielectric layer includes one or a combination of silicon oxide (SiO2), silicon nitride (SiN), silicon oxynitride (SiON), and low-k dielectric material. As shown in Figure 10a and 11aThe second dielectric layer 501 at the bottom of the first groove 205 is etched to remove the bottom second dielectric layer while retaining the second dielectric layer 501 located on the sidewall of the first groove 205. In some embodiments, a dry etching process can be used to etch the second dielectric layer 501 at the bottom of the first groove 205. Specifically, a plasma etching process can be used to perform anisotropic etching on the second dielectric layer 501 to remove the second dielectric layer 501 located at the bottom of the first groove 205. Figure 11a As shown, a first sacrificial dielectric layer 601 is filled in the first trench isolation structure 204 and the first groove 205, which can be formed by chemical vapor deposition, physical vapor deposition, or atomic layer deposition. Since the second dielectric layer 501 at the bottom of the first groove 205 is etched, the filled first sacrificial dielectric layer 601 is in direct contact with the first substrate 2011 in the substrate 201. In some embodiments, only a portion of the second dielectric layer 501 at the bottom of the first groove 205 may be removed, so that the first sacrificial dielectric layer 601 is not in direct contact with the first substrate 2011, but rather in direct contact with the remaining second dielectric layer 501. In this disclosure, there is no specific limitation on whether the first sacrificial dielectric layer is in direct contact with the substrate. In some embodiments, the material of the first sacrificial dielectric layer 601 is polycrystalline silicon or a low-k dielectric material.
[0067] Step S04: Forming a third groove, the third groove being located in the second region of the substrate and extending along the second direction, and the third groove being located within the substrate, specifically including; such as Figures 12-13 A mask layer (not shown) is formed above the second portion 302 of the initial stacked structure 300. The second portion 302 is then patterned using dry etching, wet etching, or a combination of both to form a second trench isolation structure 208. This second trench isolation structure 208 extends along the second direction Y and exposes a portion of the substrate 201's surface located in the second region II. Through this exposed surface, the substrate 201 is subjected to dry or wet etching to form a third groove 209 located in the second region II of the substrate 201. This third groove 209 extends along the second direction Y and into the substrate 201 along the third direction Z. Figures 12-13 It can be seen that the third groove 209 is achieved by etching the substrate exposed by the second trench isolation 208. Therefore, the third groove 209 and the second trench isolation structure 208 are interconnected. In some embodiments, the third groove 209 and the second trench isolation structure 208 can be formed in the same step, that is, while the second part 302 is patterned, the substrate 201 is also patterned to form the third groove 209 located in the substrate 201. This disclosure does not specifically limit this aspect.
[0068] Step S05: forming a third dielectric layer on the sidewall of the third groove; etching the substrate along the bottom of the third groove to form a fourth groove inside the substrate, the fourth groove exposing the side surface of the second dielectric layer along the first direction; filling the fourth groove with a fourth dielectric layer; the fourth dielectric layer inside the substrate and the second dielectric layer inside the substrate are connected to each other, specifically including: Figure 14 As shown, the second part 302 is selectively etched by the second trench isolation structure 208 to remove the first semiconductor layer 202 in the second part 302. In some embodiments, a wet etching process can be used to remove the first semiconductor layer 202, and by using an etching selectivity ratio (such as greater than 10:1) between the first semiconductor layer 202 and the second semiconductor layer 203, the first semiconductor layer 202 on the second region II is removed, while the second semiconductor layer 203 is not etched or is etched in a small amount, thereby forming a plurality of second gaps 210 between the second semiconductor layer 203, and the plurality of second gaps 210 are in communication with the second trench isolation structure 208. Figure 15 As shown, a third dielectric layer 701 is deposited by a chemical vapor deposition, physical vapor deposition or atomic layer deposition process, and the third dielectric layer 701 fills the second gap 210, the sidewall of the second trench isolation structure 208, and the sidewall and bottom of the third groove 209. In some embodiments, after the third dielectric layer 701 is deposited, a chemical mechanical polishing process can be used to remove the top third dielectric layer 701, so that the top of the third dielectric layer 701 after polishing is flush with the top surface of the uppermost second semiconductor layer 203 or the mask layer. In some embodiments, the material of the deposited third dielectric layer includes one or a combination of silicon oxide (SiO2), silicon nitride (SiN), silicon oxynitride (SiON), and low-k dielectric material. Figure 16 As shown, the third dielectric layer 701 at the bottom of the third groove 209 is etched to remove the third dielectric layer at the bottom while retaining the third dielectric layer 701 at the sidewall of the third groove 209. In some embodiments, a dry etching process can be used to etch the third dielectric layer 701 at the bottom of the third groove 209, specifically, an anisotropic etching process can be used to etch the third dielectric layer 701, to remove the third dielectric layer at the bottom of the third groove 209, while the third dielectric layer 701 at the sidewall of the third groove 209 and the second trench isolation structure 208 is not etched or is etched in a small amount. By removing the third dielectric layer 701 at the bottom of the third groove 209, part of the surface of the substrate 201 is exposed. Figure 17As shown, the third medium layer 701 of the sidewall of the third recess 209 is used as an etching mask to etch the substrate 201 exposed at the bottom of the third recess 209 to form a fourth recess 211 inside the substrate 201, and the fourth recess 211 is located in the second region II of the substrate 201. Figure 17 As can be seen, the fourth recess 211 formed by etching is located inside the substrate 201, that is, the substrate 201 in the second region II is separated into a third substrate 2013 located below the fourth recess 211 and a fourth substrate 2014 located above the fourth recess 211 by the third recess 209. In some embodiments, the fourth recess 211 extends along the first direction X and the second direction Y and covers the entire second region II. In some embodiments, the fourth recess 211 is formed by etching the substrate 201 by a wet isotropic etching process. In the wet etching process, the etching selectivity of the substrate 201 and the third medium layer 701 is relatively large (e.g., greater than 10:1), so that the third medium layer 701 can be used as an etching stop layer and is not etched or is etched in a small amount during the etching process to remove part of the substrate 201. As shown in Figure 17 The fourth recess 211 located inside the substrate is in communication with the third recess 209, and the fourth recess 211 exposes the side of the second medium layer 501 along the first direction X. As shown in Figure 18 The fourth medium layer 801 is deposited by a process such as chemical vapor deposition, physical vapor deposition, or atomic layer deposition, and the fourth medium layer 801 fills the fourth recess 211 and covers the sidewall of the third medium layer 701. In some embodiments, the material of the deposited fourth medium layer includes one or a combination of silicon oxide (SiO2), silicon nitride (SiN), silicon oxynitride (SiON), and low-k dielectric material. As shown in Figure 18 The filled fourth medium layer 801 is connected to the second medium layer 501 located inside the substrate in the first region I. In some embodiments, the material of the fourth medium layer 801 is the same as that of the second medium layer 501, such as both being silicon oxide material.
[0069] As shown in Figure 19 The fourth medium layer 801 at the bottom of the third recess 209 is etched to remove the fourth medium layer at the bottom while retaining the fourth medium layer 801 at the sidewall of the third recess 209. In some embodiments, a dry etching process can be used to etch the fourth medium layer 801 at the bottom of the third recess 209, and specifically, a plasma etching process can be used to perform an anisotropic etching process on the fourth medium layer 801 to remove the fourth medium layer 801 at the bottom of the third recess 209. As shown in Figure 19As shown, the second sacrificial dielectric layer 901 is filled in the second trench isolation structure 208 and the third recess 209, which can be formed by chemical vapor deposition, physical vapor deposition, atomic layer deposition or the like. Since the fourth dielectric layer 801 at the bottom of the third recess 209 is etched, the filled second sacrificial dielectric layer 901 is in direct contact with the third substrate 2013 in the substrate 201. In some embodiments, only part of the fourth dielectric layer 801 at the bottom of the third recess 209 can be removed, so that the second sacrificial dielectric layer 901 is not in direct contact with the third substrate 2013, but in direct contact with the remaining fourth dielectric layer 801. In the embodiments of the present disclosure, whether the second sacrificial dielectric layer is in direct contact with the substrate is not specifically limited. In some embodiments, the material of the second sacrificial dielectric layer 901 is polysilicon or low-k dielectric material.
[0070] In some embodiments, the first substrate 2011 and the third substrate 2013 are connected to each other, and the second substrate 2012 and the fourth substrate 2014 are connected to each other. As shown in FIG. 2B, the first substrate 2011 and the third substrate 2013 are connected to each other through the second dielectric layer 501, and the second substrate 2012 and the fourth substrate 2014 are connected to each other through the fourth dielectric layer 801. Figure 19 As shown, the thickness of the first substrate 2011 and the third substrate 2013 is the same, and those skilled in the art can understand that, in the process of etching the substrate to form the second recess 207 and the fourth recess 211, a wet isotropic etching process is used, so that the upper surface of the first substrate 2011 and the third substrate 2013 or the lower surface of the second substrate 2012 and the fourth substrate is not a flat surface, i.e., an irregular surface with an arc or curved shape. As shown in FIG. 2B, the upper surface of the first substrate 2011 and the third substrate 2013 is not a flat surface, and the lower surface of the second substrate 2012 and the fourth substrate 2014 is not a flat surface. Figures 21-22 As shown, along the second direction Y, the interface between the second dielectric layer 501 and the first substrate 2011 and / or the second substrate 2012 has a curved surface shape, and along the first direction, the interface between the fourth dielectric layer 801 and the third substrate 2013 and / or the fourth substrate 2014 has a curved surface shape.
[0071] In some embodiments, in order to expose the side surface of the second dielectric layer 501 through the fourth recess 211, the etching time for etching the substrate of the second region to form the fourth recess 211 is greater than the etching time for etching the substrate of the first region to form the second recess 207, so that the depth of the fourth recess 211 etched into the substrate is greater than the depth of the second recess 207 etched into the substrate. As shown in FIG. 2B, the fourth recess 211 etched into the substrate is deeper than the second recess 207 etched into the substrate. Figure 20As shown, the thickness of the fourth dielectric layer 801 filled in the fourth recess is greater than the thickness of the second dielectric layer 501 filled in the second recess. In some embodiments, the fourth dielectric layer 801 and the second dielectric layer 501 located in the fourth recess 211 and the second recess 207 have an irregular surface with an arc-shaped curved shape in contact with the surface of the substrate (including the first substrate 2011, the second substrate 2012, the third substrate 2013, and the fourth substrate 2014), and at this time, the thickness of the fourth dielectric layer 801 filled in the fourth recess is greater than the thickness of the second dielectric layer 501 filled in the second recess refers to the average thickness.
[0072] In another aspect of the present disclosure, a semiconductor structure is disclosed, which is formed by the above method for manufacturing a semiconductor structure, such as Figures 21-23 As shown, the semiconductor structure includes a substrate 201, a stacked device layer 400 located above the substrate 201, the substrate 201 including a first substrate 2011 located in a first region I, a second substrate 2012, and a third substrate 2013 and a fourth substrate 2014 located in a second region II, a second dielectric layer 501 located between the first substrate 2011 and the second substrate 2013 in a third direction Z, and a fourth dielectric layer 801 located between the third substrate 2013 and the fourth substrate 2014, wherein the second dielectric layer 501 and the fourth dielectric layer 801 are connected to each other, the first substrate 2011 and the third substrate 2013 are connected to each other, and the second substrate 2012 and the fourth substrate 2014 are connected to each other. The thickness of the fourth dielectric layer 801 is greater than the thickness of the second dielectric layer 501.
[0073] In some embodiments, as shown in Figure 22 As shown, the interface between the second dielectric layer 501 and the first substrate 2011 and / or the second substrate 2012 has a curved shape in the second direction Y, and in some embodiments, as shown in Figure 23 As shown, the interface between the fourth dielectric layer 801 and the third substrate 2013 and / or the fourth substrate 2014 has a curved shape in the first direction.
[0074] In some embodiments, the stacked device layer 400 includes a plurality of transistor structures (not shown) and / or a plurality of capacitor structures (not shown) stacked in the third direction Z, and each layer of transistor structures and corresponding capacitor structures are electrically connected to form a memory cell structure.
[0075] In summary, the preparation method of the semiconductor structure and the semiconductor structure provided by the embodiments of the present disclosure form an epitaxial stack structure on a substrate, improve the lattice consistency of the epitaxial structure, reduce the generation of dislocations or defects, form a first trench isolation structure and a second trench isolation structure by etching the stack structure to expose part of the surface of the substrate, etch the substrate through the first trench isolation structure and the second trench isolation structure to form a first groove and a third groove that penetrate into the interior of the substrate, and perform lateral etching on the interior of the substrate through the first groove and the third groove to form a second groove and a fourth groove in the interior of the substrate, fill an insulating layer in the second groove and the fourth groove, and the insulating layer can protect the bottom substrate from being etched and play the role of an etching stop layer. At the same time, due to the isolation effect of the insulating layer, the generation of leakage current can be effectively avoided. In addition, the upper part of the substrate and the stack structure always maintain an integral structure, which can effectively prevent the stack structure from being peeled off from the substrate, improve the stability of the stack device structure, and improve the electrical performance thereof.
[0076] The various semiconductor structures shown in the specific embodiments can be used in electronic devices with storage functions. The electronic device can be a terminal device, such as a mobile phone, a tablet computer, a smart bracelet, or a personal computer (PC), a server, a workstation, etc. The storage function in the electronic device can be realized by a memory such as a dynamic random access memory (DRAM), a ferroelectric random access memory (FRAM), a phase change memory (PCM), a magnetic random access memory (MRAM), or a resistive random access memory (RRAM).
[0077] The above merely describes the specific embodiments of the present disclosure, but the protection scope of the present disclosure is not limited thereto. Any person skilled in the art can easily think of changes or replacements within the technical scope disclosed by the present disclosure, which should be covered within the protection scope of the present disclosure. Therefore, the protection scope of the present disclosure should be subject to the protection scope of the claims.
Claims
1. A method for fabricating a semiconductor structure, characterized in that, include: Provide substrate; The substrate includes a first region and a second region distributed along a first direction, and a stacked structure is formed on the substrate; A plurality of first grooves are formed, the plurality of first grooves being located in the first region of the substrate and in the substrate, the first grooves extending along a first direction, and the plurality of first grooves being spaced apart along a second direction; the plane defined by the first direction and the second direction is parallel to the surface of the substrate; A first dielectric layer is formed on the sidewall of the first groove; The substrate is etched along the bottom of the first groove to form a second groove inside the substrate. Along the second direction, adjacent first grooves are interconnected through the second groove. The second dielectric layer is filled into the second groove.
2. The method for preparing a semiconductor structure according to claim 1, characterized in that, Further includes: A third groove is formed, the third groove being located in the second region of the substrate and extending along the second direction, and the third groove being located in the substrate; A third dielectric layer is formed on the sidewall of the third groove; The substrate is etched along the bottom of the third groove to form a fourth groove inside the substrate, the fourth groove exposing the side of the second dielectric layer along the first direction; A fourth dielectric layer is filled into the fourth groove; The fourth dielectric layer located inside the substrate is interconnected with the second dielectric layer located inside the substrate.
3. The method for preparing a semiconductor structure according to claim 2, characterized in that, Before forming the plurality of first grooves, the method further includes: patterning the stacked structure to form an initial stacked structure, the initial stacked structure including a plurality of first portions located in the first region and a second portion located in the second region; the plurality of first portions extend along the first direction, and the second portions extend along the second direction; Multiple first portions are arranged at intervals along the second direction, and a first trench isolation structure is formed between adjacent first portions; The substrate at the bottom of the first trench isolation structure is etched to form the first groove; The first groove is connected to the first trench isolation structure.
4. The method for preparing a semiconductor structure according to claim 3, characterized in that, Before forming the third groove, the method further includes: patterning the second portion of the second region to form a second trench isolation structure, the second trench isolation structure extending along the second direction, and etching the substrate at the bottom of the second trench isolation structure to form the third groove; The third groove is connected to the second trench isolation structure.
5. The method for preparing a semiconductor structure according to claim 2, characterized in that, The second groove isolates the substrate located in the first region into a first substrate located below the second groove and a second substrate located above the second groove. The fourth groove isolates the substrate located in the second region into a third substrate located below the fourth groove and a fourth substrate located above the fourth groove. The first substrate and the third substrate are interconnected, and the second substrate and the fourth substrate are interconnected.
6. The method for preparing a semiconductor structure according to claim 4, characterized in that, Further including: at The first trench isolation structure is filled with a first sacrificial dielectric layer, and the second trench isolation structure is filled with a second sacrificial dielectric layer. The first sacrificial dielectric layer and / or the second sacrificial dielectric layer are made of polycrystalline silicon or low-k dielectric material.
7. The method for preparing a semiconductor structure according to claim 6, characterized in that: The first sacrificial dielectric layer and / or the second sacrificial dielectric layer are in contact with the substrate, or a second dielectric layer or a fourth dielectric layer is disposed between the first sacrificial dielectric layer and / or the second sacrificial dielectric layer and the substrate.
8. The method for preparing a semiconductor structure according to any one of claims 1-5, characterized in that: The stacked structure includes a first semiconductor layer and a second semiconductor layer stacked sequentially, wherein the first semiconductor layer is germanium-silicon and the second semiconductor layer is silicon.
9. The method for preparing a semiconductor structure according to claim 2, characterized in that: The first dielectric layer, the second dielectric layer, the third dielectric layer, or the fourth dielectric layer are made of one or more of silicon oxide, silicon nitride, silicon oxynitride, and low-k dielectric materials.
10. The method for preparing a semiconductor structure according to claim 2, characterized in that: Along a third direction, the depth of the fourth groove is greater than or equal to the depth of the second groove, and the third direction intersects the plane defined by the first direction and the second direction.
11. The method for preparing a semiconductor structure according to claim 10, characterized in that: Along the third direction, the thickness of the fourth dielectric layer is greater than the thickness of the second dielectric layer.
12. A semiconductor structure, characterized in that, include: The substrate includes a first region and a second region distributed along a first direction; A stacked device layer is located on the upper surface of the substrate; The substrate includes a first substrate and a second substrate located in the first region, and a third substrate and a fourth substrate located in the second region; the first substrate and the second substrate are spaced apart along a third direction, and the third substrate and the fourth substrate are spaced apart along a third direction; the first direction is parallel to the surface of the substrate, and the third direction intersects the surface of the substrate; A second dielectric layer is located between the first substrate and the second substrate; A fourth dielectric layer is located between the third substrate and the fourth substrate; The second dielectric layer and the fourth dielectric layer are interconnected. Along the third direction, the thickness of the fourth dielectric layer is greater than the thickness of the second dielectric layer.
13. The semiconductor structure according to claim 12, characterized in that, Along the first direction, the interface between the fourth dielectric layer and the third substrate and / or the fourth substrate is curved.
14. The semiconductor structure according to claim 12, characterized in that, Along the second direction, the interface between the second dielectric layer and the first substrate and / or the second substrate is curved, and the plane defined by the first direction and the second direction is parallel to the surface of the substrate.
15. The semiconductor structure according to claim 13, characterized in that, The stacked device layer includes a plurality of transistor structures and / or a plurality of capacitor structures stacked along the third direction.