Power device and method of manufacturing the same

Abstract

The application relates to a power device and a preparation method thereof, and relates to the technical field of semiconductors. In the power device and the preparation method thereof, a high electric field at a gate trench can be led to a first columnar structure arranged at the lower side of a contact area. Since the first columnar structure extends from a source trench to a substrate direction, current is transmitted from the contact area to the first columnar structure, so that a transverse electric field is formed between the contact area and an epitaxial structure, between the first columnar structure and the epitaxial structure. The transverse electric field can disperse the longitudinal electric field at the lower side of the gate trench, so that the longitudinal electric field is uniformly distributed to avoid the electric field being concentrated at the lower side of the gate trench, the electric field intensity of the gate is reduced, and the pressure resistance and reliability of the device are improved. In addition, the first columnar structure can reduce the doping concentration of a drift region, so that the on-resistance of the device is reduced.

Description

Technical Field

[0001] This application relates to the field of semiconductor technology, and in particular to a power device and a method for fabricating the same. Background Technology

[0002] Trenched silicon carbide power devices have seen rapid development in the new energy industry due to their excellent high voltage and high temperature resistance. Among them, the double-trench structure, with its even higher voltage resistance, has been extensively studied.

[0003] Traditional dual-trench silicon carbide power devices employ a process of filling the source trench with polysilicon to protect the gate oxide layer, thereby improving the device's voltage withstand characteristics. However, this method offers limited improvement in voltage withstand performance and requires multiple high-energy ion implantations under these process conditions, which can easily lead to punch-through. Summary of the Invention

[0004] Therefore, it is necessary to provide a power device and its fabrication method to address the aforementioned problems of dual-groove silicon carbide power devices.

[0005] To achieve the above objectives, this application provides a method for fabricating a power device, comprising:

[0006] Provide substrate;

[0007] An epitaxial structure is formed on one side of the substrate. The epitaxial structure includes a drift region, a well region, a source region, and a plurality of first columnar structures. The well region is located on the side of the drift region away from the substrate, and the source region is located on the side of the well region away from the drift region. The first columnar structures are located within the drift region. The drift region and the source region have a first conductivity type, and the first columnar structures and the well region have a second conductivity type. The plurality of first columnar structures are arranged at intervals, and the first columnar structures extend from the epitaxial structure toward the substrate.

[0008] A source trench and a gate trench are formed on the side of the epitaxial structure away from the substrate, and the source trench exposes the first columnar structure.

[0009] The sidewalls and bottom of the source trench are implanted with first ions to form a contact region, the contact region having a second conductivity type; wherein the first conductivity type is opposite to the second conductivity type.

[0010] In one embodiment, the doping concentration of the first ion implantation is 3E13cm. -3 The implantation angles for the first ion implantation include 0°~5°, 40°~50°, and -40°~-50°.

[0011] In one embodiment, after forming the source trench and gate trench on the side of the epitaxial structure away from the substrate, the process includes:

[0012] The structure after forming the source trench and the gate trench is subjected to a first annealing process. The temperature of the first annealing process is 1400°C, the processing gas during the first annealing process is H2, and the time of the first annealing process is 30s.

[0013] In one embodiment, forming an epitaxial structure on one side of the substrate includes:

[0014] An epitaxial initial structure is formed on one side of the substrate, the epitaxial initial structure including an epitaxial layer and a first columnar initial structure located within the epitaxial layer;

[0015] A second ion implantation is performed on the surface layer of the epitaxial initial structure to form an initial well region, the remaining epitaxial layer serves as a drift region, and the remaining first columnar initial structure serves as a first columnar structure.

[0016] A third ion implantation is performed on the surface of the initial well region to form a source region, and the remaining initial well region serves as the well region.

[0017] In one embodiment, after performing a first ion implantation in the source trench to form a contact region on the sidewall of the source trench, the process includes:

[0018] A gate is formed within the gate trench;

[0019] A dielectric layer is formed on the side of the gate away from the substrate, the dielectric layer exposing the source trench and a portion of the epitaxial structure;

[0020] A source is formed that fills the source trench and covers the dielectric layer and the exposed portion of the epitaxial structure.

[0021] In one embodiment, before forming the source trench that fills the source trench and covers the exposed portion of the epitaxial structure and the dielectric layer, the process includes:

[0022] An ohmic contact layer is formed on one side of the epitaxial structure exposed in the dielectric layer.

[0023] In one embodiment, after forming the source trench that fills the source trench and covers the dielectric layer and the exposed portion of the epitaxial structure, the process includes:

[0024] A drain electrode is formed on the side of the substrate away from the epitaxial structure.

[0025] On the other hand, this application also provides a power device, including:

[0026] Substrate;

[0027] An epitaxial structure is located on one side of the substrate. The epitaxial structure includes a drift region, a well region, a source region, and a plurality of first columnar structures. The well region is located on the side of the drift region away from the substrate, and the source region is located on the side of the well region away from the drift region. The first columnar structures are located within the drift region. The drift region and the source region have a first conductivity type, and the first columnar structures and the well region have a second conductivity type. The plurality of first columnar structures are arranged at intervals, and the first columnar structures extend from the epitaxial structure toward the substrate.

[0028] Multiple gate trenches and multiple source trenches, the gate trenches and the source trenches extending from the epitaxial structure toward the substrate side, the source trenches exposing the first columnar structure;

[0029] The contact region is located on the sidewall and bottom of the source trench of the epitaxial structure, and the contact region has a second conductivity type; wherein the first conductivity type is opposite to the second conductivity type.

[0030] In one embodiment, the power device further includes:

[0031] A gate, wherein the gate is located within the gate trench;

[0032] A dielectric layer is located on the side of the epitaxial structure away from the substrate, and the dielectric layer covers the gate.

[0033] The source electrode is located on the side of the epitaxial structure away from the substrate, the source electrode fills the source trench and covers the dielectric layer and the exposed epitaxial structure.

[0034] In one embodiment, the source electrode is made of a metallic material, including aluminum or tungsten.

[0035] Compared with existing technologies, the above technical solution has the following advantages:

[0036] In this power device and its fabrication method, an epitaxial structure is formed on one side of a substrate. The epitaxial structure includes a drift region, a well region, a source region, and multiple first pillar-shaped structures. The drift region and the source region have a first conductivity type, and the first pillar-shaped structures and the well region have a second conductivity type. The multiple first pillar-shaped structures are arranged at intervals, and the first pillar-shaped structures extend from the epitaxial structure toward the substrate. The epitaxial structure is processed to form source trenches and gate trenches located between the source trenches. The source trenches expose the first pillar-shaped structures. Subsequently, a first ion implantation is performed on the sidewalls and bottom of the source trench to form a contact region. The contact region can guide the high electric field at the gate trench to the first columnar structure set below the contact region. Since the first columnar structure extends from the source trench towards the substrate, the current will be transmitted from the contact region to the first columnar structure, so that a transverse electric field is formed between the contact region and the epitaxial structure, and between the first columnar structure and the epitaxial structure. This transverse electric field can disperse the longitudinal electric field below the gate trench, making it uniformly distributed and avoiding the electric field concentration below the gate trench, reducing the electric field strength of the gate, and improving the device's voltage resistance and reliability.

[0037] In addition, setting the first columnar structure can reduce the doping concentration in the drift region, thereby reducing the on-resistance of the device. Attached Figure Description

[0038] To more clearly illustrate the technical solutions in the embodiments of this application or the conventional technology, the drawings used in the description of the embodiments or the conventional technology will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0039] Figure 1 This is a schematic flowchart illustrating a method for fabricating a power device according to an embodiment of this application.

[0040] Figure 2 A partial structural schematic diagram of the power device provided in this application;

[0041] Figure 3 A schematic diagram of the structure of the power device provided in this application after the formation of the well region;

[0042] Figure 4 A schematic diagram of the structure of the power device provided in this application after the source region has been formed;

[0043] Figure 5 A schematic diagram of the structure of the power device provided in this application after forming source trench and gate trench;

[0044] Figure 6 A schematic diagram of the structure of the power device provided in this application after the contact area has been formed;

[0045] Figure 7 A schematic diagram of the structure of the power device provided in this application after the formation of the gate material layer;

[0046] Figure 8 A schematic diagram of the structure of the power device provided in this application after the gate is formed;

[0047] Figure 9 A schematic diagram of the structure of the power device provided in this application after the formation of the dielectric layer and the ohmic contact layer;

[0048] Figure 10 A schematic diagram of the structure of the power device provided in this application after the source electrode is formed;

[0049] Figure 11 This is a schematic diagram of the structure of the power device provided in this application after the drain electrode has been formed.

[0050] Explanation of reference numerals in the attached figures: 01-Substrate; 02-Epiaxial structure; 02a-Initial epitaxial structure; 02b-Epiaxial layer; 021-Drift region; 022-First columnar structure; 022a-Initial first columnar structure; 03-Source trench; 04-Gate trench; 05-Contact region; 061-Initial well region; 06-Well region; 07-Source region; 08-Gate; 081-Gate oxide layer; 082-Gate material layer; 09-Dielectric layer; 10-Source; 11-Ohmic contact layer. Detailed Implementation

[0051] To facilitate understanding of this application, a more complete description will be provided below with reference to the accompanying drawings, which illustrate embodiments of the present application. However, the present application can be implemented in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided so that the disclosure of this application will be thorough and complete.

[0052] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the application.

[0053] It should be understood that when a layer is referred to as "on," "adjacent to," or "connected to" other layers, it can be directly on, adjacent to, or connected to other layers, or there can be intervening layers. Conversely, when an element is referred to as "directly on," "directly adjacent to," or "directly connected to" other layers, there are no intervening layers.

[0054] When used herein, the singular forms of “a,” “an,” and “the” may also include the plural forms unless the context clearly indicates otherwise. It should also be understood that the terms “comprising,” “including,” or “having,” etc., specify the presence of the stated feature, whole, step, operation, component, part, or combination thereof, but do not preclude the possibility of the presence or addition of one or more other features, wholes, steps, operations, components, parts, or combinations thereof.

[0055] Based on the background information, existing dual-trench silicon carbide power devices fill the source trench with polysilicon. The fabrication time for polysilicon is long, resulting in low production efficiency and high manufacturing costs. In dual-trench device structures, high-energy ion implantation is required to reduce the electric field strength of the gate oxide layer, which increases costs, limits voltage withstand capability, and necessitates reducing on-resistance. Furthermore, the sidewall implantation concentration is difficult to control, easily leading to punch-through, and stability requires further investigation.

[0056] Based on this, this application provides a power device and its fabrication method, wherein an epitaxial structure is formed on one side of a substrate. The epitaxial structure includes a drift region and a plurality of first columnar structures. The drift region has a first conductivity type, and the first columnar structures have a second conductivity type. The plurality of first columnar structures are arranged at intervals and extend from the epitaxial structure toward the substrate. The epitaxial structure is processed to form source trenches and gate trenches located between the source trenches, and the source trenches expose the first columnar structures. Subsequently, first ion implantation is performed on the sidewalls and bottom of the source trench to form a contact region. This contact region can draw the high electric field from the gate trench to the first pillar-shaped structure disposed below the contact region. Since the first pillar-shaped structure extends from the source trench towards the substrate, current flows from the contact region to the first pillar-shaped structure, creating a lateral electric field between the contact region and the epitaxial structure, and between the first pillar-shaped structure and the epitaxial structure. This lateral electric field disperses the longitudinal electric field below the gate trench, ensuring a uniform distribution and preventing field concentration below the gate trench. This reduces the electric field strength at the gate, improving the device's voltage withstand capability and reliability. Furthermore, the first pillar-shaped structure reduces the doping concentration in the drift region, thereby lowering the device's on-resistance.

[0057] To make the objectives, features and advantages of this application more apparent and understandable, the application will be further described in detail below with reference to the accompanying drawings and specific embodiments.

[0058] refer to Figure 1 , Figure 1 This application provides a schematic flowchart of a method for fabricating a power device; see reference. Figure 2 , Figure 2 This is a partial structural schematic diagram of the power device provided in this application; see reference. Figure 3 , Figure 3This is a schematic diagram of the structure of the power device after the formation of the well region, as provided in this application; see reference. Figure 4 , Figure 4 This is a schematic diagram of the structure of the power device after the source region is formed, as provided in this application; see reference. Figure 5 , Figure 5 This is a schematic diagram of the structure of the power device provided in this application after forming the source trench and the gate trench; see reference. Figure 6 , Figure 6 This is a schematic diagram of the structure of the power device after the contact region is formed, as provided in this application; the fabrication process includes:

[0059] S10: Provide substrate 01.

[0060] In this step, the substrate 01 can be a silicon carbide substrate, which has a first conductivity type. It should be noted that the first conductivity type can be N-type. In this embodiment, the substrate 01 can be N+ doped.

[0061] S20: An epitaxial structure 02 is formed on one side of the substrate 01. The epitaxial structure 02 includes a drift region 021, a well region 06, a source region 07, and a plurality of first columnar structures 022. The well region 06 is located on the side of the drift region 021 away from the substrate 01, and the source region 07 is located on the side of the well region 06 away from the drift region 021. The first columnar structures 022 are located within the drift region 021. The drift region 021 and the source region 07 have a first conductivity type, and the first columnar structures 022 and the well region 06 have a second conductivity type. The plurality of first columnar structures 022 are arranged at intervals and extend from the epitaxial structure 02 toward the substrate 01.

[0062] In this step, an epitaxial structure 02 is formed on one side of the substrate 01. The epitaxial structure 02 includes a drift region 021 and a plurality of first columnar structures 022. In some embodiments, the conductivity type of the drift region 021 can be a first conductivity type, the conductivity type of the first columnar structures 022 can be a second conductivity type, and the doping of the drift region 021 can be N-doped. The doping of the first columnar structures 022 can be P+ doped, and the material of the epitaxial structure 02 can be SiC.

[0063] Multiple first columnar structures 022 can be arranged at intervals in a direction parallel to the substrate 01, and the first columnar structures 022 extend from the epitaxial structure 02 toward the substrate 01 in a direction perpendicular to the substrate 01.

[0064] It should be noted that the first columnar structure 022 can be formed by multiple epitaxial growths, multiple implantations, or deep trench etching followed by epitaxial filling, and there are no specific limitations. The formation of the first columnar structure 022 in this application does not require high-energy ion implantation.

[0065] Well region 06 is located on the side of drift region 021 away from substrate 01, and source region 07 is located on the side of well region 06 away from drift region 021. Well region 06 has a second conductivity type and can be a P-well. Source region 07 has a first conductivity type and can be N+ doped.

[0066] S30: A source trench 03 and a gate trench 04 are formed on the side of the epitaxial structure 02 away from the substrate 01, and the source trench 03 exposes the first columnar structure 022.

[0067] In this step, a patterned hard mask is formed on the side of the epitaxial structure 02 away from the substrate 01. It should be noted that this patterned hard mask can be an 18K silicon dioxide hard mask. Photolithography is then performed on the epitaxial structure 02 based on the patterned hard mask. First, photoresist is spin-coated. Then, exposure and development are performed based on the patterned hard mask. Next, a dry etching process is used to etch the source trench 03 and the gate trench 04. Finally, the photoresist is removed to obtain the source trench 03 and the gate trench 04.

[0068] It should be noted that the gate trench 04 can be located between the source trenches 03, thereby further facilitating the formation of the source 10 on both sides of the gate 08. The depth of the source trench 03 and the gate trench 04 can be 0.9 μm, and the width can be 0.6 μm.

[0069] S40: Perform first ion implantation on the sidewalls and bottom of the source trench 03 to form a contact region 05, wherein the contact region 05 has a second conductivity type; wherein the first conductivity type is opposite to the second conductivity type.

[0070] In this step, the source trench 03 is implanted with ions to form a contact region 05. The contact region 05 covers the sidewalls and bottom of the source trench 03. The contact region 05 and the first columnar structure 022 form a superjunction structure. This superjunction structure can disperse the longitudinal electric field on the lower side of the gate trench 04, thus reducing the doping concentration of the epitaxial structure 02, which in turn reduces the doping concentration of the drift region 021, thereby reducing the drift on-resistance of the device and improving the device's withstand voltage capability.

[0071] Contact region 05 has a second conductivity type, and the doping of contact region 05 can be P+ doping.

[0072] In this embodiment, since the first columnar structure 022 extends from the source trench 03 towards the substrate 01, current is transmitted from the contact region 05 to the first columnar structure 022, creating a lateral electric field between the contact region 05 and the epitaxial structure 02, and between the first columnar structure 022 and the epitaxial structure 02. This lateral electric field can disperse the longitudinal electric field on the lower side of the gate trench 04, making it uniformly distributed and preventing the electric field from concentrating on the lower side of the gate trench 04, thus reducing the electric field strength of the gate 08 and improving the device's voltage resistance and reliability. Furthermore, providing the first columnar structure 022 can reduce the doping concentration of the drift region 021, thereby reducing the device's on-resistance.

[0073] In another embodiment of this application, the doping concentration of the first ion implantation is 3E13; the implantation angle of the first ion implantation includes 0°~5°, 40°~50°, and -40°~-50°.

[0074] Specifically, the contact region 05 formed by the first ion implantation has a second conductivity type. At this time, since the source trench 03 exposes the first columnar structure 022, low-energy ion implantation can be used when forming the contact region 05 that contacts the first columnar structure 022. That is, the doping concentration used in the first ion implantation is 3E13, which can reduce the number of high-energy ion implantations and reduce the preparation cost.

[0075] It should be noted that the first ion implantation can be P+ implantation or nitrogen ion implantation. It should also be noted that, due to the depth of the source trench 03, in order to achieve uniform implantation at the bottom and sidewalls, the implantation angle range of the first ion implantation can be set to 0°~5°, 40°~50°, and -40°~-50°, including endpoint values. For example, the implantation angle of the first ion implantation can be set to 3°, 43°, and -43°, or the implantation angle of the first ion implantation can be set to 0°, 45°, and -45°, thereby ensuring the uniformity of implantation in the contact area 05.

[0076] In addition, during the first ion implantation, a hard mask needs to be formed on the side of the epitaxial structure 02 away from the substrate 01. The first ion implantation is performed based on this hard mask, and then the patterned hard mask is removed by wet etching. After the first ion implantation, a second annealing process is performed. For example, the temperature of the second annealing process can be 1700°C, and the processing gas during the second annealing process is Ar. Annealing at 1700°C for 30 minutes can activate the ions implanted in the first ion implantation.

[0077] It should also be noted that during the second annealing process, a carbon film can be deposited first. This carbon film can prevent high-temperature annealing from damaging the wafer surface and prevent silicon atoms from sublimating, thereby improving product yield.

[0078] In another embodiment of this application, after forming the source trench 03 and the gate trench 04 on the side of the epitaxial structure 02 away from the substrate 01, the following is included:

[0079] The structure after the source trench 03 and the gate trench 04 is subjected to a first annealing treatment. The temperature of the first annealing treatment is 1400℃, the processing gas during the first annealing treatment is H2, and the time of the first annealing treatment is 30s.

[0080] Specifically, performing a first annealing treatment at 1400℃ in an H2 environment for 30 seconds can eliminate defects and internal stress generated during the etching process, repair etching damage, and improve the yield of power devices.

[0081] In another embodiment of this application, such as Figure 3 , Figure 4 As shown, an epitaxial structure 02 is formed on one side of the substrate 01, including:

[0082] An epitaxial initial structure 02a is formed on one side of the substrate 01. The epitaxial initial structure 02a includes an epitaxial layer 02b and a first columnar initial structure 022a located within the epitaxial layer 02b.

[0083] A second ion implantation is performed on the surface of the epitaxial initial structure 02a to form an initial well region 061 on the side of the epitaxial initial structure 02a away from the substrate 01. The remaining epitaxial layer 02b serves as a drift region 021, and the remaining first columnar initial structure 022a serves as a first columnar structure 022.

[0084] A third ion implantation is performed on the surface of well region 06 to form source region 07, and the remaining initial well region 061 serves as well region 06.

[0085] Specifically, such as Figure 2 As shown, an epitaxial initial structure 02a can be formed first, and the epitaxial initial structure 02a has a first columnar initial structure 022a. It should be noted that the first columnar initial structure 022a can be formed by multiple epitaxy or multiple implantation or deep trench etching plus epitaxial filling, and there is no specific limitation. The formation of the first columnar initial structure 022a in this application does not require high-energy ion implantation.

[0086] like Figure 3As shown, a second ion implantation can then be performed on the surface of the epitaxial initial structure 02a to form an initial well region 061 on the side of the epitaxial structure 02 away from the substrate 01. This initial well region 061 has a second conductivity type and can be a P-well. The dopant element for the second ion implantation can be aluminum, and the implantation concentration range can be 1E12-1E13, including endpoint values. For example, the implantation concentration can be 1E12 or 1E13, etc. The implantation depth range can be 0.5μm-1μm, including endpoint values. For example, the implantation depth can be 0.5μm, 0.6μm, or 0.9μm, etc. It should be noted that the implantation depth of the initial well region 061 can be less than the etching depth of the gate trench 04 and the source trench 03. The remaining epitaxial initial structure 02a serves as the drift region 021, and the remaining first columnar initial structure 022a serves as the first columnar structure 022.

[0087] like Figure 4 As shown, after forming the initial well region 061, a third ion implantation can be performed on the surface of the initial well region 061 to form the source region 07 within the initial well region 061. It should be noted that the source region 07 has a first conductivity type, the dopant element for the third ion implantation can be nitrogen, the implantation concentration can be 2E14, and the implantation depth can range from 0.2 μm to 0.5 μm, including endpoint values. For example, the implantation depth can be 0.2 μm, or 0.4 μm, or 0.5 μm, etc. The remaining initial well region 061 is designated as well region 06.

[0088] In another embodiment of this application, reference is made to Figure 7 , Figure 7 This is a schematic diagram of the structure of the power device provided in this application after the formation of the gate material layer; Reference Figure 8 , Figure 8 This is a schematic diagram of the structure of the power device provided in this application after the gate is formed; see reference. Figure 9 , Figure 9 This is a schematic diagram of the structure of the power device provided in this application after the formation of the dielectric layer and the ohmic contact layer; Reference Figure 10 , Figure 10 This is a schematic diagram of the structure of the power device provided in this application after the formation of the source electrode; after performing a first ion implantation in the source trench 03 to form a contact region 05 on the sidewall of the source trench 03, it includes:

[0089] A gate 08 is formed within the gate trench 04;

[0090] A dielectric layer 09 is formed on the side of the gate 08 away from the substrate 01, and the dielectric layer 09 exposes the source trench 03 and part of the epitaxial structure 02;

[0091] A source trench 03 is formed, which covers the dielectric layer 09 and the exposed portion of the epitaxial structure 02.

[0092] Specifically, after forming the contact region 05, a gate oxide layer 081 is formed inside the gate trench 04. It should be noted that the thickness of the gate oxide layer 081 can be 500 angstroms. Then, a gate material layer 082 is deposited on the side of the epitaxial structure 02 away from the substrate 01. This gate material layer 082 fills the source trench 03 and the gate trench 04 and covers the surface of the epitaxial structure 02.

[0093] Next, photoresist is formed on the side of the gate material layer 082 away from the substrate 01. The gate patterning mask is exposed and developed to form the gate patterned photoresist. The required pattern is then etched by dry etching. Finally, impurities are removed by wet etching chemical solution to form the gate 08.

[0094] After forming the gate 08, a dielectric material layer 091 is formed on the side of the gate 08 away from the epitaxial structure 02. This dielectric layer 09 is then etched using photolithography. This dielectric layer 09 isolates the gate 08 from the subsequently formed source 10. It should be noted that the material of the dielectric layer 09 can be silicon oxide.

[0095] Next, a source 10 is formed, filling the source trench 03 and covering the dielectric layer 09 and the exposed portion of the epitaxial structure 02. The source 10 can be made of a metal, such as aluminum or tungsten. It should be noted that, due to the need to fabricate a superjunction structure, the source trench needs to be deeper than the gate trench. With a larger aspect ratio, the metal material filling the source trench 03 of the source 10 provides a higher filling effect than existing polysilicon materials. Filling with metal allows for deeper trenches, reduces the size of the source trench, and the lower resistance of the metal material effectively lowers the overall resistance. Furthermore, the better filling effect of the metal material allows for a deeper source trench 03, further improving the device's integration density.

[0096] The source electrode 10 can be formed by physical vapor deposition (PVD). For example, Ti layer, TiN and Al layer are deposited sequentially as source electrode 10. It should be noted that the thickness of Ti layer can be 50nm-100nm, the thickness of TiN layer can be 30nm-100nm, and the thickness of Al layer can be 3.5um. There are no specific limitations.

[0097] In another embodiment of this application, such as Figure 9 As shown, before forming the source trench 03 and covering the exposed portion of the epitaxial structure 02 and the source 10 of the dielectric layer 09, the process includes:

[0098] An ohmic contact layer 11 is formed on one side of the portion of the epitaxial structure 02 exposed in the dielectric layer 09.

[0099] Specifically, before forming the source electrode 10, a metal layer can be sputtered on the side of the epitaxial structure 02 exposed in the dielectric layer 09 that is away from the substrate 01. After two annealing processes, an ohmic contact layer 11 is formed. The metal material can be Ni, Pt, nickel-platinum alloy, etc., and is not specifically limited; the above materials are only examples. After annealing, the metal forms a metal silicide on the silicon carbide surface, i.e., the ohmic contact layer 11. The low-resistance ohmic contact can significantly reduce the heat dissipation generated by the semiconductor structure during operation, improve the efficiency and reliability of the semiconductor structure, and also help to reduce the size and weight of the semiconductor structure.

[0100] In another embodiment of this application, reference is made to Figure 11 , Figure 11 A schematic diagram of the structure of the power device provided in this application after the drain is formed; after forming the source 10 that fills the source trench 03 and covers the dielectric layer 09 and the exposed portion of the epitaxial structure 02, it includes:

[0101] A drain electrode 12 is formed on the side of the substrate 01 away from the epitaxial structure 02.

[0102] Specifically, the side of the substrate 01 away from the epitaxial structure 02 can be thinned first, and then nickel can be sputtered to form an ohmic contact. After that, metals such as titanium, nickel, and silver can be used to deposit the drain electrode 12.

[0103] In another embodiment of this application, such as Figures 2-6 As shown, this application also provides a power device, which includes:

[0104] Substrate 01;

[0105] Epitaxial structure 02 is located on one side of substrate 01. Epitaxial structure 02 includes drift region 021, well region 06, source region 07 and multiple first columnar structures 022. Well region 06 is located on the side of drift region 021 away from substrate 01. Source region 07 is located on the side of well region 06 away from drift region 021. First columnar structures 022 are located within drift region 021. Drift region 021 and source region 07 have a first conductivity type. First columnar structures 022 and well region 06 have a second conductivity type. Multiple first columnar structures 022 are arranged at intervals. First columnar structures 022 extend from epitaxial structure 02 toward substrate 01.

[0106] Multiple gate trenches 04 and multiple source trenches 03 extend from the epitaxial structure 02 toward the substrate 01 side, and the source trenches 03 expose the first columnar structure 022.

[0107] Contact region 05 is located on the sidewall and bottom of source trench 03 of epitaxial structure 02, and contact region 05 has a second conductivity type; wherein the first conductivity type is the opposite of the second conductivity type.

[0108] Specifically, substrate 01 can be a silicon substrate 01, which has a first conductivity type. It should be noted that the first conductivity type can be N-type. In this embodiment, the doping of substrate 01 can be N+ doping.

[0109] The epitaxial structure 02 includes a drift region 021, a well region 06, a source region 07, and a plurality of first columnar structures 022. In some embodiments, the conductivity type of the drift region 021 can be a first conductivity type, the conductivity type of the first columnar structures 022 can be a second conductivity type, and the doping of the drift region 021 can be N-doped. The doping of the first columnar structures 022 can be P+ doped, and the material of the epitaxial structure 02 can be SiC.

[0110] Multiple first columnar structures 022 can be arranged at intervals in a direction parallel to the substrate 01, and the first columnar structures 022 extend from the epitaxial structure 02 toward the substrate 01 in a direction perpendicular to the substrate 01.

[0111] Well region 06 is located on the side of drift region 021 away from substrate 01, and source region 07 is located on the side of well region 06 away from drift region 021. Well region 06 has a second conductivity type and can be a P-well. Source region 07 has a first conductivity type and can be N+ doped.

[0112] On the side of the epitaxial structure 02 away from the substrate 01, a plurality of source trenches 03 and a plurality of gate trenches 04 are also provided. The gate trenches 04 are located between the source trenches 03, thereby further facilitating the formation of source electrodes 10 on both sides of the gate 08. The depth of the source trenches 03 and the gate trenches 04 can be 0.9 μm and the width can be 0.6 μm.

[0113] Contact region 05 is located on the sidewall of source trench 03 and has a second conductivity type. The doping of contact region 05 can be P+ doping.

[0114] In this embodiment, since the first columnar structure 022 extends from the source trench 03 towards the substrate 01, current is transmitted from the contact region 05 to the first columnar structure 022, creating a lateral electric field between the contact region 05 and the epitaxial structure 02, and between the first columnar structure 022 and the epitaxial structure 02. This lateral electric field can disperse the longitudinal electric field on the lower side of the gate trench 04, making it uniformly distributed and avoiding the electric field concentration on the lower side of the gate trench 04, thus reducing the electric field strength of the gate 08 and improving the device's voltage resistance and reliability. Furthermore, providing the first columnar structure 022 can reduce the doping concentration of the drift region 021, thereby reducing the device's on-resistance.

[0115] In another embodiment of this application, such as Figures 8-10 The power devices shown also include:

[0116] Gate 08 is located within gate trench 04;

[0117] Dielectric layer 09 is located on the side of epitaxial structure 02 away from substrate 01, and dielectric layer 09 covers gate 08;

[0118] The source 10 is located on the side of the epitaxial structure 02 away from the substrate 01. The source 10 fills the source trench 03 and covers the dielectric layer 09 and the exposed epitaxial structure 02.

[0119] Specifically, the gate 08 can be made of polysilicon, and a gate oxide layer 081 can be disposed between the gate 08 and the epitaxial structure 02. The gate oxide layer 081 can be made of silicon dioxide.

[0120] The dielectric layer 09 can be made of silicon dioxide to isolate the gate 08 and the source 10, preventing them from conducting.

[0121] The source 10 fills the source trench 03 and covers the dielectric layer 09 and the exposed epitaxial structure 02.

[0122] In another embodiment of this application, the source electrode 10 is made of a metallic material, including aluminum or tungsten.

[0123] Specifically, the source 10 can be made of a metal, such as aluminum or tungsten. It's important to note that, due to the need to fabricate a superjunction structure, the source trench needs to be deeper than the gate trench. With a larger aspect ratio, the metal material filling the source trench 03 in this source 10 provides a higher filling effect than existing polysilicon materials. Filling with metal allows for deeper trenches, reduces the size of the source trench, and the lower resistance of the metal material effectively lowers the overall resistance. Furthermore, the better filling effect of the metal material enables a deeper source trench 03, further improving the device's integration density.

[0124] In the description of this specification, references to terms such as "some embodiments," "another embodiment," etc., indicate that a specific feature, structure, material, or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of the invention. In this specification, the illustrative descriptions of the above terms do not necessarily refer to the same embodiments or examples.

[0125] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features of the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0126] The embodiments described above are merely illustrative of several implementation methods of this application, and while the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the patent application. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of this application, and these all fall within the protection scope of this application. Therefore, the protection scope of this patent application should be determined by the appended claims.

Claims

1. A method for fabricating a power device, characterized in that, include: Provide substrate; An epitaxial structure is formed on one side of the substrate. The epitaxial structure includes a drift region, a well region, a source region, and a plurality of first columnar structures. The well region is located on the side of the drift region away from the substrate, and the source region is located on the side of the well region away from the drift region. The first columnar structures are located within the drift region. The drift region and the source region have a first conductivity type, and the first columnar structures and the well region have a second conductivity type. The plurality of first columnar structures are arranged at intervals, and the first columnar structures extend from the epitaxial structure toward the substrate. A source trench and a gate trench are formed on the side of the epitaxial structure away from the substrate, and the source trench exposes the first columnar structure. The sidewalls and bottom of the source trench are implanted with a first ion to form a contact region. The first ion implantation is a low-energy ion implantation. The implantation angle of the first ion implantation includes 0°~5°, 40°~50° and -40°~-50°. The contact region has a second conductivity type. The first conductivity type is opposite to the second conductivity type. A gate is formed within the gate trench; A dielectric layer is formed on the side of the gate away from the substrate, the dielectric layer exposing the source trench and a portion of the epitaxial structure; A source electrode is formed that fills the source trench and covers the dielectric layer and the exposed portion of the epitaxial structure, wherein the source electrode is made of a metallic material.

2. The method for fabricating the power device according to claim 1, characterized in that, The doping concentration of the first ion implantation is 3E13cm. -3 .

3. The method for fabricating a power device according to claim 1, characterized in that, After forming the source trench and gate trench on the side of the epitaxial structure away from the substrate, the process includes: The structure after forming the source trench and the gate trench is subjected to a first annealing process. The temperature of the first annealing process is 1400°C, the processing gas during the first annealing process is H2, and the time of the first annealing process is 30s.

4. The method for fabricating a power device according to claim 1, characterized in that, The formation of an epitaxial structure on one side of the substrate includes: An epitaxial initial structure is formed on one side of the substrate, the epitaxial initial structure including an epitaxial layer and a first columnar initial structure located within the epitaxial layer; A second ion implantation is performed on the surface layer of the epitaxial initial structure to form an initial well region, the remaining epitaxial layer serves as a drift region, and the remaining first columnar initial structure serves as a first columnar structure. A third ion implantation is performed on the surface of the initial well region to form a source region, and the remaining initial well region serves as the well region.

5. The method for fabricating a power device according to claim 1, characterized in that, Before forming the source that fills the source trench and covers the dielectric layer and the exposed portion of the epitaxial structure, the process includes: An ohmic contact layer is formed on one side of the epitaxial structure exposed in the dielectric layer.

6. The method for fabricating a power device according to claim 1, characterized in that, After forming the source trench that fills the source trench and covers the dielectric layer and the exposed portion of the epitaxial structure, the process includes: A drain electrode is formed on the side of the substrate away from the epitaxial structure.

7. A power device, characterized in that, The power device is prepared by the preparation method according to any one of claims 1-6, and comprises: Substrate; An epitaxial structure is located on one side of the substrate. The epitaxial structure includes a drift region, a well region, a source region, and a plurality of first columnar structures. The well region is located on the side of the drift region away from the substrate, and the source region is located on the side of the well region away from the drift region. The first columnar structures are located within the drift region. The drift region and the source region have a first conductivity type, and the first columnar structures and the well region have a second conductivity type. The plurality of first columnar structures are arranged at intervals, and the first columnar structures extend from the epitaxial structure toward the substrate. Multiple gate trenches and multiple source trenches, the gate trenches and the source trenches extending from the epitaxial structure toward the substrate side, the source trenches exposing the first columnar structure; A contact region is located on the sidewall and bottom of the source trench of the epitaxial structure, and the contact region has a second conductivity type; wherein the first conductivity type is opposite to the second conductivity type; A gate, wherein the gate is located within the gate trench; A dielectric layer is located on the side of the epitaxial structure away from the substrate, and the dielectric layer covers the gate. The source electrode is located on the side of the epitaxial structure away from the substrate, the source electrode fills the source trench and covers the dielectric layer and the exposed portion of the epitaxial structure.

8. The power device according to claim 7, characterized in that, The source electrode is made of a metallic material, including aluminum or tungsten.

Images