Semiconductor structure and manufacturing method thereof

Abstract

The invention relates to the technical field of semiconductors, in particular to a semiconductor structure and a manufacturing method thereof. The semiconductor structure includes: a substrate; the fin structure is located on the substrate and comprises two fins and a first connecting part, the two fins extend in a first direction and are spaced in a second direction different from the first direction, and the first connecting part is located between the two fins and connected with the two fins; the isolation regions are positioned on two sides of each fin; the gate structure stretches across the fin structure and is located on the isolation region, the gate structure comprises a gate, and the gate stretches across a first edge part of the first connecting part in the first direction and the two fins; the first electrode region is positioned on one side of the gate structure and is positioned on the two fins and the first connecting part; and the second electrode region is positioned on the other side of the gate structure and is positioned on the two fins.

Description

Technical Field

[0001] This disclosure relates to the field of semiconductor technology, and in particular to a semiconductor structure and a method for manufacturing the same. Background Technology

[0002] With the miniaturization of integrated circuits, traditional planar transistors are no longer able to meet people's application needs due to the decline in gate control capability.

[0003] In related technologies, three-dimensional transistors with a three-gate structure have begun to be used. Summary of the Invention

[0004] According to one aspect of the present disclosure, a semiconductor structure is provided, comprising: a substrate; a fin structure on the substrate, the fin structure including: two fins extending in a first direction and spaced apart in a second direction different from the first direction, and a first connection portion located between and connected to the two fins; isolation regions located on both sides of each fin; a gate structure spanning the fin structure and located on the isolation regions, the gate structure including a gate spanning a first edge portion of the first connection portion in the first direction and the two fins; a first electrode region located on one side of the gate structure and on the two fins and the first connection portion; and a second electrode region located on the other side of the gate structure and on the two fins.

[0005] According to some embodiments of this disclosure, the fin structure further includes a second connecting portion located between and connected to the two fins; the gate also spans a second edge portion of the second connecting portion in the first direction, and the second electrode region is also located on the second connecting portion.

[0006] According to some embodiments of this disclosure, in a direction perpendicular to the first direction, the size of the first connecting portion is larger than the size of each fin.

[0007] According to some embodiments of the present disclosure, the semiconductor structure includes a plurality of said fin structures, the plurality of said fin structures being arranged in the second direction.

[0008] According to another aspect of the present disclosure, a method for manufacturing a semiconductor structure is provided. The method includes: providing a substrate structure, the substrate structure including: a substrate, a mask layer located on the substrate, a sacrificial portion extending along a first direction on the mask layer, and spacer layers on both sides of the sacrificial portion; forming at least one mask structure spanning the sacrificial portion and the spacer layers, the at least one mask structure including a first mask structure; removing a portion of the sacrificial portion not spanned by the at least one mask structure, and removing the at least one mask structure, the remaining portion of the sacrificial portion including a first sub-sacrificial portion corresponding to the first mask structure; using the remaining portion of the sacrificial portion and the spacer layers as masks, sequentially etching the mask layer and the substrate to form a fin structure, the fin structure including two fins corresponding to the spacer layers and a first sub-sacrificial portion corresponding to the first mask structure. A first connecting portion corresponding to a sacrificial portion, wherein the two fins extend in a first direction and are spaced apart in a second direction different from the first direction, the first connecting portion is located between the two fins and connected to the two fins; an isolation region is formed on both sides of each fin; a pseudo-gate structure is formed, the pseudo-gate structure spans the fin structure and is located on the isolation region, the pseudo-gate structure includes a pseudo-gate, the pseudo-gate spans the first edge portion of the first connecting portion in the first direction and the two fins; and a first electrode region and a second electrode region are formed, wherein: the first electrode region is located on one side of the pseudo-gate structure and is located on the two fins and the first connecting portion, and the second electrode region is located on the other side of the pseudo-gate structure and is located on the two fins.

[0009] According to some embodiments of this disclosure, the at least one mask structure further includes a second mask structure, the remaining portion of the sacrificial portion further includes a second sub-sacrificial portion corresponding to the second mask structure, the fin structure further includes a second connecting portion corresponding to the second sub-sacrificial portion, the second connecting portion is located between the two fins and connected to the two fins; the dummy gate also spans a second edge portion of the second connecting portion in the first direction, and the second electrode region is also located on the second connecting portion.

[0010] According to some embodiments of this disclosure, forming a pseudo-gate structure includes: forming a pseudo-gate material covering the fin structure and the isolation region; and patterning the pseudo-gate material to obtain the pseudo-gate.

[0011] According to some embodiments of this disclosure, forming the first electrode region includes: etching the first connection portion and the portions of the two fins adjacent to the first connection portion to form a first recess located on one side of the dummy gate structure; and epitaxially depositing semiconductor material in the first recess to form the first electrode region.

[0012] According to some embodiments of this disclosure, in the fin structure, in a direction perpendicular to the first direction, the size of the first connecting portion is larger than the size of each fin.

[0013] According to some embodiments of this disclosure, the substrate structure includes a plurality of sacrificial portions; sequentially etching the mask layer and the substrate to form a fin structure includes: sequentially etching the mask layer and the substrate to form a plurality of fin structures, the plurality of fin structures being arranged in the second direction. Attached Figure Description

[0014] The accompanying drawings form part of this specification, illustrating exemplary embodiments of the present disclosure, and together with the specification serve to explain the principles of the present disclosure.

[0015] This disclosure will become clearer with reference to the accompanying drawings and the following detailed description, in which:

[0016] Figure 1 This is a top view of the pseudo-gate spanning the fins, where elliptical markers indicate the location of the redundant structure.

[0017] Figure 2 This is a schematic diagram of a semiconductor structure according to some embodiments of the present disclosure.

[0018] Figure 3 This is a schematic diagram of a semiconductor structure according to other embodiments of the present disclosure.

[0019] Figure 4 This is a flowchart of a method for manufacturing a semiconductor structure according to some embodiments of the present disclosure.

[0020] Figures 5-14 This is a schematic diagram of the various stages of a method for manufacturing a semiconductor structure according to embodiments of the present disclosure.

[0021] It should be understood that the same or similar reference numerals indicate the same or similar components. Detailed Implementation

[0022] Various exemplary embodiments of the present disclosure will now be described in detail with reference to the accompanying drawings. The descriptions of the exemplary embodiments are merely illustrative and are in no way intended to limit the present disclosure or its application or use. The present disclosure may be implemented in many different forms and is not limited to the embodiments described herein. These embodiments are provided so that the present disclosure will be thorough and complete, and will fully express the scope of the disclosure to those skilled in the art. It should be noted that, unless specifically stated otherwise, the relative arrangement of components and steps, the composition of materials, numerical expressions, and values ​​set forth in these embodiments should be interpreted as exemplary only and not as limiting.

[0023] The terms "first," "second," and similar words used in this disclosure do not indicate any order, quantity, or importance, but are merely used to distinguish different parts. Words such as "including" or "containing" mean that the element preceding the word encompasses the element listed after the word, and do not exclude the possibility of encompassing other elements as well. Terms such as "above" and "below" are used only to indicate relative positional relationships, and these relative positional relationships may also change accordingly when the absolute position of the described object changes.

[0024] In this disclosure, when a specific component is described as being located between a first component and a second component, an intermediary component may or may not be present between the specific component and the first or second component. When a specific component is described as connecting to other components, the specific component may be directly connected to the other components without having an intermediary component, or it may not be directly connected to the other components but may have an intermediary component.

[0025] All terms used in this disclosure (including technical or scientific terms) have the same meaning as understood by one of ordinary skill in the art to which this disclosure pertains, unless otherwise specifically defined. It should also be understood that terms defined in a general dictionary, such as a dictionary, should be interpreted as having a meaning consistent with their meaning in the context of the relevant art, and not as having an idealized or highly formalized meaning, unless expressly defined herein.

[0026] Techniques, methods, and equipment known to those skilled in the art may not be discussed in detail, but where appropriate, such techniques, methods, and equipment should be considered part of the specification.

[0027] The inventors noted that after the adoption of 3D transistors, the manufacturing process of 3D transistors faced two challenges as transistor size was further miniaturized.

[0028] Firstly, the miniaturization of dimensions results in a limited current supply from a single fin of a three-dimensional transistor.

[0029] In related technologies, during the formation of source / drain regions, the semiconductor materials used for source / drain regions on two or more adjacent fins are epitaxially connected together to increase the current. However, when transistor sizes are small, the process of epitaxially connecting semiconductor materials to form good source / drain regions is already challenging, and epitaxially connecting semiconductor materials on adjacent fins is even more difficult.

[0030] Secondly, due to the structural characteristics of 3D transistors, there are 3D corners at the intersection of the dummy gate and the fin. During the process of patterning the dummy gate material to form the dummy gate, the reduction of the mask size can easily lead to incomplete etching of the dummy gate material, thus forming redundant structures (i.e., residual dummy gate material) at the 3D corners. Figure 1This is a top view of the dummy gate spanning the fins, with elliptical markers indicating the locations of redundant structures. The presence of redundant structures can affect the performance of the semiconductor structure. For example, redundant structures may connect to the source / drain regions in subsequent epitaxy, causing a short circuit between the gate and the source / drain. Furthermore, in subsequent dummy gate removal processes, the connection of redundant structures to the source / drain regions may lead to the risk of removing semiconductor material from those regions.

[0031] In view of this, the present disclosure proposes the following technical solutions, which help to improve the performance of 3D transistors.

[0032] This disclosure presents a semiconductor structure.

[0033] Figure 2 This is a schematic diagram of a semiconductor structure according to some embodiments of the present disclosure.

[0034] Figure 3 This is a schematic diagram of a semiconductor structure according to other embodiments of the present disclosure.

[0035] exist Figure 2 and Figure 3 In the diagram, (a) represents a top view of the semiconductor structure, (b) represents a top view of the semiconductor structure without gate structure 300, first electrode region 203a and second electrode region 203b, and (c) and (d) represent schematic diagrams of cross sections of the semiconductor structure taken along c-c' and d-d' in (a), respectively.

[0036] The following is combined Figure 2 and Figure 3 The semiconductor structures of some embodiments of this disclosure will be described.

[0037] According to some embodiments of the present disclosure, the semiconductor structure includes: a substrate 100, a fin structure 200 located on the substrate 100, an isolation region 210, a gate structure 300, a first electrode region 203a, and a second electrode region 203b.

[0038] like Figure 2 As shown in (b), the fin structure 200 includes two fins 201 and a first connecting portion 202a.

[0039] Two fins 201 extend in a first direction O1 and are spaced apart in a second direction O2, which is different from the first direction O1. The second direction O2 may, for example, be perpendicular to the first direction O1. A first connecting portion 202a is located between and connected to the two fins 201. Here, the fin structure 200 is "H"-shaped. In other words, the first connecting portion 202a is located only between the two fins 201 and does not intersect with the two fins 201.

[0040] In some embodiments, the fin structure 200 may be integrally formed with the substrate 100, that is, both are made of the same material, for example, both are semiconductor materials such as silicon, germanium, or silicon germanide. In other embodiments, the material of the fin structure 200 is different from the material of the substrate 100.

[0041] like Figure 2 As shown in (a) and (d), the gate structure 300 spans the fin structure 200 and is located on the isolation region 210. The gate structure 300 includes a gate 301 that spans a first edge portion of the first connection portion 202a in a first direction O1 and two fins 201. For example, the first edge portion refers to the right edge portion of the first connection portion 202a. It should be understood that the size of the first edge portion of the first connection portion 202a can be determined according to requirements. For example, the first edge portion can be obtained by extending a certain dimension inward from the edge (e.g., the right edge) of the first connection portion 202a.

[0042] The gate 301 can be made of a metallic material, such as tungsten.

[0043] In some embodiments, such as Figure 2 As shown in (a), (c), and (d), the gate structure 300 further includes sidewalls 302 located on both sides of the gate 301. The sidewalls 302 can be a single-layer or multi-layer structure. The material of the sidewalls 302 includes, for example, one or more of silicon nitride, silicon carbonitride, or silicon oxynitride. In some embodiments, the gate structure 300 further includes a high-dielectric-constant dielectric layer (e.g., hafnium oxide) and a work function layer (e.g., titanium nitride) between the sidewalls 302 and the gate 301.

[0044] In some embodiments, such as Figure 2 As shown in (c) and (d) in the figure, the gate structure 300 also includes a gate dielectric layer 220, which is located between the gate structure 300 and the fin structure 200.

[0045] like Figure 2 As shown in (a) and (c), the first electrode region 203a is located on one side of the gate structure 300 and on the two fins 201 and the first connection portion 202a. The second electrode region 203b is located on the other side of the gate structure 300 and on the two fins 201. For example, as... Figure 2 As shown in (a), the second electrode region 203b can be formed by combining semiconductor materials epitaxially grown on the two fins 201 respectively. Figure 2 (d) in the figure shows the merging location of the second electrode region 203b.

[0046] Figure 2The semiconductor structure shown, compared to traditional three-dimensional transistors, has a first electrode region 203a formed directly on the first connection portion 202a and the portion of the two fins 201 adjacent to the first connection portion 202a, since there is a first connection portion 202a between the two adjacent fins 201. This eliminates the need to epitaxially grow semiconductor materials on the two fins 201 separately and combine them together. This not only combines the current on the two fins 201 to increase the current, but also effectively reduces the complexity of the process.

[0047] Furthermore, since the gate 301 spans the first edge portion of the first connection portion 202a in the first direction O1 and the two fins 201, the dummy gate 301' (not shown) before the formation of the gate 301 also spans the first edge portion of the first connection portion 202a in the first direction O1 and the two fins 201. One side of the dummy gate 301' (with...) Figure 2 For example, there is no longer a 3D corner between the left side and the two fins 201, thus avoiding the formation of redundant structures and effectively improving the performance of the 3D transistor.

[0048] In some embodiments, the fin structure 200 further includes a second connecting portion 202b. Similar to the first connecting portion 202a, the second connecting portion 202b is located only between the two fins 201 and does not intersect with the two fins 201.

[0049] like Figure 3 As shown in (b), the second connecting part 202b is located between and connected to the two fins 201. Figure 3 As shown in (a) and (d), the gate 301 also spans the second edge portion of the second connection portion 202b in the first direction O1, and the second electrode region 203b is also located on the second connection portion 202b. Taking the second connection portion 202b located to the right of the first connection portion 202a as an example, the second edge portion can refer to the left edge portion of the second connection portion 202b.

[0050] In this case, the gate 301 simultaneously spans the first edge portion of the first connection portion 202a and the second edge portion of the second connection portion 202b.

[0051] In the above embodiments, the first connection portion 202a and the second connection portion 202b make it easier to form the electrode regions (i.e., the first electrode region 203a and the second electrode region 203b) on both sides of the gate structure 300, further reducing the process complexity. In addition, there are no longer 3D corners between the two sides of the dummy gate 301' (not shown) and the two fins 201, further improving the performance of the 3D transistor.

[0052] In some embodiments, the size of the first connecting portion 202a is larger than the size of each fin 201 in the direction perpendicular to the first direction O1. For example, the fins 201 and the first connecting portion 202a can be formed by a self-aligned double patterning (SADP) process such that the size of the fins 201 in the direction perpendicular to the first direction O1 is smaller than that of the first connecting portion 202a, as will be explained below.

[0053] In some embodiments, the semiconductor structure includes a plurality of fin structures 200, which are arranged in a second direction O2. For example, Figure 2 (b) and Figure 3 In (b), two fin structures 200 are shown. As some implementations, multiple fin structures 200 may span multiple consecutive gate structures 300.

[0054] This disclosure also proposes a method for manufacturing a semiconductor structure.

[0055] Figure 4 This is a flowchart of a method for manufacturing a semiconductor structure according to some embodiments of the present disclosure.

[0056] Figures 5-14 This is a schematic diagram of the various stages of a method for manufacturing a semiconductor structure according to embodiments of the present disclosure.

[0057] The following is combined Figures 4-14 The present disclosure describes the manufacturing method of the semiconductor structure and various embodiments thereof.

[0058] exist Figures 5-7 In the diagram, (a) represents a top view of the structure formed at the corresponding stage, and (b) represents a schematic diagram of the cross section of the structure taken along a-a' in (a).

[0059] First, refer to Figure 4 and Figure 7 In step S10, a substrate structure 10 is provided.

[0060] The substrate structure 10 includes: a substrate 100, a mask layer 400, a sacrificial portion 500, and a spacer layer 510.

[0061] like Figure 7 As shown, the mask layer 400 is located on the substrate 100, the sacrificial portion 500 is located on the mask layer 400 and extends along the first direction O1, and the spacer layer 510 is located on both sides of the sacrificial portion 500.

[0062] In some embodiments, with Figure 5 The initial structure shown provides a substrate structure 10, which is briefly described below.

[0063] First, such as Figure 5As shown, an initial structure 10' is provided. The initial structure 10' includes a substrate 100, a mask layer 400, and a sacrificial portion 500. For example, the sacrificial material on the mask layer 400 can be patterned to form one or more sacrificial portions 500.

[0064] Subsequently, as Figure 6 As shown, a capping layer 510' is formed over the initial structure 10' to transform the initial structure 10' into an intermediate structure 10''. The capping layer 510' covers the upper surface of the sacrificial portion 500, the side surface of the sacrificial portion 500, and the surface of the mask layer 400 not covered by the sacrificial portion 500. As one implementation, the capping layer 510' can be formed using an atomic layer deposition (ALD) process.

[0065] Finally, as Figure 7 As shown, the portion of the cover layer 510' on the upper surface of the sacrificial portion 500 and the portion of the cover layer 510' on the surface of the mask layer 400 not covered by the sacrificial portion 500 are removed, and the portion of the cover layer 510' on the side of the sacrificial portion 500 is retained as a spacer layer 510 to obtain the substrate structure 10. The spacer layer 510 is used for the subsequent formation of the fins 201.

[0066] For example, the horizontal portion of the capping layer 510' is selectively removed by an anisotropic etching process (e.g., dry etching), while the vertical portion of the capping layer 510' is retained, thereby forming a spacer layer 510. Subsequently, the polymer generated during the dry etching process can be removed by wet cleaning.

[0067] As one implementation, the thickness of the cover layer 510' is less than the dimension of the sacrificial portion 500 in the direction perpendicular to the first direction O1. Thus, in the subsequently formed fin structure 200, in the direction perpendicular to the first direction O1, the dimension of the first connecting portion 202a is larger than the dimension of each fin 201, as can be seen in [reference needed]. Figure 10 (a) will be described in detail later.

[0068] The substrate 100 can be a semiconductor substrate 100, such as silicon, germanium, germanide of silicon (e.g., silicon germanide).

[0069] The mask layer 400 can be a single-layer or multi-layer structure. For example, as... Figure 7 As shown, the mask layer 400 has three layers. In some embodiments, the three layers of the mask layer 400 from top to bottom can be a silicon oxide layer (e.g., silicon oxide layer), an amorphous silicon layer, and a silicon oxide layer (e.g., silicon oxide layer).

[0070] The material of the sacrificial part 500 can be, for example, amorphous silicon, and the material of the spacer layer 510 can be, for example, a silicon nitride (e.g., silicon nitride).

[0071] exist Figures 8-11 In the diagram, (a) represents a top view of the structure formed at the corresponding stage, and (b) and (c) represent schematic diagrams of the cross sections of the structure taken along a-a' and b-b' in (a), respectively.

[0072] Subsequently, reference Figure 4 and Figure 8 In step S20, at least one mask structure 600 is formed spanning the sacrificial portion 500 and the spacer layer 510. For example... Figure 8 As shown, at least one mask structure 600 includes a first mask structure 600a.

[0073] In some embodiments, the mask structure 600 can be formed by a photolithography process. For example, as... Figure 8 As shown, the mask structure 600 consists of three layers from bottom to top: a spin-coated carbon layer, an anti-reflective layer, and a photoresist layer.

[0074] Subsequently, reference Figure 4 and Figure 9 In step S30, the portion of the sacrificial portion 500 not crossed by at least one mask structure 600 is removed, and at least one mask structure 600 is removed. Figure 9 As shown, the remaining portion of the sacrificial portion 500 includes a first sub-sacrificial portion 501a corresponding to the first mask structure 600a.

[0075] Subsequently, reference Figure 4 and Figure 10 In step S40, the remaining portion of the sacrificial portion 500 and the spacer layer 510 are used as masks to sequentially etch the mask layer 400 and the substrate 100 to form the fin structure 200.

[0076] As one implementation, the exposed portions of the mask layer 400 and the substrate 100 can be selectively etched using an anisotropic etching process (e.g., dry etching). Subsequently, the polymer generated during the dry etching process and any remaining portions of the mask structure 600 (e.g., photoresist) can be removed by wet cleaning.

[0077] like Figure 10 As shown, the fin structure 200 includes two fins 201 corresponding to the spacer layer 510 and a first connecting portion 202a corresponding to the first sub-sacrificial portion 501a. The two fins 201 extend in a first direction O1 and are spaced apart in a second direction O2 different from the first direction O1. The first connecting portion 202a is located between the two fins 201 and connected to the two fins 201.

[0078] In some embodiments, the substrate 100 may be a single layer. For example... Figure 10As shown, the fin 201 is obtained by etching a portion of the substrate 100, meaning the fin 201 is integrally formed with the substrate 100. It should be noted that... Figure 10 (a) in the image shows the fin 201 as distinct from the substrate 100.

[0079] In other embodiments, the substrate 100 may be multilayered, such as two layers. The fin 201 is obtained by etching at least one of the uppermost layers of the substrate 100, in which case the material of the fin 201 and the substrate 100 may be different.

[0080] Thus, it was formed Figure 2 (b) or Figure 3 The “H”-shaped fin structure 200 shown in (b) has a first connecting portion 202a that can be used to combine the currents of the two fins 201. Furthermore, due to the first connecting portion 202a (and...) Figure 3 The dimensions of the second connecting portion 202b (as mentioned below) in the second direction are all defined by the sacrificial portion 500, resulting in better uniformity and avoiding subsequent adverse effects caused by inconsistent dimensions, such as affecting the performance of the work function layer.

[0081] Subsequently, reference Figure 4 and Figure 11 In step S50, isolation zones 210 are formed on both sides of each fin 201.

[0082] The isolation region 210 is used to separate adjacent three-dimensional transistors that are ultimately formed. The material of the isolation region 210 can be an insulating material, such as an oxide of silicon (e.g., silicon oxide).

[0083] exist Figures 12-14 In the diagram, (a) represents a top view of the structure formed at the corresponding stage, and (b), (c) and (d) represent schematic diagrams of the cross sections of the structure taken along a-a', c-c' and d-d' in (a), respectively.

[0084] Subsequently, reference Figure 4 and Figure 12 In step S60, a pseudo-gate structure 300' is formed.

[0085] like Figure 12 As shown in (a) and (d) in the figure, the dummy gate structure 300' spans the fin structure 200 and is located on the isolation region 210. The dummy gate structure 300' includes a dummy gate 301', which spans the first edge portion of the first connection portion 202a in the first direction O1 and two fins 201. The material of the dummy gate 301' can be polysilicon.

[0086] In some embodiments, forming a pseudo-gate structure 300' includes: forming a pseudo-gate material covering the fin structure 200 and the isolation region 210; and patterning the pseudo-gate material to obtain a pseudo-gate 301'.

[0087] In some embodiments, such as Figure 12 As shown, the pseudo-gate structure 300' also includes a mask structure 303' located above the pseudo-gate 301' for patterning the pseudo-gate material. For example, the mask structure 303' can be a single-layer or multi-layer structure.

[0088] In some embodiments, the dummy gate structure 300' may further include sidewalls 302 located on both sides of the dummy gate 301' and the dummy gate mask structure 303'. The sidewalls 302 may be retained as sidewalls 302 of the subsequently formed gate 301.

[0089] The pseudo-gate 301' spans the first edge portion of the first connecting portion 202a, which eliminates the 3D corner between one side of the pseudo-gate 301' and the two fins 201.

[0090] In some embodiments, such as Figure 12 As shown in (b), (c), and (d), a pseudo-gate dielectric layer 220' covering the fin structure 200 can be formed before the pseudo-gate structure 300' is formed. After the pseudo-gate structure 300' is formed, the exposed portion of the pseudo-gate dielectric layer 220' can be removed.

[0091] Finally, refer to Figure 4 and Figure 14 In step S70, a first electrode region 203a and a second electrode region 203b are formed.

[0092] like Figure 14 As shown, the first electrode region 203a is located on one side of the dummy gate structure 300' and on the two fins 201 and the first connecting portion 202a. The second electrode region 203b is located on the other side of the dummy gate structure 300' and on the two fins 201.

[0093] In some embodiments, it can be via Figure 13 To form Figure 14 The first electrode region 203a is shown.

[0094] like Figure 13 As shown, the first connecting portion 202a and the portions of the two fins 201 adjacent to the first connecting portion 202a are etched to form a first recess 204a located on one side of the pseudo gate structure 300'.

[0095] Subsequently, as Figure 14 As shown, semiconductor material is epitaxially grown in the first recess 204a to form the first electrode region 203a.

[0096] By forming the first electrode region 203a in the manner described in the above embodiments, the process challenges brought about by merging the epitaxial semiconductor materials on the two fins 201 can be avoided.

[0097] Thus, the semiconductor structure is formed through steps S10-S70. Since there is a first connection portion 202a between two adjacent fins 201, the first electrode region 203a can be formed directly on the first connection portion 202a and the portions of the two fins 201 adjacent to the first connection portion 202a, without needing to epitaxially grow semiconductor material on the two fins 201 separately and then combine them. This allows the current on the two fins 201 to be combined to increase the current, and also effectively reduces the process complexity. Furthermore, the dummy gate 301' spans the first edge portion of the first connection portion 202a in the first direction O1 and the two fins 201. One side of the dummy gate 301' (with...) Figure 12 For example, there is no longer a 3D corner between the left side and the two fins 201, thus avoiding the formation of redundant structures and effectively improving the performance of the 3D transistor.

[0098] In subsequent processes, the gate structure 300 can be used to replace the pseudo-gate structure 300'.

[0099] In some embodiments, such as Figure 8 As shown, at least one mask structure 600 further includes a second mask structure 600b; correspondingly, as Figure 9 As shown, the remaining portion of the sacrificial portion 500 also includes a second sub-sacrificial portion 501b corresponding to the second mask structure 600b; correspondingly, as Figure 10 As shown, the fin structure 200 also includes a second connecting portion 202b corresponding to the second sub-sacrificial portion 501b. The second connecting portion 202b is located between and connected to the two fins 201; correspondingly, as... Figure 12 As shown, the dummy gate 301' also spans the second edge portion of the second connection portion 202b in the first direction O1, and the second electrode region 203b is also located on the second connection portion 202b.

[0100] like Figure 12 As shown in (d), the pseudo gate 301' simultaneously spans the first edge portion of the first connecting portion 202a and the second edge portion of the second connecting portion 202b.

[0101] The semiconductor structure formed in the above embodiments is similar to Figure 3 The semiconductor structure shown can further reduce the process complexity of the current of the merging fin 201 and avoid the formation of redundant structures.

[0102] In some embodiments, where the fin structure 200 further includes a second connecting portion 202b, a method similar to that used for the first electrode region 203a can be employed, first via... Figure 13 Forming a second recess 204b, and filling it with semiconductor material to form Figure 14 The second electrode region 203b is shown. In this case, the second recess 204b is obtained by etching the second connecting portion 202b and the portions of the two fins 201 that are adjacent to the second connecting portion 202b. The second electrode region 203b is located on the two fins 201 and the second connecting portion 202b.

[0103] In other embodiments, where the fin structure 200 does not include the second connecting portion 202b, semiconductor materials can be epitaxially grown on the two fins 201 on the other side of the dummy gate structure 300' and then merged to form a second electrode region 203b. In this case, the second recess 204b is obtained by etching the portions of the two fins 201 located on the other side of the dummy gate structure 300', and the second electrode region 203b is located on the two fins 201, as can be seen from [reference needed]. Figure 2 (a) in the middle.

[0104] In some embodiments, the substrate structure 10 includes a plurality of sacrificial portions 500, for example Figure 5 Three are shown. Accordingly, the mask layer 400 and the substrate 100 are etched to form multiple fin structures 200, for example... Figure 10 Three fin structures 200 are shown. Multiple fin structures 200 are arranged in the second direction O2. For example, multiple fin structures 200 can share a single pseudo-gate structure 300'.

[0105] The embodiments of this disclosure have now been described in detail. To avoid obscuring the concept of this disclosure, some details known in the art have not been described. Those skilled in the art can fully understand how to implement the technical solutions disclosed herein based on the above description.

[0106] While specific embodiments of this disclosure have been described in detail by way of examples, those skilled in the art should understand that the examples are for illustrative purposes only and not intended to limit the scope of this disclosure. Those skilled in the art should understand that modifications can be made to the above embodiments or equivalent substitutions can be made to some technical features without departing from the scope and spirit of this disclosure. The scope of this disclosure is defined by the appended claims.

Claims

1. A semiconductor structure, comprising: Substrate; A fin structure located on a substrate, the fin structure comprising: Two fins extend in a first direction and are spaced apart in a second direction different from the first direction, and The first connecting part is located between the two fins and connected to the two fins; The isolation zone is located on both sides of each fin; A gate structure, spanning the fin structure and located on the isolation region, the gate structure including a gate spanning the first edge portion of the first connection in the first direction and the two fins; The first electrode region is located on one side of the gate structure and on the two fins and the first connecting portion; and The second electrode region is located on the other side of the gate structure and on the two fins.

2. The semiconductor structure according to claim 1, wherein, The fin structure further includes a second connecting portion, which is located between the two fins and connected to the two fins; The gate also spans the second edge portion of the second connection portion in the first direction, and the second electrode region is also located on the second connection portion.

3. The semiconductor structure according to claim 1 or 2, wherein, In a direction perpendicular to the first direction, the size of the first connecting portion is larger than the size of each fin.

4. The semiconductor structure according to claim 1 or 2, comprising a plurality of said fin structures, wherein the plurality of said fin structures are arranged in the second direction.

5. A method for manufacturing a semiconductor structure, comprising: A substrate structure is provided, the substrate structure comprising: Substrate, The mask layer located on the substrate, The sacrificial portion extending along the first direction on the mask layer, and Spacer layers on both sides of the sacrificial portion; At least one mask structure is formed across the sacrificial portion and the spacer layer, the at least one mask structure including a first mask structure; Remove the portion of the sacrificial portion that is not crossed by the at least one mask structure, and remove the at least one mask structure. The remaining portion of the sacrificial portion includes a first sub-sacrificial portion corresponding to the first mask structure. Using the remaining portion of the sacrificial portion and the spacer layer as a mask, the mask layer and the substrate are etched sequentially to form a fin structure. The fin structure includes two fins corresponding to the spacer layer and a first connecting portion corresponding to the first sub-sacrificial portion. The two fins extend in the first direction and are spaced apart in a second direction different from the first direction. The first connecting portion is located between the two fins and connected to the two fins. This creates isolation zones on both sides of each fin; A pseudo-gate structure is formed, the pseudo-gate structure spanning the fin structure and located on the isolation region, the pseudo-gate structure including a pseudo-gate spanning the first edge portion of the first connecting portion in the first direction and the two fins; and Forming a first electrode region and a second electrode region, wherein: The first electrode region is located on one side of the pseudo-gate structure, and is situated on the two fins and the first connecting portion. The second electrode region is located on the other side of the pseudo-gate structure and on the two fins.

6. The method according to claim 5, wherein: The at least one mask structure further includes a second mask structure, the remaining portion of the sacrificial portion further includes a second sub-sacrificial portion corresponding to the second mask structure, the fin structure further includes a second connecting portion corresponding to the second sub-sacrificial portion, the second connecting portion being located between the two fins and connected to the two fins; The dummy gate also spans the second edge portion of the second connection portion in the first direction, and the second electrode region is also located on the second connection portion.

7. The method according to claim 5 or 6, wherein, The formation of a pseudo-gate structure includes: Forming a pseudo-gate material covering the fin structure and the isolation region; and The pseudo-gate material is patterned to obtain the pseudo-gate.

8. The method according to claim 5 or 6, wherein, The formation of the first electrode region includes: The first connecting portion and the portions of each of the two fins adjacent to the first connecting portion are etched to form a first recess located on one side of the pseudo-gate structure; and Semiconductor material is epitaxially grown in the first recess to form the first electrode region.

9. The method according to claim 5 or 6, wherein, In the fin structure, in a direction perpendicular to the first direction, the size of the first connecting portion is larger than the size of each fin.

10. The method according to claim 5 or 6, wherein, The substrate structure includes a plurality of the sacrificial portions; Sequentially etching the mask layer and the substrate to form the fin structure includes: The mask layer and the substrate are etched sequentially to form a plurality of fin structures, which are arranged in the second direction.

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