Chip batteries and their fabrication methods

Abstract

This application provides a chip battery and its fabrication method, belonging to the field of semiconductor technology. It includes a substrate and at least one control circuit. Each control circuit includes a series-connected floating-gate transistor and an energy storage unit. The energy storage unit includes one or at least two parallel-connected capacitor structures. At least a portion of the floating-gate transistor is located on the substrate, and the capacitor structures are located within the substrate. Before use, the chip battery undergoes a leakage isolation operation. This leakage isolation operation includes applying a first voltage to the control gate of each floating-gate transistor, grounding one end of the control circuit, and applying a second voltage to the other end, where the first voltage is greater than the second voltage. The chip battery in this application does not have the problem of explosion or combustion, has a fast charging speed, does not have the problem of low-temperature degradation, and can achieve precise control of charging and discharging. The leakage isolation operation performed before use achieves the effect of rapid self-detection and self-isolation of leakage areas.

Description

Technical Field

[0001] This application relates to the field of semiconductor technology, specifically to a chip battery and its fabrication method. Background Technology

[0002] Currently, lithium-ion batteries are among the most commonly used rechargeable batteries. Although lithium-ion batteries are inexpensive and have high energy density, they also have a series of drawbacks. For example, lithium-ion batteries are prone to explosion and combustion, posing safety issues; they charge slowly, and the charging speed affects their lifespan; they degrade faster at low temperatures, exhibiting poor low-temperature performance; and their voltage decreases as the battery capacity diminishes.

[0003] Therefore, there is an urgent need for a rechargeable battery to address the shortcomings of existing lithium-ion batteries. Summary of the Invention

[0004] In view of this, the embodiments of this application aim to provide a chip battery and a method for manufacturing the same, so as to overcome the shortcomings of existing lithium-ion batteries.

[0005] This application provides a chip battery, including a substrate and at least one control circuit. Each control circuit includes a series-connected floating-gate transistor and an energy storage unit. The energy storage unit includes one or at least two parallel-connected capacitor structures. At least a portion of the floating-gate transistor is located on the substrate, and the capacitor structures are located within the substrate.

[0006] Before use, the chip battery performs a leakage isolation operation, which includes applying a first voltage to the control gate of each floating gate transistor, grounding one end of the control line, and applying a second voltage to the other end, wherein the first voltage is greater than the second voltage.

[0007] In some embodiments, the control circuit has at least two lines, and all the control circuits are connected in parallel.

[0008] In some embodiments, the control line has at least two shared source regions of at least a portion of the floating gate transistors of the control line.

[0009] In some embodiments, the first voltage is greater than the turn-on voltage of the floating gate transistor.

[0010] In some embodiments, the substrate has at least one deep trench, and the capacitor structure is filled in the corresponding deep trench. The capacitor structure includes an electrode layer and a dielectric layer stacked along the inner wall of the deep trench. The electrode layer has at least two layers, and the dielectric layer has at least one layer, with the dielectric layer located between two adjacent electrode layers.

[0011] In some embodiments, the sidewalls of the deep trench are serrated.

[0012] In some embodiments, the deep trench includes at least one sub-trench, the sub-trenches being arranged sequentially along the thickness direction of the substrate and interconnected with each other, and each sub-trench being sigma-shaped.

[0013] One embodiment of this application also provides a method for fabricating a chip battery, comprising:

[0014] Provide substrate;

[0015] At least one control line is formed, each control line comprising a series-connected floating-gate transistor and an energy storage unit, the energy storage unit comprising one or at least two parallel-connected capacitor structures, at least a portion of the floating-gate transistor being located on the substrate, and the capacitor structures being located within the substrate; and,

[0016] To perform leakage isolation, a first voltage is applied to the control gate of each floating gate transistor, one end of the control line is grounded, and a second voltage is applied to the other end, wherein the first voltage is greater than the second voltage.

[0017] In some embodiments, the step of forming the capacitor structure within the substrate includes:

[0018] Etch a portion of the substrate to form at least one deep trench within the substrate;

[0019] Stacked electrode layers and dielectric layers are formed on the inner wall of the deep trench, wherein the electrode layers have at least two layers and the dielectric layers have at least one layer, and the dielectric layers are located between two adjacent electrode layers.

[0020] In some embodiments, the sidewalls of the deep trench are serrated, and the step of forming the deep trench in the substrate includes:

[0021] The substrate is etched using a dry etching process to form sub-trenches within the substrate;

[0022] The substrate is etched laterally along the sub-trench using a wet etching process to make the sub-trench sigma-shaped; and...

[0023] The dry etching process and the wet etching process are alternately performed at least once at the same location on the substrate to form the deep trench.

[0024] In some embodiments, the step of forming the control circuit includes:

[0025] At least one of the capacitor structures is formed within the substrate;

[0026] At least one of the floating gate transistors is formed on the substrate;

[0027] A dielectric layer is formed on the substrate and the floating gate transistor, and a plug structure is formed within the dielectric layer; and,

[0028] A metal interconnect layer is formed on the medium, and the metal interconnect layer connects one or more of the capacitor structures in parallel through the plug structure and then connects them in series with the corresponding floating gate transistor to form the control circuit.

[0029] This application provides a chip battery, including a substrate and at least one control line. Each control line includes a floating-gate transistor and an energy storage unit connected in series. The energy storage unit includes one or at least two capacitor structures connected in parallel. At least a portion of the floating-gate transistor is located on the substrate, and the capacitor structures are located within the substrate. Before use, the chip battery performs a leakage isolation operation, which includes applying a first voltage to the control gate of each floating-gate transistor, grounding one end of the control line, and applying a second voltage to the other end, wherein the first voltage is greater than the second voltage. The unexpected effects of this application are: This application utilizes chip technology to form the capacitor structure within the substrate, storing and discharging electricity through the charging and discharging of the capacitor structure. The chip battery has no risk of explosion or combustion, charges quickly, and does not suffer from low-temperature degradation. Each control circuit is controlled by an individual floating-gate transistor, enabling precise control of charging and discharging, thus maintaining the supply voltage and avoiding voltage drop after discharge. Furthermore, the overall capacity of the chip battery can be increased by increasing the capacity of a single capacitor structure or the number of capacitor structures. Since the capacitor structure is integrated into the substrate, the space within the substrate can be fully utilized, reducing the size of the chip battery. Individual chip batteries are very thin (can be as thin as <50μm), and can be stacked with computing chips and memory chips to form an independent microcomputer system. It is also resistant to extreme environments and can be applied in fields such as exploration and medicine. Furthermore, the chip battery performs a leakage isolation operation before use. Because a high voltage is applied to the control gate of the floating gate transistor, one end of the control circuit is grounded and the other end is applied to a low voltage. For capacitor structures with leakage or short-circuit problems between the plates, electrons will flow between the source and drain terminals of the series-connected floating gate transistors and be injected into the floating gate under the action of a strong electric field, so that a certain amount of negative charge exists in the floating gate. When the chip battery is in use, the control gate of the floating gate transistor is applied to a lower operating voltage. If there is negative charge in the floating gate of the floating gate transistor, it will cancel the electric field of the control gate, and the floating gate transistor cannot be turned on. Therefore, the leakage capacitor structure is automatically isolated, and the control circuit cannot be used, achieving the effect of rapid self-detection and self-isolation of the leakage block. Attached Figure Description

[0030] Figure 1A flowchart illustrating a method for fabricating a chip battery according to an embodiment of this application.

[0031] Figure 2 This is a schematic diagram of a substrate etched using a dry etching process, provided as an embodiment of this application.

[0032] Figure 3 This is a schematic diagram of a substrate laterally etched using a wet etching process, as provided in an embodiment of this application.

[0033] Figure 4 This is a schematic diagram of a substrate structure etched again using a dry etching process, as provided in an embodiment of this application.

[0034] Figure 5 This is a schematic diagram of a substrate structure obtained by using a wet etching process to laterally etch the substrate again, as provided in an embodiment of this application.

[0035] Figure 6 This is a schematic diagram of a structure in which a second isolation layer is formed in a second sub-trench, according to an embodiment of this application.

[0036] Figure 7 This is a schematic diagram of a capacitor structure formed in a deep trench, according to an embodiment of this application.

[0037] Figure 8 This is a schematic diagram of a floating gate transistor formed on a substrate according to an embodiment of this application.

[0038] Figure 9 This is a schematic diagram of the structure of a chip battery provided in one embodiment of this application.

[0039] Figure 10 This is a top view of a chip battery provided in an embodiment of this application.

[0040] Figure 11 This is an equivalent schematic diagram of a chip battery provided in one embodiment of this application.

[0041] The attached figures are labeled as follows:

[0042] 100 - Substrate; 200 - Mask layer; 300 - Deep trench; 301 - First sub-trench; 302 - Second sub-trench; 401 - First isolation layer; 402 - Second isolation layer; 500 - Capacitor structure; 501 - Dielectric layer; 502 - Electrode layer; 600 - Floating gate transistor; 601 - Drain region; 602 - Source region; 603 - Gate structure; G - Control gate; 700 - Dielectric layer; 701 - Plug structure; P1 - First electrode; P2 - Second electrode; C1 - First capacitor; C2 - Second capacitor; Cn - nth capacitor; M1 - First transistor; M2 - Second transistor; Mn - nth transistor. Detailed Implementation

[0043] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0044] Figure 9 This is a schematic diagram of the structure of a chip battery provided in one embodiment of this application. Figure 10 This is a top view of a chip battery provided in one embodiment of this application. Figure 11 This is an equivalent schematic diagram of a chip battery provided in one embodiment of this application. Figure 9 , Figure 10 and Figure 11 As shown, the chip battery includes a substrate 100 and at least one control line. Each control line includes a series-connected floating gate transistor 600 and an energy storage unit. The energy storage unit includes one or at least two parallel-connected capacitor structures 500. At least a portion of the floating gate transistor 600 is located on the substrate 100, and the capacitor structure 500 is located within the substrate 100. Figure 9 , Figure 10 and Figure 11 The diagram schematically illustrates two control lines, each containing an energy storage unit with a capacitor structure 500. However, it should be understood that the number of control lines and the number of capacitor structures 500 in each energy storage unit should not be limited by the diagram. In practice, a chip battery has at least one control line. When a chip battery includes multiple control lines, these lines can be connected in parallel for easier control and wiring. Each control line can have one floating-gate transistor 600 and at least one capacitor structure 500. When a control line includes multiple capacitor structures 500, these structures should be connected in parallel before being connected in series with the corresponding floating-gate transistor 600.

[0045] As an optional embodiment, the control gates G of all floating gate transistors 600 can be connected together, allowing all floating gate transistors 600 to be turned on or off simultaneously. Of course, the control gates G of each floating gate transistor 600 can be independent of each other, enabling each floating gate transistor 600 to be controlled individually.

[0046] For ease of description, Figure 11 For example, suppose the chip battery has n control lines, each control line has a floating gate transistor 600 and a capacitor structure 500. The floating gate transistors 600 on the n control lines are respectively the first transistor M1, the second transistor M2...the nth transistor Mn, and the capacitor structures 500 on the n control lines are respectively the first capacitor C1, the second capacitor C2...the nth capacitor Cn. From Figure 11 As can be seen, the first transistor M1 and the first capacitor C1 are connected in series, the second transistor M2 and the second capacitor C2 are connected in series, and the nth transistor Mn and the nth capacitor Cn are connected in series; n control lines are connected in parallel, that is, one end of the n control lines is connected to each other as the first electrode P1 of the chip battery, and the other end of the n control lines is connected to each other as the second electrode P2 of the chip battery.

[0047] Please continue reading. Figure 9 Each floating-gate transistor 600 includes a source region 602, a drain region 601, and a gate structure 603. The source region 602 and drain region 601 are located within the substrate 100, and the gate structure 603 is located on the substrate 100 between the source region 602 and drain region 601. The gate structure 603 specifically includes a gate oxide layer, a floating gate, a gate dielectric layer, a control gate G, and gate sidewalls. The gate oxide layer, floating gate, gate dielectric layer, and control gate G are stacked sequentially from bottom to top on the substrate 100, and the gate sidewalls cover the sidewalls of the gate oxide layer, floating gate, gate dielectric layer, and control gate G. Therefore, a portion of the floating-gate transistor 600 (gate structure 603) is located on the substrate 100, while another portion (source region 602 and drain region 601) is located within the substrate 100. Furthermore, when the floating gate transistor 600 is connected in series with a capacitor structure 500, the drain region 601 of the floating gate transistor 600 can be connected to one end of the capacitor structure 500, and the other end of the capacitor structure 500 can serve as one end of the control circuit, while the source region 602 of the floating gate transistor 600 serves as the other end of the control circuit.

[0048] Furthermore, when there are at least two control lines, all control lines can be connected in parallel for easier control. That is, when there are at least two control lines, the source regions 602 of the floating gate transistors 600 of all control lines can be connected together. Therefore, at least some of the floating gate transistors 600 of the control lines can share the source region 602, thereby saving area and simplifying wiring. Of course, whether the floating gate transistors 600 can share the source region 602 depends on the position of each floating gate transistor 600 on the substrate 100. Multiple floating gate transistors 600 can also be designed in adjacent positions to facilitate sharing the source region 602.

[0049] In some embodiments, the source regions 602 of the floating gate transistors 600 of all control lines are independent of each other, so that there is no need to consider the relative position of the floating gate transistors 600 and the capacitor structure 500, or the floating gate transistors 600 can be simply designed near the corresponding capacitor structure 500, thereby facilitating wiring.

[0050] Please continue reading. Figure 9The substrate 100 has at least one deep trench 300, and the deep trench 300 corresponds one-to-one with the capacitor structure 500. Each capacitor structure 500 is filled in the corresponding deep trench 300. The capacitor structure 500 includes an electrode layer 502 and a dielectric layer 501 stacked along the inner wall of the deep trench 300. The electrode layer 502 has at least two layers, and the dielectric layer 501 has at least one layer. The dielectric layer 501 is located between two adjacent electrode layers 502. That is to say, the electrode layer 502 and the dielectric layer 501 are stacked alternately in the deep trench 300, and layer by layer cover the inner wall of the deep trench 300 until the deep trench 300 is filled. Figure 9 and Figure 10 The diagram schematically shows four electrode layers 502 and three dielectric layers 501, but the number of electrode layers 502 and dielectric layers 501 should not be limited to this. The number of electrode layers 502 and dielectric layers 501 can be adaptively designed according to the width of the deep trench 300, the thickness of the electrode layers 502 and dielectric layers 501, and the capacitance value required by the capacitor structure 500, which will not be elaborated here.

[0051] Furthermore, two adjacent electrode layers 502 and the dielectric layer 501 disposed between them together constitute a sub-capacitor. Two adjacent sub-capacitors share a single electrode layer 502. By connecting all the sub-capacitors in a deep trench 300 in parallel, a capacitor structure 500 can be formed, and the capacitance value of the capacitor structure 500 is equal to the sum of the capacitance values ​​of all the parallel sub-capacitors.

[0052] Please continue reading. Figure 9 The sidewalls of the deep trench 300 are serrated. Since the electrode layer 502 and the dielectric layer 501 conformally cover the inner wall of the deep trench 300, the sidewalls of the capacitor structure 500 should also be serrated. This structure can increase the facing area between two adjacent electrode layers 502 of the capacitor structure 500, thereby significantly increasing the capacitance value of the capacitor structure 500. In some embodiments, the sidewalls of the deep trench 300 are not limited to serrated shapes; they can also be wavy, arc-shaped, or straight, etc., which will not be described in detail here.

[0053] Furthermore, the deep trench 300 may include at least one sub-trench, which may be arranged sequentially and interconnected along the thickness direction of the substrate 100. Each sub-trench may be sigma-shaped, thus the sidewalls of the deep trench 300 may be serrated. For example, Figure 9In the deep trench 300, there are a first sub-trench 301 and a second sub-trench 302. The first sub-trench 301 extends from the surface of the substrate 100 into the substrate 100. The second sub-trench 302 continues to extend downward from below the first sub-trench 301. Therefore, the second sub-trench 302 is located below the first sub-trench 301 and is interconnected with the first sub-trench 301. Both the first sub-trench 301 and the second sub-trench 302 are sigma-shaped, which makes the sidewalls of the deep trench 300 serrated.

[0054] In some embodiments, an isolation layer is provided between the capacitor structure 500 and the substrate 100 to prevent short circuits between adjacent capacitor structures 500. When the deep trench 300 includes at least two sub-trenches, the isolation layer can be composed of a multilayer film, for example, Figure 9 In the middle, the isolation layer includes a first isolation layer 401 and a second isolation layer 402. The first isolation layer 401 covers the sidewall of the first sub-trench 301, and the second isolation layer 402 at least covers the inner wall of the second sub-trench 302.

[0055] Please continue reading. Figure 9 and Figure 10 The substrate 100 also has a dielectric layer 700, which covers the substrate 100, the capacitor structure 500, and the floating gate transistor 600. The dielectric layer 700 has several plug structures 701, each plug structure 701 being electrically connected to the respective electrode layer 502, the source region 602, the drain region 601, and the control gate G of the floating gate transistor 600. The dielectric layer 700 also has a metal interconnect layer (…). Figure 9 and Figure 10 (Not shown in the diagram) The metal interconnect layer can be electrically connected to the plug structure 701 and realize the interconnection between the capacitor structure 500 and the floating gate transistor 600. Specifically, the metal interconnect layer needs to connect the sub-capacitors in each capacitor structure 500 in parallel. If there are multiple capacitor structures 500 in each control line, the metal interconnect layer can also connect the multiple capacitor structures 500 in each control line in parallel (to form an energy storage unit), and then connect the energy storage unit in each control line in series with the corresponding floating gate transistor 600. If all control lines need to be connected in parallel, the metal interconnect layer can also connect all control lines in parallel.

[0056] Furthermore, the chip battery has a first electrode P1 and a second electrode P2. The first electrode P1 can be connected to one end of all the control lines, and the second electrode P2 can be connected to the other end of all the control lines. The load is connected to the first electrode P1 and the second electrode P2 respectively. Then, an operating voltage (e.g., 1.8V) is applied to the control gate G of the floating-gate transistor 600 of at least one control line in the chip battery, turning on the floating-gate transistor 600 of that control line. The capacitor structure 500 on that control line then supplies power to the load. When the chip battery needs charging, the first electrode P1 and the second electrode P2 are connected to the two ends of a power supply. An operating voltage (e.g., 1.8V) is applied to the control gate G of the floating-gate transistor 600 of each control line in the chip battery, turning on all the floating-gate transistors 600, and the power supply then charges all the capacitor structures 500. As can be seen, this application utilizes chip technology to form a capacitor structure 500 within the substrate 100. Energy storage and discharge are achieved through the charging and discharging of the capacitor structure 500. The chip battery does not have the problem of explosion or combustion, has a fast charging speed, and does not suffer from low-temperature degradation. Each control circuit is controlled by an individual floating gate transistor 600, enabling precise control of charging and discharging, thus maintaining the supply voltage and avoiding voltage drop after discharge. The capacity of the entire chip battery can be increased by increasing the capacity of a single capacitor structure 500 (e.g., increasing the depth of the deep trench or increasing the number of electrode layers 502 and dielectric layers 501) or the number of capacitor structures 500. Furthermore, since the capacitor structure 500 is fabricated within the substrate 100, the space within the substrate 100 can be fully utilized, reducing the size of the chip battery. The thickness of a single chip battery is very thin (can be as thin as <50μm). It can also be stacked with computing chips and memory chips to form an independent microcomputer system, and it is resistant to extreme environments, making it applicable to fields such as exploration and medicine.

[0057] Furthermore, since each capacitor structure 500 is composed of multiple layers of film, as the contact area increases, defects generated during the manufacturing process can easily lead to problems such as leakage and short circuits between the electrode layers 502, resulting in overheating and energy loss during chip battery charging. Therefore, it is necessary to isolate the leaking capacitor structures 500 to avoid their use. Based on this, the chip battery in this application performs a leakage isolation operation before use. The leakage isolation operation specifically includes applying a first voltage (e.g., greater than 13V) to the control gate G of each floating gate transistor 600, grounding one end of the control line, and applying a second voltage (e.g., 3.3V) to the other end, where the first voltage is greater than the second voltage. In a capacitor structure 500 with leakage and short-circuit issues between the electrode layers 502, the drain region 601 of the floating gate transistor 600 connected in series is grounded. Under the high voltage control of the control gate G, electrons flow from the drain region 601 to the source region 602 and are injected into the floating gate under the strong electric field of the control gate G, resulting in a certain amount of negative charge in the floating gate. In contrast, in a capacitor structure 500 without leakage and short-circuit issues between the electrode layers 502, the drain region 601 of the floating gate transistor 600 connected in series is floating, and there is no electron flow between the drain region 601 and the source region 602, so no electrons are injected into the floating gate. When the chip battery is in use, it applies a working voltage (e.g., 1.8V) to the control gate G of the floating gate transistor 600. Because the floating gate of the floating gate transistor 600 connected in series with the leakage capacitor structure 500 has a negative charge, it will cancel the electric field on the control gate G, causing the floating gate transistor 600 to fail to turn on. The corresponding control circuit is automatically isolated. However, the floating gate of the floating gate transistor 600 connected in series with the normal capacitor structure 500 does not have a negative charge. When a working voltage (e.g., 1.8V) is applied to the control gate G, it can be turned on normally, and the corresponding control circuit can work normally. As can be seen, the chip battery in this application performs a leakage isolation operation before use. Because a high voltage is applied to the control gate G of the floating gate transistor 600, one end of the control line is grounded and the other end is applied to a low voltage, negative charge is injected into the floating gate of the floating gate transistor 600 connected in series with the capacitor structure 500 which has leakage and short-circuit problems. When the chip battery is in use, the floating gate transistor 600 with negative charge injected into its floating gate cannot be turned on, thereby automatically isolating the capacitor structure 500 which has leakage and short-circuit problems, achieving the effect of rapid self-detection and self-isolation.

[0058] Furthermore, the first voltage needs to be greater than the turn-on voltage of the floating gate transistor 600. In order to ground one end of the control line and apply the second voltage to the other end, the first electrode P1 can be directly grounded and the second voltage can be applied to the second electrode P2, or the second electrode P2 can be grounded and the second voltage can be applied to the first electrode P1.

[0059] Based on this, one embodiment of this application also provides a method for preparing a chip battery. Figure 1This is a schematic diagram of the structure corresponding to the steps of the chip battery fabrication method provided in an embodiment of this application, as shown below. Figure 1 As shown, the method for fabricating a chip battery includes:

[0060] Step S100: Provide a substrate;

[0061] Step S200: Form at least one control line, each control line including a series-connected floating-gate transistor and an energy storage unit, the energy storage unit including one or at least two parallel-connected capacitor structures, at least a portion of the floating-gate transistor being located on the substrate, and the capacitor structures being located within the substrate; and,

[0062] Step S300: Perform leakage isolation operation by applying a first voltage to the control gate of each floating gate transistor, grounding one end of the control line, and applying a second voltage to the other end, wherein the first voltage is greater than the second voltage.

[0063] Figures 2-10 This is a schematic diagram of the structure corresponding to the corresponding steps of the chip battery fabrication method provided in an embodiment of this application. Next, we will combine... Figures 2-10 The method for preparing a chip battery according to an embodiment of this application will be described in detail.

[0064] like Figure 2 As shown, in step S100, a substrate 100 is provided. The material of the substrate 100 can be silicon, germanium, silicon-germanium, silicon-on-insulator, germanium-on-insulator, gallium arsenide, silicon carbide, etc.

[0065] Please see Figures 2-6 In step S200, a deep trench 300 is first formed in the substrate 100. Figures 2-6 Two deep trenches 300 are shown as an example.

[0066] like Figure 2 As shown, a mask layer 200 is formed on the substrate. A dry etching process is used to etch a portion of the thickness of the mask layer 200 and the substrate 100 from the surface of the mask layer 200 downwards to form a first sub-trench 301. The first sub-trench 301 extends downwards from the surface of the mask layer 200 into the substrate 100. At this time, the first sub-trench 301 has an initial morphology, which can be rectangular, U-shaped or inverted trapezoidal.

[0067] like Figure 3As shown, a wet etching process is used to continue etching the substrate 100 along the first sub-trench 301. The etchant from the wet etching process flows into the first sub-trench 301, continuing to etch the substrate 100 within the first sub-trench 301. However, because the etchant in the wet etching process is selective for crystal orientation, the substrate 100 is etched laterally within the first sub-trench 301. After etching, the shape and size of the first sub-trench 301 change, forming a sigma-shaped (also known as diamond-shaped, Σ-shaped, or sigma-shaped) first sub-trench 301. The etchant used in the wet etching process is tetramethylammonium hydroxide (TMAH), which... <111> The etching rate of the crystal orientation is lower than that of other crystal orientations, so that after etching, the shape of the first sub-trench 301 will become a sigma shape.

[0068] like Figure 4 As shown, a first isolation layer 401 is formed on the sidewall of the first sub-trench 301. A dry etching process is used to continue etching a portion of the thickness of the substrate 100 downward along the first sub-trench 301 to form a second sub-trench 302. The second sub-trench 302 is located below the first sub-trench 301 and is interconnected with the first sub-trench 301. At this time, the second sub-trench 302 has an initial morphology, which can be rectangular, U-shaped or inverted trapezoidal.

[0069] like Figure 5 As shown, a wet etching process is used to continue etching the substrate 100 along the second sub-trench 302. The etchant from the wet etching process flows into the second sub-trench 302 and continues to etch the substrate 100 within the second sub-trench 302. However, because the etchant in the wet etching process is selective for crystal orientation, the substrate 100 is etched laterally within the second sub-trench 302. After etching, the shape and size of the second sub-trench 302 will change, forming a sigma-shaped second sub-trench 302. Since a first isolation layer 401 is formed on the sidewall of the first sub-trench 301, the morphology of the first sub-trench 301 will not change when the second sub-trench 302 is formed by etching the substrate 100.

[0070] like Figure 6 As shown, a second isolation layer 402 is formed on the inner wall of the second sub-trench 302. The material of the second isolation layer 402 and the first isolation layer 401 can be the same. The first isolation layer 401 and the second isolation layer 402 can isolate the substrate 100 from the capacitor structure 500 in subsequent processes. Of course, when the second isolation layer 402 is formed on the inner wall of the second sub-trench 302, the second isolation layer 402 may also be on the surface of the first isolation layer 401, but this does not affect the implementation of this application.

[0071] Furthermore, the first sub-groove 301 and the second sub-groove 302 constitute a deep trench 300, from Figure 6As can be seen, the sidewalls of the deep trench 300 are not straight, but rather have a serrated shape with repeated bends, which significantly increases the surface area of ​​the deep trench 300. When a capacitor structure 500 is subsequently formed along the inner wall of the deep trench 300, the area of ​​the capacitor structure 500 within the deep trench 300 can be significantly increased, thereby improving the capacitance value of the capacitor structure 500.

[0072] It should be noted that in some embodiments, only one dry etching process and one wet etching process may be performed. In this case, the deep trench 300 may contain only one sub-trench, thereby increasing the capacitance value of the capacitor structure 500 without significantly increasing the complexity of the process. Alternatively, multiple dry etching processes and multiple wet etching processes may be performed alternately, so that the deep trench 300 may contain multiple sub-trenches, thereby significantly increasing the capacitance value of the capacitor structure 500. In other words, when forming the deep trench 300, dry etching and wet etching processes can be alternately performed at least once on the same location of the substrate 100. Each time a dry etching process and wet etching process are performed, a sub-trench is formed. When multiple dry etching and wet etching processes are alternately performed on the same location of the substrate 100, the sub-trenches are connected vertically, and finally a deep trench 300 with serrated sidewalls is formed. Furthermore, when a wet etching process is performed to form a sub-trench, at least one isolation layer is formed on the inner wall of the sub-trench.

[0073] In some embodiments, the sidewalls of the deep trench 300 are not limited to a sawtooth shape, but can also be wavy, arc-shaped, or straight, etc., and this application does not impose any limitations. For example, a dry etching process can be used to directly etch a portion of the depth of the substrate 100 from the surface of the substrate 100 downwards, thereby forming the deep trench 300. In this case, the sidewalls of the deep trench 300 are straight.

[0074] In some embodiments, the deep trench 300 with serrated sidewalls is not limited to being formed by alternating etching of the same location of the substrate 100 using dry etching and wet etching processes, but can also be formed by other possible processes, which will not be described in detail here.

[0075] like Figure 7As shown, stacked electrode layers 502 and dielectric layers 501 are formed on the inner wall of the deep trench 300. For example, they can be stacked sequentially in the order of one electrode layer 502, one dielectric layer 501, and another electrode layer 502. There are at least two electrode layers 502 and at least one dielectric layer 501. The dielectric layer 501 is located between two adjacent electrode layers 502. Two adjacent electrode layers 502 and the dielectric layer 501 sandwiched between them can form a sub-capacitor. All electrode layers 502 and dielectric layers 501 in each deep trench 300 constitute a capacitor structure 500. To maximize the capacitance of the capacitor structure 500, all sub-capacitors in the capacitor structure 500 can be connected in parallel. It is conceivable that the more electrode layers 502 and dielectric layers 501 there are, the more sub-capacitors each capacitor structure 500 contains, and the larger the capacitance of the capacitor structure 500.

[0076] In some embodiments, the dielectric layer 501 may be made of a high-k material, such as silicon oxide, hafnium-based oxides (e.g., HfO2, HfSiO, HfSiON, etc.), aluminum-based oxides (e.g., Al2O3), zirconium-based oxides (e.g., ZrO2), etc. The electrode layer 502 may be made of a metallic material, such as gold, silver, copper, tungsten, platinum, aluminum, etc., or other possible conductive materials.

[0077] like Figure 8 As shown, the portion of the mask layer 200 and the portion of the capacitor structure 500 protruding from the substrate 100 is removed by a process such as polishing, and then a floating gate transistor 600 is formed on the substrate 100. Specifically, the step of forming the floating gate transistor 600 on the substrate 100 may be: forming a gate structure 603 of the floating gate transistor 600 on the substrate 100, the gate structure 603 including a gate oxide layer, a floating gate, a gate dielectric layer, a control gate G, and a gate sidewall, the gate oxide layer, the floating gate, the gate dielectric layer, and the control gate G being stacked sequentially from bottom to top on the substrate 100, and the gate sidewalls covering the sidewalls of the gate oxide layer, the floating gate, the gate dielectric layer, and the control gate G; for the gate structure 60 Ion implantation is performed on the substrates 100 on both sides to form source region 602 and drain region 601 within the substrate 100. Gate structure 603 is located between adjacent source region 602 and drain region 601. The source region 602 and drain region 601 on both sides of gate structure 603 can form a floating gate transistor 600. Furthermore, a part of floating gate transistor 600 (gate structure 603) is located on substrate 100, and another part (source region 602 and drain region 601) is located within substrate 100.

[0078] In some embodiments, the floating gate transistors 600 are positioned close together, so that two or more floating gate transistors 600 can share the source region 602, thereby saving area and simplifying wiring. For example, in Figure 8In this configuration, two floating gate transistors 600 are positioned between two capacitor structures 500. Thus, the two floating gate transistors 600 can share the source region 602, but this should not be a limitation. The relative positions of the floating gate transistors 600 and the capacitor structure 500 can be designed as needed. The floating gate transistors 600 can share the source region 602 or each have its own independent source region 602.

[0079] like Figure 9 and Figure 10 As shown, a dielectric layer 700 is formed on the substrate 100 and the floating gate transistor 600, and a plug structure 701 is formed in the dielectric layer 700. Each electrode layer 502, the source region 602, the drain region 601, and the control gate G of the floating gate transistor 600 can be led out through the corresponding plug structure 701. Then, a metal interconnect layer is formed on the dielectric layer 700. Figure 9 and Figure 10 (Not shown in the diagram) The metal interconnect layer can be electrically connected to the plug structure 701, thereby connecting the sub-capacitors of each capacitor structure 500 in parallel. If there are multiple capacitor structures 500 in each control line, the metal interconnect layer can also connect the multiple capacitor structures 500 in each control line in parallel (forming an energy storage unit), and then connect the energy storage unit in each control line in series with the floating gate transistor 600. If all control lines need to be connected in parallel, the metal interconnect layer can also connect all the control lines in parallel. That is to say, the metal interconnect layer undertakes the wiring function of the chip battery. The metal interconnect layer connects one or more capacitor structures 500 in parallel through the plug structure 701 and then connects them in series with the corresponding floating gate transistor 600 to form a control line. The metal wiring layer also electrically connects one end of all control lines and leads them out as the first electrode P1 of the chip battery, and electrically connects the other end of all control lines and leads them out as the second electrode P2 of the chip battery.

[0080] Next, step S300 is executed to perform a leakage isolation operation. A first voltage (e.g., greater than 13V) is applied to the control gate G of each floating gate transistor 600, one end of the control line is grounded, and a second voltage (e.g., 3.3V) is applied to the other end. The first voltage is greater than the second voltage. Specifically, the first electrode P1 can be grounded and the second voltage can be applied to the second electrode P2, or the second electrode P2 can be grounded and the second voltage can be applied to the first electrode P1. In a capacitor structure 500 with leakage and short-circuit issues between the electrode layers 502, the drain region 601 of the floating gate transistor 600 connected in series is grounded. Under the high voltage control of the control gate G, electrons flow from the drain region 601 to the source region 602 and are injected into the floating gate under the strong electric field of the control gate G, resulting in a certain amount of negative charge in the floating gate. In contrast, in a capacitor structure 500 without leakage and short-circuit issues between the electrode layers 502, the drain region 601 of the floating gate transistor 600 connected in series is floating, and there is no electron flow between the drain region 601 and the source region 602, so no electrons are injected into the floating gate. When the chip battery is in use, a working voltage (e.g., 1.8V) is applied to the control gate G of the floating-gate transistor 600. Because the floating gate of the floating-gate transistor 600 connected in series with the leakage capacitor structure 500 has a negative charge, it cancels out the electric field on the control gate G, preventing the floating-gate transistor 600 from turning on. The corresponding control circuit is automatically isolated. However, the floating gate of the floating-gate transistor 600 connected in series with the normal capacitor structure 500 does not have a negative charge. When a working voltage (e.g., 1.8V) is applied to the control gate G, it can turn on normally, and the corresponding control circuit can function normally. In other words, once the capacitor structure 500 and the floating-gate transistor 600 of the chip battery are formed, leakage isolation can be performed. This isolates the capacitor structure 500, which may have leakage or short-circuit problems due to process defects during manufacturing, preventing overheating and energy loss during chip battery charging.

[0081] Furthermore, the capacity of the chip battery in this application can be increased by increasing the number of electrode layers 502 and dielectric layers 501 in the deep trench 300, thereby increasing the capacity of the chip battery. Calculations show that the depth of the deep trench 300 is 50 μm, the width is 1 μm, and the number of trenches is 50. The dielectric layer 501 is an aluminum oxide layer with a thickness of 2 nm (relative permittivity 9.8). The number of electrode layers 502 is 100. For a 1 cm × 1 cm chip battery with an 80% electrode area ratio, the capacitance of the capacitor structure 500 is 0.112 F. Based on a charging voltage of 36 V, a charging current of 1 A, and a charging time of 2 s, the capacity of a single chip battery is 1.12 mAh. Approximately 700 1 cm × 1 cm chip batteries can be produced from one 12-inch wafer, resulting in a total chip battery capacity of 784 mAh.

[0082] In summary, this embodiment provides a chip battery, including a substrate 100 and at least one control line. Each control line includes a series-connected floating-gate transistor 600 and an energy storage unit. The energy storage unit includes one or at least two parallel-connected capacitor structures 500. At least a portion of the floating-gate transistor 600 is located on the substrate 100, and the capacitor structures 500 are located within the substrate 100. Before use, the chip battery performs a leakage isolation operation, which includes applying a first voltage to the control gate G of each floating-gate transistor 600, grounding one end of the control line, and applying a second voltage to the other end, wherein the first voltage is greater than the second voltage. The unexpected effects of this application are as follows: This application utilizes chip technology to form a capacitor structure 500 within the substrate 100, storing and discharging electricity through the charging and discharging of the capacitor structure 500. The chip battery has no risk of explosion or combustion, charges quickly, and does not suffer from low-temperature degradation. Each control circuit is controlled by an individual floating-gate transistor 600, enabling precise control of charging and discharging, thereby maintaining the supply voltage and avoiding voltage drop after discharge. The overall capacity of the chip battery can be increased by increasing the capacity of a single capacitor structure 500 or by increasing the number of capacitor structures 500. Furthermore, since the capacitor structure 500 is integrated within the substrate 100, the space within the substrate 100 can be fully utilized, reducing the size of the chip battery. The thickness of a single chip battery is very thin (it can be as thin as <50μm). It can also be stacked with computing chips and memory chips to form an independent microcomputer system, and it is resistant to extreme environments, making it applicable to fields such as exploration and medicine. Furthermore, the chip battery performs a leakage isolation operation before use. Since a high voltage is applied to the control gate G of the floating gate transistor 600, one end of the control circuit is grounded and the other end is applied to a low voltage. For the capacitor structure 500 with leakage or short-circuit problems between the plates, electrons will flow between the source and drain terminals of the series-connected floating gate transistor 600 and be injected into the floating gate under the action of a strong electric field, so that a certain amount of negative charge exists in the floating gate. When the chip battery is in use, the control gate G of the floating gate transistor 600 is applied to a lower operating voltage. If there is negative charge in the floating gate of the floating gate transistor 600, it will cancel the electric field of the control gate G, and the floating gate transistor 600 cannot be turned on. Therefore, the leakage capacitor structure 500 is automatically isolated, realizing the effect of rapid self-detection and self-isolation of the leakage block.

[0083] It should be noted that the various embodiments in this specification are described in a progressive manner, with each embodiment focusing on the differences from other embodiments. Similar or identical parts between embodiments can be referred to interchangeably. For the systems disclosed in the embodiments, since they correspond to the methods disclosed in the embodiments, the descriptions are relatively simple, and relevant parts can be referred to the method section.

[0084] It should also be noted that although preferred embodiments have been disclosed above, these embodiments are not intended to limit this application. Any person skilled in the art can make many possible variations and modifications to the technical solutions of this application, or modify them into equivalent embodiments, without departing from the scope of the technical solutions of this application. Therefore, any simple modifications, equivalent changes, and modifications made to the above embodiments based on the technical essence of this application, without departing from the content of the technical solutions of this application, shall still fall within the scope of protection of the technical solutions of this application.

[0085] It should also be understood that, unless otherwise specified or indicated, the terms “first,” “second,” “third,” etc., in the specification are used only to distinguish the various components, elements, and steps in the specification, and not to indicate the logical or sequential relationships between the various components, elements, and steps.

[0086] Furthermore, it should be recognized that the terminology described herein is used only to describe particular embodiments and is not intended to limit the scope of this application. It must be noted that the singular forms “a” and “an” as used herein include plural bases unless the context clearly indicates the opposite. For example, a reference to “a step” or “an apparatus” means a reference to one or more steps or apparatuses, and may include secondary steps and secondary apparatuses. All conjunctions used should be understood in the broadest sense. Also, the word “or” should be understood as having the definition of logical “or”, not logical “exclusive OR”, unless the context clearly indicates the opposite. Furthermore, implementations of the methods and / or devices in the embodiments of this application may include performing selected tasks manually, automatically, or in combination.

Claims

1. A chip battery, characterized by The chip battery comprises a substrate and at least one control line, each of the control lines comprising a floating gate transistor and an energy storage unit connected in series, the energy storage unit comprising one or at least two parallel capacitor structures, at least part of the floating gate transistor being located on the substrate, the capacitor structures being located in the substrate, a drain region of the floating gate transistor being connected to one end of the capacitor structures, the other end of the capacitor structures serving as one end of the control line, and a source region of the floating gate transistor serving as the other end of the control line. Furthermore, a leakage isolation operation is performed on the chip battery, the leakage isolation operation comprising applying a first voltage to a control gate of each of the floating gate transistors, grounding one end of the control line, and applying a second voltage to the other end of the control line, the first voltage being greater than the second voltage. The control lines are at least two in number, and all the control lines are connected in parallel.

2. The chip battery according to claim 1, characterized by The control lines are at least two in number, and the floating gate transistors of at least part of the control lines share a source region.

3. The chip battery according to claim 1 or 2, characterized by The first voltage is greater than an on-voltage of the floating gate transistor.

4. The chip battery according to claim 1, wherein The substrate has at least one deep trench, and the capacitor structures are filled in the corresponding deep trenches, the capacitor structures comprising stacked plate layers and dielectric layers along inner walls of the deep trenches, the plate layers being at least two in number, the dielectric layers being at least one in number, and the dielectric layers being located between adjacent two plate layers.

5. The chip battery according to claim 1, wherein The sidewalls of the deep trenches are zigzag-shaped.

6. The chip battery according to claim 5, characterized by The deep trenches comprise at least one sub-trench, the sub-trenches being arranged in sequence along a thickness direction of the substrate and being connected to each other, and each of the sub-trenches is sigma-shaped.

7. The chip battery according to claim 6, characterized by The chip battery comprises:

8. A method of making a chip battery, characterized by providing a substrate; forming at least one control line, each of the control lines comprising a floating gate transistor and an energy storage unit connected in series, the energy storage unit comprising one or at least two parallel capacitor structures, at least part of the floating gate transistor being located on the substrate, the capacitor structures being located in the substrate, a drain region of the floating gate transistor being connected to one end of the capacitor structures, the other end of the capacitor structures serving as one end of the control line, and a source region of the floating gate transistor serving as the other end of the control line; Furthermore, a leakage isolation operation is performed on the chip battery, the leakage isolation operation comprising applying a first voltage to a control gate of each of the floating gate transistors, grounding one end of the control line, and applying a second voltage to the other end of the control line, the first voltage being greater than the second voltage. The step of forming the capacitor structures in the substrate comprises: etching a part of the substrate to form at least one deep trench in the substrate; 9. The method for preparing a chip battery as described in claim 8, characterized in that, forming stacked plate layers and dielectric layers along inner walls of the deep trenches, the plate layers being at least two in number, the dielectric layers being at least one in number, and the dielectric layers being located between adjacent two plate layers. The sidewalls of the deep trenches are zigzag-shaped, and the step of forming the deep trenches in the substrate comprises: adopting a dry etching process to etch the substrate to form sub-trenches in the substrate; 10. The method for preparing a chip battery as described in claim 9, characterized in that, adopting a wet etching process to etch the substrate transversely along the sub-trenches to make the sub-trenches sigma-shaped; and ​ ​ Alternately performing the dry etching process and the wet etching process on the same location of the substrate at least once to form the deep trench.

11. The method for preparing a chip battery according to any one of claims 8 to 10, characterized in that, The step of forming the control line includes: forming at least one of the capacitor structures in the substrate; forming at least one of the floating gate transistors on the substrate; forming a dielectric layer on the substrate and the floating gate transistors, and forming a plug structure in the dielectric layer; and forming a metal interconnection layer on the dielectric, the metal interconnection layer connecting one or at least two of the capacitor structures in parallel and connecting the corresponding floating gate transistors in series through the plug structure to form the control line.

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