Semiconductor device structure and forming method thereof

Abstract

The invention relates to a semiconductor device structure and a forming method thereof. The embodiment of the invention relates to a semiconductor device structure. The structure comprises a substrate; the insulating material is arranged on the substrate; a first fin structure extending upwardly from the substrate through the insulating material; a second fin structure extending upwardly from the substrate through the insulating material; a source / drain (S / D) feature disposed between the first fin structure and the second fin structure; and an isolation trench structure extending through the first fin structure and into the substrate, where the isolation trench structure has a doped sidewall region disposed between and in contact with the S / D feature and the isolation trench structure.

Description

Technical Field

[0001] This disclosure relates to the field of semiconductor device technology, and more specifically to semiconductor device structures and methods of forming thereof. Background Technology

[0002] As the semiconductor industry moves towards nanometer technology process nodes in pursuit of higher device density, higher performance, and lower costs, the challenges of both manufacturing and design have led to the development of multi-gate devices, such as FinFETs and Gate All-Around (GAA) transistors. To continue providing the required scaling and increased density for multi-gate devices at advanced technology nodes, it is necessary to continue reducing gate pitch. Various approaches (e.g., Polysilicon on Diffused Edges (PODE) and Continuous Polysilicon on Diffused Edges (CPODE)) have been used to scale gate pitch while preventing leakage current between transistors. However, such approaches often involve highly selective and low-selective etching processes for large-scale circuits and devices, which can result in a high risk of source / drain damage.

[0003] Therefore, improvements are needed in IC processing and manufacturing. Summary of the Invention

[0004] According to a first aspect of this disclosure, a semiconductor device structure is provided, comprising: a substrate; an insulating material disposed on the substrate; a first fin structure extending upward from the substrate through the insulating material; a second fin structure extending upward from the substrate through the insulating material; a source / drain (S / D) feature disposed between the first fin structure and the second fin structure; and an isolation trench structure extending through the first fin structure and into the substrate, wherein the isolation trench structure has a doped sidewall region disposed between the S / D feature and the isolation trench structure and in contact with the S / D feature and the isolation trench structure.

[0005] According to a second aspect of this disclosure, a method for forming a semiconductor device structure is provided, comprising: forming a plurality of fin structures from a substrate, each fin structure including a plurality of alternately stacked semiconductor layers and a plurality of sacrificial layers; forming source / drain (S / D) features on opposite sides of the fin structures; forming an isolation trench between two adjacent S / D features by removing exposed portions of the semiconductor layers and sacrificial layers; doping the isolation trench to form doped regions in the sidewalls of the isolation trench; and filling the isolation trench with a dielectric material.

[0006] According to a third aspect of this disclosure, a method for forming a semiconductor device structure is provided, comprising: forming a plurality of fin structures from a substrate, each fin structure including a plurality of alternately stacked semiconductor layers and a plurality of sacrificial layers; forming an insulating material on the substrate; forming a sacrificial gate structure on the insulating material and over a portion of the fin structure; forming source / drain (S / D) features on opposite sides of each fin structure; forming a first portion of an isolation trench by removing portions of the sacrificial gate structure and the sacrificial layers to expose the plurality of semiconductor layers of a first fin structure; exposing the isolation trench to a preprocessing process; forming a second portion of the isolation trench by removing a portion of the substrate and the first fin structure; and filling the isolation trench with a dielectric material. Attached Figure Description

[0007] Various aspects of this disclosure can be best understood by reading in conjunction with the accompanying drawings through the following detailed description. It should be noted that, in accordance with standard practice in the art, the various features are not drawn to scale. In fact, for clarity of discussion, the dimensions of the various features can be arbitrarily increased or decreased.

[0008] Figure 1 , Figure 2 , Figure 3 , Figure 4 , Figure 5 and Figure 6 These are perspective views of various stages in the fabrication of a semiconductor device structure according to some embodiments.

[0009] Figure 7A , Figure 8A , Figure 9A and Figure 10A According to some embodiments Figure 6 The AA section is a cross-sectional side view of each stage of the manufacturing process of a semiconductor device structure.

[0010] Figure 7B , Figure 8B , Figure 9B and Figure 10B According to some embodiments Figure 6 The BB line is a cross-sectional side view of each stage of the manufacturing process of a semiconductor device structure.

[0011] Figure 7C , Figure 8C , Figure 9C and Figure 10C According to some embodiments Figure 6 The CC line is a cross-sectional side view of each stage of manufacturing a semiconductor device structure.

[0012] Figure 11A-11B , Figure 12A-12B , Figures 13A-13B , Figures 14A-14B , Figures 15A-15B , Figures 16A-16B , Figures 17A-17B , Figures 18A-18B , Figures 19A-19B , Figures 20A-20B , Figures 21A-21B , Figures 22A-22B and Figures 23A-23B Manufacturing according to some embodiments Figure 10A and 10B Cross-sectional side views of one of the various stages of a semiconductor device structure, showing multiple fin structures arranged along the X and Y directions, respectively.

[0013] Figure 17A-1 An enlarged view of a portion of a semiconductor device structure is shown, revealing protective barriers in the sidewalls of an isolation trench.

[0014] Figure 18B-1 and Figure 18B-2 An isolation trench according to some alternative embodiments is shown.

[0015] Figure 24 , Figure 25 , Figure 26 , Figure 27 and Figure 28 The use of a sacrificial dielectric layer according to some alternative embodiments is illustrated.

[0016] Figures 29A-29B , Figures 30A-30B , Figures 31A-31B , Figures 32A-32B , Figures 33A-33B , Figures 34A-34B , Figures 35A-35B and Figures 36A-36B Manufacturing according to some alternative embodiments Figure 10A and 10B Cross-sectional side views of one of the various stages of a semiconductor device structure, showing multiple fin structures arranged along the X and Y directions, respectively.

[0017] Figure 37 This is a top view of a semiconductor device structure according to some embodiments.

[0018] Figure 38A , Figure 39A , Figure 40A , Figure 41A , Figure 42A , Figure 43A , Figure 44A , Figure 45A and Figure 46A According to some embodiments Figure 37 The DD line is a cross-sectional side view of each stage of the manufacturing process of a semiconductor device structure.

[0019] Figure 38B , Figure 39B , Figure 40B , Figure 41B , Figure 42B , Figure 43B , Figure 44B , Figure 45B and Figure 46B According to some embodiments Figure 37 The EE is a cross-sectional side view of each stage of the manufacturing process of a semiconductor device structure.

[0020] Figure 38C , Figure 39C , Figure 40C , Figure 41C , Figure 42C , Figure 43C , Figure 44C , Figure 45C and Figure 46C According to some embodiments Figure 37 The FF line is a cross-sectional side view of each stage of the manufacturing process of a semiconductor device structure. Detailed Implementation

[0021] The following disclosure provides numerous different embodiments or examples for implementing various features of the provided subject matter. Specific examples of components and arrangements are described below to simplify this disclosure. Of course, these are merely examples and are not intended to be limiting. For example, in the following description, forming a first feature on or over a second feature may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features such that the first and second features may not be in direct contact.

[0022] Furthermore, spatially related terms (e.g., "below," "under," "lower," "above," "above," "top," "upper," etc.) may be used herein to readily describe the relationship of one element or feature shown in a figure relative to another element(s) or feature(s). In addition to the orientation depicted in the figures, spatially related terms are also intended to encompass different orientations of the device during use or operation. The device may be oriented in other directions (rotated 90 degrees or in other orientations), and the spatially related descriptors used herein can be interpreted similarly accordingly.

[0023] As integrated circuits shrink in size, the epitaxial critical dimension (EPI CD) (also known as the spacing between epitaxial regions) becomes increasingly smaller. Small EPICDs make etching trenches in insulating structures without damaging adjacent structures (e.g., source / drain features) challenging. Exemplary insulating structures may include continuous metal on diffusion edges (CMODE) structures or continuous polysilicon on diffusion edges (CPODE) structures. CMODE or CPODE structures prevent leakage current through the epitaxial source / drain features, transistors, and the silicon substrate. To avoid photoresist stripping issues in CMODE or CPODE processes, the dicing pattern in the photoresist layer is intentionally positioned off-axis from the central axis of the gate structure. However, this offset can cause bending issues in the openings formed between the gate spacers of the gate structure, beneath the dicing pattern. Furthermore, source / drain features can be grown using multilayer epitaxial processes to improve etch resistance in peripheral regions. However, multilayer epitaxial processes can lead to voids in the source / drain features, degrading device performance. This disclosure solves the aforementioned problems by employing a highly selective sheet-cut process and a boron-based pretreatment process to achieve self-aligned CMODE or CPODE etching profiles. Embodiments of this disclosure are applicable to any device that may include a CPODE or CMODE structure, such as planar FETs, finned FETs, horizontal gate all-around (HGAA) FETs, vertical gate all-around (VGAA) FETs, and other suitable devices.

[0024] Figures 1 to 46C An exemplary process for manufacturing a semiconductor device structure 100 according to embodiments of the present disclosure is shown. It should be understood that, for additional embodiments of the method, [further details may be needed]. Figures 1 to 46C Additional operations are provided before, during, and after the processes shown, and some of these operations can be substituted or eliminated. The order of operations / processes is not restricted and can be interchanged.

[0025] Figure 1-6 These are perspective views of various stages in the fabrication of a semiconductor device structure 100 according to some embodiments. Figure 1As shown, the semiconductor device structure 100 includes a semiconductor layer stack 104 formed on the front side of a substrate 101. The substrate 101 may be a semiconductor substrate. The substrate 101 may include crystalline semiconductor materials, such as, but not limited to, silicon (Si), germanium (Ge), silicon-germanium (SiGe), gallium arsenide (GaAs), indium antimonide (InSb), gallium phosphide (GaP), gallium antimonide (GaSb), indium aluminum arsenide (InAlAs), indium gallium arsenide (InGaAs), gallium antimony phosphide (GaSbP), gallium antimony arsenide (GaAsSb), and indium phosphide (InP). In some embodiments, the substrate 101 is a silicon-on-insulator (SOI) substrate having an insulating layer (not shown) disposed between two silicon layers for reinforcement. In one aspect, the insulating layer is an oxygen-containing layer.

[0026] The substrate 101 may include various regions that have been doped with impurities (e.g., dopants having p-type or n-type conductivity). Depending on the circuit design, the dopants may be, for example, phosphorus for the n-well regions and boron for the p-well regions.

[0027] Semiconductor layer stack 104 includes alternating semiconductor layers made of different materials to facilitate the formation of nanostructured channels in multi-gate devices, such as nanostructured channel FETs. In some embodiments, semiconductor layer stack 104 includes a first semiconductor layer 106 and a second semiconductor layer 108. In some embodiments, semiconductor layer stack 104 includes alternating first semiconductor layer 106 and second semiconductor layer 108. The first semiconductor layer 106 and the second semiconductor layer 108 are made of semiconductor materials with different etch selectivity and / or oxidation rates. For example, the first semiconductor layer 106 may be made of Si, and the second semiconductor layer 108 may be made of SiGe. In some examples, the first semiconductor layer 106 may be made of SiGe, and the second semiconductor layer 108 may be made of Si. Alternatively, in some embodiments, either of semiconductor layers 106, 108 may be or include other materials, such as Ge, SiC, GeAs, GaP, InP, InAs, InSb, GaAsP, AlInAs, AlGaAs, InGaAs, GaInP, GaInAsP, or any combination thereof. In some embodiments, during the process, the second semiconductor layer 108 may be etched and replaced with other materials (e.g., SiO or SiN).

[0028] The first semiconductor layer 106 and the second semiconductor layer 108 are formed by any suitable deposition process, such as epitaxy. For example, the epitaxial growth of the layers of the semiconductor layer stack 104 can be performed by molecular beam epitaxy (MBE), metal-organic chemical vapor deposition (MOCVD), and / or other suitable epitaxial growth processes.

[0029] In a later manufacturing stage, the first semiconductor layer 106 or portions thereof may form one or more nanostructured channels of the semiconductor device structure 100. The term nanostructure is used herein to refer to any portion of material having a nanometer-scale or even micrometer-scale size and an elongated shape, regardless of the cross-sectional shape of the portion. Thus, the term refers to elongated material portions with circular and substantially circular cross-sections, as well as beam-shaped or strip-shaped material portions including, for example, cylindrical or substantially rectangular cross-sections. The one or more nanostructured channels of the semiconductor device structure 100 may be surrounded by a gate electrode. The semiconductor device structure 100 may include nanostructured transistors. Nanostructured transistors may be referred to as nanosheet transistors, nanowire transistors, gate-all-around (GAA) transistors, multi-bridge-channel (MBC) transistors, or any transistor having a gate electrode surrounding the channel. The use of the first semiconductor layer 106 to define one or more channels of the semiconductor device structure 100 is further discussed below.

[0030] Each first semiconductor layer 106 may have a thickness ranging from about 5 nm to about 30 nm. Each second semiconductor layer 108 may have a thickness equal to, less than, or greater than the thickness of the first semiconductor layer 106. In some embodiments, each second semiconductor layer 108 has a thickness ranging from about 2 nm to about 50 nm. Figure 1 As shown, three first semiconductor layers 106 and three second semiconductor layers 108 are arranged alternately for illustrative purposes and are not intended to limit the specific content described in this application. It is understood that any number of first semiconductor layers 106 and second semiconductor layers 108 can be formed in the semiconductor layer stack 104, and the number of layers depends on the predetermined number of channels in the semiconductor device structure 100.

[0031] exist Figure 2In this embodiment, fin structures 112 are formed from a semiconductor layer stack 104. Each fin structure 112 has an upper portion including semiconductor layers 106, 108 and a substrate portion 116 formed from a substrate 101. The fin structures 112 can be formed by patterning a hard mask layer (not shown) formed on the semiconductor layer stack 104 using multiple patterning operations including photolithography and etching processes. The etching process can include dry etching, wet etching, reactive ion etching (RIE), and / or other suitable processes. The photolithography process can include: forming a photoresist layer (not shown) over the hard mask layer, exposing the photoresist layer to the pattern, performing a post-exposure baking process, and developing the photoresist layer to form a mask element including the photoresist layer. In some embodiments, an electron beam lithography process can be used to pattern the photoresist layer to form the mask element. The etching process passes through the hard mask layer, through the semiconductor layer stack 104, and into the substrate 101 in the unprotected area to form trenches 114, thereby leaving a plurality of extending fin structures 112. The trenches 114 extend in the X direction. The trenches 114 can be etched using dry etching (e.g., RIE), wet etching, and / or combinations thereof. In some embodiments, each fin structure 112 has a longitudinal axis in the X direction.

[0032] exist Figure 3 In the process, after forming the fin structure 112, an insulating material 118 is formed on the substrate 101. The insulating material 118 fills the trenches 114 between adjacent fin structures 112 until the fin structure 112 is embedded in the insulating material 118. Then, a planarization operation, such as a chemical mechanical polishing (CMP) method and / or an etch-back method, is performed to expose the top of the fin structure 112. The insulating material 118 can be made of silicon oxide, silicon nitride, silicon oxynitride (SiON), SiOCN, SiCN, fluorine-doped silicate glass (FSG), low-k dielectric material, or any suitable dielectric material. The insulating material 118 can be a multilayer dielectric structure. The insulating material 118 can be formed by any suitable method, such as low-pressure chemical vapor deposition (LPCVD), plasma-enhanced CVD (PECVD), or flowable CVD (FCVD).

[0033] exist Figure 4 In this configuration, insulating material 118 is recessed to form isolation region 120. The recesses in insulating material 118 expose portions of fin structures 112, such as semiconductor layer stack 104. The recesses in insulating material 118 also expose trenches 114 between adjacent fin structures 112. Isolation region 120 can be formed using suitable processes, such as dry etching, wet etching, or combinations thereof. The top surface of insulating material 118 may be flush with or below the surface of the second semiconductor layer 108 that contacts the substrate portion 116 formed from substrate 101.

[0034] exist Figure 5 In this embodiment, one or more sacrificial gate structures 130 (only one shown) are formed on the semiconductor device structure 100. The sacrificial gate structure 130 is formed on a portion of the fin structure 112. Each sacrificial gate structure 130 may include a sacrificial gate dielectric layer 132, a sacrificial gate electrode layer 134, and a mask layer 136. The sacrificial gate dielectric layer 132, the sacrificial gate electrode layer 134, and the mask layer 136 can be formed by sequentially depositing uniform-thickness blanket layers of the sacrificial gate dielectric layer 132, the sacrificial gate electrode layer 134, and the mask layer 136, and then patterning these layers into the sacrificial gate structure 130. Gate spacers 138 are then formed on the sidewalls of the sacrificial gate structure 130. For example, the gate spacers 138 can be formed by conformally depositing one or more gate spacers 138 and anisotropically etching these layers. In some embodiments, the gate spacers 138 are also formed on the sidewalls of the exposed portion of the fin structure 112. Although one sacrificial gate structure 130 is shown, in some embodiments, two or more sacrificial gate structures may be arranged along the X direction.

[0035] The sacrificial gate dielectric layer 132 may include one or more dielectric materials, such as silicon oxide-based materials. The sacrificial gate electrode layer 134 may include silicon, such as polycrystalline silicon or amorphous silicon. The mask layer 136 may include more than one layer, such as an oxide layer and a nitride layer. The gate spacer 138 may be made of a dielectric material, such as silicon oxide, silicon nitride, silicon carbide, silicon oxynitride, SiCN, silicon oxycarbide, SiOCN, and / or combinations thereof.

[0036] The portion of the fin structure 112 covered by the sacrificial gate electrode layer 134 of the sacrificial gate structure 130 serves as the channel region of the semiconductor device structure 100.

[0037] exist Figure 6 In this configuration, the portion of fin structure 112 not covered by sacrificial gate structure 130 and gate spacer 138 is recessed to, above, or below the level of the top surface of isolation region 120. The recessed portion of fin structure 112 can be achieved by an etching process (isotropic or anisotropic etching process), and the etching process can be selective relative to one or more crystal planes of substrate 101. The etching process can be dry etching, such as RIE, NBE, etc., or wet etching, such as using tetramethylammonium hydroxide (TMAH), ammonium hydroxide (NH4OH), or any suitable etchant.

[0038] Figure 7A , Figure 7B and Figure 7C They are along Figure 6A cross-sectional side view of the semiconductor device structure 100, taken by lines AA, BB, and CC.

[0039] Figure 8A , Figure 8B and Figure 8C According to some embodiments, respectively along Figure 6 A cross-sectional side view of one of the various stages of manufacturing a semiconductor device structure 100, taken by lines AA, BB, and CC. (See attached image.) Figure 8A As shown, the edge portions of each second semiconductor layer 108 of the semiconductor layer stack 104 are horizontally removed along the X direction. Removing the edge portions of the second semiconductor layer 108 forms a cavity. In some embodiments, portions of the second semiconductor layer 108 are removed by a selective wet etching process. When the second semiconductor layer 108 is made of SiGe and the first semiconductor layer 106 is made of silicon, the second semiconductor layer 108 can be selectively etched using a wet etchant, such as, but not limited to, ammonium hydroxide (NH4OH), tetramethylammonium hydroxide (TMAH), ethylenediamine catechol (EDP), or potassium hydroxide (KOH) solution.

[0040] After removing the edge portions of each second semiconductor layer 108, a dielectric layer is deposited in the cavity to form dielectric spacers 144. The dielectric spacers 144 can be made of a low-k dielectric material, such as SiON, SiCN, SiOC, SiOCN, or SiN. The dielectric spacers 144 can be formed by first forming a conformal dielectric layer using a conformal deposition process (e.g., ALD), followed by anisotropic etching to remove portions of the conformal dielectric layer other than the dielectric spacers 144. During the anisotropic etching process, the dielectric spacers 144 are protected by the first semiconductor layer 106. The remaining second semiconductor layer 108 is covered between the dielectric spacers 144 along the X direction.

[0041] Figure 9A , Figure 9B and Figure 9C According to some embodiments, respectively along Figure 6 A cross-sectional side view of one of the various stages of manufacturing a semiconductor device structure 100, taken by lines AA, BB, and CC. (See attached image.) Figure 9A and Figure 9CAs shown, source / drain (S / D) features 146 are formed from a first semiconductor layer 106 and a substrate portion 116. In some embodiments, S / D features 146 may be grown vertically and horizontally to form facets that may correspond to crystal planes of the material used for the substrate portion 116. In this disclosure, source regions and drain regions are used interchangeably, and their structures are substantially the same. Furthermore, one or more source / drain regions may individually or collectively refer to a source or drain, depending on the context. S / D features 146 may be formed from one or more layers of Si, SiP, SiC, and SiCP for an n-channel FET or one or more layers of Si, SiGe, and Ge for a p-channel FET. For p-channel FETs, p-type dopants (e.g., boron (B)) may also be included in S / D features 146. S / D features 146 may be formed using epitaxial growth methods such as CVD, ALD, or MBE.

[0042] Figure 10A , Figure 10B and Figure 10C According to some embodiments, respectively along Figure 6 A cross-sectional side view of one of the various stages of manufacturing a semiconductor device structure 100, taken by lines AA, BB, and CC. Figure 10A , Figure 10B and Figure 10C In this process, a contact etch stop layer (CESL) 162 is conformally formed on the exposed surface of the semiconductor device structure 100. CESL 162 covers the sidewalls of the sacrificial gate structure 130, the insulating material 118, and the S / D feature 146. CESL 162 may comprise oxygen-containing or nitrogen-containing materials, such as silicon nitride, silicon carbide nitride, silicon oxynitride, carbon nitride, silicon oxide, silicon carbon oxide, etc., or combinations thereof, and may be formed by CVD, PECVD, ALD, or any suitable deposition technique. Next, an interlayer dielectric (ILD) layer 164 is formed on the CESL 162 over the semiconductor device structure 100. The material used for the ILD layer 164 may include compounds containing Si, O, C, and / or H, such as silicon oxide, SiCOH, or SiOC. Organic materials (e.g., polymers) may also be used for the ILD layer 164. The ILD layer 164 may be deposited by a PECVD process or other suitable deposition techniques. In some embodiments, after the ILD layer 164 is formed, the semiconductor device structure 100 may be subjected to heat treatment to solidify the ILD layer 164.

[0043] After the formation of the ILD layer 164, a planarization operation such as CMP is performed on the semiconductor device structure 100 until the sacrificial gate electrode layer 134 is exposed. In some embodiments, after the planarization process, the ILD layer 164 is recessed, and a capping layer 139 is formed on the recessed ILD layer 164. The capping layer 139 may include a nitride, such as silicon nitride, to protect the ILD layer 164 during subsequent processes. A second planarization process may be performed to remove portions of the capping layer 139 formed on the sacrificial gate electrode layer 134. After the planarization process, the top surfaces of the capping layer 139, CESL 162, gate spacer 138, and sacrificial gate electrode layer 134 are substantially coplanar.

[0044] Figure 11A-11B to Figures 18A-18B and Figures 21A-21B to Figures 23A-23B Manufacturing according to some exemplary embodiments Figure 11A and Figure 11B Cross-sectional side views of one of the various stages of the semiconductor device structure 100, showing multiple fin structures arranged along the X and Y directions respectively. Figure 12A and Figure 12B In this configuration, a mask structure 1302 is formed on the top surface of a sacrificial gate electrode layer 134, a gate spacer 138, a CESL 162, and a cap layer 139 (or, if no cap layer 139 is present, a first ILD layer 164). The mask structure 1302 may include a hard mask 1304 and a resist layer 1306. The hard mask 1304 may be any suitable masking material. In some embodiments, the hard mask 1304 is formed of a nitrogen-containing material, such as SiN or SiCN. The resist layer 1306 may be a single-layer photoresist or a three-layer photoresist. An exemplary three-layer photoresist may include a bottom layer 1308, an intermediate layer 1310 disposed above the bottom layer 1308, and a top photoresist layer 1312 disposed above the intermediate layer 1310. The resist layer 1306 may be formed by any suitable process, such as spin coating. The bottom layer 1308 may be a bottom antireflective coating (BARC) layer. The intermediate layer 1310 may be a silicon-containing inorganic polymer, which provides anti-reflective properties and / or hard mask properties for the photolithography process. The top photoresist layer 1312 may be a DUV resist (KrF), argon fluoride (ArF) resist, EUV resist, electron beam (e-beam) resist, or ion beam resist.

[0045] exist Figure 13A and Figure 13BIn this process, the top layer of photoresist 1312 is patterned to form a plurality of photoresist mandrels spaced apart from each other by openings. For ease of illustration, two openings 1402a and 1402b are shown. The patterned top layer of photoresist 1312 serves as a mask to transfer the pattern in the top layer of photoresist 1312 (i.e., openings 1402a and 1402b) into the intermediate layer 1310, the bottom layer 1308, and the mask layer 1304. Openings 1402a and 1402b define isolation trenches to be formed in the substrate portions of the fin structures 102b and 102c. Isolation trenches can be disposed between adjacent active regions. The term "active region" refers to the region where a transistor is formed or to be formed. As will be discussed in more detail below, isolation trenches can be formed by performing a fin dicing (or slicing) process. The isolation trenches are filled with a dielectric to form a continuous polysilicon (CPODE) trench on the diffusion edge. This fin cutting (or slicing) process can be called the CPODE process. The term "diffusion edge" is equivalently called the active edge, which is the edge adjacent to an adjacent active region. The CPODE process can be used to reduce gate pitch, thereby increasing the density of multi-gate devices and thus improving the device performance required for large-scale circuits and devices.

[0046] exist Figure 14A and Figure 14B In the middle, the top layer of photoresist 1312 ( Figure 13A and Figure 13B The patterns (i.e., openings 1402a, 1402b) in the hard mask 1304 are transferred to the mask layer 1304 to form a patterned mask layer 1304'. The bottom layer 1308, the intermediate layer 1310, and the top photoresist layer 1312 are then removed. The formation of the patterned mask layer 1304' can be achieved through one or more photolithography processes. As a result of one or more photolithography processes, portions of the hard mask 1304 are removed, and trench patterns 1402a', 1402b' (collectively referred to as trench patterns 1402') are formed in the patterned mask layer 1304', and a portion of the sacrificial gate electrode layer 134 is exposed. Trench patterns 1402a', 1402b' are elongated openings aligned with the sacrificial gate structure 130. The removal of portions of the hard mask 1304 (and the native oxide formed thereon) can be performed using etch chemicals such as CF4, CHF3, CH2F2, CHF3, or C4F6, or combinations thereof. Then, during the subsequent removal of the exposed sacrificial gate structure and fin cutting (or slicing) process, the patterned mask layer 1304' can be used to protect the active region.

[0047] exist Figure 15A and Figure 15BIn this process, exposed sacrificial gate structures (e.g., sacrificial gate electrode layer 134) are selectively removed to form openings 1602a and 1602b (collectively referred to as opening 1602). Opening 1602 exposes gate spacer 138 and sacrificial gate dielectric layer 132. The removal of the exposed sacrificial gate structure can be performed by a selective etching process that removes sacrificial gate electrode layer 134 but substantially does not affect gate spacer 138 and sacrificial gate dielectric layer 132. Sacrificial gate dielectric layer 132 protects first semiconductor layer 106 and second semiconductor layer 108 during the etch-back process. In some embodiments, sacrificial gate dielectric layer 132 may also be removed during the selective etching process. In some embodiments, an etching chemical that is selective to the sacrificial gate structure to be etched is used. The etching chemical is selected to minimize etching of surrounding dielectric layers (e.g., insulating material 118, gate spacer 138, CESL 162, and first ILD layer 164). In some embodiments, the sacrificial gate structure 130 may be removed using chlorine-containing gases (e.g., SiCl4, BCl3, Cl2, CHCl3, CCl4, and / or BCl3), bromine-containing gases (e.g., HBr and / or CHBr3), iodine-containing gases, other suitable gases, and / or plasma and / or combinations thereof. In some embodiments, the sacrificial gate electrode layer 134 has a top flush with the top of the sacrificial gate dielectric layer 132. Subsequent fin dicing or slicing processes will remove the sacrificial gate electrode layer 134 and the sacrificial gate dielectric layer 132 from the CPODE trench.

[0048] exist Figure 16A and Figure 16B In this process, an etching process is performed to remove the sacrificial gate dielectric layer 132. The etching process can be dry etching, wet etching, or a combination thereof. The etching process selectively removes the sacrificial gate dielectric layer 132 without affecting the first semiconductor layer 106, the second semiconductor layer 108, and the sacrificial gate electrode layer 134.

[0049] Figure 17A and Figures 17B to 18A and Figure 18B The process of using plasma to dope impurities and cutting openings 1602 into the substrate portions of fin structures 102b and 102c to form isolation trenches is illustrated. Figure 17A and Figure 17BIn this process, a first semiconductor etching process 141 is performed to remove the first semiconductor layer 106 and the second semiconductor layer 108 (in some cases, a small portion of the insulating material 118 exposed due to ion bombardment), thereby forming a first segment of the isolation trench 1802. The first semiconductor etching process 141 is a fin cutting (or slicing) process. A patterned mask layer 1304' is used as an etching mask to perform the first semiconductor etching process 141, and the etching process can continue until the bottom 1802bs1 of the isolation trench 1802 reaches substantially the same height as the bottom of the S / D feature 146.

[0050] In various embodiments, the first semiconductor etching process 141 further includes a processing step. This processing step may be a doping process, in which impurities (e.g., group III elements) are simultaneously or sequentially doped into the surface (e.g., sidewalls) of the isolation trench 1802. The doped regions form protective barriers 1808 in the sidewalls of the isolation trench 1802. The sidewalls of the isolation trench 1802 include a doped first semiconductor layer 106' and a doped dielectric spacer 144'. Thus, the surface portions of the doped first semiconductor layer 106' and the doped dielectric spacer 144' serve as the protective barrier 1808. Doping of the impurities enhances the etch resistance of the S / D feature 146 during subsequent etching processes, enabling a damage-free, simple epitaxial structure of the S / D feature 46 even if photolithographic mask overlay misalignment occurs. The etch resistance of the S / D feature 146 can be improved because group III elements (trivalent) all contain three valence electrons and act as acceptors when used for silicon doping. When acceptor atoms replace tetravalent silicon atoms in a crystal, vacancies (electron holes) are created. Plasma doping with group III elements increases the electron hole concentration on the surface (e.g., sidewalls) of the isolation trench 1802. It has been observed that the high electron hole concentration in the doped regions leads to a reduced etch rate in the doped regions, thus making the doped regions protective barriers for the isolation trench 1802. As a result, the etch resistance of the S / D feature 146 is increased, and the integrity of the S / D feature 146 can remain substantially intact during subsequent etching processes.

[0051] The first semiconductor etching process 141 can be dry etching, reactive ion etching (RIE), and / or other suitable processes. In some embodiments, the first semiconductor etching process 141 is an anisotropic etching (directional etching) process. The first semiconductor etching process 141 is performed to selectively remove exposed portions of the first semiconductor layer 106, the second semiconductor layer 108, and the substrate 101 forming the fin structures 102b, 102c. A portion of the insulating material 118 surrounding the fin structures 102b, 102c may also be removed. In some embodiments, a self-aligned CPODE etching process is used to remove the exposed portions of the first semiconductor layer 106, the second semiconductor layer 108, and the substrate 101. The self-aligned CPODE etching process is configured to have high etch selectivity, such that the etch rate of the first semiconductor layer 106 and the second semiconductor layer 108 is greater than the etch rate of the dielectric spacer 144. As a result, the dielectric spacer 144 remains substantially intact after the fin cutting process.

[0052] In various embodiments, the self-aligned CPODE etching process is a plasma etching process using an etchant containing a reactive element selected from the halogen group, such as bromine, chlorine, fluorine, etc. For example, the etchant can be a bromine-based etching chemical, a chlorine-based etching chemical, or a fluorine-based etching chemical, or any combination thereof. In some embodiments, a hydrocarbon-based etching chemical is used. Other reactive gases (e.g., oxy-based etching chemicals) may also be used in conjunction with the etchant to promote the dissociation of plasma byproducts. During plasma etching, a processing step employing group III element impurities (i.e., p-type dopants) (e.g., boron, aluminum, gallium, and / or indium) is performed to dope the surface (e.g., sidewalls) of the isolation trench 1802 with group III elements. The processing step can be any suitable doping process, such as a plasma doping process or an implantation process. The processing step can be performed simultaneously with or intermittently with plasma etching. When the processing step is performed simultaneously with plasma etching, the dopant gas can flow simultaneously with the etchant. When the processing step is performed intermittently with plasma etching, the dopant gas and etchant can be supplied sequentially in a cyclic manner until the desired depth of the isolation trench 1802 is reached. In either case, the temperature of the plasma etching is controlled so that the P-type dopant is not activated. Furthermore, the P-type dopant is confined to the surface region to avoid affecting the electrical performance of the device. In any case, the P-type dopant in the doped region forms a protective barrier 1808 for isolating the trench 1802. In some embodiments, the plasma etching and processing are performed until the insulating material 118 is exposed. In this case, the top surface of the insulating material 118 may have a recess 118r with a curved or concave profile.

[0053] Exemplary hydrocarbon-based etching chemicals may include methane (CH4), ethane (C2H6), propane (C3H8), and combinations thereof. Exemplary bromine-based etching chemicals may include, but are not limited to, hydrogen bromide (HBr), bromine (Br2), boron tribromide (BBr3), and combinations thereof. Exemplary chlorine-based etching chemicals may include, but are not limited to, chlorine (Cl2), chloroform (CHCl3), carbon tetrachloride (CCl4), boron trichloride (BCl3), and combinations thereof. Exemplary fluorine-containing gases may include, but are not limited to, tetrafluoromethane (CF4), hexafluoroethane (C2F6), octafluorocyclobutane (C4F8), hexafluorobutadiene (C4F6), sulfur hexafluoride (SF6), nitrogen trifluoride (NF3), difluoromethane (CH2F2), difluoroethane (C2H4F2), trifluoromethane (CHF3), and hexafluoroane (C2F6). Exemplary oxygen-based etching chemicals may include, but are not limited to, oxygen (O2), carbon dioxide (CO2), ozone (O3), water vapor, and combinations thereof. Exemplary dopant gases used in the processing can include, but are not limited to, boron-containing gases such as diborane (B₂H₆), boron trichloride (BCl₃), borane (BH₃), boron tribromide (BBr₃), boron trifluoride (BF₃), triethyl borate (TEB), borazine (B₃N₃H₆), or alkyl-substituted derivatives of borazine, or combinations thereof. Diluent gases (e.g., helium (He), nitrogen (N₂), etc.) can also be used in conjunction with etching chemicals and / or dopant gases. Inert gases (e.g., argon (Ar), neon (Ne), krypton (Kr), etc.) can provide etching chemicals to increase the bombardment effect, thereby improving the etching rate of the first semiconductor layer 106 and the second semiconductor layer 108.

[0054] Exemplary plasma etching may include exposing a semiconductor device structure 100 to a gas mixture containing one or more etching chemicals in a high-density plasma process chamber using an ICP (inductively coupled plasma) or dipole antenna plasma source. In some embodiments, a resonant antenna plasma source or an electron cyclotron resonance (ECR) plasma source may also be used to achieve low-pressure operation (e.g., about 0.2 ± 0.05 mTorr). The plasma etching process may use plasma formed from a gas mixture containing HBr and BCl3. In some embodiments, the plasma etching process uses plasma formed from a gas mixture, for example, including CH4, BCl3, HBr, and CHF3. The plasma may be driven by an RF power generator using AC current operating at a frequency multiple of 13.56 MHz. The process chamber may be operated at a pressure of about 0.2 mTorr to about 150 mTorr and a temperature of about 20 degrees Celsius to about 120 degrees Celsius. The RF power generator is operated to provide a source power between about 100 W and about 2500 W. Higher directivity can be achieved by adding bias power to the substrate pedestal in the process chamber. In this case, a DC bias power operating in the range of approximately 0V to approximately 1000V (e.g., approximately 50V–150V) can be used. The source power and bias power can be controlled so that the ion acceleration energy is between approximately 20eV and approximately 200eV. In some cases, pulsed plasma etching can be used. In this case, the output of the power generator can be controlled by a pulse signal with a duty cycle ranging from approximately 5% to 95%. Alternatively, a self-aligned CPODE etching process can use only the bias power (zero source power) to enhance the etching directionality.

[0055] An exemplary plasma doping process may include exposing a semiconductor device structure 100 to a plasma generated in a plasma doping chamber by one or more dopant gases (e.g., boron-containing gases, such as B₂H₆ or BCl₃) and a dilution gas. The plasma doping process may be performed at a constant energy of about 2 keV to about 5 keV, a bias voltage of about -200V to about -20 kV, and a chamber pressure of about 1 mTorr to about 50 mTorr to dope plasma ions (e.g., boron) into the surface (e.g., sidewalls) of an isolation trench 1802. After the plasma doping process, the doped region (e.g., a protective barrier 1808) may have a density of about 1.0E¹⁵ atoms / cm². 3 Approximately 3.0E22 atoms / cm 3 The boron dopant concentration is within a certain range. Plasma doping can form a doped profile abrupt junction at a depth of about 5 nm to about 10 nm from the surface of the isolation trench 1802, with a doping profile abruptness of about 1 nm / decade.

[0056] As a result of the first semiconductor etching process 141, isolation trenches 1802a and 1802b (collectively referred to as isolation trenches 1802) are formed and extend into portions of the substrate 101 in which the fin structures 102b and 102c are formed. Figure 17A Impurities of a group III element (e.g., boron) form thin doped regions in the surface (e.g., sidewalls) of the isolation trench 1802, the doped regions comprising a doped first semiconductor layer 106' and a doped dielectric spacer 144'. In some embodiments, the thin doped regions (i.e., the protective barrier 1808) may be amorphous. In various embodiments, a first semiconductor etching process 141 is performed such that first segments of the isolation trenches 1802a, 1802b form a straight and symmetrical sidewall profile relative to an imaginary line passing through the center of the respective isolation trenches 1802a, 1802b in the depth direction. In some embodiments, the isolation trenches 1802a, 1802b may have a first depth D1 defined by the distance between the topmost first semiconductor layer 106 and the bottom surface 1802bs1 of the isolation trench 1802b. The first depth D1 may be selected based on a desired level of the narrowest critical dimension (CD). In some embodiments, the bottom surface 1802bs1 of the isolation trenches 1802a, 1802b is at substantially the same height as the bottom of the epitaxial S / D feature 146. In some embodiments, the bottom surface 1802bs1 of the isolation trenches 1802a, 1802b is lower than the top surface of the well portion of the substrate 101. In some embodiments, the first depth D1 is substantially equal to the height of the epitaxial S / D feature.

[0057] Figure 17A-1An enlarged view of a portion of a semiconductor device structure 100 is shown, illustrating a protective barrier 1808 in the sidewall of an isolation trench 1802. In cases where the dopant gas contains a Group III dopant (e.g., boron), a portion of the doped first semiconductor layer 106' may have a first boron concentration, and a portion of the doped dielectric spacer 144' may have a second boron concentration lower than the first boron concentration. The gate spacer 138 may have a third boron concentration lower than the second boron concentration. In some cases, the third boron concentration is almost zero. This is because the dopant gas (e.g., BCl3) can react with oxides (e.g., gate spacer 138) to form volatile byproducts (e.g., boron oxychloride), resulting in a low or essentially zero boron concentration in the gate spacer 38. The boron concentration may gradually decrease in the protective barrier 1808 in a direction away from the surface of the isolation trench 1802. In some embodiments, the boron dopant may travel a first distance in the first semiconductor layer 106, and the boron dopant may travel a second distance in the dielectric spacer 144 that is shorter than the first distance. In any case, the boron dopant may not penetrate the interface 133 defined by the first semiconductor layer 106 and the S / D feature 146. It should be noted that this doping phenomenon also applies to other Group III dopants.

[0058] exist Figure 18A and Figure 18B In this process, a second semiconductor etching process 147 is performed to further remove the exposed insulating material 118 and the substrate portions forming the fin structures 102b, 102c. Similarly, the second semiconductor etching process 147 is performed such that the second sections of the isolation trenches 1802a, 1802b form a straight and symmetrical sidewall profile relative to an imaginary line passing through the center of the respective isolation trenches 1802a, 1802b in the depth direction. The isolation trench 1802 has a uniform CD formed along its depth direction. Specifically, the second semiconductor etching process 147 is performed such that the bottom of the isolation trench 1802 (or in other words, the top surface 101ts of the exposed substrate 101) is below the interface 135 defined by the substrate 101 and the insulating material 118.

[0059] The second semiconductor etching process 147 is performed using etching chemicals similar to those used in the first semiconductor etching process 141. In some embodiments, the aforementioned processing is not performed during the second semiconductor etching process 147. In some embodiments, the processing is performed simultaneously with or intermittently with the second semiconductor etching process 147 in a manner similar to that described above. The substrate portions of the fin structures 101b, 102c can be removed by the second semiconductor etching process 147 using a plasma etching process comprising HBr and / or Cl2. In some embodiments, O2 and / or CO2 can be added to the HBr and / or Cl2-based plasma to promote the dissociation of plasma byproducts. In some embodiments, the plasma etching process can be a high-density plasma process using process conditions similar to those used in the first semiconductor etching process 141. The second semiconductor etching process 147 is performed to extend the isolation trenches 1802a, 1802b to a height substantially equal to the interface 135 defined by the substrate 101 and the insulating material 118. Isolation trenches 1802a and 1802b have a second depth D2 measured from the topmost first semiconductor layer 106 to the bottom surface 1802bs2 of the isolation trench 1802b. In other words, the depth of each isolation trench 1802a and 1802b extends from a first depth D1 to a second depth D2. Isolation trenches 1802 with a uniform CD along the depth direction can be obtained through a cyclic process. For example, Figure 17A and Figures 17B to 18A and Figure 18B The process can be repeated until the isolation trenches 1802a and 1802b reach the predetermined height (or depth).

[0060] One or more etching conditions can be controlled to achieve low-selectivity etching between silicon (e.g., substrate 101) and silicon oxide (e.g., insulating material 118). For example, during the second semiconductor etching process 147, low-voltage processes (e.g., chamber pressure below about 50 mTorr) and / or high bias power of the substrate pedestal (e.g., greater than 300 V) can be used to compensate for the etch selectivity required to remove the substrate portions of the insulating material 118 and fin structures 102b, 102c. In some embodiments, the bias power used during the second semiconductor etching process 147 is greater than the bias power of the first semiconductor etching process 141.

[0061] In some embodiments, a low etch selectivity for the second semiconductor etching process 147 can be achieved or enhanced using an etchant (e.g., Cl2 or BCl3) that removes both the target material (e.g., silicon) and the non-target material (e.g., silicon oxide). In some embodiments, the mixing ratio between the gases used in the second semiconductor etching process 147 is adjusted to achieve low etch selectivity. For example, in embodiments using BCl3 as an etchant, increasing the volume percentage of BCl3 in the etchant can reduce etch selectivity. In some embodiments, the etchant can be a mixture of HBr, BCl3, Cl2, and O2, wherein the percentage (e.g., volume percentage) of HBr in the etchant is between 0% and about 80%, the percentage of BCl3 in the etchant is between about 5% and about 80%, the percentage of Cl2 in the etchant is between 0% and about 80%, and the percentage of O2 in the etchant is between 0% and about 50%.

[0062] The low etch selectivity of the second semiconductor etching process 147 ensures that the isolation trench 1802 has an inner liner sidewall profile and that there is no "bend" in the isolation trench 1802. Bends may occur when the width of a segment of the isolation trench is greater than the width of an adjacent segment of the isolation trench.

[0063] In any case, the bottom surface 1802bs2 of the isolation trenches 1802a, 1802b can be located at a height within the accumulation region of the substrate 101. The term "accumulation region" refers to a non-conductive region in the substrate 101 located below the depletion region (a conductive region located at / near the well region of the substrate 101). The second depth D2 is sufficient to block leakage current paths through the epitaxial source / drain features and the silicon substrate. In some embodiments, the second depth D2 can be in the range of about 60 nm and about 200 nm.

[0064] In some embodiments, a second semiconductor etching process 147 is performed such that the bottom surface of the isolation trench 1802 is located below the height of the interface 135 defined by the substrate 101 and the insulating material 118. For example, the bottom surface may be located at the height of the well region of the substrate 101. During the second semiconductor etching process 147, without the use of any processing steps, a portion of the fin structures exposed through the isolation trench 1802 and the insulating material 118 surrounding the fin structures is removed, leaving most of the insulating material 118 between two adjacent fin structures substantially intact. In this case, the top of the insulating material 118 between two adjacent isolation trenches 1802 is slightly below the interface 131 defined by the insulating material 118 and the sacrificial gate electrode layer 134 (or the sacrificial gate dielectric layer 132), but above the midpoint of the height of the insulating material 118. Figure 18B As shown, the top of the insulating material 118 is above the center line "C", which extends laterally through the midpoint of the height of the insulating material 118.

[0065] When the process is performed simultaneously or intermittently with the second semiconductor etching process 147, a portion of the fin structure exposed by the isolation trench 1802 and the insulating material 118 surrounding the fin structure is significantly removed, resulting in the top of the insulating material 118 between two adjacent fin structures being lower than the midpoint of the height of the insulating material 118, as... Figure 18B-1 As shown. In some cases, the top of the insulating material 118 is below the centerline "C", which extends laterally through the midpoint of the height of the insulating material 118, and the remaining top of the insulating material 118 may have a tapered profile, as shown. Figure 18B-2 As shown.

[0066] exist Figure 19A and Figure 19B In the middle, isolation trench 1802 ( Figure 18A and Figure 18B The dielectric material 2130 is filled in. In some embodiments, a dielectric liner 2132 may be disposed between the dielectric material 2130 and the exposed surface of the isolation trench 1802. The dielectric material 2130 and the dielectric liner 2132 filled in the isolation trench 1802 form an isolation trench structure (so-called CPODE trench) 2134. A protective barrier 1808 is disposed between and in contact with the isolation trench structure 2134 and the S / D feature 146. The dielectric material 2130 and the dielectric liner 2132 may be made of oxygen-containing materials, such as silicon oxide (SiO2); nitrogen-containing materials, such as silicon nitride, silicon oxynitride (SiON), SiOCN, SiCN; low-k dielectric materials; or any suitable dielectric material. The dielectric material 2130 may include a chemically different material from the dielectric liner 2132 and may be formed by any suitable process, such as CVD, PECVD, FCVD, or ALD processes.

[0067] exist Figure 20A and Figure 20B Once the isolation trench 1802 is filled, a planarization process, such as a CMP process, can be performed. The planarization process can be performed until a portion of the cap layer 139 or ILD layer 164 is exposed.

[0068] exist Figure 21A and Figure 21BIn this process, the sacrificial gate structure 130, the sacrificial gate dielectric layer 132, and the second semiconductor layer 108 are removed. Exposed dielectric liner 2132 on the sidewalls of the dielectric material 2130 may also be removed. Removal of the sacrificial gate structure 130 and the semiconductor layer 108 forms an opening 166 between the first semiconductor layer 106. A cap layer 139, CESL 162, the first ILD layer 164, and a protective barrier 1808 protect the S / D feature 146 during the removal process. The sacrificial gate structure 130 can be removed using plasma dry etching and / or wet etching. In some embodiments, a wet etchant such as tetramethylammonium hydroxide (TMAH) solution can be used to selectively remove the sacrificial gate electrode layer 134 and the sacrificial gate dielectric layer 132, but not the gate spacer 138, the isolation trench structure 2134, the first ILD layer 164, and the CESL 162. After the sacrificial gate structure 130 is removed, the first semiconductor layer 106 and the dielectric spacer 144 are exposed to the opening 166.

[0069] exist Figure 22A and Figure 22B In this process, a replacement gate structure 190 is formed. The replacement gate structure 190 may each include a gate dielectric layer 180 and a gate electrode layer 182. In some embodiments, an interface layer (IL) 178 may be formed between the gate dielectric layer 180 and the first semiconductor layer 106. The IL 178 may also be formed on the exposed surfaces of the substrate 101, the insulating material 118, and the dielectric layer 2132. The IL 178 may include or be made of oxides (e.g., silicon oxide), nitrides (e.g., silicon nitride, silicon oxynitride, oxide oxynitride, etc.) and / or dielectric layers (e.g., hafnium silicate) formed by thermal or chemical oxidation of the first semiconductor layer 106. Next, the gate dielectric layer 180 is formed on the exposed surfaces of the semiconductor device structure 100 (e.g., on the IL (if present), the sidewalls of the gate spacer 138, the top surface of the first ILD layer 164, the CESL 162, and the cap layer 139). The gate dielectric layer 180 may be formed of a material chemically different from the sacrificial gate dielectric layer 132. The gate dielectric layer 180 may include or be made of a high-k dielectric material. The gate dielectric layer 180 may be a conformal layer formed by a conformal process, such as ALD, PECVD, molecular beam deposition (MBD), or a combination thereof.

[0070] After forming the IL (if any) and the gate dielectric layer 180, a gate electrode layer 182 is formed on the gate dielectric layer 180. The gate electrode layer 182 fills the opening 166 ( Figure 21AThe gate electrode layer 182 comprises one or more layers of conductive material, such as polysilicon, aluminum, copper, titanium, tantalum, tungsten, cobalt, molybdenum, tantalum nitride, nickel silicide, cobalt silicide, TiN, WN, WCN, TiAl, TiTaN, TiAlN, TaN, TaCN, TaC, TaSiN, metal alloys, other suitable materials, and / or combinations thereof. The gate electrode layer 182 may be formed by PVD, CVD, ALD, electroplating, or other suitable methods. In some embodiments, one or more optional conformal layers (not shown) may be conformally (or sequentially if more than one) deposited between the gate dielectric layer 180 and the gate electrode layer 182. The one or more optional conformal layers may include one or more barrier layers and / or cap layers and one or more work function tuning layers. One or more barrier layers and / or cap layers may include or be made of the following materials: tantalum and / or titanium nitrides, silicon nitrides, carbonitrides and / or aluminum nitrides; tungsten nitrides, carbonitrides and / or carbides; the like; or combinations thereof. One or more work function tuning layers may include or be made of the following materials: titanium and / or tantalum nitrides, silicon nitrides, carbonitrides, aluminum nitrides, aluminum oxides and / or aluminum carbides; tungsten nitrides, carbonitrides and / or carbides; cobalt; platinum; the like; or combinations thereof.

[0071] The portions of the gate electrode layer 182, one or more optional conformal layers (if any), and the gate dielectric layer 180 above the top surfaces of the first ILD layer 164, CESL 162, cap layer 139 (if any), and gate spacer 138 can be removed by a planarization process (e.g., CMP process). After the CMP process, the top surfaces of the isolation trench structure 2134, the first ILD layer 164, CESL 162, gate spacer 138, and gate electrode layer 182 are substantially coplanar.

[0072] exist Figure 23A and Figure 23BIn this process, the gate electrode layer 182 may optionally undergo one or more metal gate etch-back (MGEB) processes. The MGEB process is performed such that the top surfaces of the gate electrode layer 182 and the gate dielectric layer 180 are recessed to a level below the top surface of the gate spacer 138. In some embodiments, the gate spacer 138 is also recessed to a level below the top surface of the ILD layer 164. A self-aligned contact layer 192 is formed over the gate electrode layer 182. The self-aligned contact layer 192 may be a dielectric material (e.g., SiN) with etch selectivity relative to the ILD layer 164. The self-aligned contact layer 192 protects the gate electrode layer 182 during contact opening formation. A silicide layer 184 is then formed on the epitaxial source / drain feature 146, and S / D contacts 186 are formed in the contact openings on the silicide layer 84. Contacts 186 may include conductive materials such as Ru, Mo, Co, Ni, W, Ti, Ta, Cu, Al, TiN, or TaN. Although not shown, a barrier layer (e.g., TiN, TaN, etc.) may be formed on the sidewalls of the contact opening before the S / D contact 186 is formed. Then, a planarization process such as CMP is performed to remove excess deposits of contact material and expose the top surface of the gate electrode layer 182.

[0073] Figure 24 , Figure 25 , Figure 26 , Figure 27 and Figure 28 It shows that it can be used to replace Figures 7A-7C to Figures 8A-8C The illustrated embodiment uses a sacrificial dielectric layer. Figure 24 In this process, the second semiconductor layer 108 is removed. The removal of the second semiconductor layer 108 forms an opening 137. The second semiconductor layer 108 can be removed by a selective etching process, such as a selective dry etching process, a selective wet etching process, or a combination thereof. The selective etching process substantially does not affect the gate spacer 138, the first semiconductor layer 106, the sacrificial gate electrode layer 130, and the substrate 101. In some embodiments, the selective etching process is a selective wet etching process. When the second semiconductor layer 108 is made of SiGe and the first semiconductor layer 106 is made of silicon, the second semiconductor layer 108 can be selectively etched using an etchant, such as, but not limited to, ammonium hydroxide (NH4OH), tetramethylammonium hydroxide (TMAH), ethylenediamine catechol (EDP), or potassium hydroxide (KOH) solution.

[0074] exist Figure 25In this process, a sacrificial dielectric material 142 is formed in the opening 137 and on the exposed surface of the semiconductor device structure 100. In some embodiments, the sacrificial dielectric material 142 is an oxide formed by a flowable chemical vapor deposition (FCVD) process. In some embodiments, the oxide is carbon-containing silicon oxide. The use of the sacrificial dielectric material 142 helps to maintain the surface profile of the first semiconductor layer 106 during subsequent wafer (or channel) formation stages. In the conventional case where the second semiconductor layer 108 comprises Ge and the first semiconductor layer 106 comprises silicon, Ge in the second semiconductor layer 108 can diffuse into Si and react with Si to form SiGe due to the high temperatures used during the formation of subsequent epitaxial S / D features 146. When the second semiconductor layer 108 is selectively removed during the wafer formation stage, the surface portion of the first semiconductor layer 106 (which is now SiGe due to the previous reaction with Ge) is also removed. Therefore, the removal of the second semiconductor layer 108 causes additional silicon loss in the surface portion of the first semiconductor layer 106, resulting in a reduction in the thickness of the first semiconductor layer 108 and / or pitting damage. When the thickness of the silicon nanosheet channel layer (i.e., the first semiconductor layer 106) is affected, the channel resistance (Rch) of the nanosheet channel layer may increase, and its ability to conduct current (e.g., DC) may decrease. By replacing the second semiconductor layer 108 with a sacrificial dielectric layer 142 prior to the formation of the epitaxial S / D feature 146, the reaction between the first semiconductor layer 106 and the sacrificial dielectric layer 142 is minimized during the subsequent formation of the S / D feature 46, and the sacrificial dielectric layer 142 can be removed over the first semiconductor layer 104 with enhanced etch selectivity. Since the surface profile of the first semiconductor layer 106 remains substantially intact during the wafer formation stage, the channel resistance of the nanosheet channel layer does not increase, thus avoiding the problems discussed herein.

[0075] The concept of sacrificial dielectric layer 142 is applicable to the various embodiments shown in this disclosure.

[0076] exist Figure 26 In the process, an etch-back process is performed to remove the portion of the sacrificial dielectric layer 142 other than the portion of the sacrificial dielectric layer 142 formed in the opening 137. Figure 24 In some embodiments, the etch-back process is an anisotropic etching process. The etch-back process can be a selective etching process that removes the sacrificial dielectric layer 142 but substantially does not affect the sacrificial gate structure 130, gate spacer 138, first semiconductor layer 106, and substrate 101. The selective etching process is performed until the edge portions of each sacrificial dielectric layer 142 between the first semiconductor layers 106 are removed. Therefore, after the etch-back process, the majority of the sacrificial dielectric layer 142 between the first semiconductor layers 106 remains intact.

[0077] exist Figure 27 In this process, after removing the edge portions of the sacrificial dielectric material 142, a dielectric layer 144a is deposited in the cavity formed by removing the edges of the sacrificial dielectric layer 142. The dielectric layer 144a in the cavity forms a dielectric spacer 144, such as... Figure 28 As shown. The dielectric layer 144a can be made of a dielectric material, such as SiO2, Si3N4, SiC, SiCP, SiON, SiOC, SiCN, SiOCN and / or other suitable materials. The dielectric layer 144a can be deposited as a conformal dielectric layer using a conformal deposition process such as ALD.

[0078] exist Figure 28 In this process, anisotropic etching is performed to remove portions of the conformal dielectric layer 144a other than the dielectric layer 1441 formed in the cavity. The dielectric layer 144a in the cavity forms dielectric spacers 144 and is protected by a first semiconductor layer 106 during the anisotropic etching process. A sacrificial dielectric layer 142 is covered between the dielectric spacers 144 along the X direction. In some embodiments, the dielectric spacers 144 and the sacrificial dielectric material 142 comprise different materials with different etching selectivity.

[0079] After forming the dielectric spacer 144, the S / D feature 146, CESL 162, and cap layer 139 are formed, as described above. Figures 9A-9C to Figures 10A-10C As mentioned above. Figure 12A-12B to Figures 14A-14B The aforementioned process involves forming a mask structure (e.g., mask structure 1302) on top of the semiconductor device structure 100. Similarly, the mask structure is patterned to form a patterned mask layer 1304' of the exposed sacrificial gate structure 130. The exposed sacrificial gate structure (e.g., sacrificial gate electrode layer 134 and sacrificial gate dielectric layer 132) is selectively removed to form trench openings 1602a, 1602b (collectively referred to as trench opening 1602). Trench opening 1602 exposes the gate spacer 138 and the first semiconductor layer 106, as described above. Figure 29A and Figure 29B As shown. The sacrificial gate structure can be removed using chlorine-containing gases (e.g., SiCl4, BCl3, Cl2, CHCl3, CCl4 and / or BCl3), bromine-containing gases (e.g., HBr and / or CHBr3), iodine-containing gases, other suitable gases and / or plasma and / or combinations thereof.

[0080] exist Figure 30A and Figure 30BIn the process, the exposed sacrificial dielectric layer 142 is removed. The removal of the sacrificial dielectric layer 142 forms an opening 165 between the first semiconductor layers 106. The sacrificial dielectric layer 142 can be removed using any suitable etching process. The etchant used in the etching process is selected to selectively remove the sacrificial dielectric layer 142 without affecting the gate spacer 138 and the dielectric spacer 144. After the removal of the sacrificial gate structure 130, the first semiconductor layers 106 and the dielectric spacer 144 are exposed to the trench opening 165. The sacrificial dielectric layer 142 disposed between the first semiconductor layers 106 helps maintain the integrity and surface contour of the first semiconductor layers 108 during the removal process.

[0081] exist Figure 31A and Figure 31B In the process of removing the sacrificial dielectric layer 142, the semiconductor device structure 100 undergoes a pretreatment process 149. The pretreatment process 149 can be any suitable doping process configured to dope impurities (e.g., group III elements such as boron, aluminum, gallium, etc.) into the exposed surfaces (e.g., sidewalls) of the first semiconductor layer 106 and the trench opening 1602. Similarly, the doped regions form protective barriers 3108 in the exposed surfaces of the first semiconductor layer 106 and the sidewalls of the trench opening 1602. The doping of impurities enhances the etch resistance of the S / D feature 146 during subsequent etching processes, enabling a damage-free, simple epitaxial structure of the S / D feature 146 even if photolithographic mask overlay occurs.

[0082] The pretreatment process 149 may be the processing process discussed in the first semiconductor etching process 141 described above. In some embodiments, the pretreatment process 149 is performed simultaneously or intermittently with the etching process for removing the sacrificial dielectric layer 142. When the pretreatment process 149 is performed simultaneously with the etching process, the dopant gas may flow simultaneously with the etchant. When the pretreatment process 149 is performed intermittently with the etching process, the dopant gas and etchant may be supplied sequentially in a cyclic manner until the sacrificial dielectric layer 142 moves and the dopant is doped in the target region. In either case, the temperature of the pretreatment process 149 is controlled such that the P-type dopant is not activated. In any case, the P-type dopant in the doped region (e.g., the doped first semiconductor layer 106' and the doped dielectric spacer 144') forms a protective barrier 3108 for the trench opening 1602. During subsequent etching processes, the S / D feature 146 may be protected by the protective barrier 3108. When the doping gas contains a Group III dopant (e.g., boron), the doped first semiconductor layer 106' may have a first boron concentration, and the doped dielectric spacer 144 may have a second boron concentration lower than the first boron concentration. The gate spacer 138 may have a third boron concentration lower than the second boron concentration. In some cases, the third boron concentration is almost zero.

[0083] An exemplary pretreatment process 149 may include exposing a semiconductor device structure 100 to a plasma doping chamber containing plasma generated by one or more dopant gases (e.g., boron-containing gases, such as B₂H₆ or BCl₃) and a dilution gas. The plasma doping process may be performed at a constant energy between about 2 keV and about 5 keV, a bias voltage between about -200V and about -20kV, and a chamber pressure between about 1 mTorr and about 50 mTorr to dope plasma ions (e.g., boron) into the surface (e.g., sidewalls) of the trench opening 1602. After the plasma doping process, the doped region (e.g., a protective barrier 3108) may have a density of about 1.0E¹⁵ atoms / cm². 3 Approximately 3.0E22 atoms / cm 3 The boron dopant concentration is within a certain range. Plasma doping can form a doped profile abrupt junction at a depth of about 5 nm to about 10 nm from the surface of the trench opening 1602, with a doping profile abruptness of about 1 nm / decade.

[0084] exist Figure 32A and Figure 32B In this process, a semiconductor etching process 151 is performed to remove the exposed doped first semiconductor layer 106', the exposed insulating material 118, and the substrate portion forming the fin structure. The semiconductor etching process 151 can be related to the above-mentioned... Figures 18A-18BThe second semiconductor etching process 147 discussed is the same as or similar to that discussed. Similarly, semiconductor etching process 151 is performed such that the trench opening 1602 extends with a straight and symmetrical sidewall profile relative to an imaginary line passing through the center of the corresponding trench opening 1602 in the depth direction of the trench opening 1602. In some embodiments, the pretreatment process 149 described above is not performed during semiconductor etching process 151. In some embodiments, pretreatment process 149 is performed simultaneously with or intermittently with semiconductor etching process 151 in a manner similar to that described above. The substrate portion of the fin structure can be removed by semiconductor etching process 151 using a plasma etching process comprising HBr and / or Cl2. In some embodiments, O2 and / or CO2 can be added to the HBr and / or Cl2-based plasma to promote the dissociation of plasma byproducts. In some embodiments, the plasma etching process can be a high-density plasma process using process conditions similar to those of the second semiconductor etching process 147. Semiconductor etching process 151 is performed to extend the trench opening 1602 to a height below the interface 135 defined by the substrate 101 and the insulating material 118.

[0085] One or more etching conditions can be controlled to achieve low-selectivity etching between silicon (e.g., substrate 101) and silicon oxide (e.g., insulating material 118). For example, during semiconductor etching process 151, low-voltage processes (e.g., chamber pressure below about 50 mTorr) and / or high bias power of the substrate pedestal (e.g., greater than 300 V) can be used to compensate for the etch selectivity required to remove the substrate portion of the insulating material 118 and the fin structure. In some embodiments, boron trichloride (BCl3) or the like can be used to improve the etch selectivity of silicon oxide, achieving low-selectivity etching between silicon and silicon oxide. In some embodiments, the bottom surface of the trench opening 1602 can be at the height of the well region or accumulation region of the substrate 101.

[0086] Without using pretreatment process 149 during semiconductor etching process 151, a portion of the fin structure exposed through trench opening 1602 and the insulating material 118 surrounding the fin structure is removed, leaving most of the insulating material 118 between two adjacent fin structures essentially intact. In this case, the top of the insulating material 118 between two adjacent isolation trenches 1802 is slightly below the interface 131 defined by the insulating material 118 and the sacrificial gate electrode layer 134 (or sacrificial gate dielectric layer 132), but above the midpoint of the height of the insulating material 118, such as... Figure 32B As shown.

[0087] When pretreatment process 149 and semiconductor etching process 151 are performed simultaneously or intermittently, a portion of the fin structure exposed through trench opening 1602 and the insulating material 118 surrounding the fin structure is significantly removed, resulting in the top of the insulating material 18 between two adjacent fin structures being lower than the midpoint of the height of the insulating material 118, as... Figure 18B-1 As shown. In some cases, the top of the insulating material 118 is below the centerline "C", which extends laterally through the midpoint of the height of the insulating material 118, and the remaining top of the insulating material 118 may have a tapered profile, as shown. Figure 18B-2 As shown.

[0088] exist Figure 33A and Figure 33B In the trench, the opening 1602 is filled with a dielectric liner 2132a and a dielectric material 2130 to form an isolation trench structure (i.e., a CPODE trench) 2134, in a manner similar to that described above. Figures 19A-19B and Figures 20A-20B The discussion is similar. In Figure 34A and Figure 34B In the middle, in relation to the above about Figure 21A and 21B A similar approach is discussed to remove the sacrificial gate structure and sacrificial dielectric layer 142. In Figure 35A and Figure 35B In the middle, in relation to the above about Figure 22A and Figure 22B A similar approach is used to form the replacement gate structure (IL 178, gate dielectric layer 180, and gate electrode layer 182). Figure 36A and Figure 36B In the middle, the silicide layer 184 and the S / D contact 186 are in accordance with the above regarding Figure 23A and 23B Similar approaches to the discussion were formed.

[0089] Although Figure 1-36B The various embodiments described herein are for the pre-CPODE process, i.e., the front-end process (FEOL) process before metal gate formation, but these embodiments are equally applicable to the post-CPODE process (or so-called CMODE process), i.e., the middle-end process (MEOL) process after metal gate formation. Figure 37 This is a top view of a semiconductor device structure 200 according to some embodiments. The semiconductor device structure 200 is similar to the semiconductor device structure 100, and for clarity, Figure 37 Some components of the semiconductor device structure, such as the ILD layer 164, gate dielectric layer 180, and CESL 162, are omitted. Furthermore, the positions of the S / D region 146 and the isolation region 120 (i.e., insulating material 118) are for illustrative purposes only and are not precise. Figure 37As shown, the semiconductor device structure 200 includes an S / D region 146 formed on the opposite side of the gate electrode layer 182. Each gate electrode layer 182 has a longitudinal axis along the Y direction, while each fin structure 112 has a longitudinal axis along the X direction.

[0090] Figure 38A-46A According to some embodiments Figure 37 The line DD is a cross-sectional side view of various stages of manufacturing the semiconductor device structure 200. The line DD passes through the fin structure (e.g., fin structure 112) along the X direction. Figure 38B-46B According to some embodiments Figure 37 The line EE is a cross-sectional side view of various stages of manufacturing the semiconductor device structure 200. The line EE passes through the fin structure (e.g., fin structure 112) along the Y direction. Figure 38C-46C According to some embodiments Figure 37 The image shows a cross-sectional side view of various stages of the fabrication of the semiconductor device structure 200, taken by line FF. Line FF passes through the STI region (e.g., isolation region 120) along the X direction. Figures 38A-38C As shown, a mask layer 183 is formed on the top surface of the gate dielectric layer 180, the gate spacer 138, the gate electrode layer 182, the CESL 162, and the ILD layer 164. The mask layer 183 may include a dielectric layer such as SiN or a semiconductor material such as amorphous silicon.

[0091] exist Figures 39A-39C In this embodiment, a mask structure 152 is formed on a mask layer 183. In some embodiments, the mask structure 152 is a three-layer photoresist. For example, the mask structure 152 may include a base layer 154 and an intermediate layer 156 disposed on the base layer 154. The base layer 154 and the intermediate layer 156 are made of different materials such that the optical properties and / or etch properties of the base layer 154 and the intermediate layer 156 are different from each other. In some embodiments, the base layer 154 may be a carbon layer, and the intermediate layer 156 may be a silicon-rich layer designed to provide etch selectivity between the intermediate layer 156 and the base layer 154. The mask structure 152 also includes a photoresist layer 158, which may be a chemically amplified photoresist layer and may be a positive or negative photoresist. The photoresist layer 158 may include a polymer. The photoresist layer 158 is patterned to form openings 159 therein. The opening 159 is arranged to align with one or more gate electrode layers 182. In some embodiments, the opening 159 may extend along the X direction through at least three gate electrode layers 182.

[0092] exist Figure 40A-40CIn this configuration, opening 159 extends into the intermediate layer 156, the bottom layer 154, and the mask layer 180. After opening 159 extends into the mask layer 180, the mask structure 152 can be removed. Portions of the gate electrode layer 182 and the gate dielectric layer 180 are exposed in opening 159. Next, as... Figure 40B and Figure 40C As shown, by removing exposed portions of the gate electrode layer 182, the gate dielectric layer 180, and the insulating material 118, an opening 159 extends through the gate electrode layer 182 and the gate dielectric layer 180 and into the insulating material 118. The opening 159 can be formed by one or more etching processes. The opening 159 extends to a certain thickness within the insulating material 118, such that a thin layer of the insulating material 118 remains on the exposed surface of the substrate 101. Figure 40C As shown, in some embodiments, the gate spacer 138 is protected by a mask layer 183 and is not removed during the removal of portions of the gate electrode layer 182 and the gate dielectric layer 180.

[0093] exist Figures 41A-41C In this embodiment, dielectric material 185 is deposited in opening 159. The dielectric material 185 within opening 159 forms a cleaved metal gate (CMG) structure 185'. The CMG structure 185' divides the gate electrode layer 182 into two or more portions, and these two or more portions can be independently controlled. The dielectric material 185 may be a low etch resistivity material. In some embodiments, the dielectric material 185 is: a nitrogen-containing material, such as silicon nitride, silicon oxynitride (SiON), SiOCN, SiCN; an oxygen-containing material, such as silicon oxide (SiO2); a low-k dielectric material; or any suitable dielectric material. In one exemplary embodiment, the dielectric material 185 is a nitride. The dielectric material 185 can be formed by any suitable process, such as CVD, PECVD, FCVD, or ALD processes.

[0094] exist Figures 42A-42C In this process, a mask structure 152a, such as mask structure 150, is formed on dielectric material 185. Similarly, mask structure 152a is a three-layer photoresist, including a bottom layer 154, an intermediate layer 156 disposed on the bottom layer 154, and a photoresist layer 158. Photoresist layer 158 is patterned to form openings 160 therein. The patterned photoresist layer 158 is used as a mask during subsequent processes (e.g., one or more photolithography processes) to transfer the pattern (i.e., openings 160) in photoresist layer 158 into the intermediate layer 156, bottom layer 154, dielectric material 184, and mask layer 183.

[0095] In various embodiments, the opening 160 is arranged to extend through a portion of the CMG structure 185'. The opening 160 defines an isolation region to be formed in the substrate portion of the fin structure 112. The isolation region may be positioned between adjacent active regions. The term "active region" refers to the region where a transistor is formed. As will be discussed in more detail below, the isolation region can be formed by performing a fin-cutting (or slicing) process and filling the fin-cutting (or slicing) region with a dielectric. This fin-cutting (or slicing) process may be referred to as a continuous metal on diffusion edge (CMODE) process. The term "diffusion edge" is equivalently referred to as an active edge, which is the edge adjacent to an adjacent active region. The CMODE process can be used to reduce the gate pitch, thereby increasing the density of multi-gate devices and thus improving the device performance required for large-scale circuits and devices. In any case, the pattern in the photoresist layer 158 (i.e., the opening 160) is arranged at locations where the CMG structure 185' and the portion replacing the gate structure will be exposed at a later stage.

[0096] exist Figures 43A-43C In this process, the pattern (i.e., opening 160) in the photoresist layer 158 is transferred to the mask layer 183 to form a patterned mask layer, and the bottom layer 154, the intermediate layer 156, and the photoresist layer 158 are removed. The formation of the patterned mask layer 183 can be achieved through one or more photolithography processes. As a result of one or more photolithography processes, opening 160 is formed in the CMG structure 185' and the patterned mask layer 158, exposing a portion of the gate electrode layer 182. In some embodiments, opening 160 exposes a portion of the gate electrode layer 182, and the exposed portion of the gate electrode layer 182 extends through a plurality of fin structures 112. In some embodiments, the exposed portion of the gate electrode layer 182 extends over two fin structures 112, such as... Figure 43B As shown.

[0097] Once the gate electrode layer 182 is exposed, one or more photolithography processes can be stopped. As shown, opening 160 exposes portions of the CMG structure 185' and multiple gate electrode layers 182 along the Y direction. The patterned mask layer 183 can then be used to protect the active regions during subsequent fin cutting (or slicing) processes.

[0098] exist Figures 44A-44C In this process, a patterned mask layer 183 is used as a mask, and an etching process 177 removes exposed portions of the gate electrode layer 182, insulating material 118, CMG structure 185', and fin structure 112 (including the first semiconductor layer 106 and the gate dielectric layer 180 surrounding each first semiconductor layer). The etching process 177 may include a first semiconductor etching process 141, a processing process, and a second semiconductor etching process 147, and may be performed in accordance with the above description. Figures 17A-17B and Figures 18A-18B The process is performed in a similar manner. For example, a first semiconductor etching process, such as first semiconductor etching process 141, can be performed in etching process 177 to extend opening 160 through gate electrode layer 182 and first semiconductor layer 106, such that the bottom of opening 160 is at the same height as the bottom of S / D feature 146. A second semiconductor etching process, such as second semiconductor etching process 147, can be performed in etching process 177 to further extend opening 160 into substrate 101 to form isolation trenches 160ta, 160tb. Similarly, a processing step, such as pretreatment process 149, is performed in etching process 177 to dope impurities (e.g., P-type dopant) in the sidewalls of isolation trenches 160ta, 160tb. The processing step can be performed simultaneously with or intermittently with the first semiconductor etching process. The processing step can be performed together with the second semiconductor etching process or not at all. In either case, the doped regions (e.g., the first semiconductor layer 106 and the dielectric spacer 144) in the surface regions of the isolation trenches 160ta and 160tb serve as protective barriers 4408, which enhance the etch resistance of the S / D feature 146 during subsequent etching processes, enabling a damage-free and simple epitaxial structure of the S / D feature 46 even if photolithographic mask overlay shift occurs.

[0099] As a result of the fin cutting process, isolation trenches 160ta and 160tb (collectively referred to as isolation trench 160t) are formed and extended into the portion of substrate 101 that forms the fin structure 112. Isolation trench 160t will be filled with a dielectric material and form a CMODE structure. In any case, the depth of isolation trench 160t (and the subsequent CMODE structure) is sufficient to block leakage current that could otherwise flow through the epitaxial source / drain features, transistors, and silicon substrate. In some embodiments, the bottom of isolation trench 160t may be at the height of the accumulation region entering substrate 101.

[0100] exist Figure 45A-45CIn this process, a refilled dielectric material 168 is formed in an isolation trench 160t. In some embodiments, a dielectric liner (not shown) may be disposed between the dielectric material 168 and the exposed surface of the isolation trench 160t. The dielectric material 168 and the dielectric liner filling the isolation trench 160t form isolation trench structures 167ta and 167tb (collectively referred to as CMODE structure 167). The dielectric material 168 and the dielectric liner may be made of oxygen-containing materials, such as silicon oxide (SiO2); nitrogen-containing materials, such as silicon nitride, silicon oxynitride (SiON), SiOCN, SiCN; low-k dielectric materials; or any suitable dielectric material. The dielectric material 168 may include a chemically different material from the dielectric liner and may be formed by any suitable process, such as CVD, PECVD, FCVD, or ALD processes. The dielectric liner may be deposited by a conformal process such as ALD.

[0101] exist Figures 46A-46C Once the isolation trench 160t is filled, a planarization process, such as a CMP process, can be performed to remove portions of the dielectric material formed above the patterned mask layer 183. The planarization process can continue until a portion of the ILD layer 164 is exposed. In some embodiments, the isolation trench structure 167ta has a first dimension along the X direction, and the CMG structure 185' has a second dimension along the X-axis that is greater than the first dimension. The top surfaces of the isolation trench structures 167ta, 167tb, and the CMG structure 184' are substantially coplanar.

[0102] It should be understood that the aforementioned semiconductor device structures 100 and 200 may undergo further complementary metal-oxide-semiconductor (CMOS) and / or back-end processing (BEOL) processes to form various features, such as transistors, contacts / vias, interconnect metal layers, dielectric layers, passivation layers, etc. The semiconductor device structures 100 and 200 may also include back-side contacts (not shown) on the back side of the substrate 101, such that the source or drain of the epitaxial S / D feature 146 is connected to a back-side power rail (e.g., a positive voltage VDD or a negative voltage VSS) via the back-side contacts.

[0103] Embodiments of this disclosure provide an improved isolation trench structure (e.g., a CPODE / CMODE structure) having a boron-doped protective barrier disposed between the S / D feature and the isolation trench structure. The protective barrier enhances the etch resistance of the S / D feature during subsequent etching processes, enabling a damage-free, simple epitaxial structure of the S / D feature even in the event of photolithographic mask overlay misalignment. The isolation trench structure can extend into the well region of the substrate to block leakage current through the EPI transistor substrate EPI.

[0104] A semiconductor device structure is described. The structure includes a substrate; an insulating material disposed on the substrate; a first fin structure extending upward from the substrate through the insulating material; a second fin structure extending upward from the substrate through the insulating material; a source / drain (S / D) feature disposed between the first fin structure and the second fin structure; and an isolation trench structure extending through the first fin structure and into the substrate, wherein the isolation trench structure has a doped sidewall region disposed between and in contact with the S / D feature and the isolation trench structure.

[0105] Another embodiment is a method for forming a semiconductor device structure. The method includes: forming a plurality of fin structures from a substrate, each fin structure including a plurality of alternately stacked semiconductor layers and a plurality of sacrificial layers; forming source / drain (S / D) features on opposite sides of the fin structures; forming an isolation trench between two adjacent S / D features by removing exposed portions of the semiconductor layers and sacrificial layers; doping the isolation trench to form doped regions in the sidewalls of the isolation trench; and filling the isolation trench with a dielectric material.

[0106] Another embodiment is a method for forming a semiconductor device structure. The method includes: forming a plurality of fin structures from a substrate, each fin structure including a plurality of alternately stacked semiconductor layers and a plurality of sacrificial layers; forming an insulating material on the substrate; forming a sacrificial gate structure on the insulating material and over a portion of the fin structure; forming source / drain (S / D) features on opposite sides of each fin structure; forming a first portion of an isolation trench by removing portions of the sacrificial gate structure and sacrificial layers to expose the plurality of semiconductor layers of a first fin structure; exposing the isolation trench to a preprocessing process; forming a second portion of the isolation trench by removing a portion of the substrate and the first fin structure; and filling the isolation trench with a dielectric material.

[0107] The foregoing outlines features of several embodiments to enable those skilled in the art to better understand aspects of this disclosure. Those skilled in the art will understand that they can readily use this disclosure as the basis for designing or modifying other processes and structures to achieve the same purposes and / or advantages of the embodiments described herein. Those skilled in the art will also recognize that such equivalent constructions do not depart from the spirit and scope of this disclosure, and that various changes, substitutions, and alterations can be made herein without departing from the spirit and scope of this disclosure.

[0108] Example 1 is a semiconductor device structure comprising: a substrate; an insulating material disposed on the substrate; a first fin structure extending upward from the substrate through the insulating material; a second fin structure extending upward from the substrate through the insulating material; a source / drain (S / D) feature disposed between the first fin structure and the second fin structure; and an isolation trench structure extending through the first fin structure and into the substrate, wherein the isolation trench structure has a doped sidewall region disposed between the S / D feature and the isolation trench structure and in contact with the S / D feature and the isolation trench structure.

[0109] Example 2 is the semiconductor device structure described in Example 1, wherein the doped sidewall region comprises a dopant from a group III element.

[0110] Example 3 is the semiconductor device structure described in Example 2, wherein the doped sidewall region has a first boron concentration.

[0111] Example 4 is the semiconductor device structure described in Example 3, further comprising: a dielectric spacer in the doped sidewall region, wherein the dielectric spacer has a second boron concentration less than the first boron concentration.

[0112] Example 5 is a semiconductor device structure as described in Example 1, wherein the doped sidewall region has a first bottom at a first height, and the S / D feature has a second bottom at a second height substantially the same as the first height.

[0113] Example 6 is a method for forming a semiconductor device structure, comprising: forming a plurality of fin structures from a substrate, each fin structure including a plurality of alternately stacked semiconductor layers and a plurality of sacrificial layers; forming source / drain (S / D) features on opposite sides of the fin structures; forming an isolation trench between two adjacent S / D features by removing exposed portions of the semiconductor layers and sacrificial layers; doping the isolation trench to form doped regions in the sidewalls of the isolation trench; and filling the isolation trench with a dielectric material.

[0114] Example 7 is the method described in Example 6, wherein the doping process is a plasma doping process or an implantation process.

[0115] Example 8 is the method described in Example 6, wherein the doped region comprises a Group III element.

[0116] Example 9 is the method described in Example 8, wherein the doping process is performed by exposing the isolation trench to plasma formed of the following materials: diborane (B2H6), boron trichloride (BCl3), borane (BH3), boron tribromide (BBr3), boron trifluoride (BF3), triethyl borate (TEB), borazine (B3N3H6), or alkyl-substituted derivatives of borazine, or combinations thereof.

[0117] Example 10 is the method of Example 6, wherein the exposed portions of the semiconductor layer and the sacrificial layer are removed by using a plasma etching process with an etchant containing halogen groups.

[0118] Example 11 is the method described in Example 6, wherein the sacrificial layer comprises silicon germanium.

[0119] Example 12 is the method described in Example 6, wherein the sacrificial layer comprises a dielectric.

[0120] Example 13 is a method for forming a semiconductor device structure, comprising: forming a plurality of fin structures from a substrate, each fin structure including a plurality of alternately stacked semiconductor layers and a plurality of sacrificial layers; forming an insulating material on the substrate; forming a sacrificial gate structure on the insulating material and over a portion of the fin structure; forming source / drain (S / D) features on opposite sides of each fin structure; forming a first portion of an isolation trench by removing portions of the sacrificial gate structure and the sacrificial layers to expose the plurality of semiconductor layers of a first fin structure; exposing the isolation trench to a preprocessing process; forming a second portion of the isolation trench by removing a portion of the substrate and the first fin structure; and filling the isolation trench with a dielectric material.

[0121] Example 14 is the method of Example 13, further comprising: removing the edges of each sacrificial layer to form a cavity before forming the S / D feature; and forming a dielectric layer in the cavity to form a dielectric spacer.

[0122] Example 15 is the method described in Example 14, wherein the pretreatment process is a doping process using a dopant gas including boron.

[0123] Example 16 is the method of Example 15, wherein the pretreatment process forms a doped region in the sidewall of a first portion of the isolation trench, and the doped region includes the semiconductor layer and the dielectric spacer.

[0124] Example 17 is the method of Example 16, wherein the semiconductor layer has a first boron concentration and the dielectric spacer has a second boron concentration less than the first boron concentration.

[0125] Example 18 is the method of Example 13, wherein the first and second portions of the isolation trench are formed by an etchant comprising a brominated etching chemical.

[0126] Example 19 is the method of Example 13, wherein the first portion of the isolation trench has a first bottom at a first height, and the S / D feature has a second bottom at a second height substantially the same as the first height.

[0127] Example 20 is the method of Example 13, further comprising: exposing the isolation trench to a dopant gas including boron while forming a second portion of the isolation trench.

Claims

1. A semiconductor device structure, comprising: Substrate; An insulating material is disposed on the substrate; A first fin structure extends upward from the substrate through the insulating material; A second fin structure extends upward from the substrate through the insulating material; A source / drain (S / D) feature is disposed between the first fin structure and the second fin structure; as well as An isolation trench structure extends through the first fin structure and into the substrate. The isolation trench structure has a doped sidewall region, which is disposed between the S / D feature and the isolation trench structure and is in contact with both the S / D feature and the isolation trench structure.

2. The semiconductor device structure according to claim 1, wherein, The doped sidewall regions include dopants from group III elements.

3. The semiconductor device structure according to claim 2, wherein, The doped sidewall region has a first boron concentration.

4. The semiconductor device structure according to claim 3, further comprising: A dielectric spacer in the doped sidewall region, wherein the dielectric spacer has a second boron concentration that is less than the first boron concentration.

5. The semiconductor device structure according to claim 1, wherein, The doped sidewall region has a first bottom at a first height, and the S / D feature has a second bottom at a second height that is substantially the same as the first height.

6. A method for forming a semiconductor device structure, comprising: Multiple fin structures are formed from a substrate, each fin structure comprising multiple semiconductor layers and multiple sacrificial layers stacked alternately; A source / drain (S / D) feature is formed on the opposite side of the fin structure; An isolation trench is formed between two adjacent S / D features by removing the exposed portions of the semiconductor layer and the sacrificial layer; The isolation trench is doped to form a doped region in the sidewall of the isolation trench; as well as The isolation trench is filled with a dielectric material.

7. The method according to claim 6, wherein, The doping process is a plasma doping process or an implantation process.

8. The method according to claim 6, wherein, The doped region includes group III elements.

9. The method according to claim 8, wherein, The doping process is performed by exposing the isolation trench to plasma formed from the following materials: diborane (B2H6), boron trichloride (BCl3), borane (BH3), boron tribromide (BBr3), boron trifluoride (BF3), triethyl borate (TEB), borazine (B3N3H6), or alkyl-substituted derivatives of borazine, or combinations thereof.

10. A method for forming a semiconductor device structure, comprising: Multiple fin structures are formed from a substrate, each fin structure comprising multiple semiconductor layers and multiple sacrificial layers stacked alternately; An insulating material is formed on the substrate; A sacrificial gate structure is formed on the insulating material and over a portion of the fin structure; Source / drain (S / D) features are formed on opposite sides of each fin structure; The first portion of the isolation trench is formed by removing portions of the sacrificial gate structure and the sacrificial layer to expose the plurality of semiconductor layers of the first fin structure; The isolation trench is exposed to the pretreatment process; The second portion of the isolation trench is formed by removing a portion of the substrate and the first fin structure; as well as The isolation trench is filled with a dielectric material.

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