Semiconductor device

Abstract

A semiconductor device includes: an insulating base layer; a fin-type pattern on the insulating base layer and extending in a first direction; a plurality of channel structures on the fin-type pattern and spaced apart from each other in a first direction, each of the plurality of channel structures including a plurality of channel layers spaced apart from each other in a second direction perpendicular to the first direction; a plurality of gate structures surrounding the plurality of channel structures, respectively, and extending in a third direction intersecting with the first direction; a source / drain pattern including a first source / drain pattern connected to a side surface of some of the plurality of channel structures; an internal spacer between the plurality of gate structures and the source / drain pattern; and a plurality of bottom isolation patterns under the plurality of gate structures, respectively, and between the insulating base layer and the fin-type pattern.

Description

[0001] This application is based on and claims priority to Korean Patent Application No. 10-2024-0074429, filed on June 7, 2024, in the Korean Intellectual Property Office, the disclosure of which is incorporated herein by reference in its entirety. TECHNICAL FIELD

[0002] The disclosed example embodiments relate to semiconductor devices. BACKGROUND

[0003] As the demand for high performance, high speed, and / or multi-functionality of semiconductor devices increases, the degree of integration of semiconductor devices has increased. In accordance with the trend of high integration of semiconductor devices, semiconductor devices having a backside power delivery network (BSPDN) structure in which a power rail, or referred to as a power track, is disposed on a backside of a wafer have been developed. Further, efforts have been made to develop semiconductor devices having a three-dimensional channel structure in order to overcome the limitation of operating characteristics due to the size reduction of such devices, such as a planar metal-oxide semiconductor (MOS) field effect transistor (FET) (MOSFET).

[0004] The information disclosed in this Background section of the detailed description is for the purpose of providing context for the present application and as such represents techniques and / or technical information that is known to the inventors or is developed by the inventors prior to or during the development of the present application. Accordingly, it will be understood that information disclosed in this Background section of the detailed description can include information that does not form part of the prior art to the public. SUMMARY

[0005] One or more example embodiments provide semiconductor devices having improved electrical characteristics and reliability.

[0006] Additional aspects will be set forth in part in the description which follows, and in part will be apparent from the description, or can be learned by practice of the presented embodiments.

[0007] According to an aspect of example embodiments, a semiconductor device can include: an insulating base layer; a fin-type pattern on the insulating base layer and extending in a first direction; a plurality of channel structures on the fin-type pattern and spaced apart from each other in the first direction, each of the plurality of channel structures including a plurality of channel layers spaced apart from each other in a second direction perpendicular to the first direction; a plurality of gate structures respectively on the plurality of channel structures and extending in a third direction intersecting the first direction; a source / drain pattern including a first source / drain pattern connected to side surfaces of some of the plurality of channel structures; an internal spacer between the plurality of gate structures and the source / drain pattern; a plurality of bottom isolation patterns respectively under the plurality of gate structures and between the insulating base layer and the fin-type pattern, the plurality of bottom isolation patterns being spaced apart from each other in the first direction and including a same material as a material of the internal spacer; and a lower contact structure penetrating the insulating base layer and connected to the first source / drain pattern, the lower contact structure passing between first bottom isolation patterns among the plurality of bottom isolation patterns adjacent to the first source / drain pattern.

[0008] According to an aspect of example embodiments, a semiconductor device can include: an insulating base layer; a fin-type structure on the insulating base layer and extending in a first direction; a plurality of channel structures on the fin-type structure and spaced apart from each other in the first direction, each of the plurality of channel structures including a plurality of channel layers spaced apart from each other in a second direction perpendicular to the first direction; a plurality of gate structures respectively on the plurality of channel structures and extending in a third direction intersecting the first direction; a source / drain pattern including a first source / drain pattern connected to side surfaces of some of the plurality of channel structures; an internal spacer between the plurality of gate structures and the source / drain pattern; and a lower contact structure penetrating the insulating base layer and connected to the first source / drain pattern, wherein the fin-type structure includes: first and second fin-type patterns on the insulating base layer; a plurality of first bottom isolation patterns respectively under the plurality of gate structures and spaced apart from each other in the first direction, the plurality of first bottom isolation patterns being between the insulating base layer and the first fin-type pattern; and a plurality of second bottom isolation patterns respectively under the plurality of gate structures and spaced apart from each other in the first direction, the plurality of second bottom isolation patterns being between the first and second fin-type patterns, wherein each of the plurality of first and second bottom isolation patterns includes a same material as a material of the internal spacer, and wherein the lower contact structure penetrates between third bottom isolation patterns among the plurality of first bottom isolation patterns adjacent to the first source / drain pattern and fourth bottom isolation patterns among the plurality of second bottom isolation patterns adjacent to the first source / drain pattern.

[0009] According to an aspect of example embodiments, a semiconductor device can include: an insulating base layer; a plurality of channel layers on the insulating base layer and spaced apart from each other; a gate structure surrounding the plurality of channel layers; a first source / drain pattern and a second source / drain pattern on the insulating base layer; an internal spacer in the gate structure and between the plurality of channel layers and the first source / drain pattern and the second source / drain pattern; a bottom isolation pattern on an upper surface of the insulating base layer and below the plurality of channel layers, the bottom isolation pattern including a same material as a material of the internal spacer; a first contact structure penetrating the insulating base layer, contacting a first side of the bottom isolation pattern, and connected to the first source / drain pattern; a second contact structure connected to the second source / drain pattern; and a bottom sacrificial pattern below the second source / drain pattern, at a same height as the bottom isolation pattern, and connected to a second side of the bottom isolation pattern. BRIEF DESCRIPTION OF DRAWINGS

[0010] The above and other aspects, features, and advantages of certain example embodiments of the present disclosure will be more apparent from the following description taken in conjunction with the accompanying drawings, in which:

[0011] FIG. 1 is a plan view illustrating a semiconductor device according to one or more embodiments.

[0012] FIG. 2 is a cross-sectional view taken along line I-I' of the semiconductor device of FIG. 1 according to one or more embodiments.

[0013] FIG. 3A , FIG. 3B and FIG. 3C are cross-sectional views taken along lines II1-II1', II2a-II2a', and II2b-II2b' of the semiconductor device of FIG. 1 according to one or more embodiments, respectively.

[0014] FIG. 4A and FIG. 4B are partial enlarged views illustrating "A1" and "B1" of FIG. 2 according to one or more embodiments, respectively.

[0015] FIG. 5 is a partial enlarged view illustrating "C" of FIG. 2 according to one or more embodiments.

[0016] FIG. 6 is a cross-sectional view illustrating a semiconductor device according to one or more embodiments.

[0017] FIG. 7A and FIG. 7Bare cross-sectional views each illustrating a semiconductor device according to one or more embodiments. FIG. 6 are enlarged views of a portion of "A2" and "B2" of

[0018] FIG. 8 are cross-sectional views each illustrating a semiconductor device according to one or more embodiments.

[0019] FIG. 9 are enlarged views of a portion of "B3" of FIG. 8

[0020] FIG. 10 are cross-sectional views each illustrating a semiconductor device according to one or more embodiments.

[0021] FIG. 11A to FIG. 11D are cross-sectional views each illustrating a method of manufacturing a semiconductor device according to one or more embodiments.

[0022] FIG. 12A to FIG. 12D are cross-sectional views each illustrating a method of manufacturing a semiconductor device according to one or more embodiments.

[0023] FIG. 13A to FIG. 13D are cross-sectional views each illustrating a method of manufacturing a semiconductor device according to one or more embodiments.

[0024] FIG. 14A to FIG. 14E are cross-sectional views each illustrating a method of manufacturing a semiconductor device according to one or more embodiments. DETAILED DESCRIPTION

[0025] Hereinafter, example embodiments disclosed will be described in detail with reference to the accompanying drawings. In the drawings, like reference numerals are used for the same components and redundant descriptions thereof will be omitted. Embodiments described herein are example embodiments, and thus, the disclosure is not limited thereto and can be implemented in various other forms.

[0026] As used herein, expressions such as "at least one of a, b, and c" when following a list of elements, modify the entire group of elements and do not modify the individual elements of the group. For example, the expression "at least one of a, b, and c" is understood to include only a, only b, only c, both a and b, both a and c, both b and c, or all of a, b, and c.

[0027] ​It will be understood that when an element or layer is referred to as being "on" or "connected to" or "coupled to" another element or layer, it can be directly on, connected, or coupled to the other element or layer, or intervening elements or layers can be present. In contrast, when an element or layer is referred to as being "directly on", "directly connected to", or "directly coupled to" another element or layer, there are no intervening elements or layers present. It will also be understood that when an element is referred to as being "on" or "connected to" or "coupled to" another element, it can be directly on, connected, or coupled to the other element, or intervening elements can be present. In contrast, when an element is referred to as being "directly on", "directly connected to", or "directly coupled to" another element, there are no intervening elements present. Like numbers refer to like elements throughout.

[0028] FIG. 1 is a plan view showing a semiconductor device according to one or more embodiments. FIG. 2 is a cross-sectional view taken along line I-I' of the semiconductor device of FIG. 1 . FIG. 3A , FIG. 3B and FIG. 3C are cross-sectional views taken along lines II1-II1', II2a-II2a', and II2b-II2b' of the semiconductor device of FIG. 1 , respectively, according to one or more embodiments.

[0029] Referring to FIG. 1 , FIG. 2 and FIG. 3A to FIG. 3C , the semiconductor device 100 according to one or more embodiments can include an insulating base layer 210, a fin-type structure FS extending in a first direction (e.g., X direction) on the insulating base layer 210, a plurality of channel layers 130 stacked on one region of the fin-type structure FS in a direction (e.g., Z direction) perpendicular to an upper surface of the insulating base layer 210 and spaced apart from each other, a gate structure GS extending in a second direction (e.g., Y direction) intersecting the first direction (e.g., X direction) and surrounding the plurality of channel layers 130, and a plurality of source / drain patterns 150A and 150B connected to two side surfaces of the plurality of channel layers 130 in the first direction (e.g., X direction), respectively.

[0030] In one or more embodiments, the insulating base layer 210 can include an insulating pattern 210P protruding from a region corresponding to the fin-type pattern 105P on the upper surface of the insulating base layer 210. The insulating base layer 210 can be a substrate including a semiconductor material (e.g., see "101" of FIG. 11A ) (e.g., see FIG. 13A ) followed by an additional process (e.g., see FIG. 13Bformed by oxidizing the substrate in a series of manufacturing processes of the semiconductor device 100. The insulating base layer 210 can include an insulating material such as an oxide or a nitride. For example, the insulating base layer 210 can be a spin-on hard mask (SOH), a flowable oxide (FOX), a Toszilazane (TOSZ), an undoped silicate glass (USG), a borosilicate glass (BSG), a phosphosilicate glass (PSG), a borophosphosilicate glass (BPSG), a plasma enhanced tetraethyl orthosilicate (PETEOS), a fluorosilicate glass (FSG), a high-density plasma (HDP) oxide, a plasma enhanced oxide (PEOX), a flowable chemical vapor deposition (CVD) (FCVD) oxide, or a combination thereof. The insulating base layer 210 can be formed using a chemical vapor deposition (CVD) process, a flowable CVD process, or a spin-on process.

[0031] Referring to FIG. 2 and FIG. 3A to FIG. 3C , the insulating base layer 210 can include a fin-type structure FS extending in a first direction (e.g., an X direction). The device isolation layer 110 can define the fin-type structure FS on the insulating base layer 210. The fin-type structure FS can include an insulating pattern 210P, a fin-type pattern 105P, and a plurality of bottom isolation patterns 170P between the insulating pattern 210P and the fin-type pattern 105P. The device isolation layer 110 can be disposed on the insulating base layer 210 to cover both side surfaces of the insulating pattern 210P. An upper region of the insulating pattern 210P can be exposed from an upper surface of the device isolation layer 110. The insulating pattern 210P can be a structure corresponding to a lower region of the active pattern, and the insulating pattern 210P can be obtained in a process of replacing the semiconductor substrate described above with the insulating base layer 210 (see FIG. 13A and FIG. 13B ). Referring to FIG. 3A to FIG. 3C , the insulating pattern 210P is shown to have a visually different interface with the device isolation layer 110, but in one or more embodiments, the insulating base layer 210 can be formed of the same material (e.g., silicon oxide) as the device isolation layer 110, and in this case, the interface between the insulating pattern 210P and the device isolation layer 110 can be difficult to identify visually.

[0032] Referring to FIG. 2 and FIG. 3AAs described above, the plurality of channel layers 130 can be stacked on the fin-type structure FS (in particular, the fin-type pattern 105P) and spaced apart from each other. The semiconductor device 100 can include source / drain patterns 150 (i.e., a first source / drain pattern 150A and a second source / drain pattern 150B) connected to two side surfaces of the plurality of channel layers 130, respectively, in a first direction (e.g., the X direction). In one or more embodiments, in a second direction (e.g., the Y direction), the plurality of channel layers 130 can have a width that is the same as or similar to a width of the fin-type pattern 105P. The number of channel layers 130 is shown to be three, but the number and shape of the channel layers 130 can be changed in various ways. In one or more embodiments, the widths of the plurality of channel layers 130 can be slightly different from each other. For example, the widths of the uppermost channel layer and the lowermost channel layer can be greater than the widths of the channel layers disposed between the uppermost channel layer and the lowermost channel layer.

[0033] The plurality of channel layers 130 can include a semiconductor material that can set a channel region of a transistor. For example, the plurality of channel layers 130 can include at least one of silicon (Si), silicon germanium (SiGe), and germanium (Ge). In one or more embodiments, the plurality of channel layers 130 can include silicon.

[0034] As FIG. 2 and FIG. 3A As shown in FIGS. 1A and 1B, in one or more embodiments, the gate structure GS can include a gate electrode 145 extending in the second direction (e.g., the Y direction) and surrounding the plurality of channel layers 130, a gate insulating film 142 disposed between the gate electrode 145 and the plurality of channel layers 130, a gate spacer 141 disposed on both side surfaces of a portion of the gate electrode 145 disposed on the uppermost channel layer, and a gate cover layer 147 disposed on the gate electrode 145 and the gate insulating film 142 between the gate spacers 141.

[0035] The gate electrode 145 can include an electrically conductive material. For example, the gate electrode 145 can include at least one of W, Ti, Ta, Mo, TiN, TaN, WN, TiON, TiAlC, TiAlN, and TaAlC. In one or more embodiments, the gate electrode 145 can include a semiconductor material such as doped polysilicon. At least one of the gate electrodes 145 can include a multi-layer structure formed of different materials.

[0036] The gate insulating film 142 can include a dielectric material. For example, the gate insulating film 142 can include an oxide, a nitride, or a high-k material. A high-k material can refer to a dielectric material having a dielectric constant higher than that of silicon oxide (SiO2), and the high-k material can be, for example, one of aluminum oxide (Al2O3), tantalum oxide (Ta2O3), titanium oxide (TiO2), yttrium oxide (Y2O3), zirconium oxide (ZrO2), zirconium silicon oxide (ZrSi x O y ), hafnium oxide (HfO2), hafnium silicon oxide (HfSi x O y ), lanthanum oxide (La2O3), lanthanum aluminum oxide (LaAl x O y ), lanthanum hafnium oxide (LaHf x O y ), hafnium aluminum oxide (HfAl x O y ), and praseodymium oxide (Pr2O3). In one or more embodiments, the gate insulating film 142 can include two or more different dielectric films.

[0037] The gate spacer 141 can include an insulating material. For example, the gate spacer 141 can include at least one of silicon oxide, silicon nitride, and silicon oxynitride. In one or more embodiments, the gate spacer 141 can include a multi-layer structure formed of different materials. The gate capping layer 147 can include, for example, silicon nitride, silicon oxynitride, silicon carbonitride, or silicon carbonoxynitride.

[0038] The gate structure GS according to one or more embodiments can include an inner spacer 170S. The inner spacer 170S can be disposed on both sides of a gate electrode portion 145S disposed between the plurality of channel layers 130 and between the lowermost channel layer and the fin-type pattern 105P. The gate electrode portion 145S can be surrounded by a gate insulating portion 142S in a first direction (e.g., the X direction). The gate electrode portion 145S and the gate insulating portion 142S can be spaced apart from the first source / drain pattern 150A and the second source / drain pattern 150B by the inner spacer 170S. In one or more embodiments, the inner spacer 170S can not be included in the gate structure GS and can be disposed between the gate structure GS and the first source / drain pattern 150A and the second source / drain pattern 150B.

[0039] The inner spacer 170S employed in one or more embodiments can be disposed after a formation process of the source / drain pattern 150. For example, the inner spacer 170S can be formed together with the bottom isolation pattern 170P during a formation process of the gate structure GS (see FIG. 2B). In one or more embodiments, the inner spacer 170S can be formed after the formation process of the gate structure GS. For example, the inner spacer 170S can be formed after the gate structure GS is formed on the substrate 100 (see FIG. 2B). FIG. 12B). Thus, as described above, the inner spacers 170S can include a material of the material of the bottom isolation pattern 170P. For example, the inner spacers 170S can include a low-k dielectric material such as an oxide, a nitride, and a nitride oxide.

[0040] FIG. 4A is a partial enlarged view showing FIG. 2 “A1” of FIG. 1A according to one or more embodiments.

[0041] Referring to FIG. 4A and FIG. 2 , the inner spacers 170S can have a first side surface CA1 in contact with the gate insulating portions 142S of the gate structure GS, and each of the first side surfaces CA1 can have a concave surface. In one or more embodiments, a middle portion of each of the inner spacers 170S can have a width d1 smaller than a width d2 of the upper and lower ends of the inner spacers 170S, unlike the inner spacers formed before the source / drain pattern 150 is formed. Further, as described above, since the inner spacers 170S are formed after the source / drain pattern 150 is formed, the source / drain pattern 150 can have a structure in which the source / drain pattern 150 is slightly recessed between the channel layers 130. Accordingly, the inner spacers 170S can have a second side surface CA2 in contact with the source / drain pattern 150, and each of the second side surfaces CA2 can also have a concave surface.

[0042] As shown in FIG. 2 , the first source / drain pattern 150A and the second source / drain pattern 150B can be disposed on regions of the insulating pattern 210P at both sides of the gate structure GS, respectively. The regions of the insulating pattern 210P on which the first source / drain pattern 150A and the second source / drain pattern 150B are formed can be slightly recessed regions. As described above, the first source / drain pattern 150A and the second source / drain pattern 150B can be connected to two side surfaces of the plurality of channel layers 130 as channel regions, respectively.

[0043] Referring to FIG. 2 , FIG. 3B and FIG. 3C , each of the first source / drain pattern 150A and the second source / drain pattern 150B of one or more embodiments can include a first epitaxial layer 150a and a second epitaxial layer 150b on the first epitaxial layer 150a. The first epitaxial layer 150a can directly contact side surfaces of the plurality of channel layers 130.

[0044] The first and second epitaxial layers 150a and 150b can include different materials. For example, in the case of a p-type metal-oxide-semiconductor (MOS) field-effect transistor (FET) (MOSFET) (PMOSFET), the first and second epitaxial layers 150a and 150b can include SiGe with different Ge compositions (e.g., the second epitaxial layer 150b can include a higher Ge content), or the first and second epitaxial layers 150a and 150b can include Si and SiGe, respectively. However, in the case of an n-type MOSFET (NMOSFET), both the first and second epitaxial layers 150a and 150b can include Si. In one or more embodiments, the first and second epitaxial layers 150a and 150b can include different types of impurities or different concentrations of the same impurity.

[0045] Referring to FIG. 2 , the plurality of bottom isolation patterns 170P can be spaced apart from each other in the first direction (e.g., the X direction) between the insulating pattern 210P and the fin-type pattern 105P. The plurality of bottom isolation patterns 170P can be respectively located under the plurality of gate structures GS. In one or more embodiments, each of the bottom isolation patterns 170P can have a thickness t1 that is smaller than a thickness t0 of the gaps of the plurality of channel layers 130, and a width W1 of each of the bottom isolation patterns 170P in the first direction (e.g., the X direction) can be greater than a width W0 of each of the plurality of channel layers 130 in the first direction (e.g., the X direction).

[0046] In one or more embodiments, the bottom isolation patterns 170P can be formed together during a formation process of the inner spacers 170S (see FIG. 12B ). The bottom isolation patterns 170P can include the same material as the inner spacers 170S. For example, the bottom isolation patterns 170P can include a low-k dielectric material such as an oxide, a nitride, and a nitride-oxide.

[0047] In one or more embodiments, a first source / drain pattern 150A among the plurality of source / drain patterns 150 can be connected to a lower contact structure 280 that penetrates the insulating base layer 210. The lower contact structure 280 can be connected to the first source / drain pattern 150A by passing through between the bottom isolation patterns 170P among the bottom isolation patterns 170P adjacent to the first source / drain pattern 150A. The bottom isolation patterns 170P adjacent to the first source / drain pattern 150A can be used as a self-alignment structure to align a position of the lower contact structure 280.

[0048] FIG. 4B is a partial enlarged view of “B1” shown in FIG. 2 FIG. 1A according to one or more embodiments. FIG. 5is a partial enlarged view of "C" shown according to one or more embodiments FIG. 2

[0049] Referring to FIG. 3B , FIG. 4B and FIG. 5 and FIG. 2 , the lower contact structure 280 can include a contact extension 280E connected to the first source / drain pattern 150A by passing through the bottom isolation pattern 170P adjacent to the first source / drain pattern 150A from the insulating base layer 210. The bottom isolation pattern 170P adjacent to the first source / drain pattern 150A can align the lower contact structure 280 so that the contact extension 280E is directed toward the approximate center of the bottom of the first source / drain pattern 150A. In this way, the width Wb of the portion where the contact extension 280E begins can be defined by the space in the first direction (e.g., the X direction) between the bottom isolation patterns 170P adjacent to the first source / drain pattern 150A.

[0050] Referring to FIG. 5 and FIG. 2 , the lower contact structure 280 can have a stepped structure ST in the portion where the contact extension 280E begins. The width Wb of the contact extension 280E defined between the bottom isolation patterns 170P adjacent to the first source / drain pattern 150A can be smaller than the width Wa of another portion of the lower contact structure 280 adjacent to the insulating base layer 210. The contact extension 280E can have a width Wc similar to or smaller than the defined width Wb.

[0051] Referring to FIG. 3B , it is shown that the width of the lower contact structure 280 in the second direction (e.g., the Y direction) can be smaller than the width of the fin-type structure FS in the second direction (e.g., the Y direction), and some bottom sacrificial patterns 220P' remain around the lower contact structure 280, but embodiments are not limited thereto, and in one or more embodiments, depending on the etching conditions for forming the contact hole, the remaining bottom sacrificial patterns can be very few or almost non-existent. In one or more embodiments, in the contact hole forming process (see FIG. 13C ), the width of the lower contact structure in the second direction can be designed to correspond to the width of the fin-type structure FS in the second direction, as a result, the relevant bottom sacrificial patterns can be removed. In addition, as shown in FIG. 3B , in the cross-section in the second direction (e.g., the Y direction), unlike the cross-sections in FIG. 2 and FIG. 5 , the lower contact structure 280 can have a side surface with a relatively small step or almost no step.

[0052] ​In one or more embodiments, as the region reserved from the active pattern, the fin-type pattern 105P can include a semiconductor material (such as silicon), as described above. In this case, the lower contact structure 280 can include a contact plug 285 and an insulating liner 281 disposed on the side surface of the contact plug 285. The lower contact structure 280 can be electrically isolated from the fin-type pattern 105P by the insulating liner 281. For example, the contact plug 285 can include a conductive material (such as Cu, Co, Mo, Ru, W, or alloys thereof). For example, the insulating liner 281 can include SiO2, SiN, SiCN, SiC, SiCOH, SiON, Al2O3, AlN, or combinations thereof.

[0053] In one or more embodiments, the fin-type pattern 105P can include silicon oxide. The reserved active pattern can be oxidized using an additional thermal oxidation process, etc. In this case, the lower contact structure 280 can include a contact plug 285 and a conductive barrier 282 disposed on the surface of the contact plug 285 (see FIG. 6 and FIG. 10 ).

[0054] The semiconductor device 100 according to one or more embodiments can include an upper contact structure 180 connected to the second source / drain pattern 150B between the plurality of gate structures GS.

[0055] Referring to FIG. 2 and FIG. 3C , the fin-type structure FS can further include a bottom sacrificial pattern 220P disposed between the bottom isolation patterns 170P adjacent to the second source / drain pattern 150B among the bottom isolation patterns 170P. The bottom sacrificial pattern 220P can be disposed at the same height as the bottom isolation patterns 170P below the second source / drain pattern 150B. In one or more embodiments, the bottom isolation patterns 170P can have a convex side surface toward the bottom sacrificial pattern 220P.

[0056] In one or more embodiments, each of the bottom sacrificial patterns 220P can have a width W2 in a first direction (e.g., the X direction) that is smaller than a width W1 of each of the bottom isolation patterns 170P in the first direction (e.g., the X direction). The bottom sacrificial patterns 220P can be used as a sacrificial structure that defines a formation region of the lower contact structure 280, and the bottom sacrificial patterns 220P below the first source / drain pattern 150A can be removed to define a hole for forming the lower contact structure 280 (see FIG. 13C ).

[0057] Accordingly, a width W2 of the bottom sacrificial pattern 220P in the first direction (e.g., the X direction) can be substantially equal to a width Wb of a portion of the lower contact structure 280 between the bottom isolation patterns 170P adjacent to the first source / drain pattern 150A (see FIG. 1). In one or more embodiments, the width W2 of the bottom sacrificial pattern 220P in the first direction (e.g., the X direction) can be substantially equal to a width Wb of a portion of the lower contact structure 280 between the bottom isolation patterns 170P adjacent to the second source / drain pattern 150B (see FIG. 1). FIG. 2 and FIG. 5 .

[0058] The bottom sacrificial pattern 220P remaining in the final structure can be disposed under the second source / drain pattern 150B connected to the upper contact structure 180.

[0059] The bottom sacrificial pattern 220P can include materials of the plurality of channel layers 130 and the fin-type pattern 105P and the selectively removable material. For example, the bottom sacrificial pattern 220P can include silicon germanium, and the plurality of channel layers 130 can include silicon. In one or more embodiments, the fin-type pattern 105P can also include silicon or silicon oxide oxidized from silicon.

[0060] The semiconductor device 100 according to one or more embodiments can also include a first interlayer insulating layer 161 disposed on the device isolation layer 110 to cover the first source / drain pattern 150A and the second source / drain pattern 150B, and a second interlayer insulating layer 162 covering the gate structure GS on the first interlayer insulating layer 161. For example, the first interlayer insulating layer 161 and the second interlayer insulating layer 162 can be SOH, FOX, TOSZ, USG, BSG, PSG, BPSG, PETEOS, FSG, HDP oxide, PEOX, FCVD oxide, or a combination thereof. The first interlayer insulating layer 161 and the second interlayer insulating layer 162 can be formed using a chemical vapor deposition, a fluid CVD process, or a spin-on process.

[0061] Referring to FIG. 2 and FIG. 3B , the contact extension 280E of the lower contact structure 280 can contact the second epitaxial layer 150b. In one or more embodiments, an upper portion of the lower contact structure 280 can horizontally overlap with a lowermost channel layer among the channel layers 130, or can be disposed at a height higher than a height of the lowermost channel layer.

[0062] Referring to FIG. 2 and FIG. 3C , a lower portion of the upper contact structure 180 can horizontally overlap with an uppermost channel layer among the channel layers 130, or can be disposed at a height lower than a height of the uppermost channel layer. The upper contact structure 180 can include a contact plug and a conductive barrier surrounding the contact plug. For example, the contact plug can include Cu, Co, Mo, Ru, W, or an alloy thereof. For example, the conductive barrier can include Ta, TaN, Mn, MnN, WN, Ti, TiN, or a combination thereof.

[0063] A semiconductor device 100 according to one or more embodiments may have a dual-sided interconnect structure including a front-side interconnect structure 190 and a back-side interconnect structure 290. The front-side interconnect structure 190 is disposed on the upper surface of the semiconductor device 100, and the back-side interconnect structure is disposed on the lower surface of the semiconductor device 100.

[0064] The front interconnect structure 190 may include an upper interconnect insulating layer 191 and an upper interconnect line M1 disposed in the upper interconnect insulating layer 191. Similarly, the back interconnect structure 290 may include a lower interconnect insulating layer 291 and a lower interconnect line M2 disposed in the lower interconnect insulating layer 291. For example, the upper interconnect insulating layer 191 and the lower interconnect insulating layer 291 may include silicon oxide, silicon oxynitride, SiOC, SiCOH, or combinations thereof. For example, the upper interconnect line M1 and the lower interconnect line M2 may include copper or a copper-containing alloy. In one or more embodiments, the lower interconnect line M2 may be configured as a power line for power transmission and may supply power for device operation to the first source / drain pattern 150A via the lower contact structure 280.

[0065] The bottom isolation pattern 170P and the bottom sacrificial pattern 220P can be introduced as a self-aligned structure of the lower contact structure 280, and can be implemented in various forms in various example embodiments (see [link to example]). FIG. 6 to FIG. 9 ).

[0066] FIG. 6 This is a cross-sectional view showing a semiconductor device according to one or more embodiments. FIG. 7A and FIG. 7B The embodiments are shown separately according to one or more examples. FIG. 6 Enlarged views of parts “A2” and “B2”.

[0067] Reference FIG. 6 , FIG. 7A and FIG. 7B In addition to the gate insulating film including multiple insulating layers (e.g., interface insulating film 142S1 and high-k dielectric film 142S2), the bottom isolation pattern 170PA including multiple insulating layers (e.g., first insulating film 142S1' and third insulating film 142S2'), the fin pattern 105PA being configured as an insulating structure, and the lower contact structure 280A being formed without an insulating liner, the semiconductor device 100A according to one or more embodiments is compatible with... FIG. 1 to FIG. 5 The semiconductor device 100 shown is similar. Descriptions of those aspects that are the same or similar to those described above may be omitted.

[0068] The gate insulating film in one or more embodiments can include an interface insulating film 142S1 and a high-k dielectric film 142S2. The interface insulating film 142S1 can be formed before the internal spacers 170S are formed, and the high-k dielectric film 142S2 can be formed after the internal spacers 170S are formed and before the gate electrode 145 is formed. Referring to FIG. 6 and FIG. 7A Each of the internal spacers 170S can be disposed between the interface insulating film 142S1 and the high-k dielectric film 142S2. The high-k dielectric film 142S2 can surround the gate electrode portion 145S between the internal spacers 170S and the gate electrode portion 145S in the second direction (e.g., Y direction).

[0069] In one or more embodiments, the interface insulating film 142S1 and the internal spacers 170S can include the same material (such as silicon oxide). In one or more embodiments, the interface insulating film 142S1 and the internal spacers 170S can include different materials. For example, the interface insulating film 142S1 can include silicon oxide, and the internal spacers 170S can include silicon nitride or silicon oxynitride.

[0070] In one or more embodiments, the bottom isolation pattern 170PA can have a multi-layer structure. Referring to FIG. 6 and FIG. 7B The bottom isolation pattern 170PA can include the same material layers (e.g., first and third insulating films 142S1' and 142S2') as the interface insulating film 142S1 and the high-k dielectric film 142S2, respectively, and the same material portion (e.g., second insulating film 170P') as the internal spacers 170S. For example, the bottom isolation pattern 170PA can sequentially include the first through third insulating films 142S1', 170P', and 142S2' from an inner surface of the bottom isolation pattern 170PA. The first insulating film 142S1' can include the same material as the material of the interface insulating film 142S1, the second insulating film 170P' includes the same material as the material of the internal spacers 170S, and the third insulating film 142S2' can include the same material as the material of the high-k dielectric film 142S2. In one or more embodiments, the thickness of the second insulating film 170P' can be greater than the thickness of each of the first and third insulating films 142S1' and 142S2'. In one or more embodiments, the bottom isolation pattern 170PA can have a thickness t1' and / or a width W1' that are slightly greater than the thickness t1 and / or the width W1 of the above-described bottom isolation pattern 170P. In one or more embodiments, the width W2' of the bottom sacrificial pattern 220P in the first direction (e.g., X direction) can be smaller than the width W1' of the bottom isolation pattern 170PA in the first direction (e.g., X direction), but is not limited thereto.

[0071] In one or more embodiments, the fin-type pattern 105PA can be provided as an insulating structure. For example, the fin-type pattern 105PA can include silicon oxide. In one or more embodiments, the remaining active pattern can be oxidized by an oxidation process, such as an additional thermal oxidation process, and can be converted into a thermal oxide layer. In this case, the lower contact structure 280A can be provided without an insulating liner. The lower contact structure 280A can include a contact plug 285 and a conductive barrier 282 provided on a surface of the contact plug 285. For example, the contact plug 285 can include Cu, Co, Mo, Ru, W, or alloys thereof. For example, the conductive barrier 282 can include Ta, TaN, Mn, MnN, WN, Ti, TiN, or combinations thereof.

[0072] FIG. 8 is a cross-sectional view illustrating a semiconductor device according to one or more embodiments. FIG. 9 is a cross-sectional view illustrating a semiconductor device according to one or more embodiments. FIG. 8 is a partial enlarged view of “B3” of

[0073] Referring to FIG. 8 , except that the bottom isolation patterns 170P1 and 170P2 and the bottom sacrificial patterns 220P1 and 220P2 are introduced as a multi-layer (e.g., dual-layer) structure, the contact extension 280E of the lower contact structure 280 has a changed shape due to the dual-layer structure, and a portion of the bottom isolation pattern 170P1 has a void VD, the semiconductor device 100B according to one or more embodiments can be understood as similar to the semiconductor device 100 illustrated in FIG. 1 to FIG. 5 . Descriptions of aspects that are the same as or similar to those described above can be omitted.

[0074] The bottom isolation structure in one or more embodiments can be provided as a dual-layer structure in a fin-type structure FS’. The fin-type structure FS’ includes a first fin-type pattern 105P1 and a second fin-type pattern 105P2 sequentially provided on an insulating pattern 210P of an insulating base layer 210. The first fin-type pattern 105P1 and the second fin-type pattern 105P2 can be semiconductor patterns. A first bottom isolation pattern 170P1 can be spaced apart from each other in a first direction (e.g., X direction) under each of the plurality of gate structures GS between the insulating base layer 210 and the first fin-type pattern 105P1, and a second bottom isolation pattern 170P2 can be spaced apart from each other in the first direction (e.g., X direction) under each of the plurality of gate structures GS between the first fin-type pattern 105P1 and the second fin-type pattern 105P2. Each of the first bottom isolation pattern 170P1 and the second bottom isolation pattern 170P2 can include the same material as that of the internal spacer 170S.

[0075] The first bottom isolation patterns 170P1 and the second bottom isolation patterns 170P2 can have different thicknesses t1a and t1b and different widths W1a and W1b. In one or more embodiments, a first thickness t1a of each of the first bottom isolation patterns 170P1 can be greater than a second thickness t1b of each of the second bottom isolation patterns 170P2. Each of the first thickness t1a and the second thickness t1b can be less than a thickness t0 of the gaps between the plurality of channel layers 130. Further, a first width W1a of each of the first bottom isolation patterns 170P1 in the first direction (e.g., the X direction) can be less than a second width W1b of each of the second bottom isolation patterns 170P2 in the first direction (e.g., the X direction). The width W1a of the first bottom isolation patterns 170P1 and the width W1b of the second bottom isolation patterns 170P2 can be adjusted using the respective thicknesses t1a and t1b. For example, in the sacrificial layer removal process (see FIG. 2B), since the amount (volume) of etching of the sacrificial material is relatively constant, the widths of the gap regions OP2a and OP2b formed can also be adjusted differently by setting the thicknesses of the bottom sacrificial layers 220L1 and 220L2 differently. FIG. 14C

[0076] The second source / drain patterns 150B can be connected to the upper contact structures 180, and the first bottom sacrificial patterns 220P1 can be disposed between first bottom isolation patterns of the first bottom isolation patterns 170P1 that are adjacent to the second source / drain patterns 150B. Similarly, the second bottom sacrificial patterns 220P2 can be disposed between second bottom isolation patterns of the second bottom isolation patterns 170P2 that are adjacent to the second source / drain patterns 150B. A center of each of the first bottom sacrificial patterns 220P1 and the second bottom sacrificial patterns 220P2 can substantially overlap each other in a direction (e.g., the Z direction) that is perpendicular to a center of the second source / drain patterns 150B (i.e., perpendicular to the first direction / X direction). That is, the center of each of the first bottom sacrificial patterns 220P1 and the second bottom sacrificial patterns 220P2 can substantially align or overlap with the center of the second source / drain patterns 150B in the Z direction.

[0077] Similar to the first bottom isolation patterns 170P1 and the second bottom isolation patterns 170P2, a first thickness t1a of the first bottom sacrificial patterns 220P1 can be greater than a second thickness t1b of the second bottom sacrificial patterns 220P2. Further, a first width W2a of the first bottom sacrificial patterns 220P1 in the first direction (e.g., the X direction) can be greater than a second width W2b of the second bottom sacrificial patterns 220P2 in the first direction (e.g., the X direction) as compared to the first bottom isolation patterns 170P1 and the second bottom isolation patterns 170P2.

[0078] ​The lower contact structure 280 can penetrate the insulating base layer 210 and be connected to the first source / drain pattern 150A. As described above, the lower contact structure 280 can be defined by the gap between the first bottom isolation patterns 170P1 adjacent to the first source / drain pattern 150A among the first bottom isolation patterns 170P1 and the gap between the second bottom isolation patterns 170P2 adjacent to the first source / drain pattern 150A among the second bottom isolation patterns 170P2. The gap between the first bottom isolation patterns 170P1 adjacent to the first source / drain pattern 150A can correspond to the width of the first bottom sacrificial pattern 220P1, and the gap between the second bottom isolation patterns 170P2 adjacent to the first source / drain pattern 150A can correspond to the width of the second bottom sacrificial pattern 220P2. In one or more embodiments, the center of each of the gaps can substantially overlap with each other in a vertical direction (e.g., Z direction) from the center of the first source / drain pattern 150A (that is, the center of each of the gaps can be substantially aligned or overlapped with the center of the first source / drain pattern 150A in the Z direction), and thus the first bottom isolation patterns 170P1 and the second bottom isolation patterns 170P2 adjacent to the first source / drain pattern 150A can be used as a self-alignment structure of the lower contact structure 280.

[0079] In one or more embodiments, the gap between the second bottom isolation patterns 170P2 adjacent to the first source / drain pattern 150A can be smaller than the gap between the first bottom isolation patterns 170P1 adjacent to the first source / drain pattern 150A. Referring to FIG. 2B, the gap between the second bottom isolation patterns 170P2 adjacent to the first source / drain pattern 150A can be smaller than the gap between the first bottom isolation patterns 170P1 adjacent to the first source / drain pattern 150A. FIG. 8 FIG. 9 Due to the double-layer bottom isolation structure, the lower contact structure 280 can have two stepped portions ST1 and ST2. The first stepped portion ST1 can be disposed in a region where the contact extension 280E starts due to the gap between the first bottom isolation patterns 170P1 adjacent to the first source / drain pattern 150A, and the second stepped portion ST2 can be disposed in a middle region of the contact extension 280E due to the gap between the second bottom isolation patterns 170P2 adjacent to the first source / drain pattern 150A.

[0080] At least one of the first bottom isolation patterns 170P1 and the second bottom isolation patterns 170P2 can not be completely filled, and a portion of at least one of the first bottom isolation patterns 170P1 and the second bottom isolation patterns 170P2 can remain as a void VD. In one or more embodiments, the first bottom isolation patterns 170P1 can have the void VD.

[0081] FIG. 10 is a cross-sectional view illustrating a semiconductor device according to one or more embodiments.

[0082] Referring to​FIG. 10 , except that the semiconductor device 100C includes a vertical sacrificial pattern 230P extending under the second source / drain pattern 150B toward the insulating base layer 210, the fin-type pattern 105PA is provided as an insulating structure, the lower contact structure 280A is formed without an insulating liner, and the structure of the contact extension 280E' is different, the semiconductor device 100C according to one or more embodiments can be understood as similar to the semiconductor device 100 shown in FIG. 1 to FIG. 5 . The description of aspects that are the same as or similar to those described above can be omitted.

[0083] The semiconductor device 100C according to one or more embodiments can also include a vertical sacrificial pattern 230P extending under the second source / drain pattern 150B toward the insulating base layer 210. By forming a recess deeper toward the fin-type pattern when forming the source / drain pattern (see FIG. 11C ), the vertical sacrificial pattern 230P can be introduced as a sacrificial structure for forming the lower contact structure 280A. For example, the fin-type pattern 105P can include silicon, and the vertical sacrificial pattern 230P can include silicon germanium. The bottom isolation pattern 170P adjacent to the second source / drain pattern 150B can extend to the inside of the vertical sacrificial pattern 230P. When forming the second gap region for the bottom isolation pattern 170P (see FIG. 12A “OP2” in ), two end regions of the second gap region can extend vertically in the vertical sacrificial pattern 230P, so that two ends of the final bottom isolation pattern 170P can have a thickness greater than that of other regions of the final bottom isolation pattern 170P.

[0084] In one or more embodiments, the fin-type pattern 105PA can be provided as an insulating structure. For example, the fin-type pattern 105PA can include silicon oxide. In one or more embodiments, the remaining active pattern can be oxidized by an oxidation process, such as an additional thermal oxidation process, and can be converted into a thermal oxide layer. In this case, the lower contact structure 280A can be provided without an insulating liner. The lower contact structure 280A can include a contact plug 285 and a conductive barrier 282 provided on the surface of the contact plug 285. Since the lower contact structure 280A is formed in a space (corresponding to the dashed region 280D) from which the vertical sacrificial pattern provided under the first source / drain pattern 150A is removed, the contact extension 280E' can be slightly expanded in the width direction (e.g., the X direction).

[0085] The method of manufacturing a semiconductor device according to one or more embodiments can include a self-alignment process of a lower contact structure using a bottom sacrificial pattern between bottom isolation patterns. The method of manufacturing a semiconductor device FIG. 1 to FIG. 5 The semiconductor device 100 shown in can be manufactured by the method of manufacturing a semiconductor device 100 according to one or more embodiments.FIG. 11A to FIG. 11D (formation of a source / drain pattern), FIG. 12A to FIG. 12D (formation of a gate structure and an upper contact structure), and FIG. 13A to FIG. 13D (formation of a lower contact structure) are described. FIG. 11A to FIG. 11D , FIG. 12A to FIG. 12D and FIG. 13A to FIG. 13D may be cross-sectional views corresponding to cross-sections shown in FIG. 2 , respectively.

[0086] FIG. 11A to FIG. 11D are cross-sectional views illustrating a method of manufacturing a semiconductor device according to one or more embodiments. That is, FIG. 11A to FIG. 11D illustrate a process of forming a source / drain pattern.

[0087] Referring to FIG. 11A , a bottom sacrificial layer 220L and a semiconductor layer 105' can be sequentially formed on a substrate 101, and a sacrificial layer 120L and a semiconductor layer 130L can be alternately stacked on the semiconductor layer 105'.

[0088] The substrate 101 can include a semiconductor material (e.g., a group IV semiconductor, a group III-V compound semiconductor, or a group II-VI compound semiconductor). For example, the group IV semiconductor can include silicon (Si), germanium (Ge), or silicon germanium (SiGe). The substrate 101 can include a bulk wafer, an epitaxial layer, or a silicon-on-insulator (SOI) layer.

[0089] The bottom sacrificial layer 220L and the semiconductor layer 105' can be formed on the substrate 101, and the sacrificial layer 120L and the semiconductor layer 130L can be alternately stacked on the semiconductor layer 105', thereby forming a semiconductor stack SL. The bottom sacrificial layer 220L and the sacrificial layer 120L can have a composition different from that of the semiconductor layers 105' and 130L so as to have selectivity (e.g., etch selectivity) with respect to the semiconductor layers 105' and 130L. The bottom sacrificial layer 220L can have a thickness t1 smaller than a thickness t0 of the sacrificial layer 120L. In a sacrificial pattern removal process (see FIG. 12A ), since an etching amount (volume) of the sacrificial material is relatively constant, the thickness of the bottom sacrificial layer 220L can be formed to be smaller than that of the sacrificial layer 120L, and thus a width of a second gap region OP2 can be greater than a width of a first gap region OP1.

[0090] In one or more embodiments, the bottom sacrificial layer 220L and the sacrificial layer 120L can have a germanium concentration greater than a germanium concentration of the semiconductor layers 105' and 130L. For example, the semiconductor layers 105' and 130L can include silicon. The bottom sacrificial layer 220L and the sacrificial layer 120L can include silicon germanium having a relatively high germanium concentration (e.g., 15 at% (atomic percent) or more).

[0091] Next, referring to FIG. 11B The semiconductor stack SL can be patterned into a plurality of fin-type structures FST extending in a first direction (e.g., the X-direction), and a plurality of dummy gate structures DG extending in a second direction (e.g., the Y-direction) can be formed.

[0092] In this process, portions of the semiconductor layer 105', the bottom sacrificial layer 220L, and the base 101 can be removed along with the sacrificial layer 120L and the semiconductor layer 130L, thereby forming a fin-type structure FST extending in a first direction (e.g., the X-direction). In the fin-type structure FST, the semiconductor layer 105' and portions of the base 101 can be disposed as a preliminary fin-type pattern 105. In one or more embodiments, the preliminary fin-type pattern 105 can include a fin-type pattern 105P and a fin-type pattern portion 105U. Next, as shown in FIG. 3A to FIG. 3C A device isolation layer 110 can be formed in a peripheral region of the fin-type structure, as shown in

[0093] Next, a dummy gate structure DG and a gate spacer 141 extending in a second direction (e.g., the Y-direction) by intersecting the fin-type structure FST can be formed. The dummy gate structure DG can define a formation region of a gate structure GS. The dummy gate structure DG can be arranged at a constant pitch in the first direction (e.g., the X-direction).

[0094] The dummy gate structure DG can include a sacrificial gate layer 245 and a mask pattern 247 stacked sequentially. The mask pattern 247 can be used to pattern the sacrificial gate layer 245. For example, the sacrificial gate layer 245 can include polysilicon. The sacrificial gate layer 245 can also be formed of multiple layers. The mask pattern 247 can include silicon oxide and / or silicon nitride. The gate spacer 141 can be formed on both sidewalls of the dummy gate structure DG. As described above, the gate spacer 141 can be formed of a low-k material, and can include at least one of SiO, SiN, SiCN, SiOC, SiON, and SiOCN, for example.

[0095] Next, referring to FIG. 11C A recess RS can be formed by removing exposed regions of the fin-type structure FST from the dummy gate structure DG.

[0096] The dummy gate structure DG and the gate spacers 141 can be used as a mask to remove the exposed regions of the fin-type structure FST, thereby forming the recesses RS. The recesses RS can have a depth that extends to a portion of the fin-type pattern 105P on the bottom sacrificial layer 220L. The channel layer 130 can have a channel length in a first direction (e.g., the X-direction). Similar to the channel layer 130, the sacrificial pattern 120 can have a length that corresponds to the length of the channel layer 130. In one or more embodiments, the sacrificial pattern 120 can be partially removed to have notches ID during the recess formation process or by an additional etching process.

[0097] As described in the example embodiments of FIG. 10 , in this process, the recesses RS can be formed to have a depth that extends to a height that is lower than the height of the bottom sacrificial layer 220L. In this case, the regions that are additionally recessed in the fin-type pattern 105P (or the fin-type pattern 105PA in FIG. 10 ) can be set as spaces for forming the vertical sacrificial patterns 230P, and the vertical sacrificial patterns 230P can be formed as epitaxial layers before the process of forming the source / drain patterns (see FIG. 11D ). The vertical sacrificial patterns 230P can include a material that has selectivity (e.g., etching selectivity) with respect to the material of the substrate 101. For example, the substrate 101 can be silicon, and the vertical sacrificial patterns 230P can be silicon germanium (SiGe). The vertical sacrificial patterns 230P can have a relatively high germanium composition ratio (e.g., 15 at% or more) similar to the sacrificial pattern 120.

[0098] Next, referring to FIG. 11D , an epitaxial layer growth process can be performed for the first source / drain patterns 150A and the second source / drain patterns 150B.

[0099] The epitaxial layer can be grown from the bottom surface of the fin-type pattern 105P that is exposed by the recesses RS, and the side surfaces of the sacrificial pattern 120 and the channel layer 130, thereby forming the first source / drain patterns 150A and the second source / drain patterns 150B. The first source / drain patterns 150A and the second source / drain patterns 150B can include impurities by in-situ doping. The first source / drain patterns 150A and the second source / drain patterns 150B can be connected to the sacrificial pattern 120 and the channel layer 130 in the recesses RS. The first source / drain patterns 150A and the second source / drain patterns 150B can have a recessed portion toward each of the sacrificial pattern 120.

[0100] The first and second source / drain patterns 150A and 150B can include a first epitaxial layer 150a and a second epitaxial layer 150b disposed on the first epitaxial layer 150a. In one or more embodiments, the first epitaxial layer 150a can directly contact side surfaces of the plurality of channel layers 130. In one or more embodiments, as described above, the first and second epitaxial layers 150a and 150b can include different materials and / or impurities.

[0101] FIG. 12A to FIG. 12D is a cross-sectional view illustrating a method of manufacturing a semiconductor device according to one or more embodiments. That is, FIG. 12A to FIG. 12D processes of forming a gate structure and an upper contact structure.

[0102] Referring to FIG. 12A A first interlayer insulating layer 161 can be formed, and the dummy gate structure DG and the sacrificial pattern 120 can be removed.

[0103] The first interlayer insulating layer 161 can be formed to cover the dummy gate structure DG and the first and second source / drain patterns 150A and 150B, and the first interlayer insulating layer 161 can be formed by performing a planarization process. Through the planarization process, the exposed sacrificial pattern 120 can be selectively removed after the mask pattern 247 and the sacrificial gate layer 245 are removed. Thus, a gate space DH from which the mask pattern 247 and the sacrificial gate layer 245 are removed and a first gap region OP1 from which the sacrificial pattern is removed can be formed. The gate space DH and the first gap region OP1 can be disposed as spaces for forming the gate structure GS surrounding the channel layer 130.

[0104] In this process, the exposed portions of the bottom sacrificial layer 220L can also be removed together with the sacrificial pattern 120 after the mask pattern 247 and the sacrificial gate layer 245 are removed. The exposed portions of the bottom sacrificial layer 220L can be removed to form a second gap region OP2. Since the thickness of the bottom sacrificial layer 220L is smaller than the thickness of the sacrificial pattern 120, the bottom sacrificial layer 220L can be additionally etched in a width direction (i.e., in a first direction (e.g., X direction)). After this process, the remaining portions of the bottom sacrificial layer can be disposed as a bottom sacrificial pattern 220P between the second gap regions OP2. Centers of the bottom sacrificial pattern 220P can be aligned to overlap each other in a direction (e.g., Z direction) substantially perpendicular to the centers of the source / drain patterns 150. That is, the centers of the bottom sacrificial pattern 220P can be aligned or overlapped with the centers of the source / drain patterns 150 in the Z direction. Thus, the bottom sacrificial pattern 220P can be advantageously used as a self-alignment structure for forming a lower contact structure 280.

[0105] Next, referring to FIG. 12BA process of forming the inner spacers 170S in the first gap regions OP1 can be performed.

[0106] The inner spacers 170S can be formed in each end portion of each of the first gap regions OP1 using a combination of a selective etching process and a deposition process of the insulating material. In this process, the insulating material of the inner spacers 170S can also be deposited in the second gap regions OP2, thereby forming the bottom isolation pattern 170P. In one or more embodiments, the insulating material of the gate insulating film can additionally be deposited in the second gap regions OP2 as well as the insulating material of the inner spacers 170S to form the bottom isolation pattern 170PA (see FIG. 6 ), or the second gap regions OP2 can not be completely filled and the bottom isolation pattern 170P1 can have a void VD (see FIG. 8 and FIG. 9 ).

[0107] Next, referring to FIG. 12C , the gate structure GS surrounding the channel layer 130 can be formed.

[0108] The gate insulating film 142 and the gate electrode 145 can be sequentially formed to form the gate structure GS. In one or more embodiments, the gate insulating film 142 can be conformally formed in the gate spaces DH and the remaining spaces of the first gap regions OP1 in which the inner spacers 170S are formed. After the gate insulating film 142 is formed, the remaining spaces of the first gap regions OP1 and the gate spaces DH can be filled with the gate electrode 145. After the gate electrode 145 in the gate spaces DH is etched back, the gate capping layer 147 can be formed in the removed regions of the gate electrode.

[0109] Next, referring to FIG. 12D , the upper contact structure 180 connected to the second source / drain pattern 150B can be formed, and the front side interconnect structure 190 connected to the upper contact structure 180 can be formed.

[0110] After the second interlayer insulating layer 162 is formed, the contact hole connected to the second source / drain pattern 150B by penetrating the first interlayer insulating layer 161 and the second interlayer insulating layer 162 can be formed, and the conductive material can be filled in the contact hole, thereby forming the upper contact structure 180. The lower surface of the contact hole can extend into the second source / drain pattern 150B.

[0111] FIG. 13A to FIG. 13D is a cross-sectional view illustrating a method of manufacturing a semiconductor device according to one or more embodiments. That is, FIG. 13A to FIG. 13D a process of forming the lower contact structure is illustrated.

[0112] Referring to FIG. 13AA portion of the substrate 101 under the bottom isolation pattern 170P and the bottom sacrificial pattern 220P can be selectively removed.

[0113] In the process of removing the substrate, the bottom isolation pattern 170P and the bottom sacrificial pattern 220P can be used as an etching stop layer. Before the process of removing the substrate 101, a process of polishing the substrate 101 by a certain thickness can be first performed. For example, the substrate 101 can be removed by a lapping process, a grinding process, or a polishing process, and the substrate 101 can be thinned. Then, the remaining area of the substrate can also be removed by a wet etching process and / or an oxidation process. In this process, the fin-type pattern portion 105U disposed under the bottom isolation pattern 170P and the bottom sacrificial pattern 220P can be removed.

[0114] Next, referring to FIG. 2B, a process of removing the substrate 101 from the area of the fin-type pattern portion 105U can be performed. FIG. 13B An insulating base layer 210 can be formed in the area where the substrate 101 is removed.

[0115] The insulating base layer 210 can be formed in the area from which the substrate 101 is removed to cover the bottom isolation pattern 170P and the bottom sacrificial pattern 220P. The insulating base layer 210 can have an insulating pattern 210P protruding from an area corresponding to the fin-type pattern 105P on the upper surface of the insulating base layer 210. The insulating pattern 210P can have a structure extending in a first direction (e.g., the X direction) (see FIG. 2C). FIG. 2 For example, the insulating base layer 210 can have SOH, FOX, TOSZ, USG, BSG, PSG, BPSG, PETEOS, FSG, HDP oxide, PEOX, FCVD oxide, or a combination thereof. The insulating base layer 210 can be formed using a CVD, a fluid CVD process, or a spin coating process.

[0116] Next, referring to FIG. 2B, a process of removing the substrate 101 from the area of the fin-type pattern portion 105U can be performed. FIG. 13C A contact hole OH connected to the first source / drain pattern 150A can be formed in the insulating base layer 210.

[0117] A photo mask PM can be formed on the insulating base layer 210, and the photo mask PM can be used to form a contact hole OH connected to the first source / drain pattern 150A. The contact hole OH can have a first hole portion OH1 penetrating the insulating base layer 210 and a second hole portion OH2 extending from the area between the bottom isolation pattern 170P to the first source / drain pattern 150A. The process can include a first etching process for forming the first hole portion OH1 and a second etching process for forming the second hole portion OH2. The second etching process can be performed as an etching process for a semiconductor (e.g., silicon) after removing the bottom sacrificial pattern 220P between the bottom isolation pattern 170P adjacent to the first source / drain pattern 150A after the first etching process. Since the second hole portion OH2 is formed in the area from which the bottom sacrificial pattern 220P precisely aligned in a direction perpendicular to the first source / drain pattern 150A (e.g., Z direction) is removed, the second hole portion OH2 can be properly aligned with the first source / drain pattern 150A. The contact hole OH can have a step portion between the first hole portion OH1 and the second hole portion OH2, and the width of the second hole portion OH2 in the first direction (e.g., X direction) can be smaller than the width of the first hole portion OH1 in the first direction (e.g., X direction).

[0118] Next, referring to FIG. 13D A lower contact structure 280 connected to the first source / drain pattern 150A can be formed in the contact hole OH.

[0119] In this process, an insulating liner 281 is formed on the inner surface of the contact hole, and a contact opening is formed to expose the first source / drain pattern. A contact plug 285 connected to the first source / drain pattern is formed by forming a conductive material in the contact opening. Thus, the lower contact structure 280 can be formed. For example, the contact plug 285 can include a conductive material such as Cu, Co, Mo, Ru, W, or alloys thereof. For example, the insulating liner 281 can include SiO2, SiN, SiCN, SiC, SiCOH, SiON, Al2O3, AlN, or combinations thereof.

[0120] The lower contact structure 280 may include a contact extension 280E that extends from the insulating base layer 210 through the region between the bottom isolation pattern 170P adjacent to the first source / drain pattern 150A and connects to the first source / drain pattern 150A. The contact extension may be disposed in a second aperture. The width of the initial portion of the contact extension 280E may be defined by the region between the bottom isolation pattern 170P adjacent to the first source / drain pattern 150A, and as described above, the lower contact structure 280 may have a stepped structure ST in the initial portion of the contact extension 280E. The width of the contact extension 280E defined between the bottom isolation pattern 170P adjacent to the first source / drain pattern 150A may be smaller than the width of another portion of the lower contact structure 280 adjacent to the insulating base layer 210.

[0121] Next, as FIG. 2 As shown, the semiconductor device 100 can be configured by forming a back-side interconnect structure 290 connected to the lower contact structure 280.

[0122] FIG. 14A to FIG. 14E This is a cross-sectional view illustrating a method of manufacturing a semiconductor device according to one or more embodiments. FIG. 14A to FIG. 14E The method for manufacturing a semiconductor device shown in the figure can be understood as FIG. 8 The manufacturing process of the semiconductor device 100B is shown in the figure.

[0123] Reference FIG. 14A A first bottom sacrificial layer 220L1, a first semiconductor layer 105a, a second bottom sacrificial layer 220L2, and a second semiconductor layer 105b can be sequentially stacked on a substrate 101, and a sacrificial layer 120L and a semiconductor layer 130L can be alternately stacked on the second semiconductor layer 105b to form a semiconductor stack SL.

[0124] The first bottom sacrificial layer 220L1, the second bottom sacrificial layer 220L2, and the sacrificial layer 120L may have compositions different from those of the first semiconductor layer 105a, the second semiconductor layer 105b, and the semiconductor layer 130L. In one or more embodiments, the first bottom sacrificial layer 220L1 may have a greater thickness than the second bottom sacrificial layer 220L2, and the first bottom sacrificial layer 220L1 and the second bottom sacrificial layer 220L2 may have a smaller thickness than the sacrificial layer 120L.

[0125] In one or more embodiments, the first bottom sacrificial layer 220L1 and the second bottom sacrificial layer 220L2, and the sacrificial layer 120L can have a germanium concentration greater than that of the first semiconductor layer 105a and the second semiconductor layer 105b, and the semiconductor layer 130L. For example, the first semiconductor layer 105a and the second semiconductor layer 105b, and the semiconductor layer 130L can include silicon. The first bottom sacrificial layer 220L1 and the second bottom sacrificial layer 220L2, and the sacrificial layer 120L can include silicon germanium having a relatively high germanium concentration (e.g., 15 at% or more).

[0126] Next, referring to FIG. 14B The semiconductor stack SL can be patterned into a plurality of fin-type structures FST extending in a first direction (e.g., the X direction), and a plurality of dummy gate structures DG extending in a second direction (e.g., the Y direction) can be formed.

[0127] In this process, the first bottom sacrificial layer 220L1 and the second bottom sacrificial layer 220L2, the first semiconductor layer 105a and the second semiconductor layer 105b, and portions of the substrate 101 can be removed together with the sacrificial layer 120L and the semiconductor layer 130L, thereby forming a fin-type structure FST extending in a first direction (e.g., the X direction). In the fin-type structure FST, the first semiconductor layer 105a and the second semiconductor layer 105b, and portions of the substrate 101 can be disposed as a preliminary fin-type pattern 105. In one or more embodiments, the preliminary fin-type pattern 105 can include a first fin-type pattern 105P1 and a second fin-type pattern 105P2, and a fin-type pattern portion 105U. Further, as shown in FIG. 3A to FIG. 3C A device isolation layer 110 can be formed in a peripheral region of the fin-type structure FST.

[0128] Next, the dummy gate structures DG and the gate spacers 141 extending in a second direction (e.g., the Y direction) by intersecting the fin-type structure FST can be formed. Then, a process of forming a series of source / drain patterns can be performed (see FIG. 11C and FIG. 11D ).

[0129] Next, referring to FIG. 14C The first interlayer insulating layer 161 can be formed to cover the dummy gate structures DG, and the first source / drain pattern 150A and the second source / drain pattern 150B, and the first interlayer insulating layer 161 can be formed by performing a planarization process. Through the planarization process, the exposed sacrificial pattern 120 can be selectively removed after the mask pattern 247 and the sacrificial gate layer 245 are removed.

[0130] Accordingly, a gate space DH from which the mask pattern 247 and the sacrificial gate layer 245 are removed and a first gap region OP1 from which the sacrificial pattern is removed can be formed. The gate space DH and the first gap region OP1 can be provided as spaces for forming the gate structure GS surrounding the channel layer 130.

[0131] In this process, after the mask pattern 247 and the sacrificial gate layer 245 are removed, the exposed portions of the first bottom sacrificial layer 220L1 and the second bottom sacrificial layer 220L2 can also be removed together with the sacrificial pattern 120. The exposed portions of the first bottom sacrificial layer 220L1 and the second bottom sacrificial layer 220L2 can be removed to form a second lower gap region OP2a and a second upper gap region OP2b. After this process, the remaining portions of the first bottom sacrificial layer 220L1 can be provided as first bottom sacrificial patterns 220P1 between the second lower gap regions OP2a, and the remaining portions of the second bottom sacrificial layer 220L2 can be provided as second bottom sacrificial patterns 220P2 between the second upper gap regions OP2b. The centers of the first bottom sacrificial patterns 220P1 and the second bottom sacrificial patterns 220P2 can be aligned to overlap each other in a direction (e.g., Z direction) substantially perpendicular to the centers of the source / drain patterns 150. That is, the centers of the first bottom sacrificial patterns 220P1 and the second bottom sacrificial patterns 220P2 can be aligned with or overlap the centers of the source / drain patterns 150 in the Z direction. Accordingly, the first bottom sacrificial patterns 220P1 and the second bottom sacrificial patterns 220P2 can be advantageously used as self-aligned structures for forming the lower contact structure 280.

[0132] Due to the thickness conditions of the first bottom sacrificial layer 220L1 and the second bottom sacrificial layer 220L2, a first width W1a of each of the second lower gap regions OP2a in a first direction (e.g., X direction) can be smaller than a second width W1b of each of the second upper gap regions OP2b in the first direction (e.g., X direction). In contrast, a first width W2a of each of the first bottom sacrificial patterns 220P1 in the first direction (e.g., X direction) can be larger than a second width W2b of each of the second bottom sacrificial patterns 220P2 in the first direction (e.g., X direction).

[0133] Reference will now be made to FIG. 14DA process to form the inner spacers 170S in the first gap region OP1 can be performed, and an insulating material of the inner spacers 170S can be deposited inside the second lower gap region OP2a and the second upper gap region OP2b, thereby forming the first bottom isolation pattern 170P1 and the second bottom isolation pattern 170P2. In one or more embodiments, the second upper gap region OP2b can be substantially filled to form the second bottom isolation pattern 170P2, while the first bottom isolation pattern 170P1 formed in the second lower gap region OP2a can have a void VD.

[0134] Next, a gate structure GS surrounding the channel layer 130 can be formed (see FIG. 12C ), and an upper contact structure 180 connected to the second source / drain pattern 150B and a front side interconnect structure 190 connected to the upper contact structure 180 can be formed (see FIG. 12D ). Next, the first bottom isolation pattern 170P1 and the first bottom sacrificial pattern 220P1 can be used as an etch stop layer, so that a portion of the base 101 can be selectively removed (see FIG. 13A ), and an insulating base layer 210 can be formed in the area where the base 101 is removed (see FIG. 13B ).

[0135] Next, referring to FIG. 14E , a contact hole OH connected to the first source / drain pattern 150A can be formed in the insulating base layer 210.

[0136] A photo mask PM can be formed on the insulating base layer 210, and the photo mask PM can be used to form a contact hole OH connected to the first source / drain pattern 150A. The contact hole OH can have a first hole portion OH1 penetrating the insulating base layer 210, a second hole portion OH2a between the first bottom isolation pattern 170P1 and the second bottom isolation pattern 170P2, and a third hole portion OH2b extending from the area between the second bottom isolation patterns 170P2 into the first source / drain pattern 150A. The process can include a first etching process to form the first hole portion OH1, a second etching process to form the second hole portion OH2a, and a third etching process to form the third hole portion OH2b. The second etching process can be performed as an etching process for a semiconductor (e.g., silicon) after performing the first etching process and then removing the first bottom sacrificial pattern 220P1 between the first bottom isolation pattern 170P1 adjacent to the first source / drain pattern 150A. The third etching process can be performed as an etching process for a semiconductor (e.g., silicon) after performing the second etching process and then removing the second bottom sacrificial pattern 220P2 between the second bottom isolation pattern 170P2 adjacent to the first source / drain pattern 150A. In one or more embodiments, some of the etching processes can be combined. For example, the second etching process and the third etching process can be performed simultaneously. The contact hole OH can have a first step portion between the first hole portion OH1 and the second hole portion OH2a, and can have a second step portion between the second hole portion OH2a and the third hole portion OH2b. Through this process, the contact hole OH for the lower contact structure can be precisely aligned with the first source / drain pattern 150A. A lower contact structure 280 connected to the first source / drain pattern 150A can be formed in the precisely aligned contact hole OH. Then, as shown in FIG. 1B, the semiconductor device 100B can be provided by forming a backside interconnect structure 290 connected to the lower contact structure 280. FIG. 8

[0137] According to one or more embodiments, a bottom isolation pattern can be introduced under the channel layer and the gate structure, and a bottom contact structure can be self-aligned using a bottom sacrificial pattern provided between the bottom isolation patterns.

[0138] Each of the embodiments provided in the above description does not exclude association with one or more features of another example or another embodiment also provided herein or not provided herein but consistent with the disclosure.

[0139] While the disclosure has been particularly shown and described with reference to the disclosed embodiments, it will be understood that various changes in form and details can be made therein without departing from the spirit and scope of the appended claims.​

Claims

1. A semiconductor device, comprising: Insulating base layer; A fin-shaped pattern is formed on the insulating base layer and extends in the first direction; Multiple channel structures are spaced apart from each other on a fin pattern and in a first direction, each of the multiple channel structures comprising multiple channel layers spaced apart from each other in a second direction perpendicular to the first direction; Multiple gate structures are respectively surrounding the multiple channel structures and extending upward on a third side intersecting the first direction; Source / drain pattern, including a first source / drain pattern connected to the side surfaces of some of the plurality of channel structures; Multiple internal spacers are located between the multiple gate structures and the source / drain patterns; Multiple bottom isolation patterns are respectively located below the multiple gate structures and between the insulating base layer and the fin pattern. The multiple bottom isolation patterns are spaced apart from each other in a first direction and include the same material as the multiple internal spacers. as well as The lower contact structure penetrates the insulating base layer and connects to the first source / drain pattern, passing between the first bottom isolation patterns adjacent to the first source / drain pattern among the plurality of bottom isolation patterns.

2. The semiconductor device of claim 1, wherein, The source / drain pattern also includes: a second source / drain pattern, and The semiconductor device further includes an upper contact structure connected to a second source / drain pattern.

3. The semiconductor device of claim 2, further comprising: The bottom sacrificial pattern is between the second bottom isolation patterns that are adjacent to the second source / drain pattern among the plurality of bottom isolation patterns.

4. The semiconductor device as claimed in claim 3, wherein, In the first direction, the width of the bottom sacrificial pattern is smaller than the width of each of the second bottom isolation patterns adjacent to the second source / drain pattern.

5. The semiconductor device of claim 3, wherein, In the first direction, the width of the bottom sacrificial pattern is the same as the width of the portion of the lower contact structure between the first bottom isolation pattern and the first source / drain pattern.

6. The semiconductor device of claim 3, wherein, Each of the plurality of channel layers comprises silicon, and The bottom sacrificial pattern includes silicon and germanium.

7. The semiconductor device of claim 3, further comprising: The vertical sacrificial pattern lies below the second source / drain pattern and extends toward the insulating base layer. Each of the second bottom isolation patterns adjacent to the second source / drain pattern includes a portion extending into the vertical sacrificial pattern.

8. The semiconductor device of claim 1, wherein, The portion of the lower contact structure between the first bottom isolation pattern adjacent to the first source / drain pattern has a smaller width than the portion of the lower contact structure below the first bottom isolation pattern adjacent to the first source / drain pattern.

9. The semiconductor device of claim 1, wherein, The lower contact structure includes: a contact plug and an insulating liner that electrically isolates the contact plug from the fin pattern.

10. The semiconductor device of claim 1, wherein, Each of the plurality of bottom isolation patterns has a thickness smaller than the thickness of the gap between the plurality of channel layers.

11. The semiconductor device of claim 10, wherein, Each of the plurality of bottom isolation patterns has a width in a first direction that is greater than the width of each of the plurality of channel layers in the first direction.

12. The semiconductor device of claim 1, wherein, At least one of the plurality of bottom isolation patterns includes a gap.

13. The semiconductor device of claim 1, wherein, Each of the plurality of internal spacers has at least one side surface that contacts at least one gate insulating portion of the plurality of gate structures, and Each of the plurality of internal spacers has at least one side surface with a concave side surface.

14. The semiconductor device of claim 1, wherein, In a cross-section along the first direction, each of the plurality of internal spacers is wider at its upper and lower ends than its middle portion along the second direction.

15. A semiconductor device, comprising: Insulating base layer; A fin-shaped structure, on an insulating base layer, extending in a first direction; Multiple channel structures are spaced apart from each other in a first direction, and each of the multiple channel structures includes multiple channel layers spaced apart from each other in a second direction perpendicular to the first direction; Multiple gate structures are respectively surrounding the multiple channel structures and extending upward on a third side intersecting the first direction; Source / drain pattern, including a first source / drain pattern connected to the side surfaces of some of the plurality of channel structures; Internal spacers are located between the plurality of gate structures and the source / drain patterns; as well as The lower contact structure penetrates the insulating base layer and connects to the first source / drain pattern. The fin-shaped structure includes: The first fin pattern and the second fin pattern are on the insulating base layer. A plurality of first bottom isolation patterns are respectively located below the plurality of gate structures and spaced apart from each other in a first direction, the plurality of first bottom isolation patterns being located between the insulating base layer and the first fin pattern, and A plurality of second bottom isolation patterns are respectively located below the plurality of gate structures and spaced apart from each other in a first direction, the plurality of second bottom isolation patterns being located between the first fin pattern and the second fin pattern. Each of the plurality of first bottom isolation patterns and the plurality of second bottom isolation patterns includes the same material as the material of the inner spacer, and The lower contact structure penetrates between the third bottom isolation pattern adjacent to the first source / drain pattern among the plurality of first bottom isolation patterns and between the fourth bottom isolation pattern adjacent to the first source / drain pattern among the plurality of second bottom isolation patterns.

16. The semiconductor device of claim 15, wherein, The source / drain pattern also includes: a second source / drain pattern. The semiconductor device further includes: an upper contact structure connected to a second source / drain pattern, and The fin-shaped structure also includes: The first bottom sacrificial pattern, between the fifth bottom isolation pattern adjacent to the second source / drain pattern among the plurality of first bottom isolation patterns, and The second bottom sacrificial pattern is disposed between the sixth bottom isolation pattern, which is adjacent to the second source / drain pattern, among the plurality of second bottom isolation patterns.

17. The semiconductor device of claim 15, wherein, The first thickness of each of the plurality of first bottom isolation patterns is greater than the second thickness of each of the plurality of second bottom isolation patterns, and The first thickness and the second thickness are smaller than the thickness of the gap between the plurality of channel layers.

18. The semiconductor device of claim 17, wherein, In a first direction, the first width of each of the plurality of first bottom isolation patterns is smaller than the second width of each of the plurality of second bottom isolation patterns.

19. The semiconductor device of claim 15, wherein, At least one of the plurality of first bottom isolation patterns and the plurality of second bottom isolation patterns includes a gap.

20. A semiconductor device, comprising: Insulating base layer; Multiple channel layers, on an insulating base layer, and spaced apart from each other; A gate structure surrounding the plurality of channel layers; First source / drain pattern and second source / drain pattern on insulating base layer; An internal spacer is located between the gate structure and the first source / drain pattern and the second source / drain pattern; The bottom isolation pattern, on the upper surface of the insulating base layer and below the plurality of channel layers, comprises the same material as the inner spacers; The first contact structure penetrates the insulating base layer and connects to the first source / drain pattern; The second contact structure is connected to the second source / drain pattern; as well as The bottom sacrificial pattern is located below the second source / drain pattern and at the same height as the bottom isolation pattern.

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