Solar cell and manufacturing method thereof, photovoltaic module

Abstract

The embodiment of the present disclosure relates to the photovoltaic field, and provides a solar cell, a manufacturing method thereof and a photovoltaic module, wherein the solar cell can comprise: a substrate, a back surface comprising a first region, a second region and a spacing region arranged at intervals, the spacing region comprising a platform region and a transition region, a spacing between the first region and a front surface being a first spacing, a spacing between the platform region and the front surface being a second spacing, a spacing between the second region and the front surface being a third spacing, the first spacing being greater than the second spacing, the second spacing being greater than the third spacing, the transition region extending from the platform region to the second region, and the transition region being provided with a first textured structure; a tunneling layer, the tunneling layer being located on the first region; a first doped conductive layer, the first doped conductive layer covering a surface of the tunneling layer; an amorphous silicon layer, the amorphous silicon layer covering at least surfaces of the second region and the spacing region; a second doped conductive layer, the second doped conductive layer covering a surface of the amorphous silicon layer away from the substrate; a first electrode; and a second electrode. The reliability of the solar cell can be improved.

Description

Technical Field

[0001] This disclosure relates to the photovoltaic field, and in particular to a solar cell and its manufacturing method, and a photovoltaic module. Background Technology

[0002] Currently, with the gradual depletion of fossil fuels, solar cells are becoming increasingly widely used as a new energy alternative. A solar cell is a device that converts solar energy into electrical energy. Solar cells utilize the photovoltaic principle to generate charge carriers, and then use electrodes to extract these carriers, thus facilitating the efficient use of electrical energy. Summary of the Invention

[0003] This disclosure provides a solar cell and a method for manufacturing the same, as well as a photovoltaic module, which can at least improve the reliability of the solar cell.

[0004] According to some embodiments of this disclosure, one aspect of this disclosure provides a solar cell, comprising: a substrate, the substrate including a front side and a back side opposite to each other, the back side including a first region and a second region arranged at intervals, and an interval region located between the first region and the second region, the interval region including a plateau region and a transition region, the plateau region being adjacent to the first region, the transition region being located between the plateau region and the second region, the distance between the first region and the front side being a first distance, the distance between the plateau region and the front side being a second distance, the distance between the second region and the front side being a third distance, the first distance being greater than the second distance being greater than the third distance, the transition region extending from the plateau region to the second region, and the transition region having a first textured structure; a tunneling layer, the tunneling layer being located on the first region; a first doped conductive layer, the first doped conductive layer covering the surface of the tunneling layer away from the substrate; an amorphous silicon layer, the amorphous silicon layer at least covering the surfaces of the second region and the interval region; a second doped conductive layer, the second doped conductive layer covering the surface of the amorphous silicon layer away from the substrate; a first electrode, the first electrode being electrically connected to the first doped conductive layer; and a second electrode, the second electrode being electrically connected to the second doped conductive layer.

[0005] In some embodiments, the angle between the surface of the transition region and the surface of the platform region is 130° to 150°.

[0006] In some embodiments, the height difference between the platform area and the second area along the thickness direction of the substrate is a first height, the distance between the platform area and the second area along the direction from the first area to the second area is a first width, and the ratio between the first height and the first width is 0.4 to 1.2.

[0007] In some embodiments, the first width is 5μm to 10μm, and / or the first height is 4μm to 6μm.

[0008] In some embodiments, the width of the platform region is 100nm~500nm along the direction from the first region to the second region.

[0009] In some embodiments, the second region is provided with a second velvet structure, and the size of the first velvet structure is smaller than the size of the second velvet structure.

[0010] In some embodiments, the first velvet structure comprises a plurality of columnar portions.

[0011] In some embodiments, the amorphous silicon layer further covers the top surface of the portion of the first doped conductive layer, and the thickness of the amorphous silicon layer located on the top surface of the first doped conductive layer is greater than the thickness of the amorphous silicon layer located in the transition region.

[0012] In some embodiments, the thickness of the amorphous silicon layer located on the top surface of the first doped conductive layer is 6 nm to 7 nm, and / or the thickness of the amorphous silicon layer located in the transition region is 4 nm to 5 nm.

[0013] According to some embodiments of this disclosure, another aspect of this disclosure provides a method for manufacturing a solar cell, comprising: providing a substrate, the substrate including a front side and a back side opposite to each other, the back side including a first region and a second region arranged at intervals, and an interval region located between the first region and the second region, the interval region including a plateau region and a transition region, the plateau region being adjacent to the first region, and the transition region being located between the plateau region and the second region; forming a tunneling layer, the tunneling layer being located on the first region; forming a first doped conductive layer, the first doped conductive layer covering the surface of the tunneling layer away from the substrate; etching the transition region and the second region of the substrate, the thickness of the transition region gradually decreasing along the direction from the first region to the second region, the transition region having a first textured structure; forming an amorphous silicon layer, the amorphous silicon layer at least covering the surface of the second region and the interval region; forming a second doped conductive layer, the second doped conductive layer covering the surface of the amorphous silicon layer away from the substrate; forming a first electrode, the first electrode being electrically connected to the first doped conductive layer; and forming a second electrode, the second electrode being electrically connected to the second doped conductive layer.

[0014] In some embodiments, the process parameters for etching the substrate include: a concentration of 2% to 3% for the etching reagent, a concentration of 0.6% to 1% for the additive, a process temperature of 75°C to 80°C, and a process time of 100s to 300s.

[0015] In some embodiments, etching the transition region and the second region of the substrate further includes: performing a texturing process, wherein the texturing process forms a second textured surface structure on the surface of the second region, and the process parameters of the texturing process include: the concentration of the etching reagent is 2%~3%, the concentration of the additive is 0.8%~1.5%, the process temperature is 75℃~80℃, and the process time is 500s~700s.

[0016] In some embodiments, the method of forming the amorphous silicon layer includes forming the amorphous silicon layer by chemical vapor deposition at a process temperature of less than or equal to 250°C.

[0017] According to some embodiments of this disclosure, another aspect of this disclosure also provides a photovoltaic module, including: a battery string, the battery string including: a plurality of solar cells as described above, or solar cells formed by the method of manufacturing solar cells as described above; a solder ribbon, the solder ribbon being electrically connected to at least two of the solar cells to connect adjacent solar cells in series; an encapsulating film, the encapsulating film being used to cover the surface of the battery string; and a cover plate, the cover plate being used to cover the surface of the encapsulating film away from the battery string.

[0018] The technical solution provided by the embodiments of this disclosure has at least the following advantages: a platform region and a transition region are provided between the first region and the second region to facilitate the transition between the first region and the second region, avoiding a sudden change in height between the first region and the second region. This allows the amorphous silicon layer to cover the surface of the spacer region relatively uniformly during the formation of the amorphous silicon layer, thereby improving the passivation effect of the amorphous silicon layer on the substrate. At the same time, a first textured structure is provided on the transition region. The transition region with the first textured structure can improve the adhesion of the amorphous silicon layer material, thereby improving the uniformity of the formed amorphous silicon layer and the passivation effect of the amorphous silicon layer. Attached Figure Description

[0019] One or more embodiments are illustrated by way of example with corresponding pictures in the accompanying drawings. These illustrations do not constitute a limitation on the embodiments. Unless otherwise stated, the pictures in the accompanying drawings do not constitute a limitation on scale. In order to more clearly illustrate the technical solutions in the embodiments of this disclosure or the conventional technology, the drawings used in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this disclosure. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0020] Figure 1 This is a schematic diagram of the structure of a solar cell provided in one embodiment of the present disclosure;

[0021] Figure 2This is a schematic diagram of a SEM structure provided in an embodiment of the present disclosure;

[0022] Figure 3 This is a schematic diagram of the structure of a substrate provided in one embodiment of the present disclosure;

[0023] Figure 4 This is a schematic diagram of a structure for forming a tunneling layer according to an embodiment of the present disclosure;

[0024] Figure 5 This is a schematic diagram of a structure for forming a first doped conductive layer according to an embodiment of the present disclosure;

[0025] Figure 6 This is a schematic diagram of a structure for forming a front passivation layer and a front antireflection layer according to an embodiment of the present disclosure;

[0026] Figure 7 This is a schematic diagram of a structure for forming an amorphous silicon layer and a second doped conductive layer according to an embodiment of the present disclosure;

[0027] Figure 8 This is a schematic diagram of a structure for forming a first conductive layer and a second conductive layer according to an embodiment of the present disclosure;

[0028] Figure 9 A partial perspective view of a photovoltaic module provided in yet another embodiment of this disclosure;

[0029] Figure 10 This is a partial cross-sectional view of a photovoltaic module provided in yet another embodiment of the present disclosure.

[0030] Explanation of reference numerals in the attached figures

[0031] 100, Substrate; 110, Front side; 120, Back side; 130, First region; 140, Second region; 150, Spacer region; 160, Plateau region; 170, Transition region; 180, First textured structure; 101, Tunneling layer; 102, First doped conductive layer; 103, Amorphous silicon layer; 104, Second doped conductive layer; 105, First electrode; 106, Second electrode; 107, First conductive layer; 108, Second conductive layer; 109, Front passivation layer; 200, Front antireflection layer.

[0032] 40. Solar cell; 41. Encapsulating film; 42. Cover plate; 43. Solder strip. Detailed Implementation

[0033] Currently, during the formation of amorphous silicon layers, the height difference between the first and second regions makes it difficult for the amorphous silicon layer to adhere to the spacer region, resulting in uneven deposition of the amorphous silicon layer and a decrease in its passivation capability.

[0034] In this embodiment, a platform region and a transition region are provided between the first region and the second region to facilitate the transition between the first region and the second region, avoiding abrupt changes in height between the first region and the second region. This allows the amorphous silicon layer to cover the surface of the spacer region relatively uniformly during the formation of the amorphous silicon layer, thereby improving the passivation effect of the amorphous silicon layer on the substrate. Simultaneously, a first textured structure is provided on the transition region. The transition region with the first textured structure can improve the adhesion of the amorphous silicon layer material, thereby improving the uniformity of the formed amorphous silicon layer and enhancing the passivation effect of the amorphous silicon layer.

[0035] In the description of the embodiments of this disclosure, technical terms such as "first" and "second" are used only to distinguish different objects and should not be construed as indicating or implying relative importance or implicitly specifying the number, specific order, or primary or secondary relationship of the indicated technical features. In the description of the embodiments of this disclosure, "a plurality of" means two or more, unless otherwise explicitly defined.

[0036] In this document, the term "embodiment" means that a particular feature, structure, or characteristic described in connection with an embodiment may be included in at least one embodiment of this disclosure. The appearance of this phrase in various places throughout the specification does not necessarily refer to the same embodiment, nor is it a separate or alternative embodiment mutually exclusive with other embodiments. It will be explicitly and implicitly understood by those skilled in the art that the embodiments described herein can be combined with other embodiments.

[0037] In the description of the embodiments of this disclosure, the term "and / or" is merely a description of the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent three cases: A exists, A and B exist simultaneously, and B exists. Additionally, the character " / " in this document generally indicates that the preceding and following related objects have an "or" relationship.

[0038] In the description of embodiments of this disclosure, the term "multiple" refers to two or more (including two), similarly, "multiple sets" refers to two or more (including two sets), and "multiple pieces" refers to two or more (including two pieces).

[0039] In the description of the embodiments of this disclosure, the technical terms "center," "longitudinal," "lateral," "length," "width," "thickness," "upper," "lower," "front," "rear," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," "outer," "clockwise," "counterclockwise," "axial," "radial," and "circumferential" indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are only for the convenience of describing the embodiments of this disclosure and simplifying the description, and are not intended to indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on the embodiments of this disclosure.

[0040] In the description of the embodiments of this disclosure, unless otherwise expressly specified and limited, technical terms such as "installation," "connection," "joining," and "fixing" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral part; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; they can refer to the internal communication of two components or the interaction between two components. Those skilled in the art can understand the specific meaning of the above terms in the embodiments of this disclosure according to the specific circumstances.

[0041] In the accompanying drawings corresponding to the embodiments of this disclosure, the thickness and area of ​​the layers are enlarged for better understanding and ease of description. When describing a component (such as a layer, film, region, or substrate) on or on the surface of another component, the component may be "directly" located on the surface of the other component, or there may be a third component between the two components. Conversely, when describing a component on the surface of another component, or when another component is formed or disposed on the surface of a component, it indicates that there is no third component between the two components. Furthermore, when describing a component as being "generally" formed on another component, it means that the component is not formed on the entire surface (or front surface) of the other component, nor is it formed on a portion of the edge of the entire surface.

[0042] In the description of embodiments of this disclosure, when a component "includes" another component, other components are not excluded unless otherwise stated, and may be further included. Furthermore, when a component such as a layer, film, region, or plate is referred to as being "on / located" on another component, it can be "directly" on the other component (i.e., located on the surface of the other component with no other components between them), or another component may be present therein. Additionally, when a component such as a layer, film, region, or plate is "directly located" on another component, or when a component such as a layer, film, region, or plate is located on the surface of another component, it indicates that no other components are located therein.

[0043] The terminology used in the description of the various embodiments herein is for the purpose of describing particular embodiments only and is not intended to be limiting. As used in the description and claims of the various embodiments described, the term "component" is also intended to include the plural form unless the context clearly indicates otherwise. Components include layers, films, regions, or plates, etc.

[0044] The embodiments of this disclosure will now be described in detail with reference to the accompanying drawings. However, those skilled in the art will understand that many technical details have been provided in the embodiments of this disclosure to facilitate a better understanding of the disclosure. However, the technical solutions claimed in this disclosure can be implemented even without these technical details and various variations and modifications based on the following embodiments.

[0045] refer to Figure 1 and Figure 2 , Figure 1 This is a schematic diagram of the structure of a solar cell according to an embodiment of the present disclosure. Figure 2 This is a schematic diagram of a SEM structure provided in an embodiment of the present disclosure.

[0046] In some embodiments, the solar cell may include: a substrate 100, the substrate 100 including a front side 110 and a back side 120 opposite to each other, the back side 120 including a first region 130 and a second region 140 arranged at intervals, and a gap region 150 located between the first region 130 and the second region 140, the gap region 150 including a platform region 160 and a transition region 170, the platform region 160 being adjacent to the first region 130, the transition region 170 being located between the platform region 160 and the second region 140, the distance between the first region 130 and the front side 110 being a first distance, the distance between the platform region 160 and the front side 110 being a second distance, the distance between the second region 140 and the front side 110 being a third distance, the first distance being greater than the second distance being greater than the third distance, the transition region 170 extending from the platform region 160 to the second region 140, and the transition region 170 being provided with a first textured surface structure 180.

[0047] The solar cell may also include a tunneling layer 101, which is located on the first region 130.

[0048] The solar cell may further include: a first doped conductive layer 102, which covers the surface of the tunneling layer 101 away from the substrate 100.

[0049] The solar cell may also include an amorphous silicon layer 103, which at least covers the surfaces of the second region 140 and the spacer region 150.

[0050] The solar cell may further include a second doped conductive layer 104, which covers the surface of the amorphous silicon layer 103 away from the substrate 100.

[0051] The solar cell may also include a first electrode 105, which is electrically connected to a first doped conductive layer 102.

[0052] The solar cell may also include a second electrode 106, which is electrically connected to the second doped conductive layer 104.

[0053] In this embodiment, a platform region 160 and a transition region 170 are provided between the first region 130 and the second region 140. The platform region 160 and the transition region 170 serve as a transition between the first region 130 and the second region 140, avoiding abrupt changes in height between the first region 130 and the second region 140. This allows the amorphous silicon layer 103 to cover the surface of the spacer region 150 relatively uniformly during the formation of the amorphous silicon layer 103, thereby improving the passivation effect of the amorphous silicon layer 103 on the substrate 100. At the same time, a first textured structure 180 is provided on the transition region 170. The transition region 170 with the first textured structure 180 can improve the adhesion of the amorphous silicon layer 103 material, thereby improving the uniformity of the formed amorphous silicon layer 103 and enhancing the passivation effect of the amorphous silicon layer 103.

[0054] In some embodiments, the solar cell is a single-sided cell, in which case the front side 110 of the substrate 100 can serve as a light-receiving surface to receive incident light, and the back side 120 serves as a backlighting surface. In some embodiments, the cell is a double-sided cell, in which case both the front side 110 and the back side 120 of the substrate 100 can serve as light-receiving surfaces and can both be used to receive incident light. It is understood that the backlighting surface referred to in the embodiments of this disclosure can also receive incident light, but the degree of reception of incident light is weaker than that of the light-receiving surface, and therefore it is defined as a backlighting surface.

[0055] A texturing process can be performed on the front side 110 of the substrate 100 to form a textured surface, thereby enhancing the absorption and utilization rate of incident light on the front side 110 of the substrate 100. In some embodiments, the textured surface can be a pyramid textured surface. As a common textured surface, pyramid textured surface not only reduces the reflectivity of the substrate 100 surface but also forms light traps, enhancing the absorption effect of the substrate 100 on incident light and improving the photoelectric conversion efficiency of the solar cell.

[0056] The first region 130 of the substrate 100 is used to cooperate with the first doped conductive layer 102 to complete the collection of the first type of charge carriers, and the second region 140 of the substrate 100 is used to cooperate with the second doped conductive layer 104 to complete the collection of the second type of charge carriers, thereby cooperating with the first electrode 105 and the second electrode 106 for output; the spacer region 150 is used to separate the first region 130 and the second region 140, thereby avoiding contact between the first doped conductive layer 102 and the second doped conductive layer 104, so as to improve the insulation between the first doped conductive layer 102 and the second doped conductive layer 104.

[0057] The plateau region 160 of the spacer region 150 serves as a transition between the height difference between the first region 130 and the second region 140, while the transition region 170 serves as a connection between the plateau region 160 and the second region 140, thereby making the passivation layer formed more uniform in the subsequent formation of the amorphous silicon layer 103 and the passivation layer.

[0058] In some embodiments, the angle between the surface of the transition region 170 and the surface of the platform region 160 is 130° to 150°, for example, 130°, 135°, 140°, 145° or 150°, etc. It is understandable that the larger the angle between the surface of the transition region 170 and the surface of the platform region 160, the smoother the transition from the platform region 160 to the second region 140. In the subsequent formation of the amorphous silicon layer 103, the more uniform the amorphous silicon layer 103 coverage, the better the passivation effect provided by the amorphous silicon layer 103, which can improve the carrier transport capability. When the angle between the surface of the transition region 170 and the surface of the platform region 160 is too large, it means that the size of the spacer region 150 is too large, or the difference between the second spacing and the third spacing is too small. If the size of the spacer region 150 is too large, it will cause the size of the first doped conductive layer 102 and the second doped conductive layer 104 to decrease, affecting the ability of the first doped conductive layer 102 and the second doped conductive layer 104 to collect carriers. If the difference between the second spacing and the third spacing is too small, it means that not much substrate 100 was etched in the process of forming the first doped conductive layer 102, which will increase the difficulty of the solar cell manufacturing method.

[0059] Understandably, when forming the first doped conductive layer 102, it is typically formed to cover the entire back surface 120. Subsequently, the first doped conductive layer 102 located in the spacer region 150 and the second region 140 is removed by etching. During the etching process, in order to completely remove the first doped conductive layer 102 located in the spacer region 150 and the second region 140, a portion of the substrate 100 is etched. Therefore, the first region 130, the second region 140, and the spacer region 150 are formed on the back surface 120 with different heights. If the difference between the second and third spacings is too small, it means that more precise control is required during the etching of the first doped conductive layer 102 located in the spacer region 150 and the second region 140, increasing the difficulty of etching the first doped conductive layer 102.

[0060] In some embodiments, along the thickness direction of the base 100, the height difference between the platform region 160 and the second region 140 is the first height, and along the direction from the first region 130 to the second region 140, the distance between the platform region 160 and the second region 140 is the first width. The ratio between the first height and the first width is 0.4 to 1.2, for example, 0.4, 0.6, 0.8, 1.0, or 1.2, etc. Understandably, if the ratio between the first height and the first width is larger, the slope of the transition region 170 will be greater, and the slope from the platform region 160 to the second region 140 will be steeper, which will increase the difficulty of attaching the amorphous silicon layer 103 and affect the reliability of the amorphous silicon layer 103. If the ratio between the first height and the first width is too small, although the slope from the platform region 160 to the second region 140 will be gentler, it will result in the width of the spacing region 150 being too large. Under the condition that the size of the solar cell is fixed, this will affect the coverage area of ​​the second doped conductive layer 104, resulting in a decrease in the ability of the second doped conductive layer 104 to collect charge carriers. Therefore, setting the ratio between the first height and the first width to 0.4 to 1.2 takes into account improving the reliability of the amorphous silicon layer 103 while avoiding affecting the ability of the solar cell to collect charge carriers.

[0061] It is understandable that the ratio between the first height and the first width also affects the angle between the surface of the transition region 170 and the surface of the platform region 160. The larger the ratio between the first height and the first width, the smaller the angle between the surface of the transition region 170 and the surface of the platform region 160. The smaller the ratio between the first height and the first width, the larger the angle between the surface of the transition region 170 and the surface of the platform region 160.

[0062] In some embodiments, the first width is 5μm to 10μm, for example, 5μm, 6μm, 7μm, 8μm, 9μm, or 10μm. If the first width is greater than 10μm, the width of the spacer region 150 will be too large, which will affect the coverage area of ​​the second doped conductive layer 104 when the cell size is fixed, resulting in a decrease in the ability of the second doped conductive layer 104 to collect charge carriers. If the first width is less than 5μm, it will also affect the angle between the surface of the transition region 170 and the surface of the plateau region 160, resulting in an excessively large angle between the surface of the transition region 170 and the surface of the plateau region 160, affecting the adhesion of the amorphous silicon layer 103 on the surface of the transition region 170, and affecting the reliability of the connection between the amorphous silicon layer 103 and the substrate 100.

[0063] In some embodiments, the first height is 4μm to 6μm, such as 4μm, 4.2μm, 4.5μm, 5μm, 5.6μm, or 6μm, etc. If the first height is greater than 6μm, the surface tilt of the transition region 170 will be too large, which will affect the adhesion of the amorphous silicon layer 103 material on the surface of the transition region 170 when the amorphous silicon layer 103 is formed, and will affect the passivation effect of the amorphous silicon layer 103. If the first height is less than 4μm, the height difference between the platform region 160 and the first region 130 will be too large, which will affect the reliability of the amorphous silicon layer 103 covering the sidewall of the first region 130.

[0064] In some embodiments, the width of the platform region 160 along the direction from the first region 130 to the second region 140 is 100nm to 500nm, for example, 100nm, 150nm, 200nm, 280nm, 350nm, 440nm, or 500nm, etc. It is understood that the formation efficiency of the amorphous silicon layer 103 on the platform region 160 is greater than that on the transition region 170. Therefore, by controlling the width of the platform region 160, the size of the thicker amorphous silicon layer 103 can be controlled, thereby reducing the width of the thicker portions of the deposited amorphous silicon layer 103 and further improving the uniformity of the thickness of different regions of the amorphous silicon layer 103. This improves the passivation effect of the amorphous silicon layer 103.

[0065] In some embodiments, a second textured structure is provided on the second region 140, and the size of the first textured structure 180 is smaller than the size of the second textured structure. The first textured structure 180 is used to increase the surface roughness of the transition region 170 to further improve the deposition quality of the amorphous silicon layer 103, thereby improving the passivation effect of the amorphous silicon layer 103. The second textured structure is used to reflect light transmitted to the second region 140 back into the substrate 100 to increase the light absorption rate of the substrate 100. Therefore, the size of the first textured structure 180 does not need to be too large; it is sufficient to set the first textured structure 180 to have a certain size to increase the surface roughness of the transition region 170. Reducing the size of the first textured structure 180 can also reduce the etching of the transition region 170, thereby reducing damage to the substrate 100.

[0066] In some embodiments, the first velvet structure 180 is composed of a plurality of columnar portions, as shown in the reference. Figure 2 , Figure 2 The image shows a SEM image of the transition region 170. It can be seen that the surface of the transition region 170 is composed of multiple interconnected columnar parts. Since the sides of the columnar parts are arc-shaped, they are interconnected to form a structure similar to a half-wave shape.

[0067] In some embodiments, the tunneling layer 101 has a chemical passivation effect on the substrate 100, reducing the defect state density of the substrate 100 by saturating the dangling bonds on the surface of the substrate 100.

[0068] The material of the tunneling layer 101 may include dielectric materials with tunneling properties such as silicon oxide, silicon nitride, silicon oxynitride, intrinsic amorphous silicon, and intrinsic polycrystalline silicon.

[0069] The thickness of the tunneling layer 101 can be 1.2nm to 2nm, for example, 1.2nm, 1.3nm, 1.5nm, 1.8nm, or 2nm, etc. It is understandable that the thicker the tunneling layer 101, the better the passivation effect of the substrate 100. However, if the thickness of the tunneling layer 101 is too thick, it will affect the tunneling of charge carriers. Therefore, the thickness of the tunneling layer 101 is set to 1.2nm to 2nm.

[0070] The first doped conductive layer 102 serves to collect charge carriers. Taking the N-type ions doped in the first doped conductive layer 102 as an example, the first doped conductive layer 102 collects electrons in the substrate 100 and transmits them to the first electrode 105, from which they are output.

[0071] The first doped conductive layer 102 also serves as a field passivation layer. The first doped conductive layer 102 forms an electrostatic field pointing towards the interior of the substrate 100 on the back side 120 of the substrate 100, causing minority carriers to escape from the interface, thereby reducing the minority carrier concentration and reducing the carrier recombination rate at the interface of the substrate 100. This increases the open-circuit voltage, short-circuit current, and fill factor of the solar cell, thereby improving the photoelectric conversion efficiency of the solar cell.

[0072] The material of the first doped conductive layer 102 may include at least one of amorphous silicon, polycrystalline silicon, or silicon carbide.

[0073] In some embodiments, the amorphous silicon layer 103 also covers the top surface and sidewalls of the first doped conductive layer 102 near the spacer region 150. Here, the top surface refers to the surface of the first doped conductive layer 102 away from the substrate 100, and the sidewalls refer to the surface of the first doped conductive layer 102 facing the second region 140.

[0074] In some embodiments, the thickness of the amorphous silicon layer 103 located on the top surface of the first doped conductive layer 102 is greater than the thickness of the amorphous silicon layer 103 located in the transition region 170. It is understood that the top surface of the first doped conductive layer 102 is close to a plane, and the efficiency of forming the amorphous silicon layer 103 on a plane is higher. The transition region 170 is a slope, and the efficiency of forming the amorphous silicon layer 103 on a slope is lower. Therefore, in the same amount of time, the thickness of the amorphous silicon layer 103 formed on the top surface of the first doped conductive layer 102 is greater.

[0075] Similarly, the thickness of the amorphous silicon layer 103 formed on the plateau region 160 is greater than the thickness of the amorphous silicon layer 103 located in the transition region 170. It can be understood that there is a height difference between the first region 130 and the plateau region 160, and the amorphous silicon layer 103 located in the first region 130 is situated on the top surface of the first doped conductive layer 102, further increasing the height difference between the amorphous silicon layer 103 in the first region 130 and the amorphous silicon layer 103 in the plateau region 160. Therefore, the thickness of the amorphous silicon layer 103 located on the sidewall of the first doped conductive layer 102 is less than the thickness of the amorphous silicon layer 103 located in the plateau region 160. Simultaneously, the transition region 170 is sloped, and the thickness of the amorphous silicon layer 103 located in the transition region 170 is less than the thickness of the amorphous silicon layer 103 located in the plateau region 160. The thickness of layer 103 results in uneven thickness of the entire amorphous silicon layer 103. Uneven thickness of the amorphous silicon layer 103 reduces its passivation capability. Therefore, on the one hand, the embodiment of this disclosure retains the platform region 160 to avoid the existence of only a slope between the first region 130 and the transition region 170, which would lead to an excessive thickness difference between the amorphous silicon layer 103 in the transition region 170 and the amorphous silicon layer 103 in the first region 130, further reducing the passivation capability of the amorphous silicon layer 103. On the other hand, a first textured structure 180 is provided on the transition region 170 to increase the surface roughness of the transition region 170 to facilitate the deposition of the amorphous silicon layer 103, thereby reducing the thickness difference of the amorphous silicon layer 103 in different regions and improving the passivation contact effect of the amorphous silicon layer 103.

[0076] Meanwhile, the angle between the surface of the transition region 170 and the surface of the platform region 160 is set to 130°~150°. By reducing the tilt of the transition region 170, the efficiency of forming the amorphous silicon layer 103 in the transition region 170 is further improved, so that the thickness of the amorphous silicon layer 103 is relatively uniform and the passivation effect of the amorphous silicon layer 103 is improved.

[0077] In some embodiments, the thickness of the amorphous silicon layer 103 located on the top surface of the first doped conductive layer 102 is 6nm to 7nm, for example, 6nm, 6.2nm, 6.5nm, 6.7nm or 7nm, and / or the thickness of the amorphous silicon located in the transition region 170 is 4nm to 5nm, for example, 4nm, 4.2nm, 4.4nm, 4.7nm or 5nm, etc.

[0078] As can be seen, in this embodiment, although the thickness of the amorphous silicon layer 103 located in the transition region 170 is still different from the thickness of the amorphous silicon layer 103 located on the top surface of the first doped conductive layer 102, the difference between the thickness of the amorphous silicon layer 103 located in the transition region 170 and the thickness of the amorphous silicon layer 103 located on the top surface of the first doped conductive layer 102 is reduced by adjusting the angle between the transition region 170 and the platform region 160, thereby improving the relative uniformity of the thickness of each part of the amorphous silicon layer 103 and improving the passivation effect of the amorphous silicon layer 103.

[0079] The amorphous silicon layer 103 is made of intrinsic amorphous silicon. By utilizing the excellent surface passivation properties of intrinsic amorphous silicon, carrier recombination on the back surface can be significantly reduced. Furthermore, by using hydrogen atoms in intrinsic amorphous silicon to passivate dangling bonds, the surface state density is reduced, thereby reducing recombination and increasing the open-circuit voltage and fill factor. In addition, intrinsic amorphous silicon has low absorption of visible light, especially in the long wavelength range.

[0080] In this embodiment of the disclosure, by reducing the platform width and controlling the angle between the surface of the transition region 170 and the surface of the platform region 160, the minority carrier lifetime and photoluminescence brightness can be effectively improved. The photoluminescence brightness actually corresponds to the passivation effect. Therefore, by controlling the platform width and controlling the angle between the surface of the transition region 170 and the surface of the platform region 160, the minority carrier lifetime and the passivation effect of the amorphous silicon layer 103 can be effectively improved.

[0081] In some embodiments, the second doped conductive layer 104 may be an amorphous silicon layer doped with doped ions, such as doped with P-type dopant. The second doped conductive layer 104 serves to collect holes and transmit them via the second electrode 106.

[0082] A portion of the second doped conductive layer 104 is located above the first doped conductive layer 102 near the spacer region 150, and another portion of the second doped conductive layer 104 is located near the sidewall of the first doped conductive layer 102 near the spacer region 150. It is understood that the lateral transport capability of charge carriers within the amorphous silicon layer 103 is poor. Therefore, even if the second doped conductive layer 104 is located on the sidewall of the first doped conductive layer 102, there will be no problem of large-scale carrier recombination at the contact interface, nor will there be a large amount of leakage. Therefore, the amorphous silicon layer 103 can be directly positioned to contact the sidewall of the first doped conductive layer 102, thereby reducing the process of forming grooves or isolation layers on the back surface 120, and improving the carrier collection capability of the second doped conductive layer 104, thus improving the performance of the solar cell.

[0083] In some embodiments, the solar cell may further include a first conductive layer 107 located in the first region 130, which at least covers the top surface of the first doped conductive layer 102.

[0084] The first electrode 105 is electrically connected to the first conductive layer 107. The first conductive layer 107 collects the charge carriers in the first doped conductive layer 102 and uses the good lateral transport capability in the first conductive layer 107 to gather the charge carriers onto the first electrode 105.

[0085] The electrical connection between one component and another means that both components are made of conductive materials and are directly connected or connected via other conductive materials. Therefore, when the solar cell is generating electricity, there is current transfer between the two components.

[0086] In some embodiments, the material of the first conductive layer 107 may be at least one of tin-doped indium oxide, tungsten-doped indium oxide, cesium-doped indium oxide, tin oxide, aluminum-doped zinc oxide, and aluminum-zinc oxide. These materials have good light transmittance, do not block light, and also have a certain passivation effect, which can further improve the reliability of the solar cell.

[0087] The first conductive layer 107 can also cover the top surface of the second doped conductive layer 104 located on the first region 130.

[0088] In some embodiments, the solar cell may further include a second conductive layer 108, which is located at least in the second region 140, covers the top surface of the second doped conductive layer 104, and is spaced apart from the first conductive layer 107.

[0089] The second electrode 106 is electrically connected to the second conductive layer 108. The second conductive layer 108 collects the charge carriers in the second doped conductive layer 104 and utilizes the good lateral transport capability of the second conductive layer 108 to gather the charge carriers onto the second electrode 106.

[0090] In some embodiments, the material of the second conductive layer 108 may be at least one of tin-doped indium oxide, tungsten-doped indium oxide, cesium-doped indium oxide, tin oxide, aluminum-doped zinc oxide, and aluminum-zinc oxide. These materials have good light transmittance, do not block light, and also have a certain passivation effect, which can further improve the reliability of the solar cell.

[0091] The second conductive layer 108 may also cover part of the surface of the second doped conductive layer 104 located in the transition region 170.

[0092] The materials of the first electrode 105 and the second electrode 106 can be at least one of silver, gold, aluminum, copper, and nickel.

[0093] In some embodiments, the solar cell further includes a front passivation layer 109 and a front antireflection layer 200, wherein the front passivation layer 109 is a front passivation layer. The front passivation layer 109 can be a single-layer structure or a stacked structure, and the material of the front passivation layer 109 can be one or more of the following materials: silicon oxide, silicon nitride, silicon oxynitride, silicon carbonitride, titanium oxide, hafnium oxide, or aluminum oxide; the front antireflection layer 200 has a high refractive index to reduce frontal reflection damage, and the material of the front antireflection layer 200 can be any one or more of silicon nitride or silicon oxynitride.

[0094] In this embodiment, a platform region 160 and a transition region 170 are provided between the first region 130 and the second region 140. The platform region 160 and the transition region 170 serve as a transition between the first region 130 and the second region 140, avoiding abrupt changes in height between the first region 130 and the second region 140. This allows the amorphous silicon layer 103 to cover the surface of the spacer region 150 relatively uniformly during the formation of the amorphous silicon layer 103, thereby improving the passivation effect of the amorphous silicon layer 103 on the substrate 100. At the same time, a first textured structure 180 is provided on the transition region 170. The textured structure of the transition region 170 can improve the adhesion of the amorphous silicon layer 103 material, thereby improving the uniformity of the formed amorphous silicon layer 103 and enhancing the passivation effect of the amorphous silicon layer 103.

[0095] Another embodiment of this disclosure also provides a method for manufacturing a solar cell. This method can be used to form the aforementioned solar cell. The method for manufacturing a solar cell provided in another embodiment of this disclosure will be described below with reference to the accompanying drawings. It should be noted that the same or corresponding parts as those in the above embodiments can be referred to the above embodiments, and will not be repeated hereafter.

[0096] refer to Figures 3 to 8 and Figure 1 , Figures 3 to 8 and Figure 1 This is a schematic diagram of the structure corresponding to each step of a method for manufacturing a solar cell according to an embodiment of this disclosure.

[0097] In some embodiments, a method for manufacturing a solar cell may include: providing a substrate 100, the substrate 100 including a front side 110 and a back side 120 opposite to each other, the back side 120 including a first region 130 and a second region 140 spaced apart, and a spacer region 150 located between the first region 130 and the second region 140, the spacer region 150 including a platform region 160 and a transition region 170, the platform region 160 being adjacent to the first region 130, and the transition region 170 being located between the platform region 160 and the second region 140.

[0098] The method of manufacturing a solar cell may also include: forming a tunneling layer 101, which is located on the first region 130.

[0099] The method of manufacturing a solar cell may further include: forming a first doped conductive layer 102, wherein the first doped conductive layer 102 covers the surface of the tunneling layer 101 away from the substrate 100.

[0100] The method for manufacturing a solar cell may also include: etching the transition region 170 and the second region 140 of the substrate 100, the thickness of the transition region 170 gradually decreasing along the direction from the first region 130 to the second region 140, and a first textured structure 180 provided on the transition region 170.

[0101] The method of manufacturing a solar cell may further include: forming an amorphous silicon layer 103, wherein the amorphous silicon layer 103 at least covers the surfaces of the second region 140 and the spacer region 150.

[0102] The method for manufacturing a solar cell may further include: forming a second doped conductive layer 104, the second doped conductive layer 104 covering the surface of the amorphous silicon layer 103 away from the substrate 100.

[0103] The method for manufacturing a solar cell may further include: forming a first electrode 105, wherein the first electrode 105 is electrically connected to a first doped conductive layer 102.

[0104] The method for manufacturing a solar cell may further include: forming a second electrode 106, wherein the second electrode 106 is electrically connected to a second doped conductive layer 104.

[0105] refer to Figure 3 Provides a base of 100.

[0106] It is understandable that the substrate 100 can be cleaned and polished before forming the tunneling layer 101 on the substrate 100 to facilitate subsequent process steps.

[0107] refer to Figure 4 This forms tunnel layer 101.

[0108] In some embodiments, a tunneling layer 101 covering the entire back surface 120 can be formed on the back surface 120 using low-pressure chemical vapor deposition (LPCVD), where covering the entire back surface 120 means the tunneling layer 101 covering the entire back surface 120.

[0109] refer to Figure 5 The first doped conductive layer 102 is formed.

[0110] In some embodiments, a polysilicon layer may be formed on the surface of the tunneling layer 101 by low-pressure chemical vapor deposition (LPCVD), and then the polysilicon layer may be doped to form a doped conductive layer. The doped conductive layers of the spacer region 150 and the second region 140 may be removed, and the remaining doped conductive layer serves as the first doped conductive layer 102.

[0111] In some embodiments, a glass layer is formed on the surface of the doped conductive layer during the doping of the polysilicon layer. Therefore, a mask layer can be formed during the removal of the doped conductive layer. The mask layer has a mask pattern that exposes the doped conductive layer in the spacer region 150 and the second region 140. The doped conductive layer is then removed by etching.

[0112] In some embodiments, the mask layer may be made of silicon oxide or silicon nitride.

[0113] In some embodiments, after forming the first doped conductive layer 102, the substrate 100 is further etched. The process parameters for etching the substrate 100 may include: the concentration of the etching reagent is 2% to 3%, for example, 2%, 2.1%, 2.2%, 2.3%, 2.5%, 2.7%, 2.9% or 3%; the concentration of the additive is 0.6% to 1%, for example, 0.6%, 0.7%, 0.8%, 0.9% or 1%; the process temperature is 75°C to 80°C, for example, 75°C, 76°C, 77°C, 78°C, 79°C or 80°C; and the process time is 100s to 300s, for example, 100s, 150s, 180s, 200s, 250s, 270s or 300s.

[0114] The concentration of etching reagent, the concentration of additives, and the process temperature are related to the etching rate of substrate 100, while the process time is related to the etching depth of substrate 100. By controlling the concentration of etching reagent, the concentration of additives, the process temperature, and the process time, the etching depth of substrate 100 can be easily controlled.

[0115] In some embodiments, the size of the platform region 160 can be controlled by adjusting the type of additive during the etching process of the substrate 100.

[0116] In some embodiments, the transition region 170 and the second region 140 of the etched substrate 100 further include: performing a texturing process, wherein the texturing process forms a second textured surface structure on the surface of the second region 140, and the process parameters of the texturing process include: the concentration of the etching reagent is 2% to 3%, for example, 2%, 2.1%, 2.2%, 2.3%, 2.5%, 2.7%, 2.9% or 3%; the concentration of the additive is 0.8% to 1.5%, for example, 0.8%, 0.9%, 1%, 1.1%, 1.3% or 1.5%; the process temperature is 75°C to 80°C, for example, 75°C, 76°C, 77°C, 78°C, 79°C or 80°C; and the process time is 500s to 700s, for example, 500s, 550s, 580s, 600s, 650s, 670s or 700s.

[0117] The texturing process is used to form a second textured structure on the surface of the second region 140, so as to improve the uniformity of the subsequent formation of the amorphous silicon layer 103, thereby improving the passivation effect of the amorphous silicon layer 103.

[0118] refer to Figure 6 This forms a front passivation layer 109 and a front antireflection layer 200.

[0119] A front passivation layer 109 and a front antireflection layer 200 can be formed on the front side 110 of the substrate 100 by deposition.

[0120] refer to Figure 7 An amorphous silicon layer 103 and a second doped conductive layer 104 are formed.

[0121] In some embodiments, the method for forming the amorphous silicon layer 103 includes: forming the amorphous silicon layer 103 by chemical vapor deposition at a process temperature less than or equal to 250°C. It is understood that amorphous silicon materials will transform into polycrystalline silicon materials at high temperatures; therefore, it is necessary to control the process temperature below 250°C to avoid abnormalities in the amorphous silicon layer 103. Simultaneously, due to the low-temperature environment, chemical vapor deposition may result in uneven deposition at locations with height differences, such as the junction of the first region 130 and the plateau region 160, and the junction of the plateau region 160 and the transition region 170. Due to these height differences, the thickness of the amorphous silicon layer 103 at different locations will vary. The amorphous silicon layer 103 in regions 60 and 140 is relatively thick, while the amorphous silicon layer 103 in the transition region 170 and on the sidewall of the first region 130 is relatively thin. Both the thicker and thinner layers will lead to a decrease in the passivation effect of the amorphous silicon layer 103. Therefore, in this embodiment, a first textured structure 180 is provided on the transition region 170 to reduce the thickness difference between the amorphous silicon layer 103 in the transition region 170 and the amorphous silicon layer 103 in the platform region 160, thereby improving the passivation effect of the amorphous silicon layer 103.

[0122] At the same time, the size of the platform region 160 is reduced to reduce the size of the thicker amorphous silicon layer 103, further improving the relative uniformity of the thickness of the amorphous silicon layer 103, thereby further improving the passivation effect of the amorphous silicon layer 103.

[0123] In some embodiments, after forming the amorphous silicon layer 103, a doped amorphous silicon material can be formed by deposition to form the second doped conductive layer 104.

[0124] In some embodiments, a doped amorphous silicon material can be deposited at a process temperature of less than or equal to 250°C to form a second doped conductive layer 104.

[0125] In some embodiments, after forming the second doped conductive layer 104, a patterning process is performed to remove a portion of the second doped conductive layer 104 and the amorphous silicon layer 103 located in the first region 130. Removing a portion of the second doped conductive layer 104 and the amorphous silicon layer 103 facilitates the electrical connection between the first electrode 105 and the first doped conductive layer 102.

[0126] refer to Figure 8 A first conductive layer 107 and a second conductive layer 108 are formed.

[0127] In some embodiments, an initial conductive layer can be formed by deposition, which covers the surfaces of the first doped conductive layer 102 and the second doped conductive layer 104. Then, a portion of the initial conductive layer located in the spacer region 150 is etched to form the first conductive layer 107 and the second conductive layer 108.

[0128] In some embodiments, the initial conductive layer can be etched by removing part of the initial conductive layer through ink etching or laser patterning.

[0129] refer to Figure 1 This forms the first electrode 105 and the second electrode 106.

[0130] In some embodiments, the first electrode 105 and the second electrode 106 can be formed sequentially by screen printing.

[0131] Another embodiment of this disclosure also provides a photovoltaic module, which may include the solar cell as in some or all of the above embodiments, or the solar cell formed by the solar cell forming method as in some or all of the above embodiments. It should be noted that the parts that are the same as or corresponding to the above embodiments can be referred to the above embodiments, and will not be repeated below.

[0132] refer to Figure 9 and Figure 10 ,in,Figure 9 This is a partial three-dimensional schematic diagram of a photovoltaic module provided in another embodiment of the present disclosure. Figure 10 for Figure 9 A partial cross-sectional schematic diagram along the first section direction AA1.

[0133] In some embodiments, the photovoltaic module includes: a battery string, which includes: a plurality of solar cells 40 as described in some or all of the above embodiments, or includes solar cells 40 formed by the method of forming solar cells as described above; and a solder ribbon 43 electrically connected to at least two solar cells 40 to connect adjacent solar cells 40 in series.

[0134] The photovoltaic module also includes an encapsulating film 41, which is used to cover the surface of the cell string.

[0135] The photovoltaic module also includes a cover plate 42, which is used to cover the surface of the encapsulating film 41 away from the battery string.

[0136] In some embodiments, the encapsulating film 41 includes a first encapsulating layer and a second encapsulating layer. The first encapsulating layer covers one of the front or back sides of the solar cell, and the second encapsulating layer covers the other of the front or back sides of the solar cell. Specifically, at least one of the first or second encapsulating layer can be an organic encapsulating film such as polyvinyl butyral (PVB) film, ethylene-vinyl acetate copolymer (EVA) film, polyvinyl octene elastomer (POE) film, or polyethylene terephthalate (PET) film. Alternatively, at least one of the first or second encapsulating layer can also be an EP film, an EPE film, or a PVP film. Here, EP film refers to a co-extruded film composed of stacked EVA film and POE film; EPE film refers to a co-extruded film formed by sequentially stacking EVA film + POE film + EVA film; and PVP film refers to a co-extruded film formed by stacking POE film + EVA film + POE film. Co-extruded films can be prepared by sequentially extruding one or more raw materials onto another pre-made film during the film processing, or by bonding different types of pre-made films together.

[0137] In some cases, the first encapsulation layer and the second encapsulation layer still have a boundary line before lamination. After lamination, the photovoltaic module will no longer have the concept of a first encapsulation layer and a second encapsulation layer. That is, the first encapsulation layer and the second encapsulation layer have formed an integral encapsulation film 41.

[0138] In some embodiments, the cover plate 42 can be a glass cover plate, a plastic cover plate, or other cover plate with light-transmitting function. Specifically, the surface of the cover plate 42 facing the encapsulating film 41 can be an uneven surface or a textured surface containing multiple raised structures, thereby increasing the utilization rate of incident light. The cover plate 42 includes a first cover plate and a second cover plate, the first cover plate being opposite to the first encapsulation layer, and the second cover plate being opposite to the second encapsulation layer.

[0139] Those skilled in the art will understand that the above embodiments are specific examples of implementing this disclosure, and in practical applications, various changes in form and detail may be made without departing from the spirit and scope of the embodiments of this disclosure. Any person skilled in the art can make various modifications and alterations without departing from the spirit and scope of the embodiments of this disclosure; therefore, the scope of protection of the embodiments of this disclosure should be determined by the scope defined in the claims.

Claims

1. A solar cell, characterized in that, include: The base includes a front and a back side facing each other. The back side includes a first area and a second area arranged at intervals, and an interval area located between the first area and the second area. The interval area includes a platform area and a transition area. The platform area is adjacent to the first area, and the transition area is located between the platform area and the second area. The distance between the first area and the front side is a first distance, the distance between the platform area and the front side is a second distance, and the distance between the second area and the front side is a third distance. The first distance is greater than the second distance and the third distance. The transition area extends from the platform area to the second area, and a first velvet structure is provided on the transition area. A tunneling layer located on the first region; A first doped conductive layer covers the surface of the tunneling layer away from the substrate; An amorphous silicon layer, wherein the amorphous silicon layer at least covers the surfaces of the second region and the spacer region; A second doped conductive layer covers the surface of the amorphous silicon layer away from the substrate; The first electrode is electrically connected to the first doped conductive layer; The second electrode is electrically connected to the second doped conductive layer.

2. The solar cell according to claim 1, characterized in that, The angle between the surface of the transition zone and the surface of the platform zone is 130°~150°.

3. The solar cell according to claim 1, characterized in that, Along the thickness direction of the base, the height difference between the platform area and the second area is the first height, and along the direction from the first area to the second area, the distance between the platform area and the second area is the first width. The ratio between the first height and the first width is 0.4 to 1.

2.

4. The solar cell according to claim 3, characterized in that, The first width is 5μm to 10μm, and / or the first height is 4μm to 6μm.

5. The solar cell according to claim 1, characterized in that, Along the direction from the first region to the second region, the width of the platform region is 100nm~500nm.

6. The solar cell according to claim 1, characterized in that, The second area is provided with a second velvet structure, and the size of the first velvet structure is smaller than the size of the second velvet structure.

7. The solar cell according to claim 1, characterized in that, The first velvet structure is composed of multiple columnar parts.

8. The solar cell according to claim 1, characterized in that, The amorphous silicon layer also covers part of the top surface of the first doped conductive layer, and the thickness of the amorphous silicon layer located on the top surface of the first doped conductive layer is greater than the thickness of the amorphous silicon layer located in the transition region.

9. The solar cell according to claim 1 or 8, characterized in that, The thickness of the amorphous silicon layer located on the top surface of the first doped conductive layer is 6 nm to 7 nm, and / or the thickness of the amorphous silicon layer located in the transition region is 4 nm to 5 nm.

10. A method for manufacturing a solar cell, characterized in that, include: A substrate is provided, the substrate including a front side and a back side, the back side including a first area and a second area arranged at intervals, and a spacer area located between the first area and the second area, the spacer area including a platform area and a transition area, the platform area being adjacent to the first area, and the transition area being located between the platform area and the second area; A tunneling layer is formed, which is located on the first region; A first doped conductive layer is formed, which covers the surface of the tunneling layer away from the substrate; The transition region and the second region of the substrate are etched. The thickness of the transition region gradually decreases along the direction from the first region to the second region. A first textured structure is provided on the transition region. An amorphous silicon layer is formed, the amorphous silicon layer at least covering the surfaces of the second region and the spacer region; A second doped conductive layer is formed, which covers the surface of the amorphous silicon layer away from the substrate. A first electrode is formed, and the first electrode is electrically connected to the first doped conductive layer; A second electrode is formed, and the second electrode is electrically connected to the second doped conductive layer.

11. The method for manufacturing a solar cell according to claim 10, characterized in that, The etching process parameters for the substrate include: the concentration of the etching reagent is 2%~3%, the concentration of the additive is 0.6%~1%, the process temperature is 75℃~80℃, and the process time is 100s~300s.

12. The method for manufacturing a solar cell according to claim 10, characterized in that, Etching the transition region and the second region of the substrate further includes: performing a texturing process, wherein the texturing process forms a second textured surface structure on the surface of the second region, and the process parameters of the texturing process include: the concentration of the etching reagent is 2%~3%, the concentration of the additive is 0.8%~1.5%, the process temperature is 75℃~80℃, and the process time is 500s~700s.

13. The method for manufacturing a solar cell according to claim 10, characterized in that, The method for forming the amorphous silicon layer includes forming the amorphous silicon layer by chemical vapor deposition at a process temperature of less than or equal to 250°C.

14. A photovoltaic module, characterized in that, include: A battery string, comprising: a plurality of solar cells as described in any one of claims 1 to 9, or solar cells formed by a method of manufacturing solar cells as described in any one of claims 10 to 13; and solder ribbons electrically connected to at least two of the solar cells to connect adjacent solar cells in series. An encapsulating film, the encapsulating film being used to cover the surface of the battery string; A cover plate for covering the surface of the encapsulating film away from the battery string.

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