Method for manufacturing backside illuminated image sensor and backside illuminated image sensor

Abstract

The embodiment of the application discloses a manufacturing method of a back-illuminated image sensor and the back-illuminated image sensor. The method comprises the following steps: providing a device wafer, wherein the device wafer comprises a functional area and a pad area, and a pad window is formed on the back surface of the device wafer in the pad area, and the pad window exposes a pad; sequentially depositing a first dielectric layer and an etching stop layer on the back surface of the device wafer, wherein the first dielectric layer and the etching stop layer cover the back surface of the device wafer and the sidewall and bottom of the pad window; patterning and removing the etching stop layer in the pad area; depositing a second dielectric layer on the back surface of the device wafer, wherein the second dielectric layer covers the back surface of the device wafer and overfills the pad window; patterning and removing the second dielectric layer in the functional area based on the reserved etching stop layer; and after the etching stop layer is removed by ashing, performing chemical mechanical polishing on the pad area to planarize the back surface of the device wafer. The embodiment of the application reduces the probability of the generation of pad edge cracks in the chemical mechanical polishing process, thereby improving the device yield and reliability.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of semiconductor manufacturing, in particular to a manufacturing method of a backside illumination image sensor and a backside illumination image sensor. BACKGROUND

[0002] A backside illumination (BSI) image sensor has become a mainstream structure of high-pixel-density imaging chips because it can place a photodiode above a metal interconnection layer, thereby significantly improving the photoelectric conversion efficiency of a pixel. In a typical manufacturing process of a backside illumination image sensor, after a front surface of a device wafer completes a pixel array, a plurality of metal interconnection layers, and a top layer pad (for example, an aluminum pad, AlPAD), the device wafer needs to be bonded to a blank carrier wafer, and then the back surface of the device wafer is thinned and deep hole etched to expose the pad window. Subsequently, deep hole filling and chemical mechanical polishing (CMP) are sequentially completed. However, as the pixel size is reduced and the aspect ratio of the pad window is increased, an abrupt step close to 90° is formed in the pad area after the deep hole etching of the back surface of the device wafer. After the one-time backfilling of the deep hole of the back surface with a dielectric layer (for example, an oxide) and the surface planarization treatment, the surface planarization treatment is divided into two steps. First, the dielectric layer in the functional area (which can also be referred to as a pixel array area) outside the pad area is removed in a large area through an etching process. Then, the back surface of the device wafer is planarized as a whole through a CMP process. However, over-etching occurs when the dielectric layer in the functional area is etched, resulting in the formation of sharp corners near the abrupt step. Stress is highly concentrated at the sharp corners, and the CMP process is prone to induce pad cracks at the edges of the pad. The cracks not only expand further in subsequent high-temperature processes, causing the pad to peel off or even break, but also cause the probe contact to fail during the WAT (Wafer Acceptance Test) stage, thereby reducing the yield and reliability of the product. SUMMARY

[0003] In view of the above problems, the purpose of the present application is to provide a manufacturing method of a backside illumination image sensor and a backside illumination image sensor, which can achieve global planarization of the back surface of the device wafer without increasing the number of masks, effectively eliminate the stress concentration phenomenon at the sharp corners at the edges of the pad area, and reduce the probability of the occurrence of pad cracks during the chemical mechanical polishing process, thereby improving the yield and reliability of the device.

[0004] According to a first aspect of an embodiment of the present application, a manufacturing method of a backside illumination image sensor is provided, which includes:

[0005] providing a device wafer, the device wafer including a functional area and a pad area, and a pad in the pad area being exposed through a pad window in the back surface of the device wafer;

[0006] depositing a first dielectric layer and an etching stop layer on the back surface of the device wafer in sequence, the first dielectric layer and the etching stop layer covering the back surface of the device wafer and the sidewall and the bottom of the solder pad window;

[0007] graphically removing the etching stop layer of the solder pad region;

[0008] depositing a second dielectric layer on the back surface of the device wafer, the second dielectric layer covering the back surface of the device wafer and overfilling the solder pad window;

[0009] graphically removing the second dielectric layer of the functional region based on the reserved etching stop layer;

[0010] after the etching stop layer is removed by ashing, performing chemical mechanical polishing on the solder pad region to planarize the back surface of the device wafer.

[0011] Optionally, the front surface of the device wafer is sequentially stacked with a pixel array and a metal interconnection structure, the metal interconnection structure covering the pixel array, and the metal interconnection structure in the solder pad region outside the functional region is provided with the solder pad closest to the top layer of the back surface of the device wafer.

[0012] Optionally, before the first dielectric layer and the etching stop layer are deposited on the back surface of the device wafer in sequence, the manufacturing method further comprises:

[0013] depositing a bonding layer on the surface of a carrier wafer;

[0014] bonding the carrier wafer and the front surface of the device wafer through the bonding layer to form a composite wafer;

[0015] turning over the composite wafer to thin the back surface of the device wafer;

[0016] etching the back surface of the device wafer in the solder pad region to form the solder pad window.

[0017] Optionally, the graphically removing the etching stop layer of the solder pad region comprises:

[0018] coating photoresist on the etching stop layer on the back surface of the device wafer, exposing and developing to form an opening corresponding to the solder pad region in the photoresist;

[0019] etching the etching stop layer with the photoresist as a mask, only retaining the etching stop layer of the functional region, and the etching stop layer directly above the solder pad region is removed and etching stops at the first dielectric layer.

[0020] Optionally, the graphically removing the second dielectric layer of the functional region based on the reserved etching stop layer comprises:

[0021] coating photoresist on the second dielectric layer on the back side of the device wafer, exposing and developing to form openings in the photoresist corresponding to the functional areas;

[0022] etching the second dielectric layer of the functional areas with the photoresist as a mask, and stopping at the surface of the etching stop layer.

[0023] Optionally, after the ashing removes the etching stop layer, the pad area is subjected to chemical mechanical polishing to planarize the back side of the device wafer, comprising:

[0024] ashing to remove the etching stop layer of the functional areas;

[0025] chemically mechanically polishing the second dielectric layer of the pad area, wherein the first dielectric layer of the functional area is used to detect the chemical mechanical polishing endpoint in real time.

[0026] Optionally, the orthographic projection of the pad area overlaps the orthographic projection of the pad window.

[0027] Optionally, after the flip of the composite wafer and the thinning of the back side of the device wafer, the manufacturing method further comprises:

[0028] forming a grid structure in the area between the pixels on the back side of the device wafer.

[0029] Optionally, the material of the etching stop layer comprises amorphous carbon.

[0030] According to a second aspect of the embodiments of the present application, a back-illuminated image sensor is provided, which is manufactured according to the manufacturing method.

[0031] The unexpected technical effects of the present application are:

[0032] After the patterned removal of the etching stop layer of the pad area, a structure system with partition characteristics is formed on the back side of the device wafer. The retained etching stop layer of the functional area not only serves as the etching endpoint mark of the subsequent second dielectric layer, but also avoids over-etching of the dielectric layer of the functional area, thereby avoiding the occurrence of sharp corners near the steep steps of the pad window. At the same time, the retained etching stop layer of the functional area further forms a virtual polishing stop layer (i.e. the first dielectric layer of the functional area on the back side of the device wafer) in the CMP process of the pad area, avoiding the occurrence of pad edge cracks in the pad window caused by the CMP process. Through the dual function integration of the etching stop layer, the global planarization of the back side of the device wafer is achieved without increasing the number of masks, effectively eliminating the stress concentration phenomenon at the pad edge sharp corners of the pad area, reducing the probability of the occurrence of pad edge cracks in the chemical mechanical polishing process, and thereby improving the device yield and reliability. BRIEF DESCRIPTION OF DRAWINGS

[0033] The above and other objects, features and advantages of the present application will become more apparent from the following description when taken in conjunction with the accompanying drawings, in which:

[0034] FIG. 1A FIG. 1 shows a schematic diagram of a pad region with a sharp corner near a steep step caused by over-etching the functional region of the dielectric layer in the prior art;

[0035] FIG. 1B FIG. 1 shows a schematic diagram of a pad region with a sharp corner near a steep step caused by over-etching the functional region of the dielectric layer in the prior art;

[0036] FIG. 1C FIG. 1 shows a schematic diagram of a pad region with a sharp corner near a steep step caused by over-etching the functional region of the dielectric layer in the prior art;

[0037] FIG. 1D FIG. 1 shows a schematic diagram of a pad region with a sharp corner near a steep step caused by over-etching the functional region of the dielectric layer in the prior art;

[0038] FIG. 1E FIG. 1 shows a schematic diagram of a pad region with a sharp corner near a steep step caused by over-etching the functional region of the dielectric layer in the prior art;

[0039] FIG. 1F FIG. 1 shows a schematic diagram of a pad region with a sharp corner near a steep step caused by over-etching the functional region of the dielectric layer in the prior art;

[0040] FIG. 2 FIG. 1 shows a schematic diagram of a pad region with a sharp corner near a steep step caused by over-etching the functional region of the dielectric layer in the prior art;

[0041] FIGS. 3A-3I FIG. 1 shows a schematic diagram of a pad region with a sharp corner near a steep step caused by over-etching the functional region of the dielectric layer in the prior art;

[0042] FIG. 4A FIG. 1 shows a schematic diagram of a pad region with a sharp corner near a steep step caused by over-etching the functional region of the dielectric layer in the prior art;

[0043] FIG. 4B FIG. 1 shows a schematic diagram of a pad region with a sharp corner near a steep step caused by over-etching the functional region of the dielectric layer in the prior art.

[0044] Figure reference numerals: 100 - First back-illuminated image sensor; 110 - First carrier wafer; 120 - First bonding layer; 130 - First device wafer; 140 - First functional area; 150 - First pad area; 131 - First metal interconnect structure; 132 - First support dielectric layer; 133 - First interconnect metal line; 134 - First pad; 135 - First pixel array layer; 136 - First grid structure layer; 137 - Through-fill dielectric layer; 138 - Sharp corner; 139 - Crack; 300 - Second back-illuminated sensor Image sensor; 310-Second carrier wafer; 320-Second bonding layer; 330-Second device wafer; 340-Second functional region; 350-Second pad region; 331-Second metal interconnect structure; 332-Second support dielectric layer; 333-Second interconnect metal line; 334-Second pad; 335-Second pixel array layer; 336-Second grid structure layer; 337-Pad window; 338-First dielectric layer; 339-Etch stop layer; 361-Photoresist; 362-Second dielectric layer. Detailed Implementation

[0045] The present application will now be described in more detail with reference to the accompanying drawings. In the various drawings, the same elements are indicated by similar reference numerals. For clarity, the various parts in the drawings are not drawn to scale. Furthermore, some well-known parts may not be shown.

[0046] This application may be presented in various forms, some of which will be described below.

[0047] FIG. 1A and FIG. 1B The diagram illustrates how over-etching of the dielectric layer in the functional region in related technologies can lead to sharp corners near steep steps in the solder pad area. For example... FIG. 1AAs shown, the first back-illuminated image sensor 100 includes a first device wafer 130 and a first carrier wafer 110, which are bonded together by a first bonding layer 120. A pixel array and a first metal interconnect structure 131 are sequentially stacked on the front side of the first device wafer 130. The first metal interconnect structure 131 includes a first supporting dielectric layer 132 and first interconnect metal lines 133 embedded in the first supporting dielectric layer. The first supporting dielectric layer 132 supports and protects the first interconnect metal lines 133 and prepares for subsequent bonding. The material of the first supporting dielectric layer 132 is, for example, silicon oxide or other low dielectric material layers, and the first supporting dielectric layer 132 can be formed by processes such as chemical vapor deposition (CVD) and physical vapor deposition (PVD). The first interconnect metal lines 133 can be made of metal materials with low resistance, such as aluminum (Al), copper (Cu), tungsten (W), etc. The first interconnect metal lines 133 can be formed, for example, using a damascus damascene process. The first metal interconnect structure 131 can also be formed using other suitable conventional processes in the art, which will not be described in detail here.

[0048] The first device wafer 130 includes a first functional region 140 and a first pad region 150 located outside the first functional region 140. A pixel array in the first pixel array layer 135 is located within the first functional region 140. A first metal interconnect structure 131 covers the pixel array. In the first pad region 150, the first metal interconnect structure 131 has a first pad 134 disposed on the topmost layer near the back surface of the first device wafer 130. Pixels in the pixel array can also be referred to as photosensitive regions, which are used to convert light signals into electrical signals. A photosensitive region is, for example, a photodiode, which is a PN junction composed of different types of semiconductor materials. In some embodiments, a first grid structure layer 136 is formed on the back surface of the first device wafer 130. The grid structure corresponds to the region formed between adjacent pixels, and the grid structure helps to isolate individual pixels, reduce optical crosstalk between pixels, and improve image quality. The pixel array and grid structure can adopt structures conventional in the art. In some embodiments, the back surface of the first device wafer 130 is subsequently thinned and deep-hole etched to expose the first pad 134 to form a pad window. As pixel size shrinks and the aspect ratio of the pad window increases, the pad window of the first pad region 150 will form a steep step of nearly 90° after deep hole etching on the back side of the first device wafer 130. Subsequently, a via-filling dielectric layer 137 is deposited on the back side of the first device wafer 130 to complete deep hole filling and perform surface planarization. Surface planarization is performed in two steps: first, a large area of ​​the via-filling dielectric layer 137 in the first functional region 140 outside the first pad region 150 is removed using an etching process; then, the entire back side of the first device wafer 130 is planarized using a CMP process. However, as... FIG. 1A and FIG. 1BAs shown, over-etching occurs when the via filling dielectric layer 137 of the first functional region 140 is etched, resulting in sharp corners 138 near the steep step of the pad window.

[0049] FIG. 1C 、 FIG. 1D and FIG. 1E As shown, the chemical mechanical polishing of the pad region dielectric layer in the related art causes cracks at the edge of the pad. FIG. 1C 、 FIG. 1D and FIG. 1E As shown, the entire back surface of the first device wafer 130 is planarized by the CMP process, and the stress is highly concentrated at the sharp corners 138, which easily induces cracks 139 at the edge of the first pad 134. FIG. 1F As shown, the chemical mechanical polishing of the pad region dielectric layer in the related art causes cracks at the edge of the pad. FIG. 1F As shown, the spatial distribution density of the cracks 139 at the edge of the first pad 134 of the entire first device wafer 130 in the related art is intuitively presented, and obviously, most of the devices in the entire first device wafer 130 have cracks 139 at the edge of the first pad 134. The cracks 139 not only further expand in the subsequent high-temperature process, causing the first pad 134 to peel off or even break, but also cause the probe contact to fail in the WAT (Wafer Acceptance Test) stage, reducing the product yield and reliability.

[0050] Based on this, the application provides a manufacturing method of a back-illuminated image sensor and a back-illuminated image sensor, which realizes global planarization of the back surface of the device wafer without increasing the number of masks, effectively eliminates the stress concentration phenomenon at the sharp corners at the edge of the pad region, reduces the probability of cracks (Pad Crack) at the edge of the pad during the chemical mechanical polishing process, and thus improves the device yield and reliability.

[0051] FIG. 2 As shown, the application provides a manufacturing method of a back-illuminated image sensor. FIGS. 3A-3I As shown, the application provides a manufacturing method of a back-illuminated image sensor. FIGS. 3A-3I The manufacturing method of the back-illuminated image sensor is described in detail as follows. FIG. 2 As shown, the manufacturing method includes: FIG. 2

[0052] In step S210, a device wafer is provided, which includes a functional region and a pad region, and the pad window of the back surface of the device wafer exposes a pad in the pad region.

[0053] In some embodiments, as shown in FIG. 3A ​As shown, the second backside illumination image sensor 300 includes a second device wafer 330. The second device wafer 330 can be any material suitable for forming a semiconductor device, such as silicon (Si), germanium (Ge), silicon germanium (SiGe), silicon carbide (SiC), gallium arsenide (GaAs), gallium phosphide (GaP), indium phosphide (InP), indium arsenide (InAs), indium antimonide (InSb), indium nitride (InN), gallium nitride (GaN), germanium silicon (GeSi), sapphire, or other III / V compound semiconductor materials, etc. The second device wafer 330 can also be a stacked structure, such as a silicon / germanium / silicon stack, etc. The second device wafer 330 can also be a silicon-on-insulator (SOI), a germanium-on-insulator (GOI), etc. The type of the second device wafer 330 can be selected according to actual production, and a P-type substrate can be used, or an N-type substrate can be used. The second device wafer 330 has a front side and a back side arranged opposite along a thickness direction, the front side is used to form a device layer, and the back side is used to form a grid structure, etc.

[0054] In some embodiments, the second device wafer 330 includes a second functional region 340 and a second pad region 350 located outside the second functional region 340. A second pixel array layer 335 and a second metal interconnect structure 331 are formed on the front side of the second device wafer 330. The pixel array in the second pixel array layer 335 is located in the second functional region 340. The pixel array and the second metal interconnect structure 331 are sequentially stacked on the front side of the second device wafer 330. The pixels in the pixel array can also be referred to as photosensitive regions, which are used to convert light signals into electrical signals. The photosensitive region is, for example, a photodiode, which is a PN junction composed of different types of semiconductor materials. In the embodiments of this application, the photosensitive region can be formed by filling different types of semiconductor materials into the trench using epitaxy, or by other suitable conventional processes in the art, without limitation. In some embodiments, the second metal interconnect structure 331 includes a second supporting dielectric layer 332 and a second interconnect metal line 333 embedded in the dielectric layer, wherein the second supporting dielectric layer 332 is used to support and protect the second interconnect metal line 333, and can also prepare for subsequent bonding. The material of the second supporting dielectric layer 332 is, for example, silicon oxide or other low dielectric material layers, and the second supporting dielectric layer 332 can be formed by processes such as chemical vapor deposition (CVD) and physical vapor deposition (PVD). The second interconnect metal line 333 can be made of a metal material with low resistance, such as aluminum (Al), copper (Cu), tungsten (W), etc. The second interconnect metal line 333 can be formed, for example, using a damascus damascene process. The second metal interconnect structure 331 can also be formed using other suitable conventional processes in the art, which will not be described in detail here. In the second pad region 350, the second metal interconnect structure 331 has a second pad 334 on the top layer near the back side of the second device wafer 330.

[0055] In some embodiments, such as FIG. 3A As shown, a second grid structure layer 336 is formed on the back side of the second device wafer 330. The grid structure is formed in the region between adjacent pixels, which helps to isolate the pixels, reduce optical crosstalk between pixels, and improve image quality. The pixel array and grid structure can adopt conventional structures in the art. In some embodiments, the second back-illuminated image sensor 300 further includes a second carrier wafer 310. The front side of the second device wafer 330 and the second carrier wafer 310 are bonded together by a second bonding layer 320. In some embodiments, a second bonding layer 320 is deposited on the surface of the second carrier wafer 310, and the second carrier wafer 310 is bonded to the front side of the second device wafer 330 by the second bonding layer 320 to form a composite wafer. The composite wafer is flipped, the back side of the second device wafer 330 is thinned, and the back side stack of the second device wafer 330 is etched in the second pad region 350 to form a pad window 337. The orthographic projection of the pad window 337 overlaps with the orthographic projection of the second pad region 350.

[0056] In step S220, a first dielectric layer and an etch stop layer are sequentially deposited on the back side of the device wafer, the first dielectric layer and the etch stop layer covering the back side of the device wafer and the sidewalls and bottom of the pad window.

[0057] In some embodiments, such as FIG. 3B As shown, a first dielectric layer 338 is formed over the back side of a second device wafer 330 using processes such as low-pressure chemical vapor deposition (LPCVD). The first dielectric layer 338 covers the second pad region 350 (including the sidewalls and bottom of the pad window 337) and the second functional region 340 on the back side of the second device wafer 330. The material of the first dielectric layer 338 is, for example, silicon oxide or other low-dielectric-content material layers. In some embodiments, such as... FIG. 3C As shown, an etch stop layer 339 is formed over the first dielectric layer 338 on the back side of the second device wafer 330 using processes such as low-pressure chemical vapor deposition (LPCVD). The etch stop layer 339 covers the second pad region 350 (including the sidewalls and bottom of the pad window 337) and the first dielectric layer 338 of the second functional region 340 on the back side of the second device wafer 330. The material of the etch stop layer 339 is, for example, amorphous carbon. It should be noted that the etch selectivity ratio of amorphous carbon to the dielectric layer is greater than 30:1, and its Young's modulus is less than 10 GPa, significantly lower than the Young's modulus of conventional oxide dielectric layers (typically greater than 70 GPa). This material characteristic allows the etch stop layer 339 to serve as a self-stopping layer in subsequent dry etching processes.

[0058] In step S230, the etch stop layer in the pad region is graphically removed.

[0059] In some embodiments, such as FIG. 3D As shown, photoresist 361 is coated over the etch stop layer 339 on the back side of the second device wafer 330 using processes such as plasma-enhanced chemical vapor deposition (PECVD). Exposure and development are then performed to form an opening in the photoresist 361 corresponding to the second pad region 350, the size of which perfectly matches the orthographic projection of the pad window 337. In some embodiments, such as... FIG. 3EAs shown, the etch stop layer 339 is etched using reactive ion etching (RIE) and other processes with photoresist 361 as a mask. Only the etch stop layer 339 of the second functional region 340 is retained, while the etch stop layer 339 directly above the second pad region 350 is removed (including the etch stop layer 339 on the sidewalls and bottom of the pad window 337), and the etching stops at the first dielectric layer 338. The etching endpoint is monitored in real time using optical emission spectroscopy (OES) to ensure precise stopping on the surface of the first dielectric layer 338. Residual photoresist 361 is then removed. It should be noted that after patterning the removal of the etch stop layer 339 of the second pad region 350, a partitioned structure is formed on the back side of the second device wafer 330. The etch stop layer 339 of the retained second functional region 340 not only serves as an etch endpoint marker for the subsequent second dielectric layer 362, but also forms a virtual polishing stop layer (i.e., the first dielectric layer of the functional region on the back side of the device wafer) in the CMP process of the second pad region 350.

[0060] In step S240, a second dielectric layer is deposited on the back side of the device wafer, the second dielectric layer covering the back side of the device wafer and overfilling the pad window.

[0061] In some embodiments, such as FIG. 3F As shown, a second dielectric layer 362 is formed over the back side of the second device wafer 330 using processes such as low-pressure chemical vapor deposition (LPCVD). The second dielectric layer 362 covers the second pad region 350 (including the sidewalls and bottom of the pad window 337) and the second functional region 340, and overfills the pad window 337. The material of the second dielectric layer 362 is, for example, silicon oxide or other low dielectric material layers.

[0062] In step S250, the second dielectric layer of the functional region is graphically removed based on the retained etch stop layer.

[0063] In some embodiments, such as FIG. 3G As shown, photoresist (not shown) is coated on the second dielectric layer 362 on the back side of the second device wafer 330 using processes such as plasma-enhanced chemical vapor deposition (PECVD). Exposure and development are then performed to form openings in the photoresist corresponding to the second functional region 340. Reactive ion etching (RIE) is then used to etch the second dielectric layer 362 of the second functional region 340 using the photoresist as a mask, with etching stopping at the surface of the etch stop layer 339. The etching endpoint is monitored in real-time using optical emission spectroscopy (OES) to ensure precise stopping at the surface of the etch stop layer 339. Residual photoresist is then removed.

[0064] In step S260, after the etch stop layer is removed by ashing, the pad area is chemically mechanically polished to planarize the back side of the device wafer.

[0065] In some embodiments, as shown in FIG. 3B, the second functional region 340 on the backside of the second device wafer 330 is ashed to remove the etch stop layer 339 of the second functional region 340 by using an oxygen plasma ashing process, which simultaneously peels off a thin layer of the second dielectric layer 362 on the second functional region 340, so that the second functional region 340 is exposed to the clean surface of the first dielectric layer 338 again. FIG. 3H In some embodiments, as shown in FIG. 3B, the second functional region 340 on the backside of the second device wafer 330 is ashed to remove the etch stop layer 339 of the second functional region 340 by using an oxygen plasma ashing process, which simultaneously peels off a thin layer of the second dielectric layer 362 on the second functional region 340, so that the second functional region 340 is exposed to the clean surface of the first dielectric layer 338 again. FIG. 3I In some embodiments, as shown in FIG. 3B, the second functional region 340 on the backside of the second device wafer 330 is ashed to remove the etch stop layer 339 of the second functional region 340 by using an oxygen plasma ashing process, which simultaneously peels off a thin layer of the second dielectric layer 362 on the second functional region 340, so that the second functional region 340 is exposed to the clean surface of the first dielectric layer 338 again.

[0066] FIG. 4A FIG. 3E shows a schematic diagram of the CMP pad region dielectric layer after pad edge according to embodiments of the present application. As shown in FIG. 3E, the overfilled second dielectric layer 362 on the second pad region 350 on the backside of the second device wafer 330 is selectively CMPed for a short time, which does not cause the pad edge crack (Pad Crack) in the pad window. FIG. 4A FIG. 3E shows a schematic diagram of the CMP pad region dielectric layer after pad edge according to embodiments of the present application. As shown in FIG. 3E, the overfilled second dielectric layer 362 on the second pad region 350 on the backside of the second device wafer 330 is selectively CMPed for a short time, which does not cause the pad edge crack (Pad Crack) in the pad window. FIG. 4B FIG. 3E shows a schematic diagram of the CMP pad region dielectric layer after pad edge according to embodiments of the present application. As shown in FIG. 3E, the overfilled second dielectric layer 362 on the second pad region 350 on the backside of the second device wafer 330 is selectively CMPed for a short time, which does not cause the pad edge crack (Pad Crack) in the pad window. FIG. 4B FIG. 3E shows a schematic diagram of the CMP pad region dielectric layer after pad edge according to embodiments of the present application. As shown in FIG. 3E, the overfilled second dielectric layer 362 on the second pad region 350 on the backside of the second device wafer 330 is selectively CMPed for a short time, which does not cause the pad edge crack (Pad Crack) in the pad window.

[0067] It should be noted that after the etching stop layer 339 of the second pad region 350 is removed by patterning, the structure system with partition characteristics is formed on the back of the second device wafer 330. The etching stop layer 339 of the reserved second functional region 340 not only serves as the etching end point mark of the subsequent second dielectric layer 362, but also avoids over-etching of the second functional region 340 dielectric layer, thereby avoiding the occurrence of sharp corners near the steep step of the pad window. Meanwhile, the etching stop layer 339 of the reserved second functional region 340 further forms a virtual polishing stop layer (i.e., the first dielectric layer 338 of the second functional region 340 on the back of the second device wafer 330) in the CMP process of the second pad region 350, thereby avoiding the occurrence of pad edge cracks (Pad Crack) in the pad window caused by the CMP process. It should be noted that through the dual-function integration of the etching stop layer 339, the global planarization of the back of the second device wafer 330 is achieved without increasing the number of masks, effectively eliminating the stress concentration phenomenon at the sharp corners of the pad edges of the second pad region 350, reducing the probability of the occurrence of pad edge cracks (Pad Crack) in the chemical mechanical polishing process, and thereby improving the device yield and reliability.

[0068] Correspondingly, the embodiment of the present application also provides a back-illuminated image sensor made according to the manufacturing method. Since the process of using the manufacturing method of the embodiment of the present application to manufacture the back-illuminated image sensor has been described in detail in the method embodiment above, it will not be repeated here.

[0069] Finally, it should be noted that the terms "first", "second" and "third" are only used for descriptive purposes and should not be construed as indicating or implying relative importance. According to the above description of the embodiments of the present application, these embodiments do not describe all the details and do not limit the application to the specific embodiments described. Obviously, many modifications and changes can be made according to the above description. The embodiments are selected and described in this specification in order to better explain the principles and practical applications of the present application, so that those skilled in the art can well utilize the present application and make modifications and uses based on the present application. The present application is limited by the claims and their full scope and equivalents.

Claims

1. A method for manufacturing a back-illuminated image sensor, comprising: A device wafer is provided, the device wafer including a functional region and a pad region, wherein a pad window on the back side of the device wafer exposes the pad in the pad region; A first dielectric layer and an etch stop layer are sequentially deposited on the back side of the device wafer, the first dielectric layer and the etch stop layer covering the back side of the device wafer and the sidewalls and bottom of the pad window; The etching stop layer of the pad region is graphically removed, leaving only the etching stop layer of the functional region. The etching stop layer directly above the pad region is removed and etching stops at the first dielectric layer. A second dielectric layer is deposited on the back side of the device wafer, the second dielectric layer covering the back side of the device wafer and overfilling the pad window; Based on the retained etch stop layer, the second dielectric layer of the functional area is graphically removed, while the second dielectric layer of the pad area is retained; After the etching stop layer is removed by ashing, the pad area is subjected to chemical mechanical polishing to planarize the back side of the device wafer, wherein the endpoint of the chemical mechanical polishing is detected in real time based on the first dielectric layer of the functional area.

2. The manufacturing method according to claim 1, wherein, The front side of the device wafer has a pixel array and a metal interconnect structure stacked sequentially, the metal interconnect structure covering the pixel array, and the metal interconnect structure having the solder pads on the top layer near the back side of the device wafer in the pad area outside the functional area.

3. The manufacturing method according to claim 2, wherein, Before sequentially depositing a first dielectric layer and an etch stop layer on the back side of the device wafer, the manufacturing method further includes: Deposit a bonding layer on the surface of the carrier wafer; The carrier wafer and the front side of the device wafer are bonded together through the bonding layer to form a composite wafer; The composite wafer is flipped over to thin the back side of the device wafer; The backside stack of the device wafer is etched in the pad area to form the pad window.

4. The manufacturing method according to claim 3, wherein, The patterning removal of the etch stop layer in the solder pad region includes: Photoresist is applied over the etch stop layer on the back side of the device wafer, and exposed and developed to form openings in the photoresist corresponding to the pad regions; The photoresist is used as a mask to etch the etch stop layer, retaining only the etch stop layer of the functional area. The etch stop layer directly above the pad area is removed and the etching stops at the first dielectric layer.

5. The manufacturing method according to claim 3, wherein, The second dielectric layer, based on the retained etch stop layer, is graphically removed from the functional region, including: Photoresist is coated over the second dielectric layer on the back side of the device wafer, exposed and developed to form an opening in the photoresist corresponding to the functional region; Using the photoresist as a mask, the second dielectric layer of the functional area is etched, and the etching stops on the surface of the etching stop layer.

6. The manufacturing method according to claim 3, wherein, After the ashing process removes the etch stop layer, the pad area is subjected to chemical mechanical polishing to planarize the back side of the device wafer, including: Ashing removes the etching stop layer in the functional area; The second dielectric layer in the pad region is subjected to chemical mechanical polishing.

7. The manufacturing method according to claim 3, wherein, The orthographic projection of the pad region overlaps with the orthographic projection of the pad window.

8. The manufacturing method according to claim 3, wherein, After flipping the composite wafer and thinning the back side of the device wafer, the manufacturing method further includes: A grid structure is formed in the area between pixels on the back side of the device wafer.

9. The manufacturing method according to claim 1, wherein, The material of the etch stop layer includes amorphous carbon.

10. A back-illuminated image sensor, manufactured according to the manufacturing method of any one of claims 1 to 9.

Images