Electroencephalogram and electromyogram signal processing device and system

Abstract

The invention discloses an electroencephalogram and electromyogram signal processing device and system. The device comprises an MCU, an LCD display circuit, an SD card storage circuit and a signal acquisition circuit. The signal acquisition circuit is used for performing impedance matching, signal filtering and analog-to-digital conversion on original electroencephalogram signals and / or original electromyographic signals accessed by the HDMI interface to obtain electroencephalogram digital signals and / or electromyographic digital signals; the MCU is used for analyzing the electroencephalogram digital signals and / or the myoelectricity digital signals, generating display data, displaying the display data through the LCD display circuit, formatting the electroencephalogram digital signals and / or the myoelectricity digital signals, generating storage data and storing the storage data through the SD card storage circuit. According to the invention, through optimized impedance matching, signal filtering and analog-to-digital conversion design, the accuracy of electroencephalogram and electromyographic signal acquisition is improved; and in combination with MCU analysis and differentiation processing, the signal display real-time performance and the storage efficiency are remarkably improved, and the requirements of clinical and scientific research scenes are met.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of brain and muscle electrical signal processing, and particularly relates to a brain and muscle electrical signal processing device and system. BACKGROUND

[0002] In the field of modern medical treatment and brain science research, the collection and processing of brain and muscle electrical signals are important links, but the existing devices have many deficiencies. On the one hand, during signal collection, due to the lack of effective impedance matching design, signal distortion or interference is easily introduced, affecting the collection accuracy. On the other hand, the processing of brain and muscle electrical signals is not fine enough, and the differences in characteristics of the two are not fully considered, and a unified filtering method is often used, which makes it difficult to effectively remove noise, and the signal processing effect is poor. In addition, the existing devices also have shortcomings in real-time display and efficient storage of signals, and cannot timely and accurately present the processed signals to the user and properly save them, limiting the application effect of the devices in clinical diagnosis, scientific research analysis and real-time monitoring scenarios.

[0003] Therefore, there is an urgent need to provide a technical solution to solve the above problems. SUMMARY

[0004] To solve the above technical problems, the present application provides a brain and muscle electrical signal processing device and system.

[0005] In a first aspect, the present application provides a brain and muscle electrical signal processing device, and the technical scheme of the device is as follows: It comprises an MCU, an LCD display circuit, an SD card storage circuit and a signal collection circuit; the MCU is connected with the LCD display circuit, the SD card storage circuit and the signal collection circuit respectively, and the signal collection circuit is further connected with an HDMI interface for connecting lead wires of a human body; The signal collection circuit is used for sequentially performing impedance matching, signal filtering and analog-to-digital conversion on original brain electrical signals and / or original muscle electrical signals connected with the HDMI interface, to obtain brain electrical digital signals and / or muscle electrical digital signals; The MCU is used for analyzing the brain electrical digital signals and / or the muscle electrical digital signals, generating display data and displaying the display data through the LCD display circuit, and performing format processing on the brain electrical digital signals and / or the muscle electrical digital signals, generating storage data and storing the storage data through the SD card storage circuit.

[0006] The brain and muscle electrical signal processing device of the present application has the following beneficial effects: The device of the present application improves the accuracy of brain and muscle electrical signal collection through optimized impedance matching, signal filtering and analog-to-digital conversion design, and significantly improves the real-time performance of signal display and the storage efficiency through MCU analysis and differential processing, meeting the needs of clinical and scientific research scenarios.

[0007] Based on the above scheme, the brain muscle signal processing device of the present application can be further improved as follows.

[0008] In an alternative manner, further comprising: a key circuit; the key circuit is connected with the MCU; The key circuit is used for receiving user operation instructions and sending them to the MCU to execute the user operation instructions through the MCU.

[0009] In an alternative manner, the signal acquisition circuit comprises: a voltage follower circuit, a filter circuit and an analog-to-digital conversion chip connected in sequence; The voltage follower circuit is used for impedance matching of the original brain electrical signals and / or original muscle electrical signals accessed by the HDMI interface, to obtain impedance-matched brain electrical signals and / or muscle electrical signals; The filter circuit is used for third-order filtering of the impedance-matched brain electrical signals to obtain filtered brain electrical signals, and / or second-order filtering of the impedance-matched muscle electrical signals to obtain filtered muscle electrical signals; The analog-to-digital conversion chip is used for analog-to-digital conversion of the filtered brain electrical signals and / or the filtered muscle electrical signals to obtain the brain electrical digital signals and / or the muscle electrical digital signals.

[0010] In an alternative manner, the voltage follower circuit comprises a voltage follower composed of an operational amplifier; the voltage follower circuit is specifically used for: Through the voltage follower, the original brain electrical signals with high impedance input are converted into brain electrical signals with low impedance output to generate the impedance-matched brain electrical signals, and / or the original muscle electrical signals with high impedance input are converted into muscle electrical signals with low impedance output to generate the impedance-matched muscle electrical signals.

[0011] In an alternative manner, the filter circuit comprises a Sallen-Key filter connected in three levels in series, wherein: The first Sallen-Key filter is configured as a high-pass filter, and the cutoff frequency of the high-pass filter is set to 0.5 Hz, which is used for removing direct current components and extremely low frequency interference in the brain electrical signals; The second Sallen-Key filter is configured as a band-pass filter, and the passband frequency range of the band-pass filter is set to 0.5 Hz to 40 Hz, which is used for extracting effective frequency band components of the brain electrical signals; The third Sallen-Key filter is configured as a 50 Hz notch filter, which is used for filtering out power frequency interference in the brain electrical signals; The filter circuit is specifically configured to: utilize the Sallen-Key filter in the three-stage series to sequentially process the impedance-matched electroencephalogram signal to generate the filtered electroencephalogram signal.

[0012] In an alternative manner, the filter circuit comprises a Sallen-Key filter in two-stage series, wherein: The first-stage Sallen-Key filter is configured as a high-pass filter, and a cutoff frequency of the high-pass filter is set to 10 Hz, for high-pass filtering processing of the electromyogram signal. The second-stage Sallen-Key filter is configured as a low-pass filter, and a cutoff frequency of the low-pass filter is set to 500 Hz, for low-pass filtering processing of the electromyogram signal. The filter circuit is specifically configured to: utilize the Sallen-Key filter in the two-stage series to perform second-order filtering processing on the impedance-matched electromyogram signal to generate the filtered electromyogram signal.

[0013] In an alternative manner, the analog-to-digital conversion chip is specifically configured to: perform sample-and-hold processing on the filtered electroencephalogram signal to obtain a sampled analog electroencephalogram signal, and convert the sampled analog electroencephalogram signal into a 24-bit electroencephalogram digital signal through a successive approximation register analog-to-digital converter, and / or perform sample-and-hold processing on the filtered electromyogram signal to obtain a sampled analog electromyogram signal, and convert the sampled analog electromyogram signal into a 24-bit electromyogram digital signal through the successive approximation register analog-to-digital converter; perform digital filtering processing on the 24-bit electroencephalogram digital signal and / or the 24-bit electromyogram digital signal through an internally integrated digital filter to obtain the electroencephalogram digital signal and / or the electromyogram digital signal.

[0014] In an alternative manner, the MCU is specifically configured to: segment the electroencephalogram digital signal in a sliding window processing manner, perform fast Fourier transform on the electroencephalogram digital signal in each time window to obtain frequency domain feature data; perform envelope detection algorithm on the electromyogram digital signal to extract amplitude variation information; fuse the frequency domain feature data and the amplitude variation information with a preset display template, and generate display data frames containing time domain waveforms and frequency domain spectrograms according to a data fusion result; write the display data frames into an internally integrated display buffer, so that the LCD display circuit reads the display data frames from the display buffer through an RGB565 interface and displays the display data frames periodically.

[0015] In an alternative mode, the MCU is specifically used for: dividing the electroencephalogram digital signal into at least one electroencephalogram signal data packet of a predetermined time length, and adding a time stamp and an electroencephalogram signal type identifier to each electroencephalogram signal data packet, and dividing the electromyogram digital signal into at least one electromyogram signal data packet of a predetermined time length, and adding a time stamp and an electromyogram signal type identifier to each electromyogram signal data packet; using an LZ4 compression algorithm to perform lossless compression processing on each electroencephalogram signal data packet and each electromyogram signal data packet respectively, to generate an electroencephalogram compression data block corresponding to each electroencephalogram signal data packet and an electromyogram compression data block corresponding to each electromyogram signal data packet; generating a corresponding electroencephalogram file header for each electroencephalogram compression data block and a corresponding electromyogram file header for each electromyogram compression data block; wherein each electroencephalogram file header and each electromyogram file header comprises: a sampling rate, a signal type, time information, and a data format description; transmitting each electroencephalogram compression data block containing an electroencephalogram file header and each electromyogram compression data block containing an electromyogram file header to the SD card storage circuit through an SDIO interface, so that the SD card storage circuit writes into an SD card storage medium in a FAT32 file system format.

[0016] In a second aspect, the present application provides a brain and muscle electrical signal processing system, which comprises the brain and muscle electrical signal processing device of the present application.

[0017] The above description is only a summary of the technical solutions of the present application. In order to more clearly understand the technical means of the present application, the following specific embodiments of the present application can be implemented according to the content of the specification, and in order to make the above and other purposes, features and advantages of the present application more obvious and easy to understand, the following specific embodiments of the present application are described. BRIEF DESCRIPTION OF DRAWINGS

[0018] The accompanying drawings are included to provide a further understanding of the application and are incorporated herein and constitute a part of the detailed description. The drawings illustrate embodiments of the application and, together with the description, serve to explain the principles of the application. In the drawings: Figure 1 Structure schematic diagram of an embodiment of a brain and muscle electrical signal processing device of the present application; Figure 2 Structure schematic diagram of a signal acquisition circuit; Figure 3 Structure schematic diagram of a brain and muscle electrical signal processing device. DETAILED DESCRIPTION

[0019] The exemplary embodiments of the present application will be described in detail with reference to the accompanying drawings. Although the exemplary embodiments of the present application are shown in the drawings, it should be understood that the present application can be implemented in various forms and should not be limited by the embodiments described herein.

[0020] Figure 1 A schematic diagram of an embodiment of a brain electromyography signal processing device provided by the present invention is shown. Figure 1 As shown, the device includes: an MCU, an LCD display circuit, an SD card storage circuit, and a signal acquisition circuit; the MCU is connected to the LCD display circuit, the SD card storage circuit, and the signal acquisition circuit, respectively, and the signal acquisition circuit is also connected to an HDMI interface for connecting to the human body lead cable.

[0021] In this context, MCU refers to Microcontroller Unit, the core processing component of the device, used for signal processing, controlling peripheral circuits, and coordinating the operation of various functional modules; for example, a GD32F470ZI chip is used to implement signal analysis, display control, and storage management functions. LCD display circuit refers to Liquid Crystal Display circuit, used to receive display data sent by the MCU and present image or text information; for example, receiving waveform data and displaying the user's EEG signal time-domain waveform via an RGB565 interface. SD card storage circuit refers to Secure Digital Card storage circuit, used to read and write data in the storage medium; for example, writing EEG digital signals to an SD card as a file via an SDIO interface. Signal acquisition circuit refers to circuit modules used to acquire, condition, and convert bioelectrical signals; for example, using an ADS1299 chip as the core, combined with voltage follower and filtering circuits to achieve signal acquisition. Human body lead wire refers to wires connecting the human body to the signal acquisition device, used to transmit bioelectrical signals; for example, collecting scalp EEG signals through electrode patches and transmitting them to the device via wires. HDMI interface refers to High Definition Multimedia Interface, which is used in this device to connect the human body cable; for example, it uses a standard HDMI physical interface to connect the cable plug.

[0022] The signal acquisition circuit is used to: sequentially perform impedance matching, signal filtering and analog-to-digital conversion on the raw EEG signal and / or raw EMG signal connected to the HDMI interface to obtain digital EEG signal and / or digital EMG signal.

[0023] The original electroencephalogram signal refers to an untreated electroencephalogram analog signal directly collected from a human body, for example, a low-frequency analog signal with a magnitude of microvolts collected from a scalp electrode. The original electromyogram signal refers to an untreated electromyogram analog signal directly collected from a human body, for example, a millivolt-level analog signal generated by muscle activity collected from a skin surface electrode. The electroencephalogram digital signal refers to a digital signal obtained after impedance matching, filtering and analog-to-digital conversion of the original electroencephalogram signal, for example, a digital signal with a sampling rate of 1000 Hz and a resolution of 24 bits output by ADS1299. The electromyogram digital signal refers to a digital signal obtained after impedance matching, filtering and analog-to-digital conversion of the original electromyogram signal, for example, a digital signal with a sampling rate of 2000 Hz and a resolution of 24 bits output by ADS1299.

[0024] The MCU is configured to analyze the electroencephalogram digital signal and / or the electromyogram digital signal, generate display data and display the display data through the LCD display circuit, and format process the electroencephalogram digital signal and / or the electromyogram digital signal, generate storage data and store the storage data through the SD card storage circuit.

[0025] The display data refers to data generated by the MCU after analyzing the digital signal for screen display, for example, a composite data frame containing time-domain waveforms and frequency-domain spectrograms.

[0026] The storage data refers to data generated by the MCU after formatting the digital signal for storage, for example, a compressed data block with a timestamp and a file header.

[0027] The technical scheme of the embodiment improves the accuracy of electroencephalogram and electromyogram signal collection through optimized impedance matching, signal filtering and analog-to-digital conversion design, significantly improves the real-time performance of signal display and the storage efficiency through MCU analysis and differential processing, and meets the needs of clinical and scientific research scenes.

[0028] In an optional mode, the device further comprises a key circuit, wherein the key circuit is connected to the MCU.

[0029] The key circuit refers to an input circuit for receiving user external operations, for example, a key matrix containing functions such as power on / off, child lock, acquisition control and marking. The MCU reads the state of the key circuit in real time through the GPIO interface, thereby realizing the key functions.

[0030] The key circuit is configured to receive user operation instructions and send the user operation instructions to the MCU, so that the MCU executes the user operation instructions.

[0031] The user operation instruction refers to a control command input by the user through the key circuit, for example, an instruction to start signal acquisition, pause recording or add an event mark.

[0032] Specifically: 1) the key circuit detects the operation action of the user through the physical key in real time, converts the operation action into an electrical signal, and transmits the electrical signal to the MCU through the GPIO interface; 2) the MCU reads the level state of the GPIO interface in a polling or interrupt manner, and analyzes the corresponding user operation instruction type according to the preset key value mapping relationship, including the on-off instruction, the child lock function instruction, the acquisition function start-stop instruction or the user marking instruction; 3) the MCU calls the corresponding control program according to the user operation instruction type, changes the output level or sends a control command to the signal acquisition circuit, the LCD display circuit or the SD card storage circuit, and performs the operation of switching the device on-off state, activating or releasing the child lock function, starting or pausing the signal acquisition process, or inserting the user marking event in the data stream.

[0033] It should be noted that each physical key in the key circuit is connected to a specific GPIO pin of the MCU and corresponds to a unique key value code; the key value mapping relationship stored in the MCU is: when it is detected that the level of GPIO pin P1 changes from high to low, it is analyzed as an on-off instruction; when it is detected that the level of GPIO pin P2 changes from high to low, it is analyzed as a child lock function instruction; when it is detected that the level of GPIO pin P3 changes from high to low, it is analyzed as an acquisition function start-stop instruction; when it is detected that the level of GPIO pin P4 changes from high to low, it is analyzed as a user marking instruction. For example, when the user presses the physical key connected to the GPIO pin P3, the level of the pin changes from high to low, and the MCU identifies the acquisition function start-stop instruction according to the key value mapping relationship, and then calls the control program to send a command to start or pause the acquisition to the signal acquisition circuit.

[0034] In the above optional mode, the key circuit is further added to enable the user to conveniently operate the device and realize the functions of starting, pausing and parameter adjusting of signal acquisition.

[0035] In an optional mode, as shown in Figure 2 The signal acquisition circuit comprises, in sequence, a voltage follower circuit, a filter circuit and an analog-to-digital conversion chip.

[0036] The voltage follower circuit refers to an impedance conversion circuit based on an operational amplifier, which is used to improve the input impedance and reduce the output impedance; for example, an OPA4340 operational amplifier is used to realize signal buffering. The filter circuit refers to a processing circuit for frequency selection of signals; for example, an active filter with a Sallen-Key topology structure is used. The analog-to-digital conversion chip refers to an integrated circuit for converting analog signals into digital signals; for example, an ADS1299 chip is used to realize multi-channel synchronous sampling and analog-to-digital conversion.

[0037] The voltage follower circuit is configured to perform impedance matching on the raw electroencephalogram signal and / or the raw electromyogram signal accessed by the HDMI interface, to obtain an impedance-matched electroencephalogram signal and / or an impedance-matched electromyogram signal.

[0038] The impedance-matched electroencephalogram signal is a processed electroencephalogram signal having a low output impedance characteristic, for example, an electroencephalogram analog signal with unchanged amplitude but enhanced driving capability. The impedance-matched electromyogram signal is a processed electromyogram signal having a low output impedance characteristic, for example, an electromyogram analog signal with unchanged amplitude but enhanced anti-interference capability.

[0039] The filter circuit is configured to perform third-order filtering on the impedance-matched electroencephalogram signal to obtain a filtered electroencephalogram signal, and / or perform second-order filtering on the impedance-matched electromyogram signal to obtain a filtered electromyogram signal.

[0040] The filtered electroencephalogram signal is a processed electroencephalogram analog signal having removed specific interference, for example, an electroencephalogram signal having removed direct current components, extremely low frequencies, and 50Hz power frequency interference. The filtered electromyogram signal is a processed electromyogram analog signal having removed specific interference, for example, an electromyogram signal filtered by a 10Hz high-pass filter and a 500Hz low-pass filter.

[0041] The analog-to-digital conversion chip is configured to perform analog-to-digital conversion on the filtered electroencephalogram signal and / or the filtered electromyogram signal to obtain the electroencephalogram digital signal and / or the electromyogram digital signal.

[0042] In the optional manner, the phased design of the signal acquisition circuit is further specified, and impedance matching, filtering, and analog-to-digital conversion are sequentially completed, thereby effectively improving the signal acquisition quality and laying a foundation for subsequent processing.

[0043] In an optional manner, the voltage follower circuit includes a voltage follower composed of an operational amplifier.

[0044] The operational amplifier is an analog integrated circuit configured to realize signal amplification, buffering, and filtering, for example, an operational amplifier of OPA4340 type. The voltage follower is a circuit configuration based on the operational amplifier, which outputs a voltage following an input voltage, has high input impedance and low output impedance, for example, an operational amplifier circuit with unit gain feedback.

[0045] The voltage follower circuit is specifically configured to: The voltage follower converts the high-impedance input raw EEG signal into a low-impedance output EEG signal, generates the impedance-matched EEG signal, and / or converts the high-impedance input raw EMG signal into a low-impedance output EMG signal, generates the impedance-matched EMG signal.

[0046] Specifically, the voltage follower receives the high-impedance raw EEG signal or the high-impedance raw EMG signal transmitted from the HDMI interface through its non-inverting input terminal, and the operational amplifier establishes a unit negative feedback between its inverting input terminal and output terminal, so that the output voltage of the operational amplifier follows the change of the input voltage in real time. At the same time, the high input impedance characteristic of the operational amplifier itself significantly reduces the current demand of the input circuit, and the low output impedance characteristic enhances the signal driving capability. Finally, the EEG signal or EMG signal with the same amplitude as the input signal but with significantly reduced output impedance is output from the output terminal, thereby completing the impedance matching process. For example, when the voltage follower composed of OPA4340 type operational amplifier receives a raw EEG signal with an amplitude of 50 microvolts and a source impedance of 1 megaohm at its non-inverting input terminal, it can generate an impedance-matched EEG signal with an amplitude of 50 microvolts but an output impedance reduced to less than 1 ohm at the output terminal.

[0047] In the above optional mode, the voltage follower circuit utilizes the operational amplifier to realize the conversion of high-impedance input signal to low-impedance output, reduce signal distortion, and enhance the stability of acquisition.

[0048] In an optional mode, the filter circuit comprises a three-stage Sallen-Key filter in series, wherein: The first-stage Sallen-Key filter is configured as a high-pass filter with a cutoff frequency set to 0.5 Hz for removing the direct current component and extremely low frequency interference in the EEG signal; The second-stage Sallen-Key filter is configured as a band-pass filter with a passband frequency range set to 0.5 Hz to 40 Hz for extracting the effective frequency band components of the EEG signal; The third-stage Sallen-Key filter is configured as a 50 Hz notch filter for filtering out the power frequency interference in the EEG signal.

[0049] The three-stage Sallen-Key filter in series refers to a filter circuit composed of three Sallen-Key topology filters in series. For example, a 0.5Hz high-pass filter, a 0.5-40Hz band-pass filter, and a 50Hz notch filter in sequence. The high-pass filter refers to a filter used to filter out low-frequency components. For example, a first-order high-pass filter with a cutoff frequency of 0.5Hz. The band-pass filter refers to a filter that allows signals in a specific frequency range to pass through. For example, a two-stage band-pass filter with a passband of 0.5Hz to 40Hz. The 50Hz notch filter refers to a filter used to filter out 50Hz power supply interference. For example, a band-stop filter with a center frequency of 50Hz.

[0050] The filter circuit is specifically used to process the impedance-matched electroencephalogram signal in sequence using the three-stage Sallen-Key filter to generate the filtered electroencephalogram signal.

[0051] Specifically, the impedance-matched electroencephalogram signal is first input to the first-stage Sallen-Key high-pass filter, which filters out the direct current component and extremely low-frequency interference components with a frequency below 0.5Hz in the signal with its 0.5Hz cutoff frequency characteristic. The high-pass filtered signal is then input to the second-stage Sallen-Key band-pass filter, which retains the effective frequency band components of the electroencephalogram signal and suppresses high-frequency and residual low-frequency noise outside the range with its 0.5Hz to 40Hz passband frequency range. Finally, the band-pass filter output signal is input to the third-stage Sallen-Key 50Hz notch filter, which filters out power supply interference and its harmonic components with its center frequency of 50Hz. The signal processed by the above three-stage filters in sequence is the filtered electroencephalogram signal that removes the main interference and retains the effective frequency band characteristics.

[0052] In the above optional manner, the filter circuit uses three-stage Sallen-Key filters to accurately remove direct current components, extremely low-frequency interference, and power frequency interference from the electroencephalogram signal, improving the spectral purity of the electroencephalogram signal.

[0053] In an optional manner, the filter circuit includes two-stage Sallen-Key filters in series, wherein: The first-stage Sallen-Key filter is configured as a high-pass filter with a cutoff frequency of 10Hz for high-pass filtering the electromyogram signal. The second-stage Sallen-Key filter is configured as a low-pass filter with a cutoff frequency of 500Hz for low-pass filtering the electromyogram signal.

[0054] The two-stage Sallen-Key filter in series refers to a filter circuit composed of two Sallen-Key topology filter stages in series; for example, a 10Hz high-pass filter and a 500Hz low-pass filter in series. The high-pass filter in the two-stage Sallen-Key filter in series refers to a filter for filtering out low-frequency noise in the electromyographic signal; for example, a high-pass filter with a cutoff frequency of 10Hz. The low-pass filter refers to a filter for filtering out high-frequency components; for example, a low-pass filter with a cutoff frequency of 500Hz.

[0055] The filter circuit is specifically used for performing second-order filtering processing on the impedance-matched electromyographic signal by using the two-stage Sallen-Key filter in series to generate the filtered electromyographic signal.

[0056] Specifically, the impedance-matched electromyographic signal is first input to the first-stage Sallen-Key high-pass filter, which filters out low-frequency motion artifacts and baseline drift in the signal with its 10Hz cutoff frequency characteristic; the high-pass filtered signal is then input to the second-stage Sallen-Key low-pass filter, which suppresses high-frequency noise and electromagnetic interference in the electromyographic signal with a frequency higher than 500Hz with its 500Hz cutoff frequency characteristic; the signal processed by the above two-stage filters in series is the filtered electromyographic signal that removes low-frequency and high-frequency interference and retains the 10Hz to 500Hz effective frequency band characteristic.

[0057] In the above optional manner, the filter circuit further uses a two-stage Sallen-Key filter to perform high-pass and low-pass processing on the electromyographic signal, effectively extracts the electromyographic signal characteristic frequency band, and enhances signal clarity.

[0058] In an optional manner, the analog-to-digital conversion chip is specifically used for: sampling and holding the filtered electroencephalographic signal to obtain a sampled analog electroencephalographic signal, and converting the sampled analog electroencephalographic signal into a 24-bit electroencephalographic digital signal through a successive approximation register analog-to-digital converter, and / or sampling and holding the filtered electromyographic signal to obtain a sampled analog electromyographic signal, and converting the sampled analog electromyographic signal into a 24-bit electromyographic digital signal through the successive approximation register analog-to-digital converter.

[0059] Wherein, the sampled analog EEG signal refers to the EEG signal instantaneous value obtained by the sample-and-hold circuit during the analog-to-digital conversion process; for example, the voltage value obtained by the ADS1299 sampling the filtered EEG signal at a specific time. The successive approximation register analog-to-digital converter refers to the type of analog-to-digital converter that uses a binary search strategy; for example, the SAR-ADC module integrated inside the ADS1299 chip. The 24-bit EEG digital signal refers to the 24-bit resolution digital signal generated by the analog-to-digital converter; for example, the 24-bit binary data output by the ADS1299 representing the EEG voltage value. The sampled analog EMG signal refers to the EMG signal instantaneous value obtained by the sample-and-hold circuit during the analog-to-digital conversion process; for example, the voltage value obtained by the ADS1299 sampling the filtered EMG signal at a specific time. The 24-bit EMG digital signal refers to the 24-bit resolution digital signal generated by the analog-to-digital converter; for example, the 24-bit binary data output by the ADS1299 representing the EMG voltage value.

[0060] Specifically: 1) The sample-and-hold circuit inside the analog-to-digital conversion chip closes the sampling switch at a specific clock rising edge to sample the input filtered EEG signal or EMG signal instantaneously, and then opens the hold switch to maintain the voltage value of the sampling capacitor at the sampling time, thereby obtaining a stable sampled analog EEG signal or sampled analog EMG signal; 2) The successive approximation register analog-to-digital converter uses an internal 2.5V reference voltage as a reference, and through a binary search algorithm, the voltage value of the sampled analog EEG signal or sampled analog EMG signal is compared with a series of comparison voltages generated in a half-decreasing manner for 24 times, starting from the most significant bit to determine the digital code value of each bit in turn, where the first comparison generates the 23rd bit digital value and the last comparison generates the 0th bit digital value; During the conversion process, the digital logic circuit controls the digital-to-analog converter to accurately generate the comparison voltage and latches the digital results of each bit output by the comparator, finally outputting a 24-bit binary format EEG digital signal or EMG digital signal.

[0061] The 24-bit EEG digital signal and / or the 24-bit EMG digital signal are digitally filtered by the internal digital filter to obtain the EEG digital signal and / or the EMG digital signal.

[0062] Wherein, the digital filter refers to an algorithm or hardware module for filtering signals in the digital domain; for example, the digital filter circuit integrated inside the ADS1299 for suppressing high-frequency noise.

[0063] Specifically: 1) The digital filter integrated in the analog-to-digital conversion chip receives the 24-bit electroencephalogram digital signal or the 24-bit electromyogram digital signal, and loads the corresponding difference equation coefficients according to the preset filter type and parameter configuration. The electroencephalogram signal processing adopts 8-order Butterworth low-pass filter coefficients with a cutoff frequency of 40Hz, and the electromyogram signal processing adopts 4-order Bessel low-pass filter coefficients with a cutoff frequency of 500Hz; 2) The digital filter performs convolution calculation on the input signal sequence and the filter coefficients through a multiply-accumulate operation unit. Each 24-bit input sample is first extended to 32-bit precision, then multiplied by a 32-bit filter coefficient, and all product results are summed in a 48-bit accumulator and subjected to saturation processing; 3) The filtered results are truncated to 24-bit valid data and the output register is updated to generate the electroencephalogram digital signal or electromyogram digital signal after digital filtering. For example, when processing the 24-bit electroencephalogram digital signal, the digital filter further suppresses high-frequency noise through the 40Hz low-pass characteristic, while maintaining the integrity and amplitude accuracy of the main electroencephalogram components such as δ wave, θ wave, α wave and β wave.

[0064] In the above optional mode, it is further specified that the analog-to-digital conversion chip converts the analog signal into a 24-bit high-precision digital signal through sample-and-hold and successive approximation register analog-to-digital conversion, and optimizes the signal quality by using internal digital filtering to provide reliable data for subsequent processing.

[0065] In an optional mode, the MCU is specifically configured to: The electroencephalogram digital signal is segmented by using a sliding window processing method, and the electroencephalogram digital signal in each time window is subjected to fast Fourier transform to obtain frequency domain feature data.

[0066] The sliding window processing method refers to a data processing method of segmenting the signal processing, and the window slides with time. For example, the electroencephalogram signal is segmented by 500 milliseconds, and slides every 100 milliseconds. The frequency domain feature data refers to the characteristic representation of the signal in the frequency domain. For example, the amplitude of each frequency component of the electroencephalogram signal obtained by fast Fourier transform.

[0067] Specifically: 1) Take the sliding step as a fixed time interval, and continuously intercept the time window on the electroencephalogram digital signal sequence with a length of 512 sampling points, where the adjacent time windows maintain a 50% overlap rate to ensure frequency domain continuity; 2) The 512-point electroencephalogram digital signal in each time window is first windowed by applying a Hanning window function to reduce spectral leakage, and then converted from time domain to frequency domain representation by a base-2 fast Fourier transform algorithm, which is implemented by a 5-stage butterfly operation unit, and each stage of operation contains 256 complex multiply-add operations; 3) After transformation, the amplitude spectrum data corresponding to the 256 frequency points in the 0-50Hz frequency band with a frequency resolution of about 0.977Hz are extracted as the frequency domain feature data of the time window. For example, when the sampling rate is 500Hz, each time window covers 1.024 seconds of electroencephalogram signal, and after fast Fourier transform, frequency domain feature data containing δ wave, θ wave, α wave and β wave energy distribution are generated.

[0068] Perform an envelope detection algorithm on the electromyogram digital signal to extract amplitude variation information.

[0069] The envelope detection algorithm refers to an information processing algorithm for extracting the envelope of a signal. For example, Hilbert transform is performed on the electromyogram signal to extract the amplitude envelope. The amplitude variation information refers to the information of the change of signal amplitude over time. For example, the sequence of amplitude change over time obtained after envelope detection of the electromyogram signal.

[0070] Specifically, the input 24-bit electromyogram digital signal is subjected to absolute value operation to obtain a full-wave rectified signal; a fourth-order Butterworth low-pass filter with a cutoff frequency of 3Hz is used to smooth the rectified signal to extract its envelope profile, where the filter is implemented by a direct II type second-order section cascade structure, each second-order section uses a difference equation to calculate the output and maintains 32-bit intermediate operation precision to avoid precision loss, and the final output envelope signal is quantized to 16 bits to obtain the amplitude variation information representing the change of electromyogram activity intensity over time. For example, when processing electromyogram digital signals with a sampling rate of 1000Hz, this algorithm can effectively extract the envelope features of the amplitude varying in the range of 10mV to 500mV during muscle contraction and relaxation.

[0071] Fuse the frequency domain feature data and the amplitude variation information with the preset display template, and generate display data frames containing time domain waveforms and frequency domain spectrograms according to the data fusion result.

[0072] The pre-set display template refers to a pre-set display layout and format template. For example, a screen layout template containing a waveform display area, a frequency spectrum display area, and a parameter display area. The data fusion result refers to the result of integrating and processing multiple feature data. For example, a composite data set obtained by fusing brain electrical frequency domain features and electromyographic amplitude information. The time domain waveform refers to a waveform representation of signal amplitude change over time. For example, a voltage change curve of a brain electrical signal on a time axis. The frequency domain spectrum refers to an energy distribution representation of a signal in the frequency domain. For example, a frequency spectrum obtained by fast Fourier transform of a brain electrical signal. The display data frame refers to a data set that constitutes a frame of display picture. For example, a complete picture data containing time domain waveform, frequency domain spectrum, and time information.

[0073] Specifically: 1) mapping each frequency band energy value in the frequency domain feature data of the brain electrical digital signal to the frequency spectrum coordinate system of the pre-set display template through a dynamic normalization algorithm, wherein the four characteristic frequency bands of δ wave, θ wave, α wave, and β wave correspond to different color coding for visual rendering; 2) simultaneously adapting the amplitude change information of the electromyographic digital signal to the horizontal time axis and vertical amplitude axis coordinate system of the time domain waveform display area through a linear interpolation algorithm; 3) using a bilinear interpolation algorithm to perform pixel-level synthesis of the fused multi-source data and the static interface elements of the display template, wherein the time domain waveform is drawn as a blue curve on the upper half of the display area, and the frequency domain spectrum is presented as a red gradient heat map in the lower half of the display area; 4) generating an RGB565 format display data frame containing complete display elements, which contains 320x240 pixels of complete display information, wherein each pixel point is composed of 16-bit color data, and the time domain waveform and the frequency domain spectrum are displayed according to the anatomical standard coordinate system.

[0074] The display data frame is written into an internal integrated display buffer, so that the LCD display circuit reads the display data frame from the display buffer through an RGB565 interface and displays it regularly.

[0075] The display buffer refers to a region in the memory for temporarily storing display data. For example, a storage area in the internal RAM of the MCU for storing the display data frame. The RGB565 interface refers to a 16-bit color depth liquid crystal screen parallel interface. For example, the MCU transmits pixel data to the LCD screen through a 16-bit data bus.

[0076] Specifically: 1) MCU transmits the generated RGB565 format display data frame to the specified storage address space of the internal display buffer in row priority order through the direct memory access controller, and the display buffer is divided into two storage areas in front and back to realize the double buffering mechanism; when a frame of data is completely written into the background buffer, the MCU switches the foreground display buffer to the storage area that has completed writing by setting the memory address remapping register, and starts the timing generator of the LCD controller to generate the pixel clock signal, the row synchronization signal and the frame synchronization signal; 2) the LCD display circuit reads the pixel data stored in the display buffer in synchronization with the pixel clock through the 16-bit parallel RGB565 interface, wherein 16-bit color values of one pixel are read in each clock cycle and converted into analog voltages to drive the corresponding pixel points of the liquid crystal screen to emit light; the whole display process is continuously carried out at a refresh rate of 60Hz, and the LCD controller automatically triggers an interrupt request after completing the reading of a frame of data, and the MCU starts to write the next display data frame into another buffer immediately after responding to the interrupt and repeats the above switching and display process.

[0077] In the above optional mode, the MCU further uses the sliding window and fast Fourier transform technology to extract the frequency domain features of the electroencephalogram signal, and generates visual display data by fusing the electromyographic amplitude change information, thereby improving the real-time performance of signal display and the information richness.

[0078] In an optional mode, the MCU is specifically used for: dividing the electroencephalogram digital signal into at least one electroencephalogram signal data packet of a predetermined time length, and adding a time stamp and an electroencephalogram signal type identifier to each electroencephalogram signal data packet, and dividing the electromyographic digital signal into at least one electromyographic signal data packet of a predetermined time length, and adding a time stamp and an electromyographic signal type identifier to each electromyographic signal data packet.

[0079] Wherein, the predetermined time length refers to a pre-set time interval; for example, the signal is divided into data packets of 1 second length for processing. The electroencephalogram signal data packet refers to an electroencephalogram digital signal segment divided according to the predetermined length; for example, an electroencephalogram signal data segment containing 1000 sampling points. The electroencephalogram signal type identifier refers to a marker for identifying the signal type; for example, adding an "EEG" identifier in the data packet to distinguish the signal type. The electromyographic signal data packet refers to an electromyographic digital signal segment divided according to the predetermined length; for example, an electromyographic signal data segment containing 2000 sampling points. The electromyographic signal type identifier refers to a marker for identifying the signal type; for example, adding an "EMG" identifier in the data packet to distinguish the signal type.

[0080] Specifically, the MCU transmits the generated RGB565 format display data frame in row priority order to a specified storage address space of an internal display buffer through a direct memory access controller, and the display buffer is divided into two storage areas in front and back to realize a double buffering mechanism; when a frame of data is completely written into the background buffer, the MCU switches the foreground display buffer to the storage area that has completed writing by setting a memory address remapping register, and simultaneously starts a timing generator of the LCD controller to generate a pixel clock signal, a row synchronization signal and a frame synchronization signal; the LCD display circuit reads the pixel data stored in the display buffer in sequence through a 16-bit parallel RGB565 interface under the synchronization of the pixel clock, wherein 16-bit color values of one pixel are read in each clock cycle and converted into analog voltages to drive the corresponding pixel points of the liquid crystal screen to emit light; the whole display process is continuously carried out at a refresh rate of 60Hz, and an interrupt request is automatically triggered after the LCD controller completes the reading of a frame of data, and the MCU starts to write the next frame of display data into another buffer immediately after responding to the interrupt and repeats the above switching and display process.

[0081] The LZ4 compression algorithm is used to perform lossless compression processing on each electroencephalogram signal data packet and each electromyogram signal data packet respectively, to generate an electroencephalogram compression data block corresponding to each electroencephalogram signal data packet and an electromyogram compression data block corresponding to each electromyogram signal data packet.

[0082] The LZ4 compression algorithm refers to a lossless data compression algorithm. For example, the LZ4 algorithm is used to compress the electroencephalogram data packet in real time. The electroencephalogram compression data block refers to a data block obtained by compressing the electroencephalogram signal data packet. For example, the electroencephalogram data block generated after LZ4 compression. The electromyogram compression data block refers to a data block obtained by compressing the electromyogram signal data packet. For example, the electromyogram data block generated after LZ4 compression.

[0083] Specifically: 1) each electroencephalogram signal data packet containing 1000 24-bit sampling points or each electromyogram signal data packet containing 2000 24-bit sampling points is processed by byte alignment in 4-byte sequence, and a hash table of the LZ4 compression algorithm is initialized and a 64KB sliding window size is set; 2) during the compression process, the LZ4 compression algorithm reads the input data sequence in sequence, calculates the 32-bit hash value of each 4-byte sequence through a hash function and looks up the matching item in the hash table, replaces the repeated sequence using length encoding and offset encoding when a match is found, and directly outputs the original data that is not matched; 3) a 2-byte token field is added at the head of the compressed data block to identify the distribution of the original data and the matching sequence, wherein the high 4 bits represent the length of the continuous original data and the low 4 bits represent the length of the matching sequence, and finally the electroencephalogram compression data block or the electromyogram compression data block containing the LZ4 frame header and the compressed data is generated.

[0084] generate a corresponding electroencephalogram file header for each compressed electroencephalogram data block and generate a corresponding electromyogram file header for each compressed electromyogram data block; wherein each electroencephalogram file header and each electromyogram file header comprises: a sampling rate, a signal type, time information, and data format description.

[0085] The electroencephalogram file header refers to file header information describing electroencephalogram data properties; for example, a data header containing a sampling rate of 1000 Hz, a signal type of EEG, and a collection timestamp. The electromyogram file header refers to file header information describing electromyogram data properties; for example, a data header containing a sampling rate of 2000 Hz, a signal type of EMG, and a collection timestamp.

[0086] Specifically: 1) allocate a fixed length file header space of 64 bytes for each compressed data block, with the first 4 bytes storing the sampling rate value in little-endian format, and the electroencephalogram signal fixedly written as 1000 to represent a sampling rate of 1000 Hz and the electromyogram signal fixedly written as 2000 to represent a sampling rate of 2000 Hz; 2) store the signal type identifier using 4 bytes in ASCII encoding, with the electroencephalogram file header written as "EEG_" and the electromyogram file header written as "EMG_"; 3) store the collection start time in UNIX timestamp format using 8 bytes, and obtain the UTC time accurate to milliseconds by reading the internal real-time clock module of the MCU; 4) store the data format description in a 16-byte area, including 4 bytes of original data length, 4 bytes of compressed data length, 2 bytes of LZ4 compression algorithm version number, 2 bytes of byte sequence identifier, and 4 bytes of CRC32 checksum; 5) reserve the remaining 32 bytes as an extension field and fill them with zero values. The completed file header is combined with the corresponding compressed data block to form a complete data storage unit.

[0087] Through the SDIO interface, each electroencephalogram compressed data block containing an electroencephalogram file header and each electromyogram compressed data block containing an electromyogram file header are transmitted to the SD card storage circuit, so that the SD card storage circuit writes to the SD card storage medium in FAT32 file system format.

[0088] The SDIO interface refers to a secure digital input-output interface for high-speed data transmission; for example, the MCU communicates with the SD card through the SDIO interface in 4-bit mode. The FAT32 file system format refers to a common file system format; for example, the SD card stores data files in FAT32 format. The SD card storage medium refers to a storage medium that meets the secure digital card standard; for example, an SDHC card with a capacity of 32 GB and a speed rating of Class 10.

[0089] Specifically: 1) MCU sends CMD16 command to SD card through SDIO interface to set the block length of 512 bytes, and then uses CMD24 command to specify the starting sector address of writing; 2) During the transmission process, MCU transmits the complete data packet containing 64-byte file header and compressed data block through the SDIO data line in 4-bit parallel mode, 4-bit data is transmitted per clock cycle, and the CRC16 check module calculates and attaches the check code in real time; 3) After receiving the data, the SD card controller temporarily stores it in the internal buffer, and automatically executes the programming operation to write the data into the flash memory unit when receiving the 512-byte data block; 4) After writing is completed, MCU checks the response state word through CMD13 command to confirm that the writing is successful, and then updates the second cluster chain item of the file allocation table and increases the file size field in the directory item by the corresponding byte number; 5) The whole writing process is carried out in a multi-block transmission mode, and continues until all data blocks are written into the continuous cluster sequence according to the FAT32 specification, and finally the last modification timestamp and file size value of the directory item are updated to complete the storage operation.

[0090] In the above optional mode, the MCU further uses the LZ4 compression algorithm to losslessly compress the signal data packet, and stores it to the SD card through the SDIO interface after adding the file header, which significantly improves the storage efficiency and guarantees the data integrity and readability.

[0091] In this embodiment, Figure 3 The complete hardware block diagram of the brain electromyographic signal processing device is shown, including six core components of MCU, key circuit, LCD display circuit, SD card storage circuit, signal acquisition circuit and power management module and their connection relationship. The power management module receives external DC power input, and supplies power to the system through two-stage voltage stabilization design: the first stage uses a switching regulator to reduce the input voltage to 5V and supply power to the analog circuit, and the second stage uses a linear voltage stabilizer to generate a 3.3V digital power supply for the MCU and digital circuit, while an independent reference voltage source provides a 2.5V precision reference voltage for the ADS1299 analog-to-digital conversion chip; A π-type filter network is arranged in the power supply path to suppress ripple interference, and magnetic bead isolation is arranged in the power supply branch of each functional module to isolate digital and analog power supply noise.

[0092] Figure 3 The MCU as the main controller is implemented by using GD32F470ZI chip, connected with the key circuit through GPIO interface, connected with the LCD display circuit through RGB565 interface, connected with the SD card storage circuit through SDIO interface, and connected with the signal acquisition circuit through SPI interface. The signal acquisition circuit takes ADS1299 analog-to-digital conversion chip as the core, is equipped with voltage follower circuit and filter circuit, and is connected with human lead wire through HDMI form interface.

[0093] Figure 3The signal flow and power distribution are shown in the figure: after the raw electroencephalogram signal and the raw electromyogram signal are input from the HDMI interface, they are sequentially subjected to impedance matching by a voltage follower circuit, signal filtering by a filter circuit (in which the electroencephalogram signal is subjected to three-order filtering processing, and the electromyogram signal is subjected to two-order filtering processing), analog-to-digital conversion by an ADS1299 chip, and finally converted into digital signals and transmitted to the MCU through the SPI interface. The MCU simultaneously processes three outputs: outputting display data to the LCD display circuit through the RGB565 interface to realize real-time waveform display, outputting storage data to the SD card storage circuit through the SDIO interface to realize persistent storage of data, and receiving user operation instructions input by the key circuit through the GPIO interface to realize device interaction control. The power supply of all functional modules is uniformly distributed and managed by the power management module. Figure 3 In the figure, the specific models and interface types of each functional module are labeled, and the device hardware architecture, data transmission path and power distribution system are completely presented.

[0094] The application further provides a brain and muscle electrical signal processing system comprising the brain and muscle electrical signal processing device.

[0095] In the specification provided herein, a large number of specific details are described. However, it can be understood that the embodiments of the application can be practiced without these specific details. Similarly, in order to simplify the application and help understand one or more of the various inventive aspects, in the above description of the exemplary embodiments of the application, various features of the embodiments of the application are sometimes grouped together into a single embodiment, figure or description thereof. Among them, the claims following the detailed description are thus expressly incorporated into the detailed description, wherein each claim itself is a separate embodiment of the application.

[0096] It should be noted that the above embodiments illustrate the application rather than limit the application, and a person skilled in the art can design alternative embodiments without departing from the scope of the appended claims. In the claims, any reference signs located between parentheses shall not constitute a limitation on the claims. The word "comprising" does not exclude the presence of elements or steps not listed in the claims. The word "a" or "an" preceding an element does not exclude the presence of several such elements. The application can be implemented by means of hardware comprising several distinct elements, and by means of a suitably programmed computer. In a unit claim enumerating several means, the several means can be embodied by one and the same item of hardware. The use of the words first, second and third, etc. does not imply any order. These words can be understood as names. The steps of the above-described embodiments, unless otherwise specified, should not be understood as limiting the order of execution.

[0097] Although the embodiments of the present application have been shown and described above, it is understood that the above-described embodiments are exemplary and are not to be construed as limiting the present application, and that variations, modifications, substitutions and changes can be made by those skilled in the art without departing from the scope of the present application.

Claims

1. A brain electromyography signal processing device, characterized in that, include: The system includes an MCU, an LCD display circuit, an SD card storage circuit, and a signal acquisition circuit. The MCU is connected to the LCD display circuit, the SD card storage circuit, and the signal acquisition circuit. The signal acquisition circuit is also connected to an HDMI interface for connecting to the human body lead wire. The signal acquisition circuit is used to: sequentially perform impedance matching, signal filtering and analog-to-digital conversion on the raw EEG signal and / or raw EMG signal connected to the HDMI interface to obtain EEG digital signal and / or EMG digital signal; The MCU is used to: parse the EEG digital signals and / or the EMG digital signals, generate display data and display it through the LCD display circuit, and format the EEG digital signals and / or the EMG digital signals to generate storage data and store it through the SD card storage circuit.

2. The brain electromyography signal processing device according to claim 1, characterized in that, Also includes: Button circuit; The button circuit is connected to the MCU; The button circuit is used to: receive user operation instructions and send them to the MCU, so that the MCU can execute the user operation instructions.

3. The brain electromyography signal processing device according to claim 1, characterized in that, The signal acquisition circuit includes: a voltage follower circuit, a filter circuit, and an analog-to-digital converter chip connected in sequence; The voltage follower circuit is used to: perform impedance matching on the raw EEG signal and / or raw EMG signal connected to the HDMI interface to obtain impedance-matched EEG signal and / or EMG signal; The filtering circuit is used to: perform third-order filtering on the impedance-matched EEG signal to obtain the filtered EEG signal, and / or perform second-order filtering on the impedance-matched EMG signal to obtain the filtered EMG signal. The analog-to-digital converter chip is used to: perform analog-to-digital conversion on the filtered EEG signal and / or the filtered EMG signal to obtain the EEG digital signal and / or the EMG digital signal.

4. The brain electromyography signal processing device according to claim 3, characterized in that, The voltage follower circuit includes: a voltage follower composed of operational amplifiers; the voltage follower circuit is specifically used for: The voltage follower converts the high-impedance input EEG signal into a low-impedance output EEG signal to generate the impedance-matched EEG signal, and / or converts the high-impedance input electromyography (EMG) signal into a low-impedance output EMG signal to generate the impedance-matched EMG signal.

5. The brain electromyography signal processing device according to claim 3, characterized in that, The filtering circuit comprises three cascaded Sallen-Key filters, wherein: The first-stage Sallen-Key filter is configured as a high-pass filter, with a cutoff frequency of 0.5Hz, used to remove DC components and extremely low-frequency interference from the EEG signal. The second-stage Sallen-Key filter is configured as a bandpass filter, with the passband frequency range set to 0.5Hz to 40Hz, for extracting the effective frequency band components of the EEG signal; The third-stage Sallen-Key filter is configured as a 50Hz notch filter to filter out power frequency interference in EEG signals. The filtering circuit is specifically used to process the impedance-matched EEG signal sequentially using the three-stage series Sallen-Key filter to generate the filtered EEG signal.

6. The brain electromyography signal processing device according to claim 3, characterized in that, The filtering circuit comprises two cascaded Sallen-Key filters, wherein: The first-stage Sallen-Key filter is configured as a high-pass filter, with a cutoff frequency of 10Hz, for high-pass filtering of electromyographic signals. The second-stage Sallen-Key filter is configured as a low-pass filter, with a cutoff frequency of 500Hz, for low-pass filtering of electromyographic signals. The filtering circuit is specifically used to: perform second-order filtering on the impedance-matched electromyographic signal using the two-stage series Sallen-Key filter to generate the filtered electromyographic signal.

7. The brain electromyography signal processing device according to any one of claims 3 to 6, characterized in that, The analog-to-digital converter chip is specifically used for: The filtered EEG signal is sampled and held to obtain a sampled analog EEG signal, and then converted into a 24-bit EEG digital signal by a successive approximation register analog-to-digital converter; and / or, the filtered EMG signal is sampled and held to obtain a sampled analog EMG signal, and then converted into a 24-bit EMG digital signal by the same successive approximation register analog-to-digital converter. The 24-bit EEG digital signal and / or the 24-bit EMG digital signal are digitally filtered using an internally integrated digital filter to obtain the EEG digital signal and / or the EMG digital signal.

8. The brain electromyography signal processing device according to claim 1, characterized in that, The MCU is specifically used for: The EEG digital signal is segmented using a sliding window processing method, and a fast Fourier transform is performed on the EEG digital signal within each time window to obtain frequency domain feature data. An envelope detection algorithm is applied to the electromyographic digital signal to extract amplitude change information; The frequency domain feature data and the amplitude change information are fused with a preset display template, and a display data frame containing time domain waveform and frequency domain spectrum is generated based on the data fusion result. The display data frame is written into the internally integrated display buffer so that the LCD display circuit periodically reads the display data frame from the display buffer and displays it via the RGB565 interface.

9. The brain electromyography signal processing device according to claim 1, characterized in that, The MCU is specifically used for: The EEG digital signal is divided into at least one EEG signal data packet of a predetermined time length, and a timestamp and EEG signal type identifier are added to each EEG signal data packet. Similarly, the EMG digital signal is divided into at least one EMG signal data packet of a predetermined time length, and a timestamp and EMG signal type identifier are added to each EMG signal data packet. The LZ4 compression algorithm is used to perform lossless compression on each EEG signal data packet and each EMG signal data packet to generate EEG compressed data block and EMG compressed data block corresponding to each EEG signal data packet. A corresponding EEG file header is generated for each compressed EEG data block, and a corresponding EMG file header is generated for each compressed EMG data block; each EEG file header and each EMG file header contains: sampling rate, signal type, time information and data format description; Through the SDIO interface, each compressed EEG data block containing an EEG header and each compressed EMG data block containing an EMG header are transmitted to the SD card storage circuit, so that the SD card storage circuit writes to the SD card storage medium in the FAT32 file system format.

10. A brain electromyography signal processing system, characterized in that, Includes the electromyography signal processing device as described in any one of claims 1 to 9.

Images