Multi-gear test mode control circuit based on negative voltage triggering and method thereof
By using a multi-level test mode control circuit based on negative voltage triggering, and utilizing the negative voltage pulse signal bat_reverse from the battery reverse connection detection terminal for cascaded frequency division and counting, the test timing and gating observation path are automatically established. This solves the problem of dependence on ATE and pin resources in mass production testing of analog mixed signal chips, and realizes a simple and timing-robust test scheme.
Patent Information
- Application Number
- CN202511420892.5
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-09-30
- Publication Date
- 2025-12-12
AI Technical Summary
Mass production testing of existing analog mixed-signal chips is highly dependent on ATE and pin resources. Adding test PADs or pins is costly, and entering test mode via MCU or register is limited by power-on timing. Soft triggering is prone to false triggering, and traditional BIST implementation requires dedicated test interfaces and complex control logic.
A multi-level test mode control circuit based on negative voltage triggering is adopted, including a frequency divider chain processing module, a timing conditioning module, a state generation module, a decoding module, and a gating module. The negative voltage trigger pulse signal bat_reverse from the battery reverse connection detection terminal is used for cascaded frequency division and counting to generate a test mode enable signal test_mode, and automatically establishes on-chip test timing and gating observation path.
It achieves a simple and timing-robust test solution that eliminates the need for additional test pins and complex communication/power-on timing control. It is suitable for large-scale mass production testing and field diagnostics, reduces ATE dependence and fixture complexity, and supports rapid tiered testing and simple readout.
Smart Images
Figure CN121114733A_ABST
Abstract
Description
TECHNICAL FIELD
[0001] The present application relates to the technical field of integrated circuits, in particular to the application of built-in self-test (BIST) in analog mixed-signal chips, and specifically to a multi-grade test mode control circuit based on negative voltage triggering and a method thereof. BACKGROUND
[0002] In the production test and field fast verification of power management IC and similar analog mixed-signal devices, as the precision of analog mixed-signal chips improves, the production test relies more on ATE and pin resources, but due to the high cost of adding test pads or pins, and the limitation of power-on timing when entering the test mode through MCU or register, soft triggering is easy to be triggered by mistake, and pure voltage threshold triggering lacks reliable synchronization. Therefore, the existing built-in self-test (BIST) reduces the dependence on ATE by establishing test timing and observation paths inside the chip, but traditional implementation often requires a special test interface and complex control logic.
[0003] Therefore, there is an urgent need for a test scheme that does not add pins, has simple triggering and robust timing, and has on-chip test timing capability in test mode, and can respond to evaluation when necessary. SUMMARY
[0004] To solve the above problems, the present application provides a multi-grade test mode control circuit based on negative voltage triggering and a method thereof, which can achieve simplicity and timing robustness without the need for additional test pins or complex communication / power-on timing control, and is suitable for large-scale production testing.
[0005] The present application adopts the following technical scheme, a multi-grade test mode control circuit based on negative voltage triggering, comprising: A frequency chain processing module is used for shaping and cascading frequency division processing of the negative voltage trigger pulse signal bat_reverse, and generating a test mode enable signal test_mode when the count reaches a threshold value ， So as to automatically establish the timing basis required for self-test on-chip in test mode; A timing conditioning module is connected with the frequency chain processing module, and is used for outputting an on-chip test beat clk_dec according to the test mode state; A state generation module is connected with the timing conditioning module, and is used for driving state sequence advancement based on the test beat clk_dec to generate a multi-bit parallel state code; A decoding module is connected with the state generation module, and is used for logically decoding the multi-bit parallel state code to generate corresponding multi-path test control signals; The gating module is connected with the decoding module, and is configured to generate a plurality of test signals according to a plurality of test control signals, and to select and output different test signals through at least one observation pin, so that the observation routing of the self-test on chip is completed.
[0006] Further, the frequency division chain processing module includes N cascaded D flip-flops, and is divided into D1~D N , and N≥2; the D terminal of each D flip-flop in the D flip-flops D1~D N-1 is connected with the inverted output terminal of the D flip-flop itself, and the inverted output terminal of the D flip-flop of the previous stage is connected with the clock terminal CLK of the D flip-flop of the next stage; the reset terminals R of the D flip-flops D1~D N are connected with a reset signal RST; the clock terminal CLK of the D flip-flop D1 is connected with a negative voltage trigger pulse signal bat_reverse, the inverted output terminal of the D flip-flop D N-1 is connected with the clock terminal CLK of the D flip-flop D N , the D terminal of the D flip-flop D N is connected with a high-level signal VDD, and the inverted output terminal of the D flip-flop D N generates a test mode enable signal test_mode after being connected with an inverter INV1. Further, the D flip-flops D1~D N-1 output 2, 4, 8,..., 2^(N-1) frequency division signals respectively, to provide a stable reference for the counting and on-chip self-test beats in the test mode; Further, the D terminal of the D flip-flop D N is connected with a high-level signal VDD, the clock terminal CLK of the D flip-flop D N is driven by the inverted output terminal of the D flip-flop D N-1 ; when the cumulative counting of the negative voltage trigger pulse signal bat_reverse by the D flip-flop D N of the current stage reaches a preset threshold, the D flip-flop D N is set and kept at the clock active edge; the inverted output of the D flip-flop D K generates the test mode enable signal test_mode through the inverter INV1, to start the on-chip self-test process; Further, the timing conditioning module includes an OR gate, and the state generation module includes K+1 cascaded T flip-flops, and is divided into T0~T K , and K≥0; the negative voltage trigger pulse signal bat_reverse and the inverted output signal of the D flip-flop D N are connected with the input terminals of the OR gate, and the output terminal of the OR gate is connected with the clock terminal CLK of the T flip-flop T0; the T flip-flops T0~T KThe reset terminals R of all three flip-flops are connected to the reset signal RST; the T flip-flops T0~T K In each stage of the T flip-flop, the T terminal is connected to its own inverting output terminal, and the inverting output terminal of the preceding stage T flip-flop is connected to the clock terminal CLK of the following stage T flip-flop; the T flip-flops T0~T K The output terminals generate status codes Q0~QK respectively, which serve as equivalent test vectors for on-chip self-testing. Furthermore, in non-test mode, the clock signal clk_dec output by the timing conditioning module is a constant high-level signal; in test mode, the clock signal clk_dec output by the timing conditioning module is in phase with the negative voltage trigger pulse signal bat_reverse at the input terminal, and is used as the on-chip self-test clock. Furthermore, the decoding module decodes the multi-bit parallel status code to generate M test control signals. The M test control signals are divided into test control signals A0~AM, and M≥0. Among them, test control signal A0 is a continuously valid signal in the test mode state, and test control signals A1~AM are activated sequentially according to the timing of the negative voltage trigger pulse signal bat_reverse. This invention also provides a multi-level test mode control method based on negative voltage triggering, comprising: The negative voltage trigger pulse signal bat_reverse generated by the battery reverse connection detection path is used as the trigger signal. It is controlled by timing and counting through N-level cascaded frequency division. When the count reaches the threshold, test_mode is set to enter the test mode. After entering test mode, the on-chip test clock clk_dec drives the state sequence to advance to form an equivalent test vector; based on the vector decoding, multiple test control signals are generated and the corresponding observation paths are selected and output externally.
[0007] Furthermore, before entering test mode, the following steps are included: S1.1 In response to the battery status, and when reverse connection of the battery is detected, a negative voltage trigger pulse signal bat_reverse is generated sequentially through the battery reverse connection detection terminal; S1.2 The negative voltage trigger pulse signal bat_reverse is processed by N-stage synchronous frequency division and outputs the frequency division signal step by step; S1.3. Use the frequency division output of the last stage as the counting reference, and when the count reaches the set threshold, set the test mode enable signal test_mode to enter the test mode. Furthermore, after entering test mode, the following steps are included: S2.1, the beat signal clk_dec output by the timing conditioning module is in phase with the negative voltage trigger pulse signal bat_reverse; S2.2, through the K+1 level cascade T flip-flop, the corresponding state code Q0~QK is output step by step; S2.3, after the test is finished, the test mode is exited through the reset signal.
[0008] The beneficial effects of the present application are that the negative voltage trigger pulse signal bat_reverse output by the battery anti-reverse connection detection end is used as the only external trigger channel, and the entering of the test mode and the multi-gear selection are realized through multi-stage synchronous frequency division processing, that is, in the test mode, the test timing can be automatically established, and different test gears are gated through the corresponding observation path for output, the results output through the corresponding observation path can be read and judged by the external instrument or ATE, so that the fast grading test and simple readout are realized, the whole control scheme hardware implementation is extremely simple, the timing is robust, and it is not necessary to add test pins or complex communication / power-on timing control, which is suitable for large-scale mass production test and supports on-site diagnosis application, and has good use value. BRIEF DESCRIPTION OF DRAWINGS
[0009] Figure 1 is the flowchart of the present application; Figure 2 is the digital timing waveform diagram in the present application; Figure 3 is the circuit principle diagram in the present application; Figure 4 is the gating module and output mapping relationship diagram in the present application; Figure 5 is the structure block diagram of the present application. DETAILED DESCRIPTION
[0010] As shown in Figures 1-5 , a multi-gear test mode control circuit based on negative voltage trigger of the present application comprises: a frequency chain processing module, used for shaping and cascade frequency division processing of the negative voltage trigger pulse signal bat_reverse, and generating a test mode enable signal test_mode when the count reaches a threshold ， so as to automatically establish the timing basis required for self-test on chip in the test mode; a timing conditioning module, connected with the frequency chain processing module, used for outputting a test beat clk_dec on chip according to the test mode state; a state generation module, connected with the timing conditioning module, used for driving a state sequence based on the test beat clk_dec to generate a multi-bit parallel state code as an equivalent test vector of on-chip self-test; The decoding module is connected with the state generating module and is configured to perform logical decoding on the multi-bit parallel state code to generate corresponding multi-path test control signals. The gating module is connected with the decoding module and is configured to generate multi-path test signals according to the multi-path test control signals, and to select and output different test signals through at least one observation pin, so as to complete the observation routing of the self-test on the chip.
[0011] The frequency division chain processing module includes N cascaded D flip-flops and is divided into D1~D N , and N≥2. The number of frequency division stages N can be flexibly configured according to timing requirements and synchronization requirements. The D terminal of each D flip-flop in the D flip-flops D1~D N-1 is connected with the inverted output terminal thereof, and the inverted output terminal of the previous D flip-flop is connected with the clock terminal CLK of the next D flip-flop. The reset terminals R of the D flip-flops D1~D N are all connected with a reset signal RST. The clock terminal CLK of the D flip-flop D1 is connected with a negative voltage trigger pulse signal bat_reverse. The inverted output terminal of the D flip-flop D N-1 is connected with the clock terminal CLK of the D flip-flop D N . The D terminal of the D flip-flop D N is connected with a high-level signal VDD. The inverted output terminal of the D flip-flop D N generates a test mode enable signal test_mode after being connected with an inverter INV1. The D flip-flops D1~D N-1 output 2, 4, 8,..., 2^(N-1) frequency division signals respectively, to provide stable references for counting and on-chip self-test beats in the test mode. The D terminal of the D flip-flop D N is connected with a high-level signal VDD, and the clock terminal CLK thereof is driven by the inverted output terminal of the D flip-flop D N-1 . When the cumulative count of the negative voltage trigger pulse signal bat_reverse by the current stage of the frequency division chain reaches a preset threshold, the D flip-flop D N is set and maintained at the clock active edge. The inverted output of the D flip-flop D N generates the test mode enable signal test_mode through the inverter INV1, to start the on-chip self-test process.
[0012] The timing conditioning module includes an OR gate OR. The state generating module includes K+1 cascaded T flip-flops and is divided into T0~T K , and K≥0. The negative voltage trigger pulse signal bat_reverse and the inverted output signal of the D flip-flop D N are both connected with the input terminals of the OR gate OR. The output terminal of the OR gate OR is connected with the clock terminal CLK of the T flip-flop T0. The T flip-flops T0~T KThe reset ends R of the T flip-flops T0-TK are connected with a reset signal RST; the T ends of each T flip-flop in the T flip-flop chain are connected with the reverse output ends of the T flip-flops themselves, and the reverse output ends of the previous T flip-flops are connected with the clock ends CLK of the subsequent T flip-flops; the output ends of the T flip-flops T0-TK correspond to generate state codes Q0-QK respectively, as equivalent test vectors for on-chip self-test. K The T ends of each T flip-flop in the T flip-flop chain are connected with the reverse output ends of the T flip-flops themselves, and the reverse output ends of the previous T flip-flops are connected with the clock ends CLK of the subsequent T flip-flops; the output ends of the T flip-flops T0-TK correspond to generate state codes Q0-QK respectively, as equivalent test vectors for on-chip self-test. K The output ends of the T flip-flops T0-TK correspond to generate state codes Q0-QK respectively, as equivalent test vectors for on-chip self-test.
[0013] In the non-test mode state, the beat signal clk_dec output by the timing conditioning module is a constant high-level signal; in the test mode state, the beat signal clk_dec output by the timing conditioning module is in-phase with the input end negative voltage trigger pulse signal bat_reverse, and is used as a beat for on-chip self-test.
[0014] The decoding module decodes the multiple-bit parallel state codes to generate M-path test control signals, the M-path test control signals are divided into test control signals A0-AM, and M≥0; wherein, the test control signal A0 is a continuous effective signal in the test mode state, and the test control signals A1-AM are sequentially activated according to the timing of the negative voltage trigger pulse signal bat_reverse.
[0015] The application further provides a multi-grade test mode control method based on negative voltage triggering, comprising: The negative voltage trigger pulse bat_reverse is taken as a trigger source, and then is subjected to timing and counting control through N-stage cascaded frequency division; when the counting reaches a threshold, the test_mode is set to enter the test mode; Specifically, before entering the test mode, the following steps are included: S1.1, in response to the battery state, and when the battery reverse connection is detected, the negative voltage trigger pulse signal bat_reverse is generated in time sequence through the battery anti-reverse connection detection end; S1.2, the negative voltage trigger pulse signal bat_reverse is subjected to N-stage synchronous frequency division processing, and 2, 4, 8... 2^(N-1) frequency division signals are output step by step; S1.3, the frequency division output of the last stage is taken as a counting reference, and when the counting reaches a set threshold (that is, after a predetermined number of negative voltage trigger pulses are received), the D flip-flop D N is set and kept, the test mode enabling signal test_mode is set through the NOT gate INV1 to enter the test mode, indicating that the test mode is started and the on-chip self-test process is enabled; Wherein, the frequency division signals of the previous N-1 stages provide the synchronization function of asynchronous signals, effectively inhibiting metastable states; the frequency division output of the last stage is taken as a counting reference, for entering the test mode and timing control; The test mode enable signal test_mode is set high when the pulse count reaches a preset threshold; After entering test mode, the on-chip test clock clk_dec drives the state sequence to advance to form an equivalent test vector; based on the vector decoding, multiple test control signals are generated and the corresponding observation paths are selected and output externally; Specifically, after entering test mode, the following steps are included: S2.1 In non-test mode, the OR gate outputs a constant high level to synchronously preset the subsequent K-stage cascaded T flip-flops and achieve initialization; after entering test mode, the clock signal clk_dec output by the OR gate is in phase with the negative voltage trigger pulse signal bat_reverse to provide a hold time margin and drive the state sequence forward. S2.2, Through the K+1 cascaded T flip-flops, the corresponding status codes Q0~QK are output step by step; S2.3 After the test is completed, exit the test mode by using the reset signal; The multi-bit status code is decoded step by step to generate M mutually exclusive test control signals {A0, A1, ..., AM}, and based on the M test control signals, corresponding multi-channel test levels are generated. Each test level can select the corresponding function module under test and observation node. Then, different test levels are selected and output through the corresponding observation path. That is to say, each test level connects the selected test signal to the corresponding observation pin STAT and outputs it to the outside in the form of voltage / level, which is convenient for external instruments or ATE to read and judge. Among them, the test control signal A0 remains valid after entering the test mode as a global test enable, such as Figure 2 As shown, the remaining test control signals are activated sequentially with the pulse sequence to select different tested functional modules and observation paths; the state generation level K and the number of test ranges M can be flexibly configured according to test requirements; M test control signals correspond to M tested signals; Test control signals A0 to AM respectively select the corresponding test signals 0 to M, realizing flexible mapping between test ranges and the tested functional modules. The specific mapping relationship and the number of test items can be flexibly configured according to product requirements. The type and number of functional modules to be tested can be configured according to the functions of the analog mixed-signal chip, including but not limited to power management, protection circuits, reference voltage, current detection, etc.
[0016] This invention uses the negative voltage trigger pulse signal bat_reverse generated by the battery reverse connection detection terminal as the sole external trigger source. The negative voltage trigger pulse signal bat_reverse continuously applied on the input side enters the test mode after on-chip timing processing and counting. In the test mode, corresponding multi-channel test levels are generated based on M-channel test control signals. Then, corresponding test conditions are established under each test level (that is, the corresponding function module under test is connected), and the corresponding signal under test is selected. The signal is output by the corresponding existing observation pin STAT for external judgment. Then, the process is looped or reset, avoiding the addition of test PADs and packaging costs.
[0017] The entire self-test process of this invention is driven solely by the number of external negative voltage trigger pulse signals bat_reverse; the continuously applied negative voltage trigger pulse signals bat_reverse at the input side provide a stable timing sequence after synchronization processing and delay buffering; exiting the test mode can be achieved by the reset signal RST, and the above complete test process can be repeated by applying the negative voltage trigger pulse signal bat_reverse sequence again.
[0018] In summary, the present invention has the following technical effects: 1. No new pins added, single-entry multiplexing: The existing negative voltage trigger pulse signal bat_reverse is reused as the only trigger channel. The signal under test is selected by the gating module and output by the existing observation pin STAT, avoiding the addition of PAD and packaging costs; 2. Robust entry and reliable timing: Multi-level synchronization + frequency division and phase / delay conditioning are used for the negative voltage trigger pulse signal bat_reverse to effectively reduce the risk of metastability and false triggering, and ensure the hold or settling time margin; 3. Lightweight self-test: After entering test mode, the analog mixed signal chip automatically establishes test conditions on the chip and selects the signal node under test; externally, only a negative pulse needs to be injected and the observation pin STAT needs to be read. No communication register configuration or complex power-on timing is required, reducing the dependence on ATE and the complexity of fixtures. 4. Progressive multi-level and parameterized control: The test control signal A0 to AM can be progressively selected through the method of "counting or interval → level window"; each test level can not only select the signal to be tested, but also load the preset test function module of the test level, which can be quickly expanded / tailored according to the product test spectrum. 5. Low hardware overhead and easy integration: It uses a small number of flip-flops and basic gate circuits to realize entry judgment, state progression and decoding. The structure is clear, the area and power consumption are small, and it is easy to reuse in various power management / analog devices. 6. Easy to mass produce and maintain: External control is only the number of negative pulses (or simple intervals), and the judgment criteria are uniform; it supports cyclic execution and reset exit, which facilitates rapid verification of production lines, aging and rework.
[0019] It will be apparent to those skilled in the art that the present invention is not limited to the details of the exemplary embodiments described above, and that the invention can be implemented in other specific forms without departing from its spirit or essential characteristics. Therefore, the embodiments should be considered in all respects as exemplary and non-limiting, and the scope of the invention is defined by the appended claims rather than the foregoing description. Thus, all variations falling within the meaning and scope of equivalents of the claims are intended to be included within the present invention. No reference numerals in the claims should be construed as limiting the scope of the claims.
[0020] Furthermore, it should be understood that although this specification describes embodiments, not every embodiment contains only one independent technical solution. This narrative style is merely for clarity. Those skilled in the art should consider the specification as a whole, and the technical solutions in each embodiment can also be appropriately combined to form other embodiments that can be understood by those skilled in the art.
Claims
1. A multi-stage test mode control circuit based on negative voltage triggering, characterized in that: include: The frequency divider chain processing module is used to shape and cascade frequency divide the negative voltage trigger pulse signal bat_reverse, and generate the test mode enable signal test_mode when the count reaches the threshold, so as to automatically establish the timing basis required for self-test on the chip in test mode. The timing conditioning module, connected to the frequency divider chain processing module, is used to output the on-chip test clock clk_dec according to the test mode status. The state generation module, connected to the timing conditioning module, is used to drive the state sequence forward based on the test beat clk_dec to generate a multi-bit parallel state code. The decoding module, connected to the state generation module, is used to perform logical decoding on the multi-bit parallel state code to generate corresponding multi-channel test control signals. The gating module, connected to the decoding module, is used to generate multiple test signals based on the multiple test control signal, and to select at least one observation pin for output of different test signals, thereby completing the observation route for self-test on the chip.
2. The multi-level test mode control circuit based on negative voltage triggering according to claim 1, characterized in that: The frequency divider chain processing module includes N cascaded D flip-flops, divided into D1~D2. N And N≥2; the D flip-flops D1~D N-1 In each stage of the D flip-flop, the D terminal is connected to its own inverting output terminal, and the inverting output terminal of the preceding stage D flip-flop is connected to the clock terminal CLK of the following stage D flip-flop; the D flip-flops D1~D2... N The reset terminals R of the D flip-flops are all connected to the reset signal RST; the clock terminal CLK of the D flip-flop D1 is connected to the negative voltage trigger pulse signal bat_reverse. N-1 The inverting output terminal of the D flip-flop is connected to the D flip-flop. N The D flip-flop is connected to the clock terminal CLK. N The D terminal is connected to a high-level signal VDD, and the D flip-flop D... N The inverted output terminal is connected to the NOT gate INV1 to generate the test mode enable signal test_mode.
3. The multi-level test mode control circuit based on negative voltage triggering according to claim 2, characterized in that: The D flip-flops D1~D N-1 The frequency division signals are output as 2, 4, 8, ..., 2^(N-1) respectively, providing a stable reference for the counting and on-chip self-test clock when entering test mode.
4. The multi-level test mode control circuit based on negative voltage triggering according to claim 2, characterized in that: The D flip-flop D N The D terminal is connected to a high-level signal VDD, and the D flip-flop D... N The clock input CLK is controlled by the D flip-flop D. N-1 The inverting output terminal is driven; when the cumulative count of the negative voltage trigger pulse signal bat_reverse by the current stage frequency divider chain reaches a preset threshold, the D flip-flop D... N The D flip-flop is set and held on its clock effective edge; N The inverted output is used to generate a test mode enable signal test_mode via the NOT gate INV1, which is used to start the on-chip self-test process.
5. The multi-level test mode control circuit based on negative voltage triggering according to claim 1, characterized in that: The timing conditioning module includes an OR gate; the state generation module includes K+1 cascaded T flip-flops, divided into T0~T1 stages. K And K≥0; the negative voltage trigger pulse signal bat_reverse and the D flip-flop D N The inverted output signals are all connected to the input of the OR gate, and the output of the OR gate is connected to the clock input CLK of the T flip-flop T0; the T flip-flops T0~T K The reset terminals R of all three flip-flops are connected to the reset signal RST; the T flip-flops T0~T K In each stage of the T flip-flop, the T terminal is connected to its own inverting output terminal, and the inverting output terminal of the preceding stage T flip-flop is connected to the clock terminal CLK of the following stage T flip-flop; the T flip-flops T0~T K The output terminals generate status codes Q0~QK respectively, which serve as equivalent test vectors for on-chip self-testing.
6. The multi-stage test mode control circuit based on negative voltage triggering according to claim 1, characterized in that: In non-test mode, the timing conditioning module outputs a constant high-level clock signal clk_dec; in test mode, the timing conditioning module outputs a clock signal clk_dec that is in phase with the input negative voltage trigger pulse signal bat_reverse, and is used as the on-chip self-test clock.
7. The multi-level test mode control circuit based on negative voltage triggering according to claim 1, characterized in that: The decoding module decodes the multi-bit parallel status code to generate M test control signals. The M test control signals are divided into test control signals A0~AM, and M≥0. Among them, test control signal A0 is a continuously valid signal in the test mode state, and test control signals A1~AM are activated sequentially according to the timing of the negative voltage trigger pulse signal bat_reverse.
8. A multi-stage test mode control method based on negative voltage triggering, characterized in that: include: The negative voltage trigger pulse signal bat_reverse generated by the battery reverse connection detection path is used as the trigger signal. It is controlled by timing and counting through N-level cascaded frequency division. When the count reaches the threshold, test_mode is set to enter the test mode. After entering test mode, the on-chip test clock clk_dec drives the state sequence to advance to form an equivalent test vector; based on the vector decoding, multiple test control signals are generated and the corresponding observation paths are selected and output externally.
9. The multi-stage test mode control method based on negative voltage triggering according to claim 8, characterized in that: Before entering test mode, the following steps are required: S1.1 In response to the battery status, and when reverse connection of the battery is detected, a negative voltage trigger pulse signal bat_reverse is generated sequentially through the battery reverse connection detection terminal; S1.2 The negative voltage trigger pulse signal bat_reverse is processed by N-stage synchronous frequency division and outputs the frequency division signal step by step; S1.
3. Use the frequency division output of the last stage as the counting reference, and when the count reaches the set threshold, set the test mode enable signal test_mode to enter the test mode.
10. The multi-stage test mode control method based on negative voltage triggering according to claim 8, characterized in that: After entering test mode, the following steps are included: S2.1 The clock signal clk_dec output by the timing conditioning module is in phase with the negative voltage trigger pulse signal bat_reverse; S2.2, Through the K+1 cascaded T flip-flops, the corresponding status codes Q0~QK are output step by step; S2.3 After the test is completed, exit the test mode by using the reset signal.