Over-current protection control circuit of low dropout regulator and low dropout regulator

Abstract

The invention discloses an overcurrent protection control circuit of a low-dropout linear regulator and the low-dropout linear regulator, and relates to the field of voltage regulators. A first sampling module is connected with a drain electrode, a grid electrode and a source electrode of a power control tube in the low-dropout linear regulator and a first current comparator; the first current comparator is further connected with the grid electrode of the first protection switch and the input voltage end of the low dropout linear regulator, the source electrode of the first protection switch is connected with the grid electrode of the power control tube, the drain electrode of the first protection switch is grounded, and the source electrode of the power control tube is connected with the voltage output end of the low dropout linear regulator; the second sampling module is respectively connected with the drain electrode of the power control tube, the grid electrode of the power control tube and the clamping module, the clamping module is connected with the grid electrode of the second protection switch through the second current comparator and is also connected with the source electrode of the power control tube, the drain electrode of the second protection switch is grounded, and the source electrode of the second protection switch is connected with the grid electrode of the power control tube. The reliability of current limiting can be improved.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of voltage stabilizers, in particular to an overcurrent protection control circuit of a low dropout linear voltage regulator and a low dropout linear voltage regulator. BACKGROUND

[0002] Low dropout linear voltage regulator (LDO) is a key sub-module in integrated circuit chip, which has the advantages of small output ripple, low output noise, easy integration, etc., and is widely used in high-performance digital-analog hybrid circuits and digital circuits. Overcurrent protection is one of the important auxiliary functions of LDO circuit, which is mainly to prevent the phenomenon of burning power tube when LDO output is shorted to ground or large current load appears, so as to achieve the purpose of chip not being damaged. When the power tube current of LDO reaches a certain value, the overcurrent protection circuit will start to prevent the power tube current from continuing to increase and shut down the LDO. When the large current of the power tube is removed, the LDO will automatically recover and restart, and the LDO will work normally.

[0003] In the existing technology, there are mainly two kinds of LDO overcurrent protection modes, one is constant overcurrent protection, and the other is foldback overcurrent protection. For constant overcurrent protection, when the LDO output current reaches the current limiting point, the power tube current remains constant, and at the same time the output voltage of the LDO is pulled to ground. Foldback overcurrent protection is to limit the output current of the LDO to a relatively small current value when the LDO reaches the current limiting point.

[0004] Whether it is constant overcurrent protection or foldback overcurrent protection, it is necessary to sample the current flowing through the power control tube in the LDO or the load current of the LDO according to a certain proportion. The sampling principle diagram of the prior art is shown in Figure 1 The drain of the power control tube of the LDO is connected to the source of MP6 and MP7, the source of the power control tube of the LDO is connected to the output voltage Vout of the LDO, the gate of the power control tube of the LDO is connected to the gate of the sampling tube MS, the source of the sampling tube MS is connected to the source of the power control tube of the LDO, the drain of MP6 is connected to the drain of the sampling tube MS, the gate of MP6 is connected to the gate of MP7, the drain of MP7 is connected to the output current terminal of the LDO, the gate of MP7 is connected to the drain of MP6, and the drain of the power control tube, the source of MP6 and the source of MP7 are also connected to the input voltage Vin of the LDO. Figure 1When the current flowing through the power control transistor or the load current of the LDO is too large, the voltage difference between Vin and Vout is less than the sum of the overdrive voltage of the sampling transistor MS1 and the threshold voltage of MP6. That is, the voltage difference between Vin and Vout is less than about 1V. MP6, MP7 and the sampling transistor MS1 operate in the non-saturation region, which causes the sampling transistor MS1 to be unable to sample the LDO load current at a certain accurate ratio, and the MOSFET MP7 to be unable to replicate the current of the MOSFET MP6 at a certain ratio. In other words, it is unable to sample the drain current of the power control transistor, thus losing the current limiting function and making the current limiting reliability low, thus failing to reliably protect the LDO. Summary of the Invention

[0005] The purpose of this application is to provide an overcurrent protection control circuit for a low-dropout linear regulator and a low-dropout linear regulator, which can improve the reliability of current limiting.

[0006] To achieve the above objectives, this application provides the following solution: In a first aspect, this application provides an overcurrent protection control circuit for a low-dropout linear regulator, the overcurrent protection control circuit comprising: First flow-limiting loop and second flow-limiting loop; The first current limiting loop includes: a first sampling module, a first current comparator, and a first protection switch; The second current limiting loop includes: a second sampling module, a clamping module, a second current comparator, and a second protection switch; The first sampling module is connected to the drain, gate, and source of the power control transistor in the low-dropout linear regulator, and to a first current comparator. The first current comparator is also connected to the gate of a first protection switch and the input voltage terminal of the low-dropout linear regulator. The source of the first protection switch is connected to the gate of the power control transistor, and the drain of the first protection switch is grounded. The source of the power control transistor is connected to the voltage output terminal of the low-dropout linear regulator, and the drain current of the power control transistor is the load current of the low-dropout linear regulator. The first sampling module is used to sample the load current of the low-dropout linear regulator. The second sampling module is connected to the drain of the power control transistor, the gate of the power control transistor, and the clamping module. The clamping module is also connected to the gate of the second protection switch through a second current comparator. The clamping module is also connected to the source of the power control transistor. The drain of the second protection switch is grounded, and the source of the second protection switch is connected to the gate of the power control transistor. The second sampling module is used to sample the load current of the low dropout linear regulator. The first and second protection switches determine whether to activate based on the comparison results between the load current of the low-dropout linear regulator and the first and second overcurrent protection current values. This allows them to adjust the gate voltage of the power control transistor to change the difference between the input voltage and the output voltage of the low-dropout linear regulator, thereby satisfying the normal operating voltage difference of the corresponding sampling module.

[0007] In one embodiment, the first protection switch and the second protection switch determine whether to activate based on a comparison between the load current of the low-dropout linear regulator and the values ​​of the first and second overcurrent protection currents. This allows them to adjust the gate voltage of the power control transistor to change the difference between the input voltage and the output voltage of the low-dropout linear regulator, thereby satisfying the normal operating voltage difference of the corresponding sampling module. This includes: The second protection switch is used to pull down the gate voltage of the power control transistor when the load current of the low-dropout linear regulator is greater than the first overcurrent protection current value and less than the second overcurrent protection current value, thereby pulling down the output voltage of the low-dropout linear regulator. This ensures that the difference between the input voltage and the output voltage of the low-dropout linear regulator meets the normal operating voltage difference of the second sampling module, so that the second sampling module can normally sample the load current of the low-dropout linear regulator. The first protection switch is used to continue to pull down the gate voltage of the power control transistor when the load current of the low-dropout linear regulator is not less than the second overcurrent protection current value, thereby pulling down the output voltage of the low-dropout linear regulator. This ensures that the difference between the input voltage and the output voltage of the low-dropout linear regulator meets the normal operating voltage difference of the first sampling module and exceeds the normal operating voltage difference of the second sampling module. This prevents the second sampling module from sampling the load current of the low-dropout linear regulator, while the first sampling module normally samples the load current of the low-dropout linear regulator.

[0008] In a second aspect, this application provides a linear regulator, characterized in that it includes a low-dropout linear regulator overcurrent protection control circuit as described in the first aspect.

[0009] According to the specific embodiments provided in this application, the following technical effects are disclosed: This application provides an overcurrent protection control circuit for a low-dropout linear regulator and the low-dropout linear regulator itself. The disclosure features a dual-loop structure with a first current-limiting loop and a second current-limiting loop. The second current-limiting loop specifically addresses the low-dropout sampling problem through the action of a second protection switch. When the load current is in a moderate overcurrent state (greater than the first overcurrent protection current value and less than the second overcurrent protection current value), the second protection switch pulls down the gate voltage of the power control transistor, thereby pulling down the output voltage Vout. This increases the voltage difference between Vin and Vout to the normal operating voltage difference range of the second sampling module, ensuring that the second sampling module can stably sample the load current and achieve protection, avoiding sampling failure under low voltage conditions in the prior art. Furthermore, when the load current reaches a severe overcurrent state (not less than the second overcurrent protection current value), the second protection switch can also prevent overcurrent. When the protection current value is reached, the first protection switch will continue to pull down the gate voltage of the power control transistor, further increasing the voltage difference between Vin and Vout. Although the voltage difference exceeds the normal operating range of the second sampling module, it just meets the working requirements of the first sampling module, ensuring that the first sampling module can take over the work and continuously sample the current to achieve protection. This achieves full coverage from low voltage difference to large voltage difference, and from medium overcurrent to severe overcurrent. This hierarchical protection mechanism not only solves the protection failure problem under specific voltage difference in the existing technology, but also ensures that the LDO can be reliably protected under various abnormal load current conditions through the coordinated work of the dual loops, significantly improving the safety and stability of LDO operation. At the same time, because it can adapt to a wider input and output voltage difference range, it effectively expands the applicable scenarios of LDO. Attached Figure Description

[0010] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0011] Figure 1 This is a schematic diagram of the LDO sampling principle in related technologies; Figure 2 This is an overcurrent protection control block of a low-dropout linear regulator illustrated according to an exemplary embodiment. Figure 1 ; Figure 3 This is a graph illustrating the relationship between LDO output voltage and LDO load current according to an exemplary embodiment; Figure 4 This is an overcurrent protection control circuit for a low-dropout linear regulator, as illustrated in an exemplary embodiment. Figure 5 This is an overcurrent protection control block of a low-dropout linear regulator illustrated according to an exemplary embodiment.Figure 2 . Detailed Implementation

[0012] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0013] To make the above-mentioned objectives, features and advantages of this application more apparent and understandable, the application will be further described in detail below with reference to the accompanying drawings and specific embodiments.

[0014] Figure 2 This is an overcurrent protection control circuit for a low-dropout linear regulator, illustrated in an exemplary embodiment. The overcurrent protection control circuit includes: First flow-limiting loop and second flow-limiting loop; The first current limiting loop includes: a first sampling module, a first current comparator, and a first protection switch; The second current limiting loop includes: a second sampling module, a clamping module, a second current comparator, and a second protection switch; The first sampling module is connected to the drain, gate, and source of the power control transistor in the LDO, and to a first current comparator. The first current comparator is also connected to the gate of a first protection switch and the input voltage terminal of the LDO. The source of the first protection switch is connected to the gate of the power control transistor, and the drain of the first protection switch is grounded. The source of the power control transistor is connected to the voltage output terminal of the LDO, and the drain current of the power control transistor is the load current of the LDO. The first sampling module is used to sample the load current of the LDO. The second sampling module is connected to the drain of the power control transistor, the gate of the power control transistor, and the clamping module. The clamping module is also connected to the gate of the second protection switch through a second current comparator. The clamping module is also connected to the source of the power control transistor. The drain of the second protection switch is grounded, and the source of the second protection switch is connected to the gate of the power control transistor. The second sampling module is used to sample the load current of the LDO. The first and second protection switches determine whether to activate based on the comparison results between the load current of the low-dropout linear regulator and the first and second overcurrent protection current values. This allows them to adjust the gate voltage of the power control transistor to change the difference between the input voltage and the output voltage of the low-dropout linear regulator, thereby satisfying the normal operating voltage difference of the corresponding sampling module.

[0015] Specifically, the second protection switch is used to pull down the gate voltage of the power control transistor when the load current of the LDO is greater than the first overcurrent protection current value and less than the second overcurrent protection current value, thereby pulling down the output voltage of the LDO, so that the difference between the input voltage and the output voltage of the LDO meets the normal operating voltage difference of the second sampling module, so that the second sampling module can sample the load current of the LDO normally. The first protection switch is used to continue to pull down the gate voltage of the power control transistor when the load current of the LDO is not less than the second overcurrent protection current value, thereby pulling down the output voltage of the LDO, so that the difference between the input voltage and the output voltage of the LDO meets the normal operating voltage difference of the first sampling module and exceeds the normal operating voltage difference of the second sampling module, so that the second sampling module cannot sample the load current of the LDO, while the first sampling module samples the load current of the LDO normally.

[0016] This disclosure proposes segmented control with two current-limiting loops, namely a first current-limiting loop and a second current-limiting loop. The LDO output voltage and LDO load current are as follows: Figure 3 As shown: Assume that when the LDO's load current Iload is less than the first overcurrent protection current value I... LIMIT1 When the voltage difference between the LDO's input voltage Vin and its output voltage Vout is small, or when the LDO is operating in the linear region, the LDO can stably output Vout.

[0017] When Iload continues to increase in I LIMIT1 Up to the second overcurrent protection current value I LIMIT0 During this interval, the second protection switch in the second current limiting loop is turned on, the second current limiting loop is working, the gate of the power control transistor POWER MOS in the LDO is pulled down by the second protection switch, Vout decreases, the voltage difference between Vin and Vout increases, the increased voltage difference meets the normal operating voltage difference of the second sampling module, the second sampling module can sample Iload normally, that is, the voltage difference between Vin and Vout meets the voltage requirements of the second sampling module operating in the saturation region.

[0018] When Iload continues to increase to I LIMIT0 When the first protection switch in the first current limiting loop opens, the first current limiting loop operates, and the gate voltage of the power control transistor POWER MOS in the LDO is pulled down by the first protection switch. At this time, the voltage difference between Vin and Vout meets the normal operating voltage difference of the first sampling module and exceeds the normal operating voltage difference of the second sampling module. Therefore, as Iload continues to increase to I... LIMIT0Subsequently, the second sampling module is unable to continue sampling the load current of the LDO, and the first sampling module takes over from the second sampling module to sample the load current of the LDO normally. That is, the voltage difference between Vin and Vout meets the voltage requirement for the first sampling module to operate in the saturation region.

[0019] The core flaw in existing technology lies in the fact that when the voltage difference between the LDO's input voltage Vin and output voltage Vout is too small (e.g., less than 1V), the sampling transistor and related MOSFETs will operate in the non-saturation region, failing to sample the load current proportionally, thus causing the current limiting protection function to fail. To address this, this disclosure designs a dual-loop structure with a first current limiting loop and a second current limiting loop. The second current limiting loop specifically addresses the low-voltage-difference sampling problem through the action of a second protection switch. When the load current is in a moderate overcurrent state (greater than the first overcurrent protection current value but less than the second overcurrent protection current value), the second protection switch will pull down the gate voltage of the power control transistor, thereby pulling down the output voltage Vout. This increases the voltage difference between Vin and Vout to the normal operating voltage difference range of the second sampling module, ensuring that the second sampling module can stably sample the load current and achieve protection, avoiding the sampling failure under low voltage difference conditions found in existing technology. Furthermore, when the load current reaches a severe overcurrent state (not less than the second overcurrent protection current value), the first protection switch will continue to pull down the gate voltage of the power control transistor. The gate voltage of the transistor further increases the voltage difference between Vin and Vout. Although the voltage difference exceeds the normal operating range of the second sampling module, it just meets the working requirements of the first sampling module, ensuring that the first sampling module can take over the work and continuously sample the current to achieve protection. This achieves full coverage from low voltage difference to large voltage difference, and from medium overcurrent to severe overcurrent. This hierarchical protection mechanism not only solves the protection failure problem under specific voltage difference in the existing technology, but also ensures that the LDO can be reliably protected under various abnormal load current conditions through the coordinated work of the dual loops. This significantly improves the safety and stability of LDO operation. At the same time, because it can adapt to a wider input and output voltage difference range, it effectively expands the applicable scenarios of LDO and enhances its practical application value.

[0020] In the following embodiments, the first protection switch MP3, the second protection switch MP0, the second MOSFET MP1, and the third MOSFET MP2 are all P-type MOSFETs. The first sampling transistor MS1, the second sampling module MS2, the first MOSFET MN1, the fourth MOSFET MN2, the fifth MOSFET MN3, the sixth MOSFET MN0, the seventh MOSFET MN3, and the eighth MOSFET MN4 are all N-type MOSFETs.

[0021] In one embodiment, such as Figure 4As shown, the first protection switch is MP3, the second sampling module is MS2 (whose main function is to sample the load current of the LDO), and the second protection switch is MP0. The clamping module includes a clamping operational amplifier and a first MOSFET MN1. The first terminal of the clamping operational amplifier is connected to the source of the power control transistor POWER MOS in the LDO, the second terminal of the clamping operational amplifier is connected to the source of the second sampling module MS2 and the drain of the first MOS transistor MN1, the third terminal of the clamping operational amplifier is connected to the gate of the first MOS transistor MN1, and the fourth and fifth terminals of the clamping operational amplifier are both grounded. The source of the first MOSFET MN1 is grounded, the gate of the first MOSFET MN1 is connected to the first terminal of the second current comparator, the second terminal of the second current comparator is connected to the input voltage terminal Vin of the LDO, the third terminal of the second current comparator is connected to the gate of the second protection switch MP0, and the fourth terminal of the second current comparator is grounded. The source of the second protection switch MP0 is connected to the gate of the power control transistor POWER MOS, and the drain of the second protection switch MP0 is grounded.

[0022] The clamping op-amp and MN1 form a negative feedback loop. Therefore, the function of the clamping op-amp is to form a negative feedback loop with MN1 so that the voltage Vs (the voltage at the source of MN1) equals Vout. The clamping op-amp is an important component of the second current limiting loop.

[0023] In one embodiment, the clamping operational amplifier includes: a second MOSFET MP1, a third MOSFET MP2, a fourth MOSFET MN2, and a fifth MOSFET MN3; The source of the second MOSFET MP1 is connected to the source of the power control transistor. The gate of the second MOSFET MP1 is connected to the gate of the third MOSFET MP2. The gate of the third MOSFET MP2 is connected to the drain of the second MOSFET MP1. The source of the third MOSFET MP2 is connected to the source of the second sampling transistor MS2 and the drain of the first MOSFET MN1. The drain of the third MOSFET MP2 is connected to the drain of the fifth MOSFET MN3. The drain of the second MOSFET MP1 is connected to the drain of the fourth MOSFET MN2. The sources of the fourth MOSFET MN2 and the fifth MOSFET MN3 are grounded. The gate of the first MOSFET MN1 is connected between the drain of the third MOSFET MP2 and the drain of the fifth MOSFET MN3.

[0024] like Figure 4As shown, MOS transistors MP1, MP2, MN2, MN3 and bias voltage Vb form a clamping operational amplifier. The source of PMOS transistor MP1 is connected to the source of the power control transistor (i.e., the LDO output voltage Vout), and its gate is connected to the gate of PMOS transistor MP2, forming a "common gate" structure. The drain of MP1 is connected to its own gate, the gate of MP2 and the drain of NMOS transistor MN2, forming the drain-gate feedback path of MP1.

[0025] The source of PMOS transistor MP2 is connected to the source of the second sampling transistor MS2 and the drain of NMOS transistor MN1. Its drain is connected to the drain of NMOS transistor MN3, and this connection point is also connected to the gate of MN1, forming a control path from the drain of MP2 to MN1.

[0026] The sources of NMOS transistors MN2 and MN3 are both grounded, and the gates of NMOS transistors MN2 and MN3 are connected to the bias voltage Vb to ensure that equal bias current is provided.

[0027] The core of this adjustment is to make the source potential and drain potential of MS2 equal, thereby ensuring that MS2 can stably sample the load current of LDO according to a preset ratio, providing a reliable basis for overcurrent judgment of the second current limiting loop.

[0028] In one embodiment, such as Figure 3 As shown, the second current comparator includes: a second current source and a sixth MOS transistor MN0; One end of the second current source is connected to the input voltage terminal Vin of the LDO, and the other end of the second current source is connected to the drain of the sixth MOS transistor MN0. The source of the sixth MOS transistor MN0 is grounded, and the gate of the sixth MOS transistor MN0 is connected to the gate of the first MOS transistor MN1. The gate of the second protection switch MP0 is connected between the second current source and the drain of the sixth MOS transistor MN0.

[0029] The main function of the second current comparator is to compare the reference current Ib2 output by the second current source with the current K2 times that of MN1. Here, K2 is a multiple of the width-to-length ratio of MN1 and the width-to-length ratio of MN0, and the width-to-length ratio of MN1 is K2 times the width-to-length ratio of MN0.

[0030] If the reference current Ib2 is greater than MN1 current K2 times, the voltage Vd is pulled to VIN, the second protection switch MP0 is not turned on, and the second protection switch MP0 does not pull down the gate voltage of the power transistor; if the reference current Ib2 is less than MN1 current K2 times, the voltage Vd is pulled low, the second protection switch MP0 is turned on, and the second protection switch MP0 pulls down the gate voltage of the power transistor, so that the voltage difference between Vin and Vout meets the operating requirements of MS2, and MS2 can accurately collect the load current of LDO.

[0031] In one embodiment, such as Figure 3 As shown, the first sampling module includes: a first sampling transistor MS1 (whose main function is to sample the load current of the LDO), a current mirror, and a seventh MOS transistor MN3; The first and second input terminals of the current mirror are both connected to the input voltage terminal of the LDO. The third input terminal of the current mirror is connected to the drain of the first sampling transistor MS1. The output terminal of the current mirror is connected to the drain of the seventh MOSFET MN3. The drain of the seventh MOSFET MN3 is connected to the gate of the seventh MOSFET MN3, and the source of the seventh MOSFET MN3 is grounded. The first terminal of the first current comparator is connected to the input voltage terminal Vin of the LDO. The second terminal of the first current comparator is connected to the gate of the seventh MOSFET MN3. The third terminal of the first current comparator is connected to the gate of the first protection switch MP3, and the fourth terminal of the first current comparator is grounded. The source of the first protection switch MP3 is connected to the gate of the first sampling transistor MS1.

[0032] The first current comparator includes: a first current source and an eighth MOSFET MN4; one end of the first current source is connected to the input voltage terminal Vin of the LDO, the other end of the first current source is connected to the drain of the eighth MOSFET MN4, the gate of the eighth MOSFET MN4 is connected to the gate of the seventh MOSFET MN3, the gate of the first protection switch MP3 is connected between the other end of the first current source and the drain of the eighth MOSFET MN4, and the source of the eighth MOSFET MN4 is grounded.

[0033] The primary function of the first current comparator is to compare the reference current Ib1 provided by the first current source with the drain-to-source current K1 times that of MN3. Here, K1 is a multiple of the aspect ratios of MN3 and MN4, where the aspect ratio of MN3 is K1 times that of MN4. If the reference current Ib1 is greater than K1 times the current of MN3, the voltage of Vc will be pulled down to Vin, the first protection switch MP3 will not open, and the first current-limiting loop will not function. If the reference current Ib1 is less than K1 times the drain-to-source current of MN3, MN4 will operate in the saturation region, the voltage of Vc will be pulled down, the first protection switch MP3 will open, and the opened first protection switch MP3 will pull down the gate voltage of the power control transistor.

[0034] The existing overcurrent protection circuit only has a first current limiting loop. Without a second current limiting loop, when there is only the first current limiting loop, the voltage difference between VIN and Vout is relatively low or the LDO is working in the linear region, which is insufficient to make the MOS transistor in the current mirror work normally. As a result, the voltage Vc is always pulled up to VIN, and MP3 cannot pull down the gate of the power control transistor, thus failing to achieve the current limiting function.

[0035] This disclosure uses a clamping operational amplifier composed of MOS transistors MP1, MP2, MN2, MN3 and bias voltage Vb, and MN1 to form a negative feedback loop clamp. Its core function is to make the clamping voltage Vs and the output voltage Vout of the LDO approximately equal. In other words, this structure ensures that the source potential of the POWER MOS and the source potential of the second sampling transistor MS2 in the second current limiting loop are approximately equal.

[0036] from Figure 4 It can be seen that the gate potential of POWER MOS is equal to the gate potential of the first sampling transistor MS1 and the second sampling transistor MS2, the source potential of POWER MOS is equal to the source potential of the first sampling transistor MS1, and both are connected to Vout, and the drain potential of POWER MOS is equal to the drain potential of the second sampling transistor MS2, and both are connected to VIN.

[0037] The aspect ratio of the POWER MOS is Ks times that of the first sampling transistor Ms1, and the aspect ratio of the POWER MOS is Ks times that of the second sampling transistor Ms2. This means that the sampling ratio of both the first sampling transistor Ms1 and the second sampling transistor Ms2 is 1:Ks, where Ks is less than 1. I Ms1 =I POWER MOS / Ks,I Ms2 =I POWER MOS / Ks.

[0038] When the LDO's load current Iload is less than I LIMIT1 At this time, neither the first nor the second current-limiting loop will operate (equivalent to the second protection switch MP0 and the first protection switch MP3 not pulling down the gate of the power control transistor), and the LDO outputs stably as shown. Figure 3 Vcc0 is shown.

[0039] When the LDO output is shorted to ground or other factors cause Iload to increase, Iload reaches the following level: Figure 3 The I shown LIMIT1 to I LIMIT0 During this interval, the second current-limiting loop operates because voltages Vs and Vout are approximately equal, the drain potential of the POWER MOS is equal to the drain potential of MS2, and the gate potential of the POWER MOS is equal to the gate potential of MS2. Since the current flowing through MN1 is much greater than the branch current flowing through MP2 and MN3, the current flowing through MN1 and the sampling current I can be approximated as equal. s1The potentials of the gate and source of MN0 and MN1 are basically equal. Therefore, the current flowing through MN0 is K2 times the load current Iload of the LDO, while the current flowing through MN1 is basically equal to the sampling current Is1. Therefore, when the K2 times current flowing through MN1 is greater than the reference current Ib2, Vd begins to gradually decrease. The second protection switch MP0 pulls down the gate of the POWER MOS, and the Vs voltage decreases and becomes equal to Vout. The current flowing through MN1 increases, and the voltage Va increases. The formula for the current flowing through MN1 is: ; In the above formula, For electron mobility, Here, W is the unit gate oxide capacitance, W / L is the width-to-length ratio of MOSFET MN1, and Vth is the threshold voltage of MOSFET MN1. Indicates the gate potential of MN1 or MN0. This represents the drain potential of MN1.

[0040] However, as the LDO load current Iload increases further, the voltage of Vout decreases further, and the voltage of Vs decreases as well. Since the VGS voltage of MN1 is approximately 1V~1.5V when the MOSFET is operating, the voltages of Vout and Vs drop to approximately 1V~1.5V, limiting the amplitude of the voltage increase of Va. The voltage of va increases to approximately 1V~1.5V and will not increase further. Therefore, the pull-down capability of MP0 is limited, requiring further pull-down from the first current limiting loop. Vin typically operates at a minimum voltage of around 3V. At this point, the voltage difference between Vin and the LDO output Vout is approximately Vin - (1V~1.5V) = 3V - 1V~3V - 1.5V = 2V~1.5V. That is, there should be at least a voltage difference of approximately 1.5V between VIN and Vout. This voltage difference can ensure... Figure 4 The medium current mirror MOSFET is operating normally in the saturation region.

[0041] The gate potential of the POWER MOS is equal to the gate potential of the second sampling transistor MS2, and the source potential of the POWER MOS is equal to the source potential of the first sampling transistor MS1. When the load current Iload of the LDO reaches the threshold current I of the first current limiting loop... LIMIT0 When current flows, because Iload passes through I LIMIT1 to I LIMIT0 Within this range, the pressure difference between VIN and Vout is sufficient to ensure... Figure 4The MOS transistor of the medium current mirror and the first sampling transistor MS1 are operating in the saturation region. At this time, the current flowing through MN4 is Ks*K0*K1 times Iload, and Ks*K0*K1 is less than 1. At the same time, the K1 times current flowing through MN3 is greater than the reference current Ib1, the Vc voltage drops, and the gate of the POWER MOS, Vout, is pulled to ground under the first protection switch MP3. Since the first current limiting loop is a negative feedback loop, the gate voltage of the POWER MOS is stabilized at a relatively constant value. Therefore, the current of the POWER MOS in the LDO is constant.

[0042] Due to the effect of the first current limiting loop, the voltage of Vout continues to decrease, the swing of voltage Va is limited or eventually drops to about 0, so MN0 is in the cutoff region, the voltage of Vd is pulled up, MP0 no longer pulls down the gate of the power transistor, the second current limiting loop loses its function, and only the first current limiting loop works.

[0043] In summary, as Figure 5 As shown, when the load current is less than I LIMIT1 At the beginning, due to the presence of the error amplifier and resistor feedback network, the LDO output voltage is stably outputting Vcc0. When the load current reaches ILIMT1, the second current limiting loop starts to operate, and Vout begins to decrease. When the load current reaches IlIMIT0, the first current limiting loop operates, Vout is pulled to ground, and the current of the LDO's power control transistor reaches a constant value. When the LDO's load current becomes less than I... LIMIT1 At that time, the LDO quickly stabilized and output Vcc0.

[0044] This disclosure presents a constant overcurrent protection control method for LDOs. In related technologies, the voltage difference between Vin and Vout is less than about 1V, making it impossible for the sampling circuit to properly sample the LDO's load current. The solution presented here can be applied to LDOs with a wide input range, solving the problems of insufficient current sampling when the voltage difference between Vin and the LDO's output voltage is small, when the LDO is operating in the linear region, and the need for an additional voltage range higher than Vin in the overcurrent circuit. This improves the accuracy and reliability of current limiting and reduces costs.

[0045] In one embodiment, this disclosure also provides a linear regulator, including a low-dropout linear regulator overcurrent protection control circuit as described in any of the foregoing embodiments.

[0046] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0047] This document uses specific examples to illustrate the principles and implementation methods of this application. The descriptions of the above embodiments are only for the purpose of helping to understand the methods and core ideas of this application. Furthermore, those skilled in the art will recognize that, based on the ideas of this application, there will be changes in the specific implementation methods and application scope. Therefore, the content of this specification should not be construed as a limitation of this application.

Claims

1. An overcurrent protection control circuit for a low-dropout linear regulator, characterized in that, The overcurrent protection control circuit includes: First flow-limiting loop and second flow-limiting loop; The first current limiting loop includes: a first sampling module, a first current comparator, and a first protection switch; The second current limiting loop includes: a second sampling module, a clamping module, a second current comparator, and a second protection switch; The first sampling module is connected to the drain, gate, and source of the power control transistor in the low-dropout linear regulator, and to a first current comparator. The first current comparator is also connected to the gate of a first protection switch and the input voltage terminal of the low-dropout linear regulator. The source of the first protection switch is connected to the gate of the power control transistor, and the drain of the first protection switch is grounded. The source of the power control transistor is connected to the voltage output terminal of the low-dropout linear regulator, and the drain current of the power control transistor is the load current of the low-dropout linear regulator. The first sampling module is used to sample the load current of the low-dropout linear regulator. The second sampling module is connected to the drain of the power control transistor, the gate of the power control transistor, and the clamping module. The clamping module is also connected to the gate of the second protection switch through a second current comparator. The clamping module is also connected to the source of the power control transistor. The drain of the second protection switch is grounded, and the source of the second protection switch is connected to the gate of the power control transistor. The second sampling module is used to sample the load current of the low dropout linear regulator. The first and second protection switches determine whether to activate based on the comparison results between the load current of the low-dropout linear regulator and the first and second overcurrent protection current values. This allows them to adjust the gate voltage of the power control transistor to change the difference between the input voltage and the output voltage of the low-dropout linear regulator, thereby satisfying the normal operating voltage difference of the corresponding sampling module.

2. The overcurrent protection control circuit according to claim 1, characterized in that, The first and second protection switches determine whether to activate based on a comparison between the load current of the low-dropout linear regulator and the values ​​of the first and second overcurrent protection currents. This allows them to adjust the gate voltage of the power control transistor to change the difference between the input and output voltages of the low-dropout linear regulator, thus satisfying the normal operating voltage difference of the corresponding sampling module. This includes: The second protection switch is used to pull down the gate voltage of the power control transistor when the load current of the low-dropout linear regulator is greater than the first overcurrent protection current value and less than the second overcurrent protection current value, thereby pulling down the output voltage of the low-dropout linear regulator. This ensures that the difference between the input voltage and the output voltage of the low-dropout linear regulator meets the normal operating voltage difference of the second sampling module, so that the second sampling module can normally sample the load current of the low-dropout linear regulator. The first protection switch is used to continue to pull down the gate voltage of the power control transistor when the load current of the low-dropout linear regulator is not less than the second overcurrent protection current value, thereby pulling down the output voltage of the low-dropout linear regulator. This ensures that the difference between the input voltage and the output voltage of the low-dropout linear regulator meets the normal operating voltage difference of the first sampling module and exceeds the normal operating voltage difference of the second sampling module. This prevents the second sampling module from sampling the load current of the low-dropout linear regulator, while the first sampling module normally samples the load current of the low-dropout linear regulator.

3. The overcurrent protection control circuit according to claim 2, characterized in that, The clamping module includes: a clamping operational amplifier and a first MOSFET; The first terminal of the clamping operational amplifier is connected to the source of the power control transistor in the low dropout linear regulator, the second terminal of the clamping operational amplifier is connected to the source of the second sampling module and the drain of the first MOS transistor, the third terminal of the clamping operational amplifier is connected to the gate of the first MOS transistor, and the fourth and fifth terminals of the clamping operational amplifier are both grounded. The source of the first MOSFET is grounded, the gate of the first MOSFET is connected to the first terminal of the second current comparator, the second terminal of the second current comparator is connected to the input voltage terminal of the low dropout linear regulator, the third terminal of the second current comparator is connected to the gate of the second protection switch, and the fourth terminal of the second current comparator is grounded. The source of the second protection switch is connected to the gate of the power control transistor, and the drain of the second protection switch is grounded.

4. The overcurrent protection control circuit according to claim 3, characterized in that, The clamping operational amplifier includes: a second MOS transistor, a third MOS transistor, a fourth MOS transistor, and a fifth MOS transistor; The source of the second MOSFET is connected to the source of the power control transistor, the gate of the second MOSFET is connected to the gate of the third MOSFET, the gate of the third MOSFET is connected to the drain of the second MOSFET, the source of the third MOSFET is connected to the source of the second sampling transistor and the drain of the first MOSFET, the drain of the third MOSFET is connected to the drain of the fifth MOSFET, the drain of the second MOSFET is connected to the drain of the fourth MOSFET, the source of the fourth MOSFET and the source of the fifth MOSFET are grounded, and the gate of the first MOSFET is connected between the drain of the third MOSFET and the drain of the fifth MOSFET.

5. The overcurrent protection control circuit according to claim 4, characterized in that, The second current comparator includes: a second current source and a sixth MOSFET; One end of the second current source is connected to the input voltage terminal of the low dropout linear regulator, and the other end of the second current source is connected to the drain of the sixth MOSFET. The source of the sixth MOSFET is grounded, and the gate of the sixth MOSFET is connected to the gate of the first MOSFET. The gate of the second protection switch is connected between the second current source and the drain of the sixth MOSFET.

6. The overcurrent protection control circuit according to claim 5, characterized in that, The first sampling module includes: a first sampling transistor, a current mirror, and a seventh MOS transistor; The first and second input terminals of the current mirror are both connected to the input voltage terminals of the low dropout linear regulator, the third input terminal of the current mirror is connected to the drain of the first sampling transistor, and the output terminal of the current mirror is connected to the drain of the seventh MOS transistor. The drain of the seventh MOS transistor is connected to the gate of the seventh MOS transistor, and the source of the seventh MOS transistor is grounded. The first terminal of the first current comparator is connected to the input voltage terminal of the low dropout linear regulator, the second terminal of the first current comparator is connected to the gate of the seventh MOSFET, the third terminal of the first current comparator is connected to the gate of the first protection switch, and the fourth terminal of the first current comparator is grounded. The source of the first protection switch is connected to the gate of the first sampling tube.

7. The overcurrent protection control circuit according to claim 6, characterized in that, The first current comparator includes: a first current source and an eighth MOSFET; One end of the first current source is connected to the input voltage terminal of the low dropout linear regulator, and the other end of the first current source is connected to the drain of the eighth MOS transistor. The gate of the eighth MOS transistor is connected to the gate of the seventh MOS transistor. The gate of the first protection switch is connected between the other end of the first current source and the drain of the eighth MOS transistor. The source of the eighth MOS transistor is grounded.

8. The overcurrent protection control circuit according to claim 7, characterized in that, The first protection switch, the second protection switch, the second MOSFET, and the third MOSFET are all P-type MOSFETs; The first sampling transistor, the second sampling module, the first MOSFET, the fourth MOSFET, the fifth MOSFET, the sixth MOSFET, the seventh MOSFET, and the eighth MOSFET are all N-type MOSFETs.

9. The overcurrent protection control circuit according to claim 8, characterized in that, The current sampling ratios of the first sampling transistor, the second sampling transistor, the current sampling ratio of the current mirror, the sixth MOS transistor, and the eighth MOS transistor are all less than 1.

10. A linear voltage regulator, characterized in that, Includes the low-dropout linear regulator overcurrent protection control circuit as described in any one of claims 1-9.

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