Methods and systems for accelerating central processing unit (CPU) operation in digital simulation

Abstract

This invention provides a method and system for accelerating the execution of a central processing unit (CPU) in digital simulation. The method is applied to a host machine with a homogeneous CPU architecture as the target machine, aiming to solve the problem of low simulation performance under homogeneous architecture. The method includes: creating virtual machine instances and virtual processors using the host machine's hardware-assisted virtualization capabilities; establishing a memory mapping relationship between the target machine and the host machine; using system calls to the virtual processor to allow the target machine's CPU instructions to be executed directly by the host machine's physical CPU without translation; capturing I / O operation instructions during execution and having them parsed by the user-space virtual machine instance to call the corresponding virtual peripheral models to perform the simulation operation. This invention fundamentally eliminates the translation overhead of CPU instructions through instruction pass-through, significantly improving the performance of digital simulation to near-real hardware levels.

Description

Technical Field

[0001] This invention relates to the field of computer virtualization technology, and more specifically, to a method and system for accelerating the operation of a central processing unit (CPU) in digital simulation. Background Technology

[0002] In the research and development of high-end equipment such as aviation and aerospace equipment, hardware virtualization simulation is a key technology for software development, debugging, and system verification. Traditional hardware virtualization simulation, especially when the host and target machines have different central processing unit (CPU) instruction set architectures (i.e., heterogeneous architectures), must adopt a fully virtualized instruction translation approach. This approach requires translating every instruction of the target machine into instructions that the host machine can recognize and execute. This translation process itself consumes a large amount of computing resources, resulting in low simulation efficiency.

[0003] With the promotion of domestically produced hardware platforms, more and more scenarios have emerged where the host and target machines use the same instruction set architecture, i.e., homogeneous architecture. However, even under homogeneous architecture, many existing virtualization simulation solutions still have performance bottlenecks. Some solutions still use or have not completely escaped the mode of instruction translation or complex simulation, resulting in their simulation speed being far from meeting the requirements of large-scale, high-efficiency co-simulation. Other optimization solutions focus on the input / output (I / O) path, such as allowing virtual machines to directly call some native resources of the host to accelerate peripheral interaction through specific mechanisms, but this approach does not fundamentally solve the core problem of low execution efficiency of general-purpose CPU instructions. For example, on the ARMv8 homogeneous platform, the running efficiency of emulators using instruction translation may only be 30% of the actual hardware performance, which cannot meet the stringent speed requirements of large-scale co-simulation.

[0004] A patent search revealed invention patent CN112256331A, which discloses a method, apparatus, and computer storage medium for accelerating virtual machine instruction parsing. The method includes the following steps: adding acceleration hardware to the host machine and connecting it to the host machine's processor via a dedicated bus; mapping the address of the cache area storing the instructions to be parsed in the virtual machine running on the host machine to the physical address of the acceleration hardware; when the virtual machine writes data, the host machine's processor initiates a write address on the dedicated bus, and the virtual machine's current instruction to be parsed is converted into an executable instruction on the host machine in the acceleration hardware; when the host machine reads data, the host machine's processor initiates a read address on the dedicated bus, and the executable instruction on the host machine is read from the acceleration hardware. This patent only optimizes instruction parsing, requires additional acceleration hardware, and does not address key simulation bottlenecks such as I / O; it lacks multi-node collaboration and flexible deployment capabilities, limiting its application scenarios.

[0005] In summary, given the problems of the existing technologies, researching a method and system for accelerating the operation of a central processing unit (CPU) for digital simulation has become a critical task that urgently needs to be addressed. Summary of the Invention

[0006] In view of the deficiencies in the prior art, the purpose of this invention is to provide a method and system for accelerating the operation of a central processing unit for digital simulation.

[0007] A method for accelerating the operation of a central processing unit (CPU) in digital simulation, provided by the present invention, is applied to a host machine having a CPU architecture homogeneous with the target machine, and includes the following steps:

[0008] Step S1: Using the host machine's hardware-assisted virtualization function, create a virtual machine instance and a virtual processor, initialize the virtual processor, and set the virtual processor's program counter to the entry address of the target machine program.

[0009] Step S2: Allocate host physical memory to the virtual machine instance and establish a mapping relationship between the target machine physical address space and the host machine physical memory. The target machine physical address space includes the address range of memory-mapped inputs / outputs.

[0010] Step S3: The instructions of the target machine program are passed through and loaded into the host machine's physical CPU through a system call to the virtual processor, and the host machine's physical CPU directly executes the instructions of the target machine program.

[0011] Step S4: When the virtual processor executes an instruction that accesses the memory-mapped input / output address range, the virtual processor captures the access operation and triggers the virtual processor to exit. It then passes the generated I / O request information to the user-mode virtual machine instance. The virtual machine instance parses the I / O request information and calls the corresponding virtual peripheral model to perform simulation operations to generate simulation running data. After the simulation operation is completed, the virtual machine instance schedules the virtual processor again through a system call, so that the virtual processor resumes execution from the instruction address pointed to by the context information saved when the virtual processor exited.

[0012] Preferably, in step S1, the hardware-assisted virtualization function is the kernel-based virtual machine (KVM) function, and the initialization of the virtual processor is completed by calling the host kernel's KVM function library interface.

[0013] Preferably, in step S2, the address range of the memory-mapped input / output is mapped to the corresponding processing logic in the virtual machine instance.

[0014] Preferably, in step S3, the virtual processor has a built-in target program identification instruction mapping table. By looking up the table, the virtual processor identifies the instruction operations and I / O operations in the target machine program. The instruction operations are directly loaded into the virtual processor and executed by the host machine hardware. The I / O operations are switched to the virtual machine instance to complete the ioctl call.

[0015] Preferably, in step S4, the I / O operating system call is an ioctl system call, and a hash page table is used to manage the address mapping of the virtual peripheral model. The virtual machine instance looks up the corresponding virtual peripheral model in the hash page table according to the target address in the I / O request information.

[0016] Preferably, in step S4, the hash page table construction process includes the following steps:

[0017] Step a1: Define a hash function that takes the target machine's physical address as input;

[0018] Step a2: Traverse all virtual peripheral models, obtain the address range of each virtual peripheral model, calculate the base address of the address range using a hash function to obtain the corresponding hash index, and store a pointer to the I / O processing function of the virtual peripheral model at the hash index position.

[0019] Preferably, before step S1, the method further includes step S0:

[0020] Step S0 generates a graphical hardware environment modeling interface to receive user input on the target chip type, peripheral modules, and target machine program loading configuration. The target chip type is used to create the corresponding virtual processor, and the peripheral modules are used to instantiate the corresponding virtual peripheral models.

[0021] Preferably, the method further includes step S5:

[0022] Step S5: The simulation running data is interacted with external simulation nodes through the data distribution service interface, and / or, service-oriented calls or containerized deployment is supported through the integration call interface.

[0023] Preferably, in step S5, the interaction with external simulation nodes through the data distribution service interface includes the following steps:

[0024] Step b1: Integrate the data distribution service client library into the virtual machine instance and predefine the data model and communication topics;

[0025] Step b2 involves starting independent virtual machine instances for the multiple target machine programs that require co-simulation. Each virtual machine instance is configured with the required published and subscribed communication topics based on the functions of the target machine programs running inside it. All virtual machine instances interact with each other in real time through the data distribution service data bus.

[0026] The present invention also provides a central processing unit (CPU) acceleration system for digital simulation, employing the above-described CPU acceleration method for digital simulation, comprising:

[0027] Module M1 utilizes the host machine's hardware-assisted virtualization capabilities to create virtual machine instances and virtual processors, initializes the virtual processors, and sets the virtual processor's program counter to the entry address of the target machine's program.

[0028] Module M2 allocates host physical memory for virtual machine instances and establishes a mapping relationship between the target machine physical address space and the host machine physical memory. The target machine physical address space includes the address range of memory-mapped inputs / outputs.

[0029] Module M3 uses system calls to pass through the virtual processor to load the instructions of the target machine program into the host machine's physical CPU, so that the host machine's physical CPU can directly execute the instructions of the target machine program.

[0030] Module M4: When the virtual processor executes an instruction that accesses a memory-mapped input / output address range, the virtual processor captures the access operation and triggers its exit. It then passes the generated I / O request information to the user-mode virtual machine instance. The virtual machine instance parses the I / O request information and calls the corresponding virtual peripheral model to perform simulation operations to generate simulation running data. After the simulation operation is completed, the virtual machine instance again schedules the virtual processor through a system call, allowing the virtual processor to resume execution from the instruction address pointed to by the context information saved when the virtual processor exited.

[0031] Compared with the prior art, the present invention has the following beneficial effects:

[0032] 1. This invention achieves "instruction pass-through" on a homogeneous CPU architecture, enabling the target machine's general-purpose computing instructions to be executed directly on the host machine's physical CPU, fundamentally avoiding the significant performance overhead of instruction translation in traditional virtualization. Real-world testing shows that this method can improve the CPU performance of digital simulation to over 80% of the real target hardware level.

[0033] 2. This invention enables the direct execution of programs developed for homogeneous low-frequency chips on high-frequency chips through precise virtual modeling of peripherals and efficient CPU simulation. This makes the software development and verification process no longer heavily dependent on specific and scarce physical hardware boards, thus accelerating the research and development process.

[0034] 3. This invention provides standardized service-oriented calls and containerized deployment interfaces, which can be seamlessly integrated into modern development and operation systems such as cloud platforms and software factories, providing an efficient and scalable simulation verification platform for automated testing and continuous integration. Attached Figure Description

[0035] Other features, objects, and advantages of the present invention will become more apparent from the following detailed description of non-limiting embodiments with reference to the accompanying drawings:

[0036] Figure 1 This is a flowchart of a method for accelerating the operation of a central processing unit in digital simulation, as described in an embodiment of the present invention.

[0037] Figure 2 This is a structural diagram of a central processing unit (CPU) acceleration system for digital simulation according to an embodiment of the present invention.

[0038] Figure 3 This is a diagram comparing the principles of two virtual schemes in this invention. Detailed Implementation

[0039] The present invention will now be described in detail with reference to specific embodiments. These embodiments will help those skilled in the art to further understand the present invention, but do not limit the invention in any way. It should be noted that those skilled in the art can make several changes and improvements without departing from the concept of the present invention. These all fall within the scope of protection of the present invention.

[0040] This invention provides a method and system for accelerating the execution of a central processing unit (CPU) in digital simulation. The method is applied to a host machine with a homogeneous CPU architecture as the target machine, aiming to solve the problem of low simulation performance under homogeneous architecture. The method includes: creating virtual machine instances and virtual processors using the host machine's hardware-assisted virtualization capabilities; establishing a memory mapping relationship between the target machine and the host machine; using system calls to the virtual processor to allow the target machine's CPU instructions to be executed directly by the host machine's physical CPU without translation; capturing I / O operation instructions during execution and having them parsed by the user-space virtual machine instance to call the corresponding virtual peripheral models to perform the simulation operation. This invention fundamentally eliminates the translation overhead of CPU instructions through instruction pass-through, significantly improving the performance of digital simulation to near-real hardware levels.

[0041] Figure 3 This is a diagram comparing the principles of two virtualization schemes in this embodiment of the invention.

[0042] like Figure 3 As shown in the left half, when an x86 architecture host machine is used to virtualize an ARM architecture target machine, a heterogeneous virtualization scheme is formed. Since the instruction sets of the two are different, the ARM instructions must be translated into x86 instructions through an "instruction translation" module before they can be executed. This process introduces significant performance overhead, resulting in low simulation efficiency.

[0043] Figure 3As shown in the right half, the homogeneous virtualization adopted in this invention uses an ARM host machine to virtualize an ARM target machine. Thanks to the same instruction set, its core "instruction execution" unit can send the target machine instructions to the host machine's physical CPU for execution at native speed through the instruction pass-through mechanism, thereby achieving high operating efficiency.

[0044] The core of this invention lies in its instruction pass-through mechanism, triggered by system calls (such as ioctl), which allows general computing instructions of the virtual target machine to bypass the translation process and be executed directly in hardware. Only when the execution flow encounters input / output operation instructions is the I / O operation capture and simulation mechanism triggered, transferring control to the user-mode virtual machine instance for processing. Figure 1 It clearly highlights the high-performance advantages brought by instruction pass-through under the homogeneous architecture.

[0045] Example 1:

[0046] Figure 1 This is a flowchart illustrating a method for accelerating the operation of a central processing unit (CPU) in digital simulation, as described in an embodiment of the present invention.

[0047] like Figure 1 As shown, this embodiment provides a method for accelerating the operation of a central processing unit (CPU) for digital simulation, applied to a host machine with a homogeneous instruction set architecture (such as ARMv8) as the target machine, including the following steps:

[0048] Step S0 generates a graphical hardware environment modeling interface to receive user input on the target chip type, peripheral modules, and target machine program loading configuration. The target chip type is used to create the corresponding virtual processor, and the peripheral modules are used to instantiate the corresponding virtual peripheral models.

[0049] First, based on the host machine's instruction set architecture, the interface displays and allows the user to select the supported target chip type (e.g., FT2000HK, FT2000-4, D2000, or E2000). Then, the user can use the provided general-purpose peripheral modules and PCIe / QSPI interface dynamic connectors to mount the required peripheral modules onto the selected target chip. On this basis, a graphical window receives the user's settings for the target machine application, board support package (BSP), and operating system image file paths and partition loading configurations. Finally, this configured target board hardware model can be saved as a custom device type, which will be displayed in the target chip selection menu for direct selection in subsequent simulation projects.

[0050] Step S1: Utilize the host machine's hardware-assisted virtualization capabilities (such as KVM) to create a virtual machine instance and a virtual CPU. Initialize the virtual CPU by setting registers (such as the program counter and stack pointer), setting the virtual CPU's program counter to the entry address of the target machine's program. The vCPU is compatible with the target processor.

[0051] Specifically, in step S1, the hardware-assisted virtualization function is the kernel-based virtual machine (KVM) function, and the initialization of the virtual processor is completed by calling the host kernel's KVM function library interface.

[0052] Furthermore, in step S1, when creating a virtual machine instance, virtual peripheral models of the kernel timer and interrupt controller are created simultaneously.

[0053] Step S2 allocates host physical memory to the virtual machine instance and establishes a mapping relationship between the target machine's physical address space and the host machine's physical memory. This allows the host machine hardware to directly perform address translation when the vCPU accesses memory. The target machine's physical address space includes the address range of Memory Mapped Input / Output (MMIO).

[0054] Specifically, in step S2, the address range of memory-mapped inputs / outputs is mapped to the corresponding processing logic in the virtual machine instance.

[0055] Step S3: The instructions of the target machine program are passed through and loaded into the host machine's physical CPU through a system call to the virtual processor, and the host machine's physical CPU executes the instructions of the target machine program directly without instruction translation.

[0056] In this embodiment, the virtual processor has a built-in target program identification instruction mapping table. By looking up the table, the instruction operations and I / O operations in the target machine program are identified. The instruction operations are directly loaded into the virtual processor and executed by the host machine hardware. The I / O operations are switched to the virtual machine instance to complete the ioctl call.

[0057] Specifically, step S3 includes the following sub-steps:

[0058] Step S3.1: Establish an instruction-distinguishing hash table to distinguish instruction execution, memory access, and I / O operations;

[0059] Step S3.2: By querying the hash table, the instructions in the target machine program are divided into I / O instructions that need to be converted into virtual peripheral memory mapping access operations and computation instructions that can be executed directly on the host machine's physical CPU.

[0060] Step S3.3: For calculation instructions, execute them directly on the host machine's physical CPU and obtain the execution results. Based on the execution results, continue to execute subsequent memory access or I / O operations and memory mapping operations.

[0061] Specifically, the host machine's physical CPU core directly reads and executes the target machine's program instructions from the mapped memory; this process is called instruction pass-through.

[0062] Step S4: When the virtual processor executes an instruction that accesses the memory-mapped input / output address range for I / O operations, the virtual processor captures the access operation and triggers the virtual processor to exit. It then passes the generated I / O request information to the user-mode virtual machine instance. The virtual machine instance parses the I / O request information and calls the corresponding virtual peripheral model to perform simulation operations to generate simulation running data. After the simulation operation is completed, the virtual machine instance schedules the virtual processor again through a system call, so that the virtual processor resumes execution from the instruction address pointed to by the context information saved when the virtual processor exited.

[0063] In this embodiment, by alternating between "instruction pass-through execution" and "I / O trap simulation", general computing instructions are directly executed by the host machine's physical CPU, and the system only traps into user mode for software simulation when processing I / O operations, thereby improving simulation efficiency.

[0064] Specifically, in step S4, the I / O operating system call is the ioctl system call, and a hash page table is used to manage the address mapping of the virtual peripheral model. The virtual machine instance looks up the corresponding virtual peripheral model in the hash page table according to the target address in the I / O request information.

[0065] Furthermore, in step S4, the virtual peripheral model simulates the logical functions in user mode, and the virtual processor accesses the virtual peripheral model through a preset interaction interface to complete the reading and writing of input / output data.

[0066] Step S5: The simulation running data is interacted with external simulation nodes through the Data Distribution Service (DDS) interface, and / or, service-oriented calls or containerized deployment is supported through the integrated call interface.

[0067] Example 2:

[0068] The present invention also provides a central processing unit (CPU) acceleration system for digital simulation. Figure 2 This is a structural diagram of a central processing unit (CPU) acceleration system for digital simulation, as described in an embodiment of the present invention. Figure 2The CPU running acceleration system for digital simulation can be implemented by executing the process steps of the CPU running acceleration method for digital simulation. That is, those skilled in the art can understand the CPU running acceleration method for digital simulation as a preferred embodiment of the CPU running acceleration system for digital simulation.

[0069] The central processing unit used for digital simulation runs an acceleration system, including:

[0070] Module M0 generates a graphical hardware environment modeling interface, which is used to receive user input on the target chip type, peripheral modules, and target machine program loading configuration. The target chip type is used to create the corresponding virtual processor, and the peripheral modules are used to instantiate the corresponding virtual peripheral models.

[0071] Module M1 utilizes the host machine's hardware-assisted virtualization capabilities to create virtual machine instances and virtual processors, initializes the virtual processors, and sets the virtual processor's program counter to the entry address of the target machine's program.

[0072] Module M2 allocates host physical memory for virtual machine instances and establishes a mapping relationship between the target machine physical address space and the host machine physical memory. The target machine physical address space includes the address range of memory-mapped inputs / outputs.

[0073] Module M3 uses system calls to load the instructions of the target machine program into the host machine's physical CPU through a virtual processor. The host machine's physical CPU then executes the instructions of the target machine program directly without instruction translation.

[0074] Specifically, module M3 includes the following sub-modules:

[0075] Module M3.1 establishes an instruction-distinguishing hash table to differentiate instruction execution, memory access, and I / O operations;

[0076] Module M3.2 distinguishes the instructions in the target machine program by querying the hash table, classifying them into I / O instructions that need to be converted into virtual peripheral memory-mapped access operations and computation instructions that can be executed directly on the host machine's physical CPU.

[0077] Module M3.3 executes computation instructions directly on the host machine's physical CPU and obtains the execution results. Based on the execution results, it continues to perform memory mapping operations for subsequent memory access or I / O operations.

[0078] Module M4: When the virtual processor executes an instruction that accesses the memory-mapped input / output address range for I / O operations, the virtual processor captures the access operation and triggers its exit. It then passes the generated I / O request information to the user-mode virtual machine instance. The virtual machine instance parses the I / O request information and calls the corresponding virtual peripheral model to perform simulation operations to generate simulation running data. After the simulation operation is completed, the virtual machine instance again schedules the virtual processor through a system call, causing the virtual processor to resume execution from the instruction address pointed to by the context information saved when the virtual processor exited.

[0079] Module M5 interacts simulation runtime data with external simulation nodes through the Data Distribution Service (DDS) interface, and / or supports service-oriented calls or containerized deployment through the integrated call interface.

[0080] Example 3:

[0081] This embodiment optimizes the performance bottlenecks that may occur in input / output (I / O) intensive application scenarios in Embodiment 1. As the number of virtual peripheral models increases, traditional I / O distribution logic (such as lengthy conditional chains) will affect overall performance due to low lookup efficiency. Therefore, this embodiment introduces an address mapping management mechanism based on hash page tables into the I / O processing logic in step S4.

[0082] Specifically, during the system initialization phase, a global hash page table is constructed to establish a fast mapping relationship between the target machine's I / O addresses and the corresponding virtual peripheral model processing functions. The construction process of this hash page table is as follows:

[0083] Step a1: Define a hash function that takes the target machine's physical address (usually its high-order bits) as input.

[0084] Step a2: Traverse all virtual peripheral models, obtain the address range of each virtual peripheral model, calculate the base address of the address range using a hash function to obtain the corresponding hash index, and store a pointer to the I / O processing function of the virtual peripheral model at the hash index position.

[0085] To resolve potential hash collisions, chaining is used.

[0086] During simulation, when an I / O operation triggers the virtual machine to exit, the user-mode virtual platform software processing flow is as follows: First, the target I / O address for this access is extracted from the virtual machine exit information; then, the address is input into a hash function to calculate the index, and the lookup is performed directly in the hash page table. The average time complexity of this lookup process is O(1); finally, the corresponding virtual peripheral model processing function is called according to the found function pointer to complete the accurate simulation of I / O behavior.

[0087] By introducing hash page tables, this embodiment significantly reduces the dispatch latency of I / O operations, thereby effectively improving the overall execution efficiency of I / O-intensive simulation tasks.

[0088] Example 4:

[0089] This embodiment aims to extend the method of the present invention to large-scale distributed collaborative simulation scenarios. Based on the method of Embodiment 1, a data distribution service (DDS) interface is integrated in step S5.

[0090] The implementation process is as follows:

[0091] Step b1: Integrate the data distribution service client library into the virtual platform software, and predefine a unified data model and communication topics based on the business requirements of collaborative simulation;

[0092] Step b2 involves launching independent virtual machine instances based on either Example 1 or 3 for the multiple target machine programs that require co-simulation. Each virtual machine instance is configured with the required published and subscribed communication topics according to the functions of the target machine program running inside it. All virtual machine instances interact with each other in real time through the data distribution service data bus.

[0093] During operation, all simulation nodes run in parallel, exchanging data in real time and reliably via the DDS data bus. The computational tasks within each node benefit from the efficient execution of instruction pass-through technology, thereby enabling distributed, high real-time, and high-performance collaborative simulation of complex systems.

[0094] In addition, step S5 can provide standardized integration call interfaces (such as RESTful API or gRPC), enabling this simulation solution to be called and integrated by external automated testing frameworks or cloud-native platforms in a service-oriented manner, thereby seamlessly integrating into modern development and operation systems.

[0095] Example 5:

[0096] This embodiment provides a graphical hardware environment modeling scheme, aiming to significantly improve the usability and configuration efficiency of the simulation system. This function corresponds to step S0 in Embodiment 1 and is further specified therein.

[0097] The specific implementation is as follows: First, a graphical hardware environment modeling interface is provided, including a component library, a visual canvas, and a property editor. The component library pre-configures various target chip types with homogeneous architectures (such as various series of ARMv8 architecture) and general peripheral modules. Users can build virtual hardware topologies on the canvas through simple drag-and-drop and connection operations, and configure parameters such as the number of cores, memory size, and target machine program loading path in the property editor. The system background automatically generates underlying information such as the device tree based on this graphical configuration. After the user completes the setup, they can directly start the simulation, and the system will automatically execute steps S1 to S4 as in Example 1 based on the current configuration. Users can also save satisfactory hardware configurations as custom device types for easy one-click loading and reuse in subsequent projects, greatly improving the efficiency and consistency of simulation environment setup.

[0098] Those skilled in the art will understand that, besides implementing the system and its various devices, modules, and units provided by this invention in the form of purely computer-readable program code, the same functions can be achieved entirely through logical programming of the method steps, making the system and its various devices, modules, and units of this invention function in the form of logic gates, switches, application-specific integrated circuits, programmable logic controllers, and embedded microcontrollers. Therefore, the system and its various devices, modules, and units provided by this invention can be considered as a hardware component, and the devices, modules, and units included therein for implementing various functions can also be considered as structures within the hardware component; alternatively, the devices, modules, and units for implementing various functions can be considered as both software modules implementing the method and structures within the hardware component.

[0099] Specific embodiments of the present invention have been described above. It should be understood that the present invention is not limited to the specific embodiments described above, and those skilled in the art can make various changes or modifications within the scope of the claims, which do not affect the essence of the present invention. Unless otherwise specified, the embodiments and features of the present invention can be arbitrarily combined with each other.

Claims

1. A method for accelerating the execution of a central processing unit (CPU) in digital simulation, applied to a host machine with a CPU architecture homogeneous with the target machine, characterized in that, Includes the following steps: Step S0: Generate a graphical hardware environment modeling interface to receive user input on the target chip type, peripheral modules, and target machine program loading configuration. The target chip type is used to create a corresponding virtual processor, and the peripheral modules are used to instantiate into corresponding virtual peripheral models. The target machine program loading configuration includes receiving user file path settings and partition loading configurations for the target machine application, board support package, and operating system image through a graphical window. Step S1: Based on the input of the target chip type, peripheral modules, and target machine program loading configuration, a virtual machine instance and a virtual processor are created using the host machine's hardware-assisted virtualization function. The virtual processor is then initialized, and its program counter is set to the entry address of the target machine program. During the creation of the virtual machine instance, virtual peripheral models for the kernel timer and interrupt controller are created simultaneously. The initialization of the virtual processor is accomplished by calling the host machine kernel's KVM function library interface. Step S2: Allocate host physical memory to the virtual machine instance and establish a mapping relationship between the target machine physical address space and the host machine physical memory. The target machine physical address space includes the address range of memory-mapped input / output. Step S3: The instructions of the target machine program are passed through and loaded into the host machine's physical CPU through a system call to the virtual processor, and the host machine's physical CPU directly executes the instructions of the target machine program. Specifically, step S3 includes the following sub-steps: Step S3.1: Establish an instruction-distinguishing hash table to distinguish instruction execution, memory access, and I / O operations; Step S3.2: By querying the hash table, the instructions in the target machine program are divided into I / O instructions that need to be converted into virtual peripheral memory mapping access operations and computation instructions that can be executed directly on the host machine's physical CPU. Step S3.3: For calculation instructions, execute them directly on the host machine's physical CPU and obtain the execution results. Based on the execution results, continue to execute subsequent memory access or I / O operations and memory mapping operations. The host machine's physical CPU core directly reads and executes the target machine's program instructions from the mapped memory; this is known as instruction pass-through. Step S4: When the virtual processor executes an instruction that accesses the memory-mapped input / output address range, the virtual processor captures the access operation and triggers the virtual processor to exit. It then passes the generated I / O request information to the user-mode virtual machine instance. The virtual machine instance parses the I / O request information and calls the corresponding virtual peripheral model to perform simulation operations to generate simulation running data. After the simulation operation is completed, the virtual machine instance calls the virtual processor again through the system to resume execution from the instruction address pointed to by the context information saved when the virtual processor exited.

2. The method for accelerating the operation of a central processing unit for digital simulation according to claim 1, characterized in that, In step S2, the address range of memory-mapped inputs / outputs is mapped to the corresponding processing logic in the virtual machine instance.

3. The method for accelerating the operation of a central processing unit for digital simulation according to claim 1, characterized in that, In step S3, the virtual processor has a built-in target program identification instruction mapping table. By looking up the table, it identifies the instruction operations and I / O operations in the target machine program. The instruction operations are directly loaded into the virtual processor and executed by the host machine hardware. The I / O operations are switched to the virtual machine instance to complete the ioctl call.

4. The method for accelerating the operation of a central processing unit for digital simulation according to claim 1, characterized in that, In step S4, the system call for I / O operation is the ioctl system call. A hash page table is used to manage the address mapping of the virtual peripheral model. The virtual machine instance looks up the corresponding virtual peripheral model in the hash page table according to the target address in the I / O request information.

5. The method for accelerating the operation of a central processing unit for digital simulation according to claim 4, characterized in that, In step S4, the hash page table construction process includes the following steps: Step a1: Define a hash function, which takes the target machine's physical address as input; Step a2: Traverse all virtual peripheral models, obtain the address range of each virtual peripheral model, and calculate the base address of the address range using the hash function to obtain the corresponding hash index. Store a pointer to the I / O processing function of the virtual peripheral model at the hash index position.

6. The method for accelerating the operation of a central processing unit for digital simulation according to claim 1, characterized in that, The method further includes step S5: Step S5: The simulation running data is interacted with external simulation nodes through the data distribution service interface, and / or, service-oriented calls or containerized deployment is supported through the integrated call interface.

7. The method for accelerating the operation of a central processing unit for digital simulation according to claim 6, characterized in that, In step S5, the interaction with external simulation nodes through the data distribution service interface includes the following steps: Step b1: Integrate the data distribution service client library into the virtual machine instance, and predefine a unified data model and communication topics based on the business requirements of collaborative simulation; Step b2 involves starting independent virtual machine instances for the multiple target machine programs that require co-simulation. Each virtual machine instance is configured with the required published and subscribed communication topics based on the functions of the target machine programs running inside it. All virtual machine instances interact with each other in real time through the data distribution service data bus.

8. A central processing unit (CPU) acceleration system for digital simulation, employing the CPU acceleration method for digital simulation as described in any one of claims 1-7, characterized in that, include: Module M1 utilizes the host machine's hardware-assisted virtualization function to create virtual machine instances and virtual processors, initializes the virtual processors, and sets the program counter of the virtual processors to the entry address of the target machine program. Module M2 allocates host physical memory to the virtual machine instance and establishes a mapping relationship between the target machine physical address space and the host machine physical memory. The target machine physical address space includes the address range of memory-mapped input / output. Module M3 uses system calls to pass through the virtual processor to load the instructions of the target machine program into the host machine's physical CPU, so that the host machine's physical CPU can directly execute the instructions of the target machine program. Module M4: When the virtual processor executes an instruction that accesses a memory-mapped input / output address range, the virtual processor captures the access operation and triggers the virtual processor to exit. It then passes the generated I / O request information to the user-mode virtual machine instance. The virtual machine instance parses the I / O request information and calls the corresponding virtual peripheral model to perform simulation operations to generate simulation running data. After the simulation operation is completed, the virtual machine instance calls the virtual processor again through the system to resume execution from the instruction address pointed to by the context information saved when the virtual processor exited.

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