Event processing method, electronic equipment and storage medium
By designing an event handling method on the ARM platform, utilizing memory mapping and an enhanced serial peripheral interface, the lack of I/O ports on the ARM64 platform was solved, achieving the same event handling functionality as the x86 platform, and improving response speed and communication efficiency.
Patent Information
- Application Number
- CN202511234946.9
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-08-29
- Publication Date
- 2025-12-12
AI Technical Summary
The lack of I/O ports on the ARM64 architecture platform causes the x86 QEvent mechanism to fail, requiring a redesign of the hardware interaction method to achieve event communication.
On the ARM platform, an event handling method is implemented by acquiring and accessing the first memory address and the second memory address, using the enhanced serial peripheral interface, including memory mapping of the status port and the data port, and using the first controller and the second controller to access event data and execute actions.
The same event handling functionality as the x86 platform was implemented on the ARM platform without I/O ports, improving response speed and communication efficiency.
Smart Images
Figure CN121116614A_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of embedded system communication technology, and more specifically to an event processing method, an electronic device, and a storage medium. Background Technology
[0002] In the x86 platform, the BIOS and the embedded controller (EC) communicate via I / O port instructions (such as IN / OUT) and the QEvent queue. However, the ARM64 architecture platform lacks I / O ports and therefore does not support the x86 QEvent mechanism, rendering the original communication protocol ineffective and necessitating a redesign of the hardware interaction method. Summary of the Invention
[0003] In order to solve the above-mentioned technical problems, the present invention aims to provide an event processing method, an electronic device, and a storage medium.
[0004] The specific technical solution adopted is as follows:
[0005] An event handling method for an ARM platform, the ARM platform including at least a first controller and a second controller, the event handling method comprising:
[0006] Obtain a first memory address and a second memory address that can be accessed by the first controller and the second controller respectively. The first memory address is used to represent the status port and the second memory address is used to represent the data port.
[0007] In response to a target event, the target data of the target event is stored in the queue of events to be processed, and the processing request corresponding to the target event is triggered by modifying the state of the first memory address using the first controller.
[0008] In response to the processing request, the target instruction for querying the target event is written to the second memory address via the second controller;
[0009] Based on the target instruction, the first controller retrieves the target data of the target event from the queue of events to be processed, and writes the target data into the second memory address;
[0010] Based on the target data, the target action is executed through the second controller.
[0011] In some embodiments, the first controller and the second controller are communicatively connected via an enhanced serial peripheral interface;
[0012] Obtaining the first memory address and the second memory address that can be accessed by the first controller and the second controller respectively includes:
[0013] The first memory address and the second memory address are obtained through memory mapping based on the enhanced serial peripheral interface.
[0014] In some embodiments, the first memory address includes at least a first register bit, the first register bit having a first state representing an event to be processed and a second state representing no event to be processed.
[0015] Using the first controller to modify the state of the first memory address to trigger the processing request corresponding to the target event includes:
[0016] The first controller sets the first register bit of the first memory address to a first state to generate a processing request corresponding to the target event;
[0017] The processing request is transmitted via a virtual channel of the enhanced serial peripheral interface.
[0018] In some embodiments, in response to the processing request, writing a target instruction for querying the target event to the second memory address via a second controller includes:
[0019] Determine whether the first identifier of the first memory address is in the first state;
[0020] If the first identifier of the first memory address is in the first state, in response to the processing request, the target instruction is written to the second memory address through the second controller.
[0021] In some embodiments, the first memory address further includes a second register bit and a third register bit. The second register bit has a first state indicating that information has been stored at the second memory address and a second state indicating that no information has been stored at the second memory address. The third register bit has a first state indicating that the information stored at the second memory address is an instruction and a second state indicating that the information stored at the second memory address is data.
[0022] When the target instruction is written to the second memory address, the second controller sets the second register bit and the third register bit of the first memory address to the first state respectively.
[0023] In some embodiments, based on the target instruction, the first controller retrieves target data of the target event from the queue of events to be processed, and writes the target data to the second memory address, including:
[0024] The first controller is used to read the first memory address in a loop and determine whether the third register bit of the first memory address is in the first state;
[0025] If the third register bit is confirmed to be in the first state, the target instruction is read, and the second register bit and the third register bit of the first memory address are set to the second state respectively;
[0026] The target data of the target event is retrieved according to the target instruction, the target data is written to the second memory address, and the fourth register bit of the first memory address is set to the first state. The fourth register bit being set to the first state indicates that the target data has been stored in the second memory address.
[0027] In some embodiments, it also includes:
[0028] When the target data is written to the second memory address, the first register bit of the first memory address is set to the second state.
[0029] In some embodiments, based on the target data, executing a target action via a second controller includes:
[0030] Determine whether the first register bit of the first memory address is set to the second state, and whether the fourth register bit is set to the first state;
[0031] When the first register bit is set to the second state and the fourth register bit is set to the first state, the target data is read from the second memory address.
[0032] An electronic device includes a first controller, a second controller, a memory, a processor, and a computer program stored in the memory and executable on the processor. When the processor executes the computer program, it implements an event handling method as described in any of the above embodiments.
[0033] A storage medium storing a computer program that, when executed by a processor, causes the processor to perform an event handling method as described in any of the above embodiments. Attached Figure Description
[0034] To more clearly illustrate the technical solutions and advantages in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.
[0035] Figure 1 This is a flowchart of an event handling method provided in Embodiment 1 of the present invention;
[0036] Figure 2This is a flowchart of an event handling method provided in Embodiment 2 of the present invention;
[0037] Figure 3 This is a flowchart of an event handling method provided in Embodiment 3 of the present invention;
[0038] Figure 4 This is a flowchart of an event handling method provided in Embodiment 4 of the present invention;
[0039] Figure 5 This is a flowchart of an event handling method provided in Embodiment 5 of the present invention;
[0040] Figure 6 This is a flowchart illustrating the BIOS processing when it actively writes data / commands in the event handling method provided in Embodiment 6 of the present invention.
[0041] Figure 7 This is a flowchart of the EC side processing when the BIOS actively writes data / commands in the event handling method provided in Embodiment 7 of the present invention;
[0042] Figure 8 This is a flowchart of the BIOS processing when the BIOS actively reads data / commands in the event handling method provided in Embodiment 8 of the present invention.
[0043] Figure 9 This is a flowchart of the EC side processing when the BIOS actively reads data / commands in the event handling method provided in Embodiment 9 of the present invention;
[0044] Figure 10 This is a flowchart of the BIOS-EC communication process in the event handling method provided in Embodiment 10 of the present invention. Detailed Implementation
[0045] To further illustrate the technical means and effects adopted by the present invention to achieve its intended purpose, the following detailed description, in conjunction with the accompanying drawings and preferred embodiments, provides a detailed explanation of the specific implementation, structure, features, and effects of an event processing method proposed according to the present invention. In the following description, different "one embodiment" or "another embodiment" do not necessarily refer to the same embodiment. Furthermore, specific features, structures, or characteristics in one or more embodiments can be combined in any suitable form.
[0046] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention pertains.
[0047] The specific solution of an event handling method provided by the present invention will be described in detail below with reference to the accompanying drawings.
[0048] This application provides an event handling method for an ARM platform, which includes at least a first controller and a second controller. The ARM platform can be used in smart devices such as mobile phones, computers, and tablets. The first controller can be used for low-level hardware control, such as an EC (Electronic Control Unit); the second controller can be used for operating system or application-level control, such as a CPU. The first and second controllers can communicate to handle interrupt events.
[0049] like Figure 1 As shown, the event handling method in this application embodiment includes at least:
[0050] Step S100: Obtain a first memory address and a second memory address that can be accessed by the first controller and the second controller respectively. The first memory address is used to represent the status port, and the second memory address is used to represent the data port.
[0051] In step S100, the first memory address and the second memory address can be obtained by mapping the I / O ports of the second controller to the host's memory space through the memory mapping function of the ARM platform. The mapping relationship can be implemented by page table mechanism to convert virtual addresses to physical addresses.
[0052] The first memory address and the second memory address are two independent addresses in the shared memory. The first controller and the second controller can access these two memory addresses through ordinary memory access instructions without the need for dedicated I / O instructions.
[0053] Accessing the first memory address and the second memory address can be understood as being able to read and write data within the first memory address and the second memory address. For example, data can be written to the first memory address and the second memory address, or data can be read from the first memory address and the second memory address.
[0054] In addition, the first memory address used to characterize the status port can be understood as being used to transmit control status information, and the second memory address used to characterize the data port can be understood as being used to transmit actual data or instructions.
[0055] Step S200: In response to the target event, store the target data of the target event into the queue of events to be processed, and use the first controller to modify the state of the first memory address to trigger the processing request corresponding to the target event;
[0056] In step 200, responding to the target event includes detecting whether there is a response to the target event via the first controller. The target event can be a hardware state change event such as a laptop lid opening / closing event or a keyboard / touchpad input event, or a power-related event such as an adapter plugging / unplugging detection.
[0057] Taking the laptop lid opening and closing event as an example, when the laptop lid is closed, the first controller detects the state change and triggers the processing request for the target event. After receiving the processing request, the second controller controls the computer to enter sleep mode.
[0058] Since the first controller is used for underlying hardware control, responding to target events through the first controller can improve response speed.
[0059] In addition, when the first controller detects a target event to be processed, it stores the target data of the target event in the queue of events to be processed, namely the QEvent queue. The QEvent queue is typically used to store event data to be processed, and the first controller can retrieve the data using a first-in, first-out (FIFO) method.
[0060] Step S300: In response to the processing request, write the target instruction to the second memory address through the second controller;
[0061] In step S300, the second controller can respond to a processing request by reading the first memory address. For example, it can determine whether a processing request has been received by observing changes in the first memory address.
[0062] The target instruction can be a set of instructions for the first controller to perform response operations. It may include basic communication instructions, such as 0x80 and 0x81: basic read / write operation instructions, where 0x80 is a read operation and 0x81 is a write operation. Or 0x84: event query (QR_EC) and configuration lock (CFG Lock) instructions. Alternatively, it may include hardware control instructions. For example, 0x85: power management instructions, 0x90: keyboard controller (KBC) instructions, and 0xA0-0xA3: fan control instructions. Step S400: Based on the target instruction, the first controller retrieves the target data of the target event from the queue of events to be processed, and writes the target data to the second memory address;
[0063] Step S500: Based on the target data, execute the target action through the second controller.
[0064] In step 500, different target events correspond to different target actions. For example, when the target event is the opening and closing of a laptop lid, the corresponding target action is to control the computer to enter sleep mode.
[0065] The event handling method provided in this application embodiment, by setting a first memory address and a second memory address that are accessed by a first controller and a second controller respectively on the ARM platform, and by having the first controller and the second controller access the corresponding memory addresses respectively, enables the virtual target event handling on the ARM platform without I / O ports and the target event handling on the x86 platform to have the same function.
[0066] In some embodiments, the first controller and the second controller can be connected to communicate via an enhanced serial peripheral interface.
[0067] Obtaining the first memory address and the second memory address, which can be accessed by the first controller and the second controller respectively, includes:
[0068] The first and second memory addresses are obtained through memory mapping based on the enhanced serial peripheral interface.
[0069] In this embodiment, the Enhanced Serial Peripheral Interface (ESPI) is an enhanced serial peripheral interface protocol that maps peripheral resources to the host memory address space through memory mapping technology. This mechanism allows the CPU to access peripheral registers as if they were ordinary memory, greatly simplifying peripheral operations.
[0070] For example, the I / O ports include a 66 status port and a 62 data port. The Enhanced Serial Peripheral Interface (ESI) can map the 66 status port to address 0xFE0B0266 in shared memory, and the 62 data port to address 0xFE0B0262 in shared memory. This can be understood as 0xFE0B0266 being the first memory address and 0xFE0B0262 being the second memory address; 0xFE0B0266 and 0xFE0B0262 correspond to the internal status register and data buffer of the first controller, respectively.
[0071] The first controller and the second controller can access the first memory address and the second memory address in the shared memory, respectively, thereby improving the access speed.
[0072] In some embodiments, the first memory address includes at least a first register bit, which has a first state indicating that there is an event to be processed and a second state indicating that there is no event to be processed. When the first memory address is 0xFE0B0266, the first register bit can be BIT5 (SCIEVT) of 0xFE0B0266, which is used to control or mark system control interrupt events, such as power state changes or hardware exception triggers.
[0073] like Figure 2 As shown, the process of triggering the processing request corresponding to the target event by modifying the state of the first memory address using the first controller includes:
[0074] Step S201: Set the first register bit of the first memory address to the first state through the first controller to generate the processing request corresponding to the target event.
[0075] Specifically, the first controller can trigger the processing request corresponding to the target event by setting the first register bit of the first memory address to 1. Conversely, setting the first register bit of the first memory address to 0 indicates that the processing request for the target event has been completed.
[0076] Step S202: Transmit the processing request through the virtual channel of the enhanced serial peripheral interface.
[0077] In this embodiment, the enhanced serial peripheral interface supports virtual wire channels, such as VWIDX0, VWIDX2, and VWIDX6. The enhanced serial peripheral interface can select any one of these channels to transmit processing requests. For example, the processing request can be sent to the second controller through the VWIDX6 channel of the enhanced serial peripheral interface.
[0078] like Figure 3 As shown, in some embodiments, in response to the processing request, writing the target instruction to the second memory address via the second controller includes:
[0079] Step S301: Determine whether the first identifier of the first memory address is in the first state;
[0080] Step S302: If the first identifier of the first memory address is in the first state, respond to the processing request and write the target instruction to the second memory address through the second controller.
[0081] Specifically, when the second controller receives a processing request for a target event, it reads the first memory address in the shared memory to determine whether the first register bit is in the first state. If the first identifier of the first memory address is in the first state, the second controller writes the target instruction related to the target event into the second memory address.
[0082] If the first identifier of the first memory address is not in the first state, but in the second state, then the entire event handling process ends.
[0083] In some embodiments, the first memory address may further include a second register bit and a third register bit.
[0084] The second register bit can have a first state indicating that there is an event processing request to be processed in the current operation cycle and a second state indicating that there is no event processing request to be processed in the current operation cycle.
[0085] The third register bit can have a first state indicating that the information stored at the second memory address is an instruction, and a second state indicating that the information stored at the second memory address is data.
[0086] For example, when the first memory address is 0xFE0B0266, the second register bit can be the BIT1 (IBF) register, and the third register bit can be the BIT3 (C_D) register.
[0087] When BIT1(IBF) is set to 1, it means that the input buffer is full and no new data can be written to the data port. When BIT1(IBF) is set to 0, it means that the input buffer is empty and new data can be written to the data port.
[0088] When BIT3(C_D) is set to 1, it indicates that the current transmission is a control command; when BIT3(C_D) is set to 0, it indicates that the current transmission is a data command.
[0089] When the target instruction is written to the second memory address, the second controller sets the second register bit and the third register bit of the first memory address to the first state respectively.
[0090] In this case, setting the second register to the first state can be understood as notifying the first controller that there is an event that needs to be processed. By setting the third register to the first state, the first controller can know that instruction data is stored in the second memory address.
[0091] like Figure 4 As shown, in some embodiments, based on the target instruction, the first controller retrieves the target data of the target event from the queue of events to be processed, and writes the target data to a second memory address, including:
[0092] Step S401: Use the first controller to read the first memory address in a loop and determine whether the third register bit of the first memory address is in the first state;
[0093] Step S402: If the third register bit is confirmed to be in the first state, the target instruction is read and the second and third register bits of the first memory address are set to the second state respectively; this step can be understood as informing the second controller that the instruction data stored in the second memory address has been read.
[0094] Step S403: Retrieve the target data of the target event according to the target instruction, write the target data to the second memory address, and set the fourth register bit of the first memory address to the first state. Setting the fourth register bit to the first state is used to indicate that the target data has been stored in the second memory address.
[0095] When the first memory address is 0xFE0B0266, the fourth register bit can be BIT0 (OBF). When BIT0 (OBF) is set to 0, it means that the output buffer is empty and no data can be read; the host needs to wait to avoid reading invalid data. When BIT0 (OBF) is set to 1, it means that the output buffer is full and contains the keyboard scan code or other data to be read; the host can safely read the data from the port.
[0096] In some embodiments, it also includes:
[0097] When target data is written to the second memory address, the first register bit at the first memory address is set to the second state. Setting the first register bit to the second state indicates that the event processing request has been completed.
[0098] like Figure 5 As shown, in some embodiments, based on target data, the target action is executed by a second controller, including:
[0099] Step S501: Determine whether the first register bit of the first memory address is set to the second state, and whether the fourth register bit is set to the first state;
[0100] Step S502: When the first register bit is set to the second state and the fourth register bit is set to the first state, read the target data from the second memory address.
[0101] In some embodiments, the first and second states of the first register bit, second register bit, third register bit, and fourth register bit of the first memory address can be represented by two different characters. For example, the first state can be the number 1, and the second state can be the number 0. Alternatively, the first state can be the letter A, and the second state can be the letter B.
[0102] This application uses an example where the first controller is the BIOS within the CPU of an ARM platform and the second controller is the EC under the ARM platform to illustrate the event handling method of this embodiment.
[0103] Before proceeding, let's first discuss the processing flow between the BIOS (second controller) and EC (first controller) when the BIOS (second controller) actively writes data / commands, and the processing flow between the BIOS (second controller) and EC (first controller) when the BIOS (second controller) actively reads data / commands.
[0104] Figure 6 The flowchart illustrates the operations performed by the BIOS (second controller) during an active write operation. The specific process is as follows:
[0105] (1) The BIOS or host sends cmd (target instruction) and writes cmd to the second memory address in shared memory (i.e., 0xFE0B0262);
[0106] (2) Next, the BIOS sets BIT1 (OBF) and BIT3 (C_D) of the first memory address (i.e., 0xFE0B0266) to 1 to notify the EC that there is a new command to be processed. Then, it waits for BIT1 (OBF) of 0xFE0B0266 to be cleared to 0 by the EC.
[0107] (3) If BIT1(OBF) is set to 0, it indicates that the EC has received the command. At this time, the EC writes data to 0xFE0B0262.
[0108] (4) Then EC sets BIT1 (OBF) of 0xFE0B0266 to 1 and clears BIT3 (C_D) to 0; then waits for BIT1 (OBF) of 0xFE0B0266 to be cleared by EC.
[0109] (5) If BIT1(OBF) is cleared, determine whether all data has been sent. If all data has been sent, end the process; if not, return to step 3.
[0110] (6) If there are multiple data, repeat steps 3 and 4.
[0111] Figure 7 The flowchart illustrates the operations performed on the EC (first controller) side when the BIOS (second controller) actively writes. The specific process is as follows:
[0112] (1) After the BIOS or host finishes sending data, the EC loop reads whether BIT1 (IBF) of 0xFE0B0266 is 1;
[0113] (2) If BIT1(IBF) is set to 1, then check whether BIT3(C_D) of 0xFE0B0266 is 1 to determine whether the received data is cmd or data; where BIT3(C_D) is 1, it means that cmd is received; BIT3(C_D) is 0, it means that data is received.
[0114] (3) If the received message is cmd, read it and save it. Then clear BIT1 (IBF) and BIT3 (C_D) of 0xFE0B0266 to 0. After saving cmd, check if it contains date. If it does not contain date, end the process.
[0115] (4) If the received data is data, save the data and clear BIT1 (IBF) and BIT3 (C_D) of 0xFE0B0266 to 0. At the same time, determine whether the data has been fully received. If all data has been received, end the process.
[0116] Figure 8 The flowchart illustrates the operations performed by the BIOS (second controller) during an active read. The specific process is as follows:
[0117] (1) The BIOS or host sends a cmd (target instruction) and writes it to the second memory address in shared memory (i.e., 0xFE0B0262); simultaneously, it sets BIT1 (OBF) and BIT3 (C_D) of the first memory address (i.e., 0xFE0B0266) to 1 to notify the EC that there is a new command to be processed. Then, it waits for BIT1 (OBF) of 0xFE0B0266 to be cleared to 0 by the EC.
[0118] (2) If BIT1(OBF) is set to 0, it indicates that the EC has received the command. At this time, the EC writes data to 0xFE0B0262, sets BIT1(OBF) of 0xFE0B0266 to 1, and clears BIT3(C_D) to 0.
[0119] (3) Then wait for BIT0(IBF) of 0xFE0B0266 to be set to 1;
[0120] (4) If BIT0(IBF) is set to 1, the BIOS reads the data stored in 0xFE0B0262 and clears BIT0(IBF) of 0xFE0B0266 to 0.
[0121] (5) If there are multiple data, repeat steps 3 and 4.
[0122] Figure 9 The flowchart illustrates the operations performed by the EC (first controller) during a BIOS (second controller) active read. The specific process is as follows:
[0123] (1) After the BIOS or host finishes sending data, the EC loop reads whether BIT1 (IBF) of 0xFE0B0266 is 1;
[0124] (2) If BIT1 (IBF) is set to 1, it indicates that data has been received; then check whether BIT3 (C_D) of 0xFE0B0266 is 1 to determine whether the received data is cmd or data; where C_D is 1, it means that cmd has been received; C_D is 2, it means that data has been received.
[0125] (3) If the received data is cmd, save cmd, process cmd, and clear BIT1 (IBF) and BIT3 (C_D) of 0xFE0B0266 to 0; if the received data is data, read the data and process it.
[0126] (4) Then the data returned by EC is written to 0xFE0B0262, and BIT1(OBF) of 0xFE0B0266 is set to 1, and waits for whether BIT1(OBF) is cleared to 0.
[0127] (5) If BIT1(OBF) is 0, determine whether there is still data to be sent. If so, continue to step 3; otherwise, end the process.
[0128] Figure 10 The communication flowchart between the BIOS (second controller) and EC (first controller) is shown below.
[0129] (1) After the EC detects the interrupt handling event (QEvent) response, it sends the interrupt handling event to the QEvent queue and sets BIT5 (SCIEVT) of 0xFE0B0266 to 1;
[0130] (2) EC will send the interrupt handling event of eSPIVWIDX6 to BIOS, and set BIT4 and BIT0 of eSPIVWIDX6 to 1, then set BIT0 of VWIDX6 to 0 and then set it back to 1.
[0131] (3) After receiving the interrupt handling event, the BIOS will determine whether BIT5 (SCIEVT) of 0xFE0B0266 is set to 1;
[0132] (4) If BIT5 (SCIEVT) of 0xFE0B0266 is set to 1, the BIOS will write 0x84 cmd to 0xFE0B0262 and set BIT1 (IBF) and BIT3 (C_D) of 0xFE0B0266 to 1; if BIT5 (SCIEVT) of 0xFE0B0266 is set to 0, the entire communication process will end directly.
[0133] (5) EC loop reads 0xFE0B0266. If it is determined that C_D of 0xFE0B0266 is 1, it reads 0x84 cmd of 0xFE0B0262 and clears BIT1 (IBF) and BIT3 (C_D) of 0xFE0B0266 to 0.
[0134] (6) EC retrieves the data from the QEvent queue according to 0x84 cmd, writes it to 0xFE0B0262, sets BIT0 (OBF) of 0xFE0B0266 to 1, and sets BIT5 (SCIEVT) to 0;
[0135] (7) The EC will send the interrupt handling event of eSPIVWIDX6 to the BIOS, set BIT4 and BIT0 of eSPIVWIDX6 to 1, and then set BIT0 of VWIDX6 to 0 and then set it back to 1.
[0136] (8) When the BIOS receives an interrupt, it determines that BIT5 (SCIEVT) of 0xFE0B0266 is 0 and BIT0 (OBF) of 0xFE0B0266 is 1;
[0137] (9) If 0xFE0B0266 BIT5 (SCIEVT) is 0 and 0xFE0B0266 BIT0 (OBF) is 1, the BIOS reads the QEvent data of 0xFE0B0262, clears 0xFE0B0266 BIT0 (OBF) to 0, processes it, and then ends the entire communication process; if 0xFE0B0266 BIT5 (SCIEVT) is not 0 and 0xFE0B0266 BIT0 (OBF) is not 1, the entire communication process ends directly.
[0138] This application also provides an electronic device, including a first controller, a second controller, a memory, a processor, and a computer program stored in the memory and executable on the processor.
[0139] The memory can be volatile memory, such as random access memory; or non-volatile memory, such as read-only memory, flash memory, hard disk or solid-state drive; or a combination of the above types of memory, and provides instructions and data to the processor.
[0140] The processor can be at least one of the following: Application Specific Integrated Circuit (ASIC), Digital Signal Processor (DSP), Digital Signal Processing Device (DSPD), Programmable Logic Device (PLD), Field Programmable Gate Array (FPGA), Central Processing Unit (CPU), Controller, Microcontroller, and Microprocessor. It is understood that, for different devices, the electronic device used to implement the above-described processor function can also be other types, and this application does not specifically limit the specific implementation. The electronic device can be a mobile phone, computer, tablet, or other smart device, all of which include the ARM platform.
[0141] When the processor executes the computer program, it implements an event handling method for an ARM platform, which includes at least a first controller and a second controller. The first controller can be used for low-level hardware control, such as an EC (Engineer Control Panel); the second controller can be used for operating system or application-level control, such as a CPU. The first and second controllers can communicate to handle interrupt events.
[0142] like Figure 1 As shown, the event handling method includes at least the following:
[0143] Step S100: Obtain a first memory address and a second memory address that can be accessed by the first controller and the second controller respectively. The first memory address is used to represent the status port, and the second memory address is used to represent the data port.
[0144] In step S100, the first memory address and the second memory address can be obtained by mapping the I / O ports of the second controller to the host's memory space through the memory mapping function of the ARM platform. The mapping relationship can be implemented by page table mechanism to convert virtual addresses to physical addresses.
[0145] The first memory address and the second memory address are two independent addresses in the shared memory. The first controller and the second controller can access these two memory addresses through ordinary memory access instructions without the need for dedicated I / O instructions.
[0146] Accessing the first memory address and the second memory address can be understood as being able to read and write data within the first memory address and the second memory address. For example, data can be written to the first memory address and the second memory address, or data can be read from the first memory address and the second memory address.
[0147] In addition, the first memory address used to characterize the status port can be understood as being used to transmit control status information, and the second memory address used to characterize the data port can be understood as being used to transmit actual data or instructions.
[0148] Step S200: In response to the target event, store the target data of the target event into the queue of events to be processed, and use the first controller to modify the state of the first memory address to trigger the processing request corresponding to the target event;
[0149] In step 200, responding to the target event includes detecting whether there is a response to the target event via the first controller. The target event can be a hardware state change event such as a laptop lid opening / closing event or a keyboard / touchpad input event, or a power-related event such as an adapter plugging / unplugging detection.
[0150] Taking the laptop lid opening and closing event as an example, when the laptop lid is closed, the first controller detects the state change and triggers the processing request for the target event. After receiving the processing request, the second controller controls the computer to enter sleep mode.
[0151] Since the first controller is used for underlying hardware control, responding to target events through the first controller can improve response speed.
[0152] Additionally, when the first controller detects a target event to process, it stores the target data of the target event in the queue of events to be processed, namely the QEvent queue. This queue contains multiple target events that need to be processed.
[0153] Step S300: In response to the processing request, write the target instruction to the second memory address through the second controller;
[0154] In step S300, the second controller can respond to a processing request by reading the first memory address. For example, it can determine whether a processing request has been received by observing changes in the first memory address.
[0155] The target instructions are the instruction set for the first controller to perform response operations. They may include basic communication instructions, such as 0x80 and 0x81: basic read / write operation instructions, where 0x80 is a read operation and 0x81 is a write operation. Or 0x84: event query (QR_EC) and configuration lock (CFG Lock) instructions. Alternatively, they may include hardware control instructions. For example, 0x85: power management instructions, 0x90: keyboard controller (KBC) instructions, and 0xA0-0xA3: fan control instructions. Step S400: Based on the target instructions, the first controller retrieves the target data of the target event from the queue of events to be processed, and writes the target data to the second memory address;
[0156] Step S500: Based on the target data, execute the target action through the second controller.
[0157] In step 500, different target events correspond to different target actions. For example, when the target event is the opening and closing of a laptop lid, the corresponding target action is to control the computer to enter sleep mode.
[0158] This application also provides a storage medium storing a computer program, which, when executed by a processor, causes the processor to perform the event handling method described in any of the above embodiments.
[0159] It should be noted that the order of the above embodiments of the present invention is merely for descriptive purposes and does not represent the superiority or inferiority of the embodiments. The processes depicted in the accompanying drawings do not necessarily require a specific or sequential order to achieve the desired result. In some embodiments, multitasking and parallel processing are also possible or may be advantageous.
[0160] The various embodiments in this specification are described in a progressive manner. The same or similar parts between the various embodiments can be referred to each other. Each embodiment focuses on describing the differences from other embodiments.
Claims
1. An event handling method for an ARM platform, the ARM platform including at least a first controller and a second controller, the event handling method comprising: Obtain a first memory address and a second memory address that can be accessed by the first controller and the second controller respectively. The first memory address is used to represent the status port and the second memory address is used to represent the data port. In response to a target event, the target data of the target event is stored in the queue of events to be processed, and the processing request corresponding to the target event is triggered by modifying the state of the first memory address using the first controller. In response to the processing request, the target instruction is written to the second memory address via the second controller; Based on the target instruction, the first controller retrieves the target data of the target event from the queue of events to be processed, and writes the target data into the second memory address; Based on the target data, the target action is executed through the second controller.
2. The event handling method as described in claim 1, wherein the first controller and the second controller are connected via an enhanced serial peripheral interface; Obtaining the first memory address and the second memory address that can be accessed by the first controller and the second controller respectively includes: The first memory address and the second memory address are obtained through memory mapping based on the enhanced serial peripheral interface.
3. The event handling method as described in claim 2, wherein the first memory address includes at least a first register bit, the first register bit having a first state representing an event to be processed and a second state representing no event to be processed; Using the first controller to modify the state of the first memory address to trigger the processing request corresponding to the target event includes: The first controller sets the first register bit of the first memory address to a first state to generate a processing request corresponding to the target event; The processing request is transmitted via a virtual channel of the enhanced serial peripheral interface.
4. The event handling method as described in claim 3, in response to the processing request, writing a target instruction for querying the target event to the second memory address via a second controller, comprising: Determine whether the first identifier of the first memory address is in the first state; If the first identifier of the first memory address is in the first state, in response to the processing request, the target instruction is written to the second memory address through the second controller.
5. The event handling method as described in claim 4, wherein the first memory address further includes a second register bit and a third register bit, the second register bit having a first state indicating that information has been stored at the second memory address and a second state indicating that no information has been stored at the second memory address; the third register bit having a first state indicating that the information stored at the second memory address is an instruction and a second state indicating that the information stored at the second memory address is data; When the target instruction is written to the second memory address, the second controller sets the second register bit and the third register bit of the first memory address to the first state respectively.
6. An event processing method as described in claim 5, comprising, based on the target instruction, using a first controller to obtain target data of the target event from the queue of events to be processed, and writing the target data into the second memory address, comprising: The first controller is used to read the first memory address in a loop and determine whether the third register bit of the first memory address is in the first state; If the third register bit is confirmed to be in the first state, the target instruction is read, and the second register bit and the third register bit of the first memory address are set to the second state respectively; The target data of the target event is retrieved according to the target instruction, the target data is written to the second memory address, and the fourth register bit of the first memory address is set to the first state. The fourth register bit being set to the first state indicates that the target data has been stored in the second memory address.
7. The event handling method as described in claim 6, further comprising: When the target data is written to the second memory address, the first register bit of the first memory address is set to the second state.
8. An event handling method as described in claim 6, wherein a target action is executed via a second controller based on the target data, comprising: Determine whether the first register bit of the first memory address is set to the second state, and whether the fourth register bit is set to the first state; When the first register bit is set to the second state and the fourth register bit is set to the first state, the target data is read from the second memory address.
9. An electronic device comprising a first controller, a second controller, a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor executes the computer program to implement an event handling method for an ARM platform, the event handling method being used on an ARM platform including at least the first controller and the second controller, the event handling method comprising: Obtain a first memory address and a second memory address that can be accessed by the first controller and the second controller respectively. The first memory address is used to represent the status port and the second memory address is used to represent the data port. In response to a target event, the target data of the target event is stored in the queue of events to be processed, and the processing request corresponding to the target event is triggered by modifying the state of the first memory address using the first controller. In response to the processing request, the target instruction is written to the second memory address via the second controller; Based on the target instruction, the first controller retrieves the target data of the target event from the queue of events to be processed, and writes the target data into the second memory address; Based on the target data, the target action is executed through the second controller.
10. A storage medium storing a computer program, wherein a processor executes the computer program to implement an event handling method for an ARM platform, the ARM platform including at least a first controller and a second controller, the event handling method comprising: Obtain a first memory address and a second memory address that can be accessed by the first controller and the second controller respectively. The first memory address is used to represent the status port and the second memory address is used to represent the data port. In response to a target event, the target data of the target event is stored in the queue of events to be processed, and the processing request corresponding to the target event is triggered by modifying the state of the first memory address using the first controller. In response to the processing request, the target instruction is written to the second memory address via the second controller; Based on the target instruction, the first controller retrieves the target data of the target event from the queue of events to be processed, and writes the target data into the second memory address; Based on the target data, the target action is executed through the second controller.