Processor supporting merging of memory access requests, data memory access method, medium and equipment

Abstract

The invention discloses a processor supporting merging of memory access requests, a data memory access method, a medium and equipment. The processor supporting the merging of the memory access requests comprises a calculation circuit which is used for generating a plurality of memory access requests; the request merging circuit is used for determining respective request parameters of the plurality of memory access requests, and the request parameters are used for controlling memory access operation; based on the respective request parameters of the plurality of memory access requests, determining different memory access requests meeting a preset merging condition in the plurality of memory access requests; merging different memory access requests meeting a preset merging condition to obtain a merged memory access request; and the cache circuit is used for processing the merged memory access request so as to complete memory access operations corresponding to different memory access requests meeting a preset merging condition. According to the embodiment of the invention, the processing efficiency of the memory access request can be improved.

Description

Technical Field

[0001] This disclosure relates to data access technologies, and in particular to a processor, data access method, medium, and apparatus that support the merging of access requests. Background Technology

[0002] As is understandable, the processor is the core hardware in a computer system, responsible for executing instructions, processing data, and controlling other hardware in the computer system.

[0003] In some cases, the processor generates multiple memory access requests, which the processor needs to process. How to improve the processor's processing efficiency for these memory access requests is a technical problem worthy of attention for those skilled in the art. Summary of the Invention

[0004] To address the aforementioned technical problems, this disclosure provides a processor, data memory access method, medium, and device that support memory access request merging.

[0005] According to one aspect of the present disclosure, a processor supporting memory access request merging is provided, comprising:

[0006] A computing circuit, wherein the computing circuit is used to generate multiple memory access requests;

[0007] A request merging circuit is used to determine the request parameters of each of the multiple memory access requests, the request parameters being parameters used to control the memory access operation; based on the request parameters of each of the multiple memory access requests, different memory access requests that meet preset merging conditions are determined; and the different memory access requests that meet the preset merging conditions are merged to obtain a merged memory access request.

[0008] A cache circuit is used to process the merged memory access request to complete the memory access operations corresponding to the different memory access requests that meet the preset merging conditions.

[0009] According to another aspect of the present disclosure, a data memory access method supporting memory access request merging is provided, including:

[0010] Multiple memory access requests are generated by the computing circuitry in the processor.

[0011] The request merging circuit in the processor performs the following operations: determining the request parameters of each of the multiple memory access requests, the request parameters being parameters used to control the memory access operation; based on the request parameters of each of the multiple memory access requests, determining the different memory access requests among the multiple memory access requests that meet the preset merging conditions; merging the different memory access requests that meet the preset merging conditions to obtain a merged memory access request.

[0012] The processor's cache circuitry processes the merged memory access requests to complete the memory access operations corresponding to the different memory access requests that meet the preset merging conditions.

[0013] According to another aspect of the present disclosure, a computer-readable storage medium is provided, the storage medium storing a computer program that is executed by a processor to perform the above-described data access method.

[0014] According to another aspect of the present disclosure, an electronic device is provided, the electronic device comprising:

[0015] processor;

[0016] Memory used to store the processor's executable instructions;

[0017] The processor is configured to read the executable instructions from the memory and execute the instructions to implement the data memory access method described above.

[0018] According to another aspect of the present disclosure, a computer program product is provided that executes the above-described data memory access method when instructions in the computer program product are executed by a processor.

[0019] Based on the processor, data memory access method, medium, device, and program product supporting memory access request merging provided in the above embodiments of this disclosure, when the computing circuit generates multiple memory access requests, the request merging circuit can merge different memory access requests that meet preset merging conditions based on the request parameters of each of the multiple memory access requests to obtain a merged memory access request. The cache circuit processes the merged memory access request, which is equivalent to processing the different memory access requests that meet the preset merging conditions, thereby completing the memory access operations corresponding to the different memory access requests that meet the preset merging conditions. In this way, through the coordinated work of the computing circuit, the request merging circuit, and the cache circuit, more than one memory access request (e.g., different memory access requests that meet the preset merging conditions) can be merged into one memory access request (e.g., a merged memory access request) for processing, without having to perform a complete pipeline operation for each memory access request generated by the computing circuit. Therefore, it is beneficial to shorten the time required to process memory access requests and improve the processing efficiency of memory access requests. Attached Figure Description

[0020] Figure 1 This is one of the schematic diagrams of a processor that supports memory access request merging, provided by some exemplary embodiments of this disclosure.

[0021] Figure 2 This is a second schematic diagram of the structure of a processor that supports memory access request merging, provided by some exemplary embodiments of this disclosure.

[0022] Figure 3 This is the third schematic diagram of a processor supporting memory access request merging, provided by some exemplary embodiments of this disclosure.

[0023] Figure 4-1 This is the fourth schematic diagram of a processor supporting memory access request merging, provided by some exemplary embodiments of this disclosure.

[0024] Figure 4-2 This is the fifth schematic diagram of a processor supporting memory access request merging, provided by some exemplary embodiments of this disclosure.

[0025] Figure 5 This is one of the flowcharts illustrating a data access method that supports memory access request merging, provided by some exemplary embodiments of this disclosure.

[0026] Figure 6 This is the second flowchart illustrating a data access method that supports memory access request merging, provided by some exemplary embodiments of this disclosure.

[0027] Figure 7 This is the third flowchart illustrating a data access method that supports memory access request merging, provided by some exemplary embodiments of this disclosure.

[0028] Figure 8 This is the fourth flowchart illustrating a data access method that supports memory access request merging, provided by some exemplary embodiments of this disclosure.

[0029] Figure 9 This is the fifth flowchart illustrating a data access method that supports memory access request merging, provided by some exemplary embodiments of this disclosure.

[0030] Figure 10 This is the sixth flowchart illustrating a data access method that supports memory access request merging, provided by some exemplary embodiments of this disclosure.

[0031] Figure 11 This is the seventh flowchart illustrating a data access method that supports memory access request merging, provided by some exemplary embodiments of this disclosure.

[0032] Figure 12 This is the eighth flowchart illustrating a data access method that supports memory access request merging, provided by some exemplary embodiments of this disclosure.

[0033] Figure 13 This is the ninth flowchart illustrating a data access method supporting memory access request merging, provided by some exemplary embodiments of this disclosure.

[0034] Figure 14 This is the tenth flowchart illustrating a data access method that supports memory access request merging, provided by some exemplary embodiments of this disclosure.

[0035] Figure 15 This is a schematic diagram of the structure of an electronic device provided by some exemplary embodiments of this disclosure. Detailed Implementation

[0036] To explain this disclosure, exemplary embodiments of the disclosure will now be described in detail with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of the disclosure, and not all of them. It should be understood that the disclosure is not limited to exemplary embodiments.

[0037] It should be noted that, unless otherwise specifically stated, the relative arrangement, numerical expressions, and values ​​of the components and steps set forth in these embodiments do not limit the scope of this disclosure.

[0038] Application Overview

[0039] Currently, processors have a wide range of applications. For example, processors can be used in many fields such as mobile communications, consumer electronics, autonomous driving, robotics, cloud computing, and smart wearables.

[0040] In some cases, the processor generates multiple memory access requests, which it needs to process. In related technologies, the processor typically processes these memory access requests in a pipelined manner. Pipelining can be understood as a technique that decomposes a task into multiple stages, allowing different stages of different tasks to execute in parallel. For example, if a memory access task is decomposed into four stages—stage 1, stage 2, stage 3, and stage 4—and the processor generates three memory access requests, then each memory access request needs to be processed through these four stages sequentially. Furthermore, while processing the first memory access request in stage 3, the second memory access request can be processed in stage 2, and the third memory access request can be processed in stage 1.

[0041] In the process of realizing this disclosure, the inventors discovered that even if the processor processes these memory access requests in a pipeline manner, the processing efficiency is still not high enough to meet actual needs. Therefore, it is necessary to take some measures to improve the processor's processing efficiency for memory access requests.

[0042] Exemplary System

[0043] In the embodiments of this disclosure, when the processor generates multiple memory access requests, it can determine whether there are any memory access requests that can be merged. If there are mergeable memory access requests, the processor can merge the mergeable memory access requests to obtain a merged memory access request, and then process the merged memory access request. In this way, by merging memory access requests, it is not necessary to perform a complete pipeline operation on each memory access request generated by the processor. Therefore, it is beneficial to shorten the time required to process memory access requests, improve the processing efficiency of memory access requests, and reduce power consumption.

[0044] Exemplary circuit

[0045] Embodiments of this disclosure provide a processor that supports memory request merging. For ease of explanation, the processor that supports memory request merging will be referred to hereafter as the target processor.

[0046] Optionally, a memory access request can be a request for reading or writing data. In one scenario, the memory access request is a read request, the request type is a read request, and the corresponding memory access operation is a read operation. In another scenario, the memory access request is a write request, the request type is a write request, and the corresponding memory access operation is a write operation. Here, a read request can also be called a load request, and a write request can also be called a store request.

[0047] Optionally, the target processor may be, but is not limited to, a central processing unit (CPU), a graphics processing unit (GPU), or a digital signal processor (DSP). If the target processor is applied in the field of intelligent driving, it can be designed into an intelligent driving chip or an intelligent cockpit chip. If the target processor is applied in the field of robotics, it can be designed into an image processing chip.

[0048] Optionally, the target processor's support for memory access request merging can be understood as follows: the target processor can merge more than one memory access request into one memory access request, and process the merged memory access request, thereby achieving the processing of the original more than one memory access request.

[0049] like Figure 1 , Figure 2 As shown, the target processor may include:

[0050] Computational circuit 10 is used to generate multiple memory access requests;

[0051] The request merging circuit 20 is used to determine the request parameters of each of the multiple memory access requests. The request parameters are parameters used to control the memory access operation. Based on the request parameters of each of the multiple memory access requests, the circuit determines the different memory access requests that meet the preset merging conditions. The circuit merges the different memory access requests that meet the preset merging conditions to obtain the merged memory access request.

[0052] The cache circuit 30 is used to process merged memory access requests to complete the memory access operations corresponding to different memory access requests that meet the preset merging conditions.

[0053] Optionally, the computing circuit 10 may be a circuit responsible for performing arithmetic operations, logical operations, etc. The computing circuit 10 may be, for example, an arithmetic logic unit (ALU), and the arithmetic operations performed by the computing circuit 10 may include, but are not limited to, addition, subtraction, multiplication, and division operations, and the logical operations performed by the computing circuit 10 may include, but are not limited to, AND, OR, and NOT operations.

[0054] Optionally, the request merging circuit 20 can be a circuit responsible for merging memory access requests, for example, it can be responsible for merging more than one memory access request into one memory access request. The request merging circuit 20 can be electrically connected to the computing circuit 10.

[0055] Optionally, the cache circuit 30 may be a circuit responsible for caching data and instructions, as well as handling memory access requests. The cache circuit 30 may be electrically connected to the request merging circuit 20. The cache circuit 30 may also be electrically connected to the downstream memory. The downstream memory may be, for example, a... Figure 2 The main memory 40 shown is, as an example, a Double Data Rate Synchronous Dynamic Random Access Memory (DDR). It should be noted that the computing circuit 10 can preferentially retrieve the required data and instructions from the cache circuit 30. If the required data and instructions cannot be retrieved from the cache circuit 30, then the required data and instructions are retrieved from the next-level memory. This facilitates faster retrieval of the required data and instructions, reduces latency, lowers power consumption, and improves performance.

[0056] The computing circuit 10 can generate multiple memory access requests. For example, if the target processor is a multi-threaded CPU, the computing circuit 10 in the multi-threaded CPU can concurrently generate multiple memory access requests. As another example, if the target processor is a general-purpose computing on graphics processing units (GPGPU), the computing circuit 10 in the GPGPU can concurrently generate multiple memory access requests. The multiple memory access requests generated by the computing circuit 10 can be represented as N memory access requests, and the computing circuit 10 can send all N memory access requests to the request merging circuit 20; where N can be an integer greater than or equal to 2. Each of the N memory access requests can carry request parameters, which are parameters used to control the memory access operation, such as the operation type, operation address, number of bytes operated on, etc.

[0057] The request merging circuit 20 can receive N memory access requests from the computing circuit 10 and extract request parameters from each of the N memory access requests to obtain the request parameters for each of the N memory access requests. The request merging circuit 20 can be pre-configured with preset merging conditions, which can be conditions used to determine whether any two memory access requests can be merged. For example, a preset merging condition could be that a specific parameter in the request parameters is the same. Based on the request parameters of each of the N memory access requests, the request merging circuit 20 can determine the different memory access requests among the N memory access requests that satisfy the preset merging conditions. For example, there can be M different memory access requests among the N memory access requests that satisfy the preset merging conditions; where M can be an integer greater than or equal to 2 and less than or equal to N. The request merging circuit 20 can merge the M memory access requests among the N memory access requests that satisfy the preset merging conditions into one memory access request, and this merged memory access request can be used as the merged memory access request. The request merging circuit 20 can send merged memory access requests to the cache circuit 30 without sending all M memory access requests that meet the preset merging conditions out of N memory access requests to the cache circuit 30.

[0058] The cache circuit 30 can receive merged memory access requests from the request merging circuit 20. Similar to the N memory access requests mentioned above, the merged memory access request can also carry request parameters. The cache circuit 30 can process the merged memory access request based on the request parameters carried by the merged memory access request. Since the merged memory access request is obtained by merging the above M memory access requests, processing the merged memory access request is equivalent to processing the above M memory access requests, thereby completing the memory access operations corresponding to the above M memory access requests respectively.

[0059] In the embodiments of this disclosure, when the computing circuit 10 generates multiple memory access requests, the request merging circuit 20 can merge different memory access requests that meet preset merging conditions based on the request parameters of each of the multiple memory access requests to obtain a merged memory access request. The cache circuit 30 processes the merged memory access request, which is equivalent to processing the different memory access requests that meet the preset merging conditions, thereby completing the memory access operations corresponding to the different memory access requests that meet the preset merging conditions. In this way, through the collaborative work of the computing circuit 10, the request merging circuit 20, and the cache circuit 30, more than one memory access request (e.g., different memory access requests that meet the preset merging conditions) can be merged into one memory access request (e.g., a merged memory access request) for processing, without having to perform a complete pipeline operation on each memory access request generated by the computing circuit 10. Therefore, it is beneficial to shorten the time required to process memory access requests and improve the processing efficiency of memory access requests.

[0060] It should be noted that, due to the merging of memory access requests, the number of memory access requests transmitted to the cache circuit 30 for processing is reduced, which helps to reduce the number of accesses to the cache circuit 30, thereby saving power consumption.

[0061] In some optional examples, the request parameters include: a request type and a request access address. The request type in the request parameters controls the type of memory access operation. If the request type in the request parameters is a read request type, the memory access operation type is a read operation; that is, the memory access operation is a read operation. If the request type in the request parameters is a write request type, the memory access operation type is a write operation. The request access address in the request parameters controls the address of the memory access operation. If the request access address in the request parameters is a read address, the memory access operation address is that read address; if the request access address in the request parameters is a write address, the memory access operation address is that write address.

[0062] Request merging circuit 20 is used to determine, based on the request parameters of each of the multiple memory access requests, different memory access requests that meet preset merging conditions, including:

[0063] Request merging circuit 20 is used to determine different memory access requests that meet preset merging conditions among multiple memory access requests based on their respective request types and request access addresses.

[0064] The preset merging conditions include: the request type is the same and the request access address is the same.

[0065] Optionally, upon receiving N memory access requests from the computing circuit 10, the request merging circuit 20 can determine the request type and the request access address of each of the N memory access requests. Based on this, the request merging circuit 20 can perform a consistency comparison on the request type of each pair of memory access requests and on the request access address of each pair of memory access requests, thereby determining memory access requests with the same request type and the same request access address. In this way, different memory access requests that meet the preset merging conditions among the N memory access requests can be identified.

[0066] In an optional example, the N access requests are 5 memory access requests. All 5 memory access requests are read requests, and all 5 memory access requests have the same access address, Address1. These 5 memory access requests can be considered as different memory access requests among the N memory access requests that meet the preset merging conditions.

[0067] In another optional example, N memory access requests are 8 memory access requests. Among these 8 memory access requests, 6 of them are read requests and their access addresses are all Address2. The access addresses of the other 2 memory access requests are Address3 and Address4, respectively. These 6 memory access requests can be considered as different memory access requests that meet the preset merging conditions among the N memory access requests.

[0068] In another optional example, N memory access requests are 8 memory access requests. Among these 8 memory access requests, 3 memory access requests are all read requests and their access addresses are all Address5. The other 5 memory access requests are all write requests and their access addresses are all Address6. These 3 memory access requests can be considered as different memory access requests that meet the preset merging conditions among the N memory access requests. These 5 memory access requests can also be considered as different memory access requests that meet the preset merging conditions among the N memory access requests.

[0069] As can be seen, for multiple memory access requests from computing circuit 10, by comparing the consistency of request types and the consistency of request access addresses, request merging circuit 20 can efficiently and reliably determine different memory access requests that meet the preset merging conditions.

[0070] In some embodiments, the request parameters may further include: a cache allocation policy, and the preset merging conditions may include: the same request type, the same request access address, and the same cache allocation policy.

[0071] It should be noted that the way the request merging circuit 20 obtains the merged memory access request can differ when the different memory access requests that meet the preset merging conditions are all read request types (hereinafter referred to as Case 1) and when they are all write request types (hereinafter referred to as Case 2). The way the cache circuit 30 processes the merged memory access request can also differ.

[0072] The following section will elaborate on scenario one.

[0073] In some optional embodiments of this disclosure, the request merging circuit 20 is used to merge different memory access requests that meet preset merging conditions to obtain merged memory access requests, including:

[0074] The request merging circuit 20 is used to respond to different access requests that meet the preset merging conditions, each of which is a read request type, to select a target memory access request from the different memory access requests that meet the preset merging conditions; and to add a tag information to the target memory access request to indicate that other memory access requests are merged into the target memory access request, thereby obtaining a merged memory access request.

[0075] Other memory access requests refer to memory access requests other than the target memory access request among different memory access requests that meet the preset merging conditions.

[0076] Optionally, the request merging circuit 20 may be pre-configured with preset selection rules. If the different access requests that meet the preset merging conditions are all read request types, the request merging circuit 20 can select one memory access request as the target memory access request from the different access requests that meet the preset merging conditions according to the preset selection rules. The preset selection rules will be illustrated later and will not be elaborated here. In addition, among the different memory access requests that meet the preset merging conditions, any memory access request other than the target memory access request can be considered as another memory access request. Therefore, the number of other memory access requests may be one or more. The request merging circuit 20 can add marking information to the target memory access request to indicate that other memory access requests are merged into the target memory access request. The target memory access request with the marked information can be considered as the merging result of the target memory access request and other memory access requests, and this merging result can be used as the merged memory access request. In this way, in the process of obtaining the merged memory access request, the target memory access request can be considered as the merger, and the other memory access requests can be considered as the merged objects.

[0077] In an optional example, the N memory access requests generated by the computing circuit 10 are 8 memory access requests, namely memory access request Q1, memory access request Q2, memory access request Q3, memory access request Q4, memory access request Q5, memory access request Q6, memory access request Q7, and memory access request Q8. Memory access requests Q1 to Q6 are all read requests, and their access addresses are all Address2. Memory access request Q7 has an access address of Address3, and memory access request Q8 has an access address of Address4. Therefore, different access requests satisfying the preset merging conditions can include memory access requests Q1 to Q6. The request merging circuit 20 can select one memory access request from Q1 to Q6 as the target memory access request. Assuming the target memory access request is memory access request Q1, then memory access requests Q2, Q3, Q4, Q5, and Q6 can each be treated as other memory access requests. The tagging information can then include tag bits corresponding to memory access requests Q1 through Q8; specifically, the tag bits corresponding to memory access requests Q1 through Q6 can be set to 1, and the tag bits corresponding to memory access requests Q7 through Q8 can be set to zero. By adding tagging information to memory access request Q1, merged memory access requests can be obtained. Since the markers for memory access requests Q1 to Q6 are set to 1 and the markers for memory access requests Q7 to Q8 are set to 0 in the merged memory access request information, it indicates that the merged memory access request is formed by merging memory access requests Q1 to Q6. Since the merged memory access request is derived from memory access request Q1, it indicates that among memory access requests Q1 to Q6, memory access request Q1 is the merger, and memory access requests Q2 to Q6 are all merged. That is, memory access requests Q2 to Q6 are merged into memory access request Q1.

[0078] By adding a marker to the target memory access request to indicate that other memory access requests are merged into the target memory access request, the request merging circuit 20 can efficiently and reliably obtain the merged memory access request. The request merging circuit 20 can send the merged memory access request to the cache circuit 30 for processing. This is equivalent to making the merged party (i.e., other memory access requests) attached to the merger (i.e., the target memory access request) and passed to the subsequent stage, without having to pass each memory access request generated by the computing circuit 10 to the subsequent stage separately. This helps to shorten the time required to process memory access requests, improve the processing efficiency of memory access requests, and reduce power consumption.

[0079] In some optional embodiments of this disclosure, the cache circuit 30 is used to process merged memory access requests to complete the memory access operations corresponding to different memory access requests that meet preset merging conditions, including:

[0080] The cache circuit 30 is used to obtain the target access data corresponding to the request access address of the merged memory access request from either the cache space of the cache circuit 30 or the storage space of the main memory 40; based on the target access data and the tag information in the merged memory access request, it generates a first read feedback corresponding to the target memory access request and a second read feedback corresponding to other memory access requests; and returns the first read feedback and the second read feedback to the computing circuit 10.

[0081] Optionally, the cache space of cache circuit 30 refers to the space in cache circuit 30 used for caching data. The storage space of main memory 40 refers to the space in main memory 40 used for storing data.

[0082] Optionally, in response to receiving a merge memory access request from the merge request merging circuit 20, the cache circuit 30 can extract the request access address (which is a shared request access address of different memory access requests that meet preset merging conditions) from the merge memory access request, and read the target access data corresponding to the request access address of the merge memory access request from either the cache space of the cache circuit 30 or the storage space of the main memory 40. Here, the cache circuit 30 can first determine whether there is hit data in its cache space for the request access address of the merge memory access request. If there is hit data in the cache space of the cache circuit 30, the hit data in the cache space of the cache circuit 30 can be read out as the target access data. If there is no hit data in the cache space of the cache circuit 30, the target access data can be read out from the storage space of the main memory 40 through interaction with the main memory 40 for the request access address of the merge memory access request. For example, if the cache space of the cache circuit 30 does not contain the data to be hit, the cache circuit 30 can send a read request to the main memory 40 for the requested access address of the merged memory access request, and receive the read data returned by the main memory 40 in response to the read request. The read data is the target access data read from the storage space of the main memory 40.

[0083] In response to reading target access data from the cache space of cache circuit 30 or from the storage space of main memory 40, cache circuit 30 can generate a first read feedback corresponding to the target memory access request and a second read feedback corresponding to other memory access requests based on the target access data and the tag information in the merged memory access request.

[0084] Here, the first read feedback corresponding to the target memory access request may include: the target access data. In some embodiments, the first read feedback corresponding to the target memory access request may further include: a status flag indicating whether the target access data is specifically read from the cache space of the cache circuit 30 or from the storage space of the main memory 40. For example, the status flag is Hi, indicating that the target access data is specifically read from the cache space of the cache circuit 30; the status flag is Miss, indicating that the target access data is specifically read from the storage space of the main memory 40.

[0085] Here, the second read feedback corresponding to other memory access requests may include: the target access data. In some embodiments, the first read feedback corresponding to other memory access requests may further include: a status flag indicating whether the target access data is specifically read from the cache space of the cache circuit 30 or from the storage space of the main memory 40.

[0086] Optionally, the cache circuit 30 can be electrically connected to the computing circuit 10. Through this electrical connection, the cache circuit 30 can send both the first and second read feedbacks to the computing circuit 10, and correspondingly, the computing circuit 10 can receive both the first and second read feedbacks. The computing circuit 10 can extract the target access data from the first and second read feedbacks respectively, and store the target access data in a register. The computing circuit 10 can then use the target access data. For example, the computing circuit 10 can perform arithmetic operations on the target access data extracted from the first read feedback, and it can perform logical operations on the target access data extracted from the second read feedback.

[0087] In this way, the cache circuit 30 can efficiently and reliably obtain the target access data corresponding to the requested access address of the merged memory access request from either the cache space of the cache circuit 30 or the storage space of the main memory 40. Based on the marking information in the merged memory access request, it can be deduced that the merged memory access request is formed by merging the target memory access request and other memory access requests. Therefore, the target access data can be used to generate the read feedback corresponding to the target memory access request and other memory access requests respectively, and the generated read feedback is returned to the computing circuit 10, thereby enabling the efficient and reliable completion of the read operations corresponding to the target memory access request and other memory access requests respectively.

[0088] The following section will elaborate on scenario two.

[0089] In some optional embodiments of this disclosure, the request merging circuit 20 is used to merge different memory access requests that meet preset merging conditions to obtain merged memory access requests, including:

[0090] The request merging circuit 20 is used to respond to different access requests that meet preset merging conditions, each of which is a write request type. From the different memory access requests that meet the preset merging conditions, it selects a target memory access request; based on the target memory access request, it obtains first write data and the first mask information corresponding to the first write data; based on other memory access requests, it obtains second write data and the second mask information corresponding to the second write data; based on the first write data, the first mask information, the second write data, and the second mask information, it merges the other memory access requests into the target memory access request to obtain a merged memory access request.

[0091] Other memory access requests refer to memory access requests other than the target memory access request among different memory access requests that meet the preset merging conditions; the bit width of any write data is the register bit width supported by the target processor, and the mask information corresponding to any write data is used to indicate the valid bit width segment and the invalid bit width segment in the bit width of the write data.

[0092] Optionally, the register width supported by the target processor may be, for example, 4 bytes, 8 bytes, etc.

[0093] Optionally, the request merging circuit 20 may be pre-configured with preset selection rules. If the different access requests that meet the preset merging conditions are all write request types, the request merging circuit 20 can select one memory access request as the target memory access request from the different access requests that meet the preset merging conditions according to the preset selection rules. The preset selection rules will be illustrated later and will not be elaborated here. In addition, among the different memory access requests that meet the preset merging conditions, any memory access request other than the target memory access request can be considered as another memory access request. Therefore, the number of other memory access requests may be one or more.

[0094] In response to identifying a target memory access request, the request merging circuit 20 can extract first write data and corresponding first mask information from the target memory access request. The first write data is the data that the computing circuit 10 needs to write through the target memory access request, and the first mask information indicates the valid and invalid bit width segments in the bit width of the first write data. For example, if the target processor supports a register bit width of 4 bytes, then the bit width of the first write data is 4 bytes, and the first mask information could be 0011, indicating that the first byte to the second byte of the first write data is an invalid bit width segment, and the third byte to the fourth byte is a valid bit width segment. As another example, if the target processor supports a register bit width of 4 bytes, then the bit width of the first write data is 4 bytes, and the first mask information could be 0101, indicating that the first and third bytes of the first write data are invalid bit width segments, and the second and fourth bytes are valid bit width segments. Similarly, the request merging circuit 20 can extract the second write data and the corresponding second mask information from other memory access requests. The second write data is the data that the calculation circuit 10 needs to write through other memory access requests, and the second mask information indicates the valid and invalid bit width segments in the bit width of the second write data. The request merging circuit 20 can merge other memory access requests into the target memory access request based on the first write data, the first mask information, the second write data, and the second mask information to obtain a merged memory access request. For example, the request merging circuit 20 can update the target memory access request based on the first write data, the first mask information, the second write data, and the second mask information to obtain a merged result of the target memory access request and other memory access requests, which can then be used as the merged memory access request.

[0095] Optionally, the request merging circuit 20 is used to merge other memory access requests into a target memory access request based on the first write data, the first mask information, the second write data, and the second mask information, to obtain a merged memory access request, including:

[0096] The request merging circuit 20 is used to perform an OR operation on the first write data and the second write data to obtain the third write data; to perform an OR operation on the first mask information and the second mask information to obtain the third mask information; to update the first write data and the first mask information in the target memory access request to the third write data and the third mask information respectively; and to add marker information to the target memory access request to indicate that other memory access requests are merged into the target memory access request, thereby obtaining the merged memory access request.

[0097] Optionally, the request merging circuit 20 can support OR operation logic. The request merging circuit 20 can use the first written data as one input to the OR operation logic and the second written data as another input. By running the OR operation logic, the third written data can be obtained. Similarly, the request merging circuit 20 can use the first mask information as one input to the OR operation logic and the second mask information as another input. By running the OR operation logic, the third mask information can be obtained. The request merging circuit 20 can update the first written data in the target memory access request to the third written data, update the first mask information in the target memory access request to the third mask information, and add marker information to the target memory access request to indicate that other memory access requests are merged into the target memory access request. The composition of the marker information is as described above for Case 1 and will not be repeated here. It should be noted that the target memory access request, in which the first written data and the first mask information have been updated and the marker information has been added, can be considered as the merging result of the target memory access request and other memory access requests. This merging result can be used as the merged memory access request. Thus, in the process of receiving merge access requests, the target access request can be considered the merger, and other access requests can be considered the merged.

[0098] In an optional example, the first written data is 4 bytes, specifically represented as 00AB. The first mask information is 0011, indicating that the first 2 bytes of the 4 bytes are invalid bit-width segments, and the last 2 bytes are valid bit-width segments. The second written data is also 4 bytes, specifically represented as CD00. The second mask information is 1100, indicating that the first 2 bytes of the 4 bytes are valid bit-width segments, and the last 2 bytes are invalid bit-width segments. The third written data, obtained by performing an OR operation on the first and second written data, can be represented as CDAB. The third mask information, obtained by performing an OR operation on the first and second mask information, can be represented as 1111. Clearly, the third mask information indicates that the first to fourth bytes of the third written data are all valid bit-width segments. The request merging circuit 20 can update the first write data (i.e., 00AB) and the first mask information (i.e., 0011) in the target memory access request to the third write data (i.e., CDAB) and the third mask information (i.e., 1111), respectively, and add tag information to the target memory access request to indicate that other memory access requests are merged into the target memory access request, thereby obtaining the merged memory access request.

[0099] In this way, based on the first write data, the first mask information, the second write data, and the second mask information, the third write data and the third mask information can be obtained efficiently and quickly through OR operation. This information can be used to update the first write data and the first mask information in the target memory access request. Combined with the addition of the tag information, the merged memory access request can be obtained efficiently and reliably. The request merging circuit 20 can send the merged memory access request to the cache circuit 30 for processing. This is equivalent to making the merged party (i.e., other memory access requests) attached to the merger (i.e., the target memory access request) and passed to the subsequent stage, without having to pass each memory access request generated by the computing circuit 10 to the subsequent stage separately. This helps to shorten the time required to process the memory access request, improve the processing efficiency of the memory access request, and reduce power consumption.

[0100] In some optional embodiments of this disclosure, the cache circuit 30 is used to process merged memory access requests to complete the memory access operations corresponding to different memory access requests that meet preset merging conditions, including:

[0101] The cache circuit 30 is used to obtain the target access data corresponding to the request access address of the merged memory access request from either the cache space of the cache circuit 30 or the storage space of the main memory 40; based on the third read data and the third mask information in the merged memory access request, update the data in the effective bit width segment of the target access data to obtain the update result data corresponding to the target access data; cache the update result data in the cache space, and generate the first write feedback corresponding to the target memory access request and the second write feedback corresponding to other memory access requests based on the tag information in the merged memory access request; and return the first write feedback and the second write feedback to the computing circuit.

[0102] Optionally, the specific method for obtaining the target access data corresponding to the requested access address of the merged memory access request from either the cache space of the cache circuit 30 or the storage space of the main memory 40 can be referred to the relevant introduction for Case 1 above, and will not be repeated here.

[0103] In response to reading the target access data from the cache space of the cache circuit 30 or from the storage space of the main memory 40, the cache circuit 30 can update the data in the valid bit width segment of the target access data based on the third read data and the third mask information in the merged memory access request, while keeping the data in the invalid bit width segment of the target access data unchanged, thereby obtaining the updated result data corresponding to the target access data.

[0104] In an optional example, the third write data is 4 bytes, specifically represented as CDAB, and the third mask information is 1111, indicating that the first to fourth bytes in the third write data are all valid bit widths. The target access data is 4 bytes. Based on the third write data and the third mask information, the cache circuit 30 can update the first byte in the target access data to C, the second byte in the target access data to D, the third byte in the target access data to A, and the fourth byte in the target access data to B, thereby obtaining the update result data corresponding to the target access data.

[0105] In response to receiving the updated result data corresponding to the target access data, the caching circuit 30 can cache the updated result data in its cache space, for example, caching the updated result data in the cache space in the form of a cache line. The caching circuit 30 can also generate a first write feedback corresponding to the target memory access request and second write feedback corresponding to other memory access requests based on the tag information in the merged memory access requests. The first write feedback corresponding to the target memory access request may include a write success notification. Similarly, the second write feedback corresponding to other memory access requests may include a write success notification.

[0106] Optionally, the cache circuit 30 can be electrically connected to the computing circuit 10. Through this electrical connection, the cache circuit 30 can send both the first write feedback and the second write feedback to the computing circuit 10. Correspondingly, the computing circuit 10 can receive both the first write feedback and the second write feedback. The computing circuit 10 can determine that the write operation for the target memory access request has ended, and that the write operation for other memory access requests has also ended.

[0107] In this way, the cache circuit 30 can efficiently and reliably obtain the target access data corresponding to the requested access address of the merged memory access request from either the cache space of the cache circuit 30 or the storage space of the main memory 40. The third read data and the third mask information in the merged memory access request can provide a valid reference for updating the target access data, thereby enabling efficient and quick acquisition of the update result data corresponding to the target access data. In addition, based on the marking information in the merged memory access request, it can be deduced that the merged memory access request is formed by merging the target memory access request and other memory access requests. Therefore, write feedback corresponding to the target memory access request and other memory access requests can be generated separately and returned to the computing circuit 10, thereby enabling efficient and reliable completion of the write operations corresponding to the target memory access request and other memory access requests respectively.

[0108] It should be noted that, for scenario two above, when merging the target memory access request with other memory access requests, OR operations can be omitted. Instead, the second write data, the second mask information, and the tag information can all be added to the target memory access request to obtain the merged memory access request. Accordingly, upon receiving the merged memory access request from the request merging circuit 20 and obtaining the target memory access data, the cache circuit 30 can first update the target memory access data based on the first write data and the first mask information in the merged memory access request to obtain intermediate updated data. Then, based on the second write data and the second mask information in the merged memory access request, it can update the target memory access data again to obtain the updated result data.

[0109] In some optional examples, such as Figure 3 , Figure 4-1 , Figure 4-2 As shown, the request merging circuit 20 may include: a plurality of interfaces 201, the request merging circuit 20 being used to receive a plurality of memory access requests from the computing circuit 10 through the plurality of interfaces 201;

[0110] The request merging circuit 20 is used to select a target memory access request from different memory access requests that meet preset merging conditions, including:

[0111] The request merging circuit 20 is used to determine the preset priority relationship between multiple interfaces 201; according to the preset priority relationship, it selects the target interface from the interfaces 201 corresponding to different memory access requests that meet the preset merging conditions; and determines the memory access request corresponding to the target interface as the target memory access request.

[0112] Optionally, the request merging circuit 20 may include multiple interfaces 201, for example, N interfaces 201. The request merging circuit 20 can receive N memory access requests from the computing circuit 10 through the N interfaces 201; wherein, the N memory access requests correspond one-to-one with the N interfaces 201.

[0113] Optionally, the request merging circuit 20 may be pre-configured with a preset priority relationship among N interfaces 201; wherein the preset priority relationship among the N interfaces 201 can represent the priority between any two interfaces 201 among the N interfaces 201. According to the preset priority relationship, the request merging circuit 20 can select the interface 201 with the highest priority, the second highest priority interface 201, or the third highest priority interface 201 from the interfaces 201 corresponding to different memory access requests that meet the preset merging conditions as the target interface. The memory access request corresponding to the target interface (i.e., the memory access request received through the target interface) can be used as the target memory access request. Thus, the preset selection rule mentioned above can be: selecting the memory access request corresponding to the interface 201 with the highest priority, or selecting the memory access request corresponding to the interface 201 with the second highest priority, or selecting the memory access request corresponding to the interface 201 with the third highest priority.

[0114] As can be seen, by referring to the preset priority relationship between different interfaces 201, and the interfaces 201 from which different memory access requests that meet the preset merging conditions come, the request merging circuit 20 can efficiently and quickly select the target memory access request.

[0115] It should be noted that when both the target memory access request and other memory access requests are read requests, the cache circuit 30 can return a first read feedback to the computing circuit 10 via the interface 201 corresponding to the target memory access request, and a second read feedback to the computing circuit 10 via the interface 201 corresponding to other memory access requests. Similarly, when both the target memory access request and other memory access requests are write requests, the cache circuit 30 can return a first write feedback to the computing circuit 10 via the interface 201 corresponding to the target memory access request, and a second write feedback to the computing circuit 10 via the interface 201 corresponding to other memory access requests.

[0116] In some optional examples, such as Figure 4-1 As shown, there are multiple cache circuits 30, and the target processor also includes:

[0117] The routing circuit 50 is used to select a cache circuit 30 that is compatible with the merged memory access request from multiple cache circuits 30; and to transmit the merged memory access request to the cache circuit 30 that is compatible with the merged memory access request.

[0118] Cache circuit 30 is used to process merged memory access requests, including:

[0119] A cache circuit 30 adapted to merge memory access requests is used to process merge memory access requests.

[0120] Optionally, the routing circuit 50 may be a circuit responsible for selecting a transmission path for a memory access request and transmitting the memory access request according to the selected transmission path. The routing circuit 50 may be electrically connected to the request merging circuit 20, and the routing circuit 50 may also be electrically connected to multiple cache circuits 30 respectively.

[0121] Optionally, the request merging circuit 20 can merge different memory access requests that meet preset merging conditions to obtain a merged memory access request, and send the merged memory access request to the cache circuit 30. Correspondingly, the routing circuit 50 can receive the merged memory access request from the request merging circuit 20, and the routing circuit 50 can select a cache circuit 30 that matches the merged memory access request from among multiple cache circuits 30. For example, the routing circuit 50 can select a cache circuit 30 that matches the merged memory access request from among multiple cache circuits 30 based on the request parameters of the merged memory access request.

[0122] In some optional embodiments of this disclosure, in response to preset merging conditions including: the request type is the same and the request access address is the same, the routing circuit 50 is used to select a cache circuit 30 from a plurality of cache circuits 30 that is compatible with the merged memory access request, including:

[0123] The routing circuit 50 is used to determine the preset address range corresponding to each of the multiple cache circuits 30; from the preset address range corresponding to each of the multiple cache circuits 30, it determines the target preset address range to which the request access address of the merged memory access request belongs; and determines the cache circuit 30 corresponding to the target preset address range as the cache circuit 30 adapted to the merged memory access request.

[0124] Optionally, the multiple cache circuits 30 can be represented as R cache circuits 30; where R can be an integer greater than or equal to 2. The routing circuit 50 can be pre-configured with preset address ranges corresponding to each of the R cache circuits 30; wherein, the relationship between any cache circuit 30 and the corresponding preset address range can be: the cache circuit 30 is used to process memory access requests whose requested access address is within the preset address range.

[0125] In response to receiving a merge memory access request from the merge request circuit 20, the routing circuit 50 can compare the requested access address of the merge memory access request with the preset address ranges corresponding to the R cache circuits 30 one by one. This allows it to reliably determine the preset address range to which the requested access address of the merge memory access request belongs, and the determined preset address range can be used as the target preset address range. The routing circuit 50 can then determine the cache circuit 30 corresponding to the target preset address range as the cache circuit 30 adapted to the merge memory access request.

[0126] In some embodiments, the routing circuit 50 may select a cache circuit 30 that is compatible with the merged memory access request from among a plurality of cache circuits 30, based on the request type and the request access address of the merged memory access request.

[0127] In other embodiments, the routing circuit 50 may utilize some load balancing strategies to select a cache circuit 30 from multiple cache circuits 30 that is compatible with the merged memory access request.

[0128] Regardless of the method used to select the cache circuit 30 adapted to the merged memory access request, the routing circuit 50 can transmit the merged memory access request to the cache circuit 30 adapted to the merged memory access request. Accordingly, the cache circuit 30 adapted to the merged memory access request can receive the merged memory access request and process the merged memory access request. The specific processing method can be referred to the relevant descriptions of Case 1 and Case 2 above, and will not be repeated here.

[0129] In this way, by setting up multiple independent cache circuits 30, each cache circuit 30 can be used to process memory access requests. Data can be read / written concurrently based on different cache circuits 30, which helps to improve memory access bandwidth and achieve high-speed data access.

[0130] In some optional examples, such as Figure 4-2 As shown, the target processor may include: a computing circuit 10, a request merging circuit 20, a routing circuit 50, and multiple cache circuits 30; wherein, multiple interfaces 201 of the request merging circuit 20 can be electrically connected to the computing circuit 10 respectively, the routing circuit 50 can be electrically connected to the request merging circuit 20 and each cache circuit 30 respectively, and each cache circuit 30 can also be electrically connected to the main memory 40. Each cache circuit 30 may include: a pipeline circuit (CachePipeline), a Miss Status Handling Register (MSHR), and a cache region, and the cache region may include: multiple cache lines (corresponding to...) Figure 4-2 (Multiple cachelines in the context). Here, Cache Pipeline is the circuitry used to implement pipelined operations, and MSHR is the circuitry used to cache missed memory access requests.

[0131] Optionally, the target processor supports registers with a bit width of 4 bytes (corresponding to...). Figure 4-2 (Register 4B in the middle).

[0132] Optionally, the bus width for the target processor to access main memory 40 can be represented as B_W. The bus can have CHN_N independent channels, and the width of each independent channel is CHN_W = B_W / CHN_N (which is greater than 4 bytes). Therefore, to maximize bus bandwidth, the computing circuit 10 can generate and issue REQ_NUM = B_W / 4 memory access requests. Furthermore, the cacheline size can be aligned to CHN_W, and the multiple cache circuits 30 can specifically be CHN_N cache circuits 30.

[0133] The request merging circuit 20 can receive REQ_NUM memory access requests from the computing circuit 10 and merge the memory access requests based on their respective request types and access addresses. For example, it can merge memory access requests with the same request type and access address. Ideally, through merging, the number of memory access requests will change from REQ_NUM to CHN_N (equivalent to obtaining CHN_N merged memory access requests as described above). The request merging circuit 20 can then send all CHN_N merged memory access requests to the routing circuit 50.

[0134] The routing circuit 50 can receive CHN_N memory access requests from the request merging circuit 20. The routing circuit 50 can send the CHN_N memory access requests to the corresponding cache circuit 30 according to their respective request access addresses.

[0135] For any of the CHN_N memory access requests, a hit / miss determination can be performed within the corresponding cache circuit 30. If a miss is found (corresponding to the request access address for the merged memory access request mentioned above, indicating that the cache space of the cache circuit 30 does not contain the hit data), a data block is requested from the main memory 40 (equivalent to reading the target access data mentioned above from the main memory 40). After the data block is returned, subsequent operations are performed. If a hit is found (corresponding to the request access address for the merged memory access request mentioned above, indicating that the cache space of the cache circuit 30 contains the hit data), the data block is read from the cache space.

[0136] It should be noted that each cache circuit 30 can work independently without interfering with each other, and interacts with the main memory 40 through an independent bus.

[0137] If the system frequency of the target processor is 1GHz, and all REQ_NUM memory access requests generated by the computing circuit 10 are effectively merged, the system bandwidth of the target processor can reach B_W GB / s; even if all REQ_NUM memory access requests generated by the computing circuit 10 cannot be merged, the actual effective bandwidth of the target processor is 4*CHN_N GB / s.

[0138] In related technologies, the processor supports register widths of up to 4 bytes. The processor includes a computation circuit and a cache circuit, with only one cache circuit. If the computation circuit generates REQ_NUM memory access requests, these requests enter the cache circuit and undergo arbitration to select one. The request with arbitration rights then enters the pipeline process. All REQ_NUM memory access requests require complete pipeline operations. The inventors discovered that even if the width of the data block returned from the lower-level memory to the cache circuit is B_W, only 4 bytes of which are valid data. Therefore, the processor's effective bandwidth is only 4GB / s. In other words, even increasing the cacheline size to match the bus width cannot truly improve the processor's system bandwidth.

[0139] Therefore, compared with related technologies, the embodiments of this disclosure can reduce back pressure caused by arbitration and improve performance by merging different memory access requests that meet preset merging conditions. They can also reduce the number of accesses to the cache circuit 30, thereby reducing power consumption. Furthermore, the different cache circuits 30 can work independently yet collaboratively, which helps to improve system bandwidth and further enhance performance.

[0140] Exemplary methods

[0141] Embodiments of this disclosure also provide a data memory access method supporting memory access request merging, applied to the target processor in any of the above embodiments. As described above, the target processor may include: computing circuitry, request merging circuitry, and caching circuitry. In some embodiments, the target processor may further include: routing circuitry.

[0142] like Figure 5 As shown, data access methods include:

[0143] Step 510: Generate multiple memory access requests using the computing circuit;

[0144] Step 520: The request merging circuit performs the following operations: determines the request parameters of each of the multiple memory access requests, the request parameters being parameters used to control the memory access operation; based on the request parameters of each of the multiple memory access requests, determines the different memory access requests that meet the preset merging conditions among the multiple memory access requests; merges the different memory access requests that meet the preset merging conditions to obtain the merged memory access request.

[0145] Step 530: The cache circuit processes the merged memory access request to complete the memory access operations corresponding to different memory access requests that meet the preset merging conditions.

[0146] In some optional examples, the request parameters include: request type and request access address;

[0147] Step 520 involves determining, based on the request parameters of each of the multiple memory access requests, different memory access requests that meet the preset merging conditions, including:

[0148] Based on the request type and access address of each of the multiple memory access requests, identify the different memory access requests that meet the preset merging conditions among the multiple memory access requests;

[0149] The preset merging conditions include: the request type is the same and the request access address is the same.

[0150] In some optional examples, such as Figure 6 As shown, step 520 merges different memory access requests that meet the preset merging conditions to obtain merged memory access requests, including:

[0151] Step 610: In response to the fact that the different access requests that meet the preset merging conditions are all read request types, select the target memory access request from the different memory access requests that meet the preset merging conditions.

[0152] Step 620: Add tag information to the target memory access request to indicate that other memory access requests have been merged into the target memory access request, and obtain the merged memory access request;

[0153] Other memory access requests refer to memory access requests other than the target memory access request among different memory access requests that meet the preset merging conditions.

[0154] In some optional examples, such as Figure 7 As shown, step 530 includes:

[0155] Step 710: Obtain the target access data corresponding to the request access address of the merged memory access request from either the cache space of the cache circuit or the storage space of the main memory through the cache circuit.

[0156] Step 720: Based on the target access data and the tag information in the merged memory access requests, the cache circuit generates the first read feedback corresponding to the target memory access request and the second read feedback corresponding to other memory access requests.

[0157] Step 730: Return the first read feedback and the second read feedback to the computing circuit through the cache circuit.

[0158] In some optional examples, such as Figure 8 As shown, step 520 merges different memory access requests that meet the preset merging conditions to obtain merged memory access requests, including:

[0159] Step 810: In response to the fact that the different access requests that meet the preset merging conditions are all write request types, select the target memory access request from the different memory access requests that meet the preset merging conditions.

[0160] Step 820: Based on the target memory access request, obtain the first write data and the first mask information corresponding to the first write data;

[0161] Step 830: Based on other memory access requests, obtain the second write data and the second mask information corresponding to the second write data;

[0162] Step 840: Based on the first write data, the first mask information, the second write data, and the second mask information, merge other memory access requests into the target memory access request to obtain the merged memory access request;

[0163] Other memory access requests refer to memory access requests other than the target memory access request among different memory access requests that meet the preset merging conditions; the bit width of any write data is the register bit width supported by the processor, and the mask information corresponding to any write data is used to indicate the valid bit width segment and the invalid bit width segment in the bit width of the write data.

[0164] In some optional examples, such as Figure 9 As shown, step 840 includes:

[0165] Step 910: Perform an OR operation on the first and second written data to obtain the third written data;

[0166] Step 920: Perform an OR operation on the first mask information and the second mask information to obtain the third mask information;

[0167] Step 930: Update the first write data and the first mask information in the target memory access request to the third write data and the third mask information respectively, and add the tag information to the target memory access request to indicate that other memory access requests are merged into the target memory access request, so as to obtain the merged memory access request.

[0168] In some optional examples, such as Figure 10As shown, step 530 includes:

[0169] Step 1010: Obtain the target access data corresponding to the request access address of the merged memory access request from either the cache space of the cache circuit or the storage space of the main memory through the cache circuit.

[0170] Step 1020: Based on the third read data and the third mask information in the merged memory access request, the cache circuit updates the data located in the effective bit width segment of the target access data to obtain the updated result data corresponding to the target access data.

[0171] Step 1030: The update result data is cached to the cache space through the cache circuit, and the first write feedback corresponding to the target memory access request and the second write feedback corresponding to other memory access requests are generated based on the marking information in the merged memory access request.

[0172] Step 1040: Return the first write feedback and the second write feedback to the computing circuit through the cache circuit.

[0173] In some optional examples, such as Figure 11 As shown, the method provided in the embodiments of this disclosure further includes:

[0174] Step 1110: Receive multiple memory access requests from the computing circuit through multiple interfaces of the request merging circuit;

[0175] Step 1120: Determine the preset priority relationship between multiple interfaces;

[0176] Step 1130: Select the target interface from the interfaces corresponding to different memory access requests that meet the preset merging conditions, according to the preset priority relationship;

[0177] Step 1140: Determine the memory access request corresponding to the target interface as the target memory access request.

[0178] Here, steps 1120 to 1140 can be an optional implementation of step 610 of this disclosure, which involves selecting a target memory access request from different memory access requests that meet preset merging conditions.

[0179] In some optional examples, the number of cache circuits is multiple, such as Figure 12 As shown, the method provided in the embodiments of this disclosure further includes:

[0180] Step 1210: Select a cache circuit that is compatible with the merged memory access request from multiple cache circuits through the routing circuit;

[0181] Step 1220: The merged memory access request is transmitted to the cache circuit adapted to the merged memory access request through the routing circuit;

[0182] Step 530, which involves processing the merged memory access request through a cache circuit, includes:

[0183] Step 1230: The merged memory access request is processed by a cache circuit adapted to the merged memory access request.

[0184] In some optional examples, the default merging criteria include: the same request type and the same request access address, such as... Figure 13 As shown, step 1210 includes:

[0185] Step 1310: Determine the preset address range corresponding to each of the multiple cache circuits through the routing circuit;

[0186] Step 1320: Determine the target preset address range to which the request access address of the merged memory access request belongs from the preset address ranges corresponding to the multiple cache circuits through the routing circuit;

[0187] Step 1330: The cache circuit corresponding to the target preset address range is determined by the routing circuit as the cache circuit that is compatible with the merged memory access request.

[0188] In some optional examples, such as Figure 14 As shown, the target processor is first powered on or reset. The computing circuitry then begins generating memory access requests, and can send up to eight memory access requests to the request merging circuitry per cycle.

[0189] The request merging circuit performs consistency comparisons on the request type and the requested access address of eight memory access requests to determine if any of them can be merged. If so, it identifies the merger and the merged request, and appends the merged request to the merger before passing it to the next stage. In this way, the routing circuit receives the merged memory access request and forwards it to the appropriate caching circuit based on the requested access address.

[0190] Once a memory access request enters the cache circuit, the cache circuit can determine whether the memory access request is a hit or a miss.

[0191] If it's a miss (corresponding to the request address for the merged memory access request mentioned above, indicating that the cache space does not contain the data to be hit), the cache circuit can retrieve the data block from main memory (equivalent to the target access data mentioned above). If the memory access request is a read request, the cache circuit can return the data block to the computation circuit; if the memory access request is a write request, the cache circuit can write new data into the data block (equivalent to updating the data in the effective bit width segment of the target access data based on the third read data and the third mask information in the merged memory access request mentioned above, obtaining the updated result data corresponding to the target access data), and then backfill the cacheline.

[0192] If it's a hit (corresponding to the request address for the merged memory access request mentioned above, confirming that the cache space contains the data that was hit), the cache circuit can directly read and use the data block in the cacheline. If the memory access request is a read request, the cache circuit can return the data block to the computation circuit; if the memory access request is a write request, the cache circuit can write new data to the data block and populate the cacheline.

[0193] In the methods disclosed herein, the various optional embodiments, optional implementation methods and optional examples disclosed in the exemplary circuit section above can be flexibly selected and combined as needed to achieve the corresponding functions and effects, and this disclosure does not list them all.

[0194] The beneficial technical effects corresponding to the exemplary embodiments of this method can be found in the corresponding beneficial technical effects of the exemplary circuit section described above, and will not be repeated here.

[0195] Exemplary electronic devices

[0196] Figure 15 The illustration shows a block diagram of an electronic device according to an embodiment of the present disclosure. The electronic device 1500 includes one or more processors 1510 and memory 1520.

[0197] The processor 1510 may be a central processing unit (CPU) or other form of processing unit with data processing capabilities and / or instruction execution capabilities, and may control other components in the electronic device 1500 to perform desired functions.

[0198] The memory 1520 may include one or more computer program products, which may include various forms of computer-readable storage media, such as volatile memory and / or non-volatile memory. Volatile memory may include, for example, random access memory (RAM) and / or cache memory. Non-volatile memory may include, for example, read-only memory (ROM), hard disk, flash memory, etc. One or more computer program instructions may be stored on the computer-readable storage medium, and the processor 1510 may execute one or more computer program instructions to implement a data access method supporting memory request merging and / or other desired functions according to the various embodiments of this disclosure described above.

[0199] In one example, the electronic device 1500 may also include an input device 1530 and an output device 1540, which are interconnected via a bus system and / or other forms of connection mechanism (not shown).

[0200] The input device 1530 may also include, for example, a keyboard, a mouse, etc.

[0201] The output device 1540 can output various information to the outside, including, for example, a display, a speaker, a printer, and a communication network and its connected remote output devices, etc.

[0202] Of course, for the sake of simplicity, Figure 15 Only some of the components of the electronic device 1500 relevant to this disclosure are shown, omitting components such as buses, input / output interfaces, etc. In addition, the electronic device 1500 may include any other suitable components depending on the specific application.

[0203] Exemplary computer program products and computer-readable storage media

[0204] In addition to the methods and apparatus described above, embodiments of this disclosure may also be computer program products comprising computer program instructions that, when executed by a processor, cause the processor to perform the steps in the methods according to various embodiments of this disclosure as described in the "Exemplary Methods" section of this specification.

[0205] Computer program products can be written in any combination of one or more programming languages ​​to perform the operations of embodiments of this disclosure. These programming languages ​​include object-oriented programming languages ​​such as Java and C++, as well as conventional procedural programming languages ​​such as C or similar languages. The program code can be executed entirely on a user's computing device, partially on a user's computing device, as a standalone software package, partially on a user's computing device and partially on a remote computing device, or entirely on a remote computing device or server.

[0206] Furthermore, embodiments of this disclosure may also be computer-readable storage media storing computer program instructions that, when executed by a processor, cause the processor to perform steps in a data memory access method supporting memory access request merging, as described in the "Exemplary Methods" section of this specification and according to various embodiments of this disclosure.

[0207] The computer-readable storage medium may be any combination of one or more readable media. A readable medium may be a readable signal medium or a readable storage medium. A readable storage medium may, for example, include, but is not limited to, electrical, magnetic, optical, electromagnetic, infrared, or semiconductor systems, apparatuses, or devices, or any combination thereof. More specific examples of readable storage media (a non-exhaustive list) include: electrical connections having one or more wires, portable disks, hard disks, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), optical fibers, portable compact disk read-only memory (CD-ROM), optical storage devices, magnetic storage devices, or any suitable combination thereof.

[0208] The basic principles of this disclosure have been described above with reference to specific embodiments. However, the advantages, benefits, and effects mentioned in this disclosure are merely examples and not limitations, and should not be considered as essential features of each embodiment of this disclosure. The specific details disclosed above are for illustrative and facilitative purposes only, and are not limitations. These details do not limit the scope of this disclosure to the necessity of employing the specific details described above.

[0209] Various modifications and variations can be made to this disclosure without departing from its spirit and scope. Therefore, if such modifications and variations fall within the scope of the claims of this disclosure and their equivalents, this disclosure is also intended to include such modifications and variations.

Claims

1. A processor that supports memory access request merging, comprising: A computing circuit, wherein the computing circuit is used to generate multiple memory access requests; A request merging circuit is used to determine the request parameters of each of the multiple memory access requests, the request parameters being parameters used to control the memory access operation; and based on the request parameters of each of the multiple memory access requests, to determine the different memory access requests among the multiple memory access requests that meet the preset merging conditions. Different memory access requests that meet the preset merging conditions are merged to obtain merged memory access requests; A cache circuit is used to process the merged memory access request to complete the memory access operations corresponding to the different memory access requests that meet the preset merging conditions.

2. The processor according to claim 1, wherein, The request parameters include: request type and request access address; The request merging circuit is used to determine, based on the request parameters of each of the multiple memory access requests, different memory access requests that meet preset merging conditions, including: The request merging circuit is used to determine different memory access requests that meet preset merging conditions among the multiple memory access requests based on the request type and the request access address of each of the multiple memory access requests. The preset merging conditions include: the request types are the same and the request access addresses are the same.

3. The processor according to claim 2, wherein, The request merging circuit is used to merge different memory access requests that meet preset merging conditions to obtain merged memory access requests, including: The request merging circuit is configured to, in response to the fact that the request types of the different access requests that meet the preset merging conditions are all read request types, select a target memory access request from the different memory access requests that meet the preset merging conditions; add tag information to the target memory access request to indicate that other memory access requests are merged into the target memory access request, thereby obtaining the merged memory access request; The other memory access requests refer to the memory access requests that meet the preset merging conditions, excluding the target memory access request.

4. The processor according to claim 3, wherein, The cache circuit is used to process the merged memory access request to complete the memory access operations corresponding to the different memory access requests that meet the preset merging conditions, including: The cache circuit is used to obtain the target access data corresponding to the requested access address of the merged memory access request from either the cache space of the cache circuit or the storage space of the main memory; based on the target access data and the tag information in the merged memory access request, generate a first read feedback corresponding to the target memory access request and a second read feedback corresponding to the other memory access requests; and return the first read feedback and the second read feedback to the computing circuit.

5. The processor according to claim 2, wherein, The request merging circuit is used to merge different memory access requests that meet preset merging conditions to obtain merged memory access requests, including: The request merging circuit is configured to, in response to the fact that the request types of the different access requests satisfying the preset merging conditions are all write request types, select a target memory access request from the different memory access requests satisfying the preset merging conditions; based on the target memory access request, obtain first write data and first mask information corresponding to the first write data; based on other memory access requests, obtain second write data and second mask information corresponding to the second write data; based on the first write data, the first mask information, the second write data, and the second mask information, merge the other memory access requests into the target memory access request to obtain the merged memory access request; Among these, the other memory access requests refer to: among the different memory access requests that meet the preset merging conditions, the other memory access requests besides the target memory access request; the bit width of any write data is the register bit width supported by the processor, and the mask information corresponding to any write data is used to indicate the valid bit width segment and the invalid bit width segment in the bit width of the write data.

6. The processor according to claim 5, wherein, The request merging circuit is used to merge the other memory access requests into the target memory access request based on the first write data, the first mask information, the second write data, and the second mask information, to obtain the merged memory access request, including: The request merging circuit is used to perform an OR operation on the first write data and the second write data to obtain the third write data; to perform an OR operation on the first mask information and the second mask information to obtain the third mask information; to update the first write data and the first mask information in the target memory access request to the third write data and the third mask information respectively; and to add marker information to the target memory access request to indicate that the other memory access requests are merged into the target memory access request, thereby obtaining the merged memory access request.

7. The processor according to claim 6, wherein, The cache circuit is used to process the merged memory access request to complete the memory access operations corresponding to the different memory access requests that meet the preset merging conditions, including: The cache circuit is used to obtain the target access data corresponding to the requested access address of the merged memory access request from either the cache space of the cache circuit or the storage space of the main memory; based on the third read data and the third mask information in the merged memory access request, update the data located in the effective bit width segment of the target access data to obtain the update result data corresponding to the target access data; cache the update result data in the cache space; and based on the tag information in the merged memory access request, generate a first write feedback corresponding to the target memory access request and a second write feedback corresponding to the other memory access requests; and return the first write feedback and the second write feedback to the computing circuit.

8. The processor according to any one of claims 4 to 7, wherein, The request merging circuit is used to receive multiple memory access requests from the computing circuit through multiple interfaces; The request merging circuit is used to select a target memory access request from the different memory access requests that meet the preset merging conditions, including: The request merging circuit is used to determine a preset priority relationship among multiple interfaces; according to the preset priority relationship, a target interface is selected from the interfaces corresponding to different memory access requests that meet the preset merging conditions; and the memory access request corresponding to the target interface is determined as the target memory access request.

9. The processor according to any one of claims 1 to 7, wherein, The number of cache circuits is multiple, and the processor also includes: A routing circuit is configured to select, from a plurality of cache circuits, a cache circuit that is compatible with the merged memory access request; and transmit the merged memory access request to the cache circuit that is compatible with the merged memory access request. The cache circuit is used to process the merged memory access request, including: The cache circuitry adapted to the merged memory access request is used to process the merged memory access request.

10. The processor according to claim 9, wherein, In response to the preset merging conditions, including that the request types are the same and the request access addresses are the same, the routing circuit is used to select, from a plurality of the caching circuits, the caching circuit that is compatible with the merged memory access request, including: The routing circuit is used to determine the preset address range corresponding to each of the plurality of cache circuits; from the preset address range corresponding to each of the plurality of cache circuits, to determine the target preset address range to which the requested access address of the merged memory access request belongs; and to determine the cache circuit corresponding to the target preset address range as the cache circuit adapted to the merged memory access request.

11. A data access method supporting memory access request merging, comprising: Multiple memory access requests are generated by the computing circuitry in the processor. The request merging circuit in the processor performs the following operations: determining the request parameters of each of the plurality of memory access requests, the request parameters being parameters used to control the memory access operation; and based on the request parameters of each of the plurality of memory access requests, determining the different memory access requests among the plurality of memory access requests that meet the preset merging conditions. Different memory access requests that meet the preset merging conditions are merged to obtain merged memory access requests; The processor's cache circuitry processes the merged memory access requests to complete the memory access operations corresponding to the different memory access requests that meet the preset merging conditions.

12. A computer-readable storage medium storing a computer program that is executed by a processor to perform the method of claim 11.

13. An electronic device, the electronic device comprising: processor; Memory used to store the processor's executable instructions; The processor is configured to read the executable instructions from the memory, and execute the instructions to implement the method of claim 11.

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