Hybrid granularity reconfigurable computing system

Abstract

The invention relates to a hybrid granularity reconfigurable computing system. The system comprises a fine granularity processing unit, a coarse granularity processing unit, a multi-layer control flow path and a multi-layer initialization flow path. The coarse granularity processing unit is used for decoupling the control flow information into coarse granularity control flow information and fine granularity control flow information, and performing coarse granularity processing on the coarse granularity control flow information; the coarse granularity processing unit is also used for decoupling the initialization stream information into coarse granularity initialization stream information and fine granularity initialization stream information, and performing coarse granularity processing on the coarse granularity initialization stream information; and the fine-grained processing unit is used for receiving fine-grained control flow information through the control flow path, receiving fine-grained initialization flow information through the initialization flow path, and performing fine-grained processing on the fine-grained control flow information and the fine-grained initialization flow information respectively. By adopting the method, the calculation efficiency can be improved.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of reconfigurable computing, and particularly relates to a hybrid-granularity reconfigurable computing system. BACKGROUND

[0002] CGRA (Coarse-Grained Reconfigurable Architecture) is a new computing architecture between traditional processors (such as central processing units CPU) and fixed-function hardware, and its core goal is to balance flexibility and energy efficiency through dynamic reconfigurability. With the rise of heterogeneous computing and domain-specific architecture (DSA), CGRA is becoming a key technology direction for breaking through the "energy efficiency wall" and "memory wall" due to its potential for "software and hardware co-optimization", and it has unique advantages in edge computing, real-time signal processing and other fields.

[0003] However, the current coarse-grained reconfigurable architecture has the problem of low computing efficiency. SUMMARY

[0004] Therefore, it is necessary to provide a hybrid-granularity reconfigurable computing system capable of improving computing efficiency.

[0005] In a first aspect, the present application provides a hybrid-granularity reconfigurable computing system, comprising a fine-grained processing unit, a coarse-grained processing unit, a multi-layer control flow path and a multi-layer initialization flow path.

[0006] The coarse-grained processing unit is configured to decouple control flow information into coarse-grained control flow information and fine-grained control flow information, perform coarse-grained processing on the coarse-grained control flow information, and transmit the fine-grained control flow information to the fine-grained processing unit through the control flow path.

[0007] The coarse-grained processing unit is further configured to decouple initialization flow information into coarse-grained initialization flow information and fine-grained initialization flow information, perform coarse-grained processing on the coarse-grained initialization flow information, and transmit the fine-grained initialization flow information to the fine-grained processing unit through the initialization flow path.

[0008] The fine-grained processing unit is configured to receive fine-grained control flow information through the control flow path, receive fine-grained initialization flow information through the initialization flow path, and perform fine-grained processing on the fine-grained control flow information and the fine-grained initialization flow information, respectively.

[0009] In one embodiment, the coarse-grained processing unit comprises:

[0010] a central processing unit, configured to output initialization stream information;

[0011] a processing unit array interface, configured to receive the initialization stream information through a first layer initialization stream channel, decouple the initialization stream information to obtain coarse-grained initialization stream information and fine-grained initialization stream information, and distribute the coarse-grained initialization stream information and the fine-grained initialization stream information;

[0012] a processing unit array controller, configured to receive the coarse-grained initialization stream information through a first initialization stream channel of a second layer, and pre-process the coarse-grained initialization stream information, so that the coarse-grained processing unit performs coarse-grained processing on the pre-processed coarse-grained initialization stream information;

[0013] the fine-grained processing unit comprises:

[0014] a Boolean processing array interface, configured to receive the fine-grained initialization stream information through a second initialization stream channel of the second layer, and perform granularity decoupling and distribution on the fine-grained initialization stream information, so that the fine-grained processing unit performs fine-grained processing on the fine-grained initialization stream information.

[0015] In one of the embodiments, the coarse-grained processing unit further comprises a coarse-grained reconfigurable architecture core unit;

[0016] the fine-grained processing unit further comprises:

[0017] a Boolean processing array, configured to perform fine-grained calculation;

[0018] a Boolean processing array shared memory, configured to store data of the Boolean processing array;

[0019] two ends of a first initialization stream channel of the third layer are connected with an initialization stream output end of the processing unit array controller and an initialization stream input end of the coarse-grained reconfigurable architecture core unit respectively;

[0020] two ends of a second initialization stream channel of the third layer are connected with a first initialization stream output end of the Boolean processing array interface and an initialization stream input end of the Boolean processing array shared memory respectively;

[0021] two ends of a third initialization stream channel of the third layer are connected with a second initialization stream output end of the Boolean processing array interface and an initialization stream input end of the Boolean processing array respectively.

[0022] In one of the embodiments, the central processing unit is further configured to output control stream information;

[0023] The processing unit array interface is further configured to receive control flow information from the central processing unit through a first layer control flow path, decouple the control flow information to obtain coarse-grained control flow information and fine-grained control flow information, and distribute the coarse-grained control flow information and the fine-grained control flow information.

[0024] The processing unit array controller is further configured to receive coarse-grained control flow information from the processing unit array interface through a first control flow path of a second layer, pre-process the coarse-grained control flow information, and supply the pre-processed coarse-grained control flow information to the coarse-grained processing unit for coarse-grained processing.

[0025] The Boolean processing array interface is further configured to receive fine-grained control flow information from the processing unit array interface through a second control flow path of the second layer, decouple and distribute the fine-grained control flow information in granularity, and supply the fine-grained control flow information to the fine-grained processing unit for fine-grained processing.

[0026] In one embodiment, the fine-grained processing unit further comprises:

[0027] An instruction distribution unit configured to schedule the fine-grained control flow information according to scheduling information.

[0028] A Boolean processing array data transmission unit configured to perform data transmission between the coarse-grained processing unit.

[0029] A Boolean processing array crossbar unit configured to perform data transmission between the Boolean processing array shared memory and the Boolean processing array.

[0030] The two ends of a first control flow path of the third layer are respectively connected to a control flow output end of the processing unit array controller and a control flow input end of the coarse-grained reconfigurable architecture core unit.

[0031] The two ends of a second control flow path of the third layer are respectively connected to a first control flow output end of the Boolean processing array interface and a control flow input end of the Boolean processing array crossbar unit.

[0032] The two ends of a third control flow path of the third layer are respectively connected to a second control flow output end of the Boolean processing array interface and a control flow input end of the Boolean processing array data transmission unit.

[0033] The two ends of a fourth control flow path of the third layer are respectively connected to a third control flow output end of the Boolean processing array interface and a control flow input end of the instruction distribution unit.

[0034] In one embodiment, the coarse-grained processing unit further comprises:

[0035] a processing unit array data transfer unit configured to perform data transfer with the Boolean processing array data transfer unit;

[0036] a processing unit array crossbar unit configured to perform data transfer between the processing unit array shared memory and the processing unit array of the coarse-grained reconfigurable architecture core unit;

[0037] a processing unit array configuration direct memory access configured to pull configuration stream from the hierarchical memory;

[0038] a processing unit array data direct memory access configured to transfer data between the hierarchical memory and the processing unit array shared memory;

[0039] the fine-grained processing unit further comprises:

[0040] a Boolean processing array configuration unit configured to store configuration information of the fine-grained processing unit;

[0041] two ends of a first control flow path of the fourth layer are connected to a first control flow output end of the coarse-grained reconfigurable architecture core unit and a control flow input end of the processing unit array data transfer unit, respectively;

[0042] two ends of a second control flow path of the fourth layer are connected to a second control flow output end of the coarse-grained reconfigurable architecture core unit and a control flow input end of the processing unit array crossbar unit, respectively;

[0043] two ends of a third control flow path of the fourth layer are connected to a third control flow output end of the coarse-grained reconfigurable architecture core unit and a control flow input end of the processing unit array configuration direct memory access, respectively;

[0044] two ends of a fourth control flow path of the fourth layer are connected to a fourth control flow output end of the coarse-grained reconfigurable architecture core unit and a control flow input end of the processing unit array data direct memory access, respectively;

[0045] two ends of a fifth control flow path of the fourth layer are connected to a fifth control flow output end of the coarse-grained reconfigurable architecture core unit and a control flow input end of the Boolean processing array configuration unit, respectively;

[0046] two ends of a sixth control flow path of the fourth layer are connected to a control flow output end of the instruction distribution unit and a control flow input end of the Boolean processing array, respectively.

[0047] In one embodiment thereof, the system further comprises a multi-layer configuration stream path, and the coarse-grained processing unit further comprises:

[0048] a hierarchical memory configured to store configuration stream information;

[0049] The coarse-grained processing unit is further configured to receive coarse-grained configuration stream information from the hierarchical memory through the first configuration flow path of the first layer, and perform coarse-grained processing on the coarse-grained configuration stream information.

[0050] The fine-grained processing unit is further configured to receive fine-grained configuration stream information through the second configuration flow path of the first layer, and to perform fine-grained processing on the fine-grained configuration stream information.

[0051] In one embodiment, the coarse-grained processing unit further includes:

[0052] The processing unit array is configured with direct memory access for obtaining coarse-grained configuration flow information of the layer memory from the first configuration flow path of the first layer;

[0053] The fine-grained processing unit further includes:

[0054] Boolean processing array configuration unit, used to obtain and store fine-grained configuration stream information from the second configuration stream path of the first layer.

[0055] In one embodiment, the coarse-grained processing unit further includes:

[0056] The coarse-grained reconfigurable architecture core unit is used to receive coarse-grained configuration stream information from the configuration stream output terminal of the direct memory access configuration of the processing unit array through the first configuration stream path of the second layer, and to perform coarse-grained calculations on it.

[0057] The fine-grained processing unit further includes:

[0058] The instruction allocation unit is used to receive fine-grained configuration stream information from the configuration stream output of the Boolean processing array configuration unit through the second configuration stream path of the second layer, and to schedule the fine-grained configuration stream information according to the scheduling information.

[0059] In one embodiment, the coarse-grained processing unit further includes:

[0060] The processing unit array controller is used to receive coarse-grained configuration stream information from the configuration stream output terminal of the coarse-grained reconfigurable architecture core unit through the first configuration stream path of the third layer, and preprocess it so that the coarse-grained processing unit can perform coarse-grained processing on the preprocessed coarse-grained configuration stream information.

[0061] The fine-grained processing unit further includes:

[0062] A Boolean processing array is used to receive fine-grained configuration stream information from the first configuration stream output of the instruction allocation unit through the second configuration stream path of the third layer, and to perform fine-grained calculations on it.

[0063] An interconnected network is used to receive fine-grained configuration stream information from the second configuration stream output of the instruction allocation unit through the third configuration stream path of the third layer, and to transmit it as a data stream across the Boolean processing array.

[0064] The aforementioned hybrid-granularity reconfigurable computing system decouples initialization flow information through a coarse-grained processing unit, resulting in coarse-grained and fine-grained initialization flow information. The coarse-grained initialization flow information undergoes coarse-grained processing, and the fine-grained initialization flow information is transmitted to the fine-grained processing unit via an initialization flow path. The fine-grained processing unit then performs fine-grained processing on the fine-grained initialization flow information. Similarly, the system decouples control flow information through a coarse-grained processing unit, resulting in coarse-grained and fine-grained control flow information. The coarse-grained control flow information undergoes coarse-grained processing, and the fine-grained control flow information is transmitted to the fine-grained processing unit via a control flow path. The fine-grained processing unit then performs fine-grained processing on the fine-grained control flow information. Thus, by setting up initialization and control flow paths, the system achieves separation of coarse and fine-grained information, as well as separate processing of control flow and initialization flow information. This eliminates the need for components to undergo invalid operations and redundant interface bandwidth due to decoupling and subsequent obfuscation, thereby improving computational efficiency. Attached Figure Description

[0065] To more clearly illustrate the technical solutions in the embodiments of this application or related technologies, the drawings used in the description of the embodiments of this application or related technologies will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other related drawings can be obtained based on these drawings without creative effort.

[0066] Figure 1 This is an application environment diagram of a hybrid granularity reconfigurable computing system in one embodiment;

[0067] Figure 2 Here is a block diagram of a hybrid granularity reconfigurable computing system as an example;

[0068] Figure 3 This is a schematic diagram of initializing the flow path in one embodiment;

[0069] Figure 4 This is a schematic diagram of the control flow path in one embodiment;

[0070] Figure 5 This is a schematic diagram illustrating the configuration of the flow path in one embodiment;

[0071] Figure 6 This is a schematic diagram illustrating the initialization, control, and configuration of a flow path in a specific example. Detailed Implementation

[0072] To make the objectives, technical solutions, and advantages of this application clearer, the following detailed description is provided in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the scope of this application.

[0073] It should be noted that the terms "first," "second," etc., used in this application can be used to describe various elements, but these elements are not limited by these terms. These terms are only used to distinguish the first element from the second element. The terms "comprising" and "having," and any variations thereof, used in this application, are intended to cover non-exclusive inclusion. The term "multiple" used in this application refers to two or more. The term "and / or" used in this application refers to one of the embodiments, or any combination of multiple embodiments.

[0074] Different technologies exhibit diverse information flow granularities. For example, in neural network technology, coarse-grained information flow typically refers to the process by which the network extracts and integrates global features of data at a high-level abstraction level. Fine-grained information flow focuses on the refined expression of local features. Coarse-grained and fine-grained are relative terms; coarse-grained information has a larger granularity than fine-grained information.

[0075] In related technologies, different types of coarse and fine granular information flows are combined and obfuscated in the traditional CGRA architecture. This requires the internal components of CGRA to separate information flows. However, the internal components of traditional CGRA neglect the design of coarse and fine granular paths, resulting in the components undergoing ineffective operations and redundant interface bandwidth after decoupling and obfuscation, which reduces computational efficiency.

[0076] To address this issue, this application proposes a hybrid granularity reconfigurable computing system that solves the problem of inefficient hardware execution caused by information flow granularity confusion by designing, controlling, configuring, and initializing the flow path.

[0077] The hybrid granularity reconfigurable computing system provided in this application embodiment can be applied to, for example... Figure 1 In the application environment shown, terminal 102 communicates with server 104 via a network. A data storage system can store the data that server 104 needs to process. The data storage system can be integrated onto server 104, or it can be located in the cloud or on another network server.

[0078] The terminal 102 can be, but is not limited to, various personal computers, laptops, smartphones, tablets, and drones. The server 104 can be a standalone physical server, a server cluster or distributed system consisting of multiple physical servers, or a cloud server providing cloud computing services.

[0079] In one exemplary embodiment, such as Figure 2 As shown, a hybrid granularity reconfigurable computing system is provided, which can be applied to... Figure 1 We will use server 104 as an example to illustrate this.

[0080] The hybrid granularity reconfigurable computing system includes a coarse-grained processing unit 201, a fine-grained processing unit 202, a multi-layer control flow path, and a multi-layer initialization flow path. Figure 2 The diagram shows a control path and an initialization path. Wherein:

[0081] The coarse-grained processing unit 201 is used to decouple the control flow information into coarse-grained control flow information and fine-grained control flow information, perform coarse-grained processing on the coarse-grained control flow information, and transmit the fine-grained control flow information to the fine-grained processing unit 202 through the control flow path.

[0082] The coarse-grained processing unit 201 is also used to decouple the initialization flow information into coarse-grained initialization flow information and fine-grained initialization flow information, perform coarse-grained processing on the coarse-grained initialization flow information, and transmit the fine-grained initialization flow information to the fine-grained processing unit 202 through the initialization flow path.

[0083] The fine-grained processing unit 202 is used to receive fine-grained control flow information through the control flow path, receive fine-grained initialization flow information through the initialization flow path, and perform fine-grained processing on the fine-grained control flow information and the fine-grained initialization flow information respectively.

[0084] Control flow information refers to information about the flow control logic during system computation, such as instruction execution order, branch jumps, and loop iterations. Initialization flow information refers to information related to the system's execution flow, data initialization order, and resource loading logic during startup and initialization phases. Control flow path refers to the path through which control flow information flows, and initialization flow path refers to the path through which initialization flow information flows.

[0085] Coarse-grained processing can be understood as processing or computation with extremely long computational steps, such as addition, subtraction, multiplication, and division; fine-grained processing can be understood as processing or computation with shorter computational steps, such as logical operations. A hybrid-granularity reconfigurable computing system refers to a system that includes both coarse-grained and fine-grained reconfigurable computing, and also includes both coarse-grained and fine-grained information flows.

[0086] For example, when the system is used to compute a neural network, the coarse-grained processing unit 201 can generate initialization flow information for the system, decouple the initialization flow information into coarse-grained initialization flow information and fine-grained initialization flow information according to granularity, perform coarse-grained processing on the coarse-grained initialization flow information, and transmit the fine-grained initialization flow information to the fine-grained processing unit 202 through the initialization flow path; the fine-grained processing unit 202 receives the fine-grained initialization flow information through the initialization flow path and performs fine-grained processing on it. The coarse-grained processing unit 201 can generate control flow information required for computation, decouple the control flow information into coarse-grained control flow information and fine-grained control flow information according to granularity, perform coarse-grained processing on the coarse-grained control flow information, and transmit the fine-grained control flow information to the fine-grained processing unit 202 through the control flow path. The fine-grained processing unit 202 receives the fine-grained control flow information through the control flow path and performs fine-grained processing on it.

[0087] For example, when performing image recognition calculations using the system of this application embodiment, the components of the system are first initialized through a multi-layer initialization flow path. The coarse-grained processing unit 201 generates initialization flow information before calculation according to control instructions, and after decoupling, transmits the fine-grained initialization information to the fine-grained processing unit 202 through the initialization flow path to initialize the fine-grained processing components. Simultaneously, the coarse-grained processing unit 201 initializes the coarse-grained components, achieving coarse-grained and fine-grained separation initialization. Then, the components of the system are controlled through a multi-layer control flow path. The coarse-grained processing unit 201 generates control flow information according to control instructions, and after decoupling, transmits the fine-grained control information to the fine-grained processing unit 202 through the control flow path to control the fine-grained processing components. Simultaneously, the coarse-grained processing unit 201 controls the coarse-grained components, achieving coarse-grained and fine-grained separation control.

[0088] In other words, by separating coarse and fine-grained information processing, the information is decoupled, eliminating the need for ineffective coupling operations and redundant interface bandwidth, thus improving computational efficiency.

[0089] The aforementioned hybrid-granularity reconfigurable computing system sets up information flow paths, decouples the flow information, and distributes it through these paths. It processes coarse-grained information in a coarse-grained manner and fine-grained information in a fine-grained manner, where the granularity of coarse-grained information is greater than that of fine-grained information. This achieves the separation of coarse and fine-grained information and also separates the processing of control flow information and initialization flow information. This eliminates the need for components to undergo invalid operations and redundant interface bandwidth due to decoupling and subsequent confusion, thereby improving computing efficiency.

[0090] The following example, using a CGRA architecture for coarse-grained processing units and a BP (Boolean Processor) array for fine-grained processing units, illustrates the information flow path of this application embodiment. BP can perform fine-grained parallel Boolean computations using Boolean values. BP primarily uses LUT units as its main units; due to the functional variability of LUTs, BP possesses computational reconfigurability. BP can complete logical computations in a relatively short time, and its performance is outstanding in fine-grained logical computations such as XOR shifts.

[0091] In one exemplary embodiment, such as Figure 3 As shown, the coarse-grained processing unit 201 includes a central processing unit 301, a processing unit array interface 302, and a processing unit array controller 303. The fine-grained processing unit includes a Boolean processing array interface 304. Wherein:

[0092] Central processing unit 301 is used to output initialization stream information;

[0093] The processing unit array interface 302 is used to receive initialization flow information through the first-layer initialization flow path 305, decouple the initialization flow information to obtain coarse-grained initialization flow information and fine-grained initialization flow information, and distribute them.

[0094] The processing unit array controller 303 is used to receive coarse-grained initialization stream information through the first initialization stream path 306 of the second layer, and preprocess the coarse-grained initialization stream information so that the coarse-grained processing unit can perform coarse-grained processing on the preprocessed coarse-grained initialization stream information.

[0095] Boolean processing array interface 304 is used to receive fine-grained initialization stream information through the second initialization stream path 307 of the second layer, and to decouple and distribute the fine-grained initialization stream information at the granular level so that the fine-grained processing unit can perform fine-grained processing on the fine-grained initialization stream information.

[0096] The processing unit array controller 303 can be used to control most of the components of the coarse-grained processing unit 201 and some of the components of the fine-grained processing unit 202.

[0097] For example, initialization primarily focuses on the computing and storage units. When the system is used for neural network computation, during the initialization phase, the central processing unit 301 generates the initialization information stream required for initialization. This stream is used to initialize the internal states of different components and prepare data. It is then transmitted to the processing unit array interface 302 via the first-layer initialization flow path 305. The initialization flow information first enters the processing unit array interface 302 to achieve initial decoupling between coarse and fine granularity. This is divided into coarse-grained initialization flow information and fine-grained initialization flow information, which are transmitted to the processing unit array controller 303 via the first initialization flow path 306 of the second layer, and to the Boolean processing array interface 304 via the second initialization flow path 307 of the second layer, respectively. In the coarse-grained processing unit 201, the processing unit array controller 303 preprocesses the coarse-grained initialization flow information, enabling the coarse-grained processing unit 201 to perform coarse-grained initialization, achieving control-level initialization and ensuring the correctness of the system's computational order. In the fine-grained processing unit 202, the fine-grained initialization stream enters the Boolean processing array interface 304, which performs a second, finer-grained decoupling and distribution operation on it, so that the fine-grained processing unit 202 can perform fine-grained initialization.

[0098] Furthermore, referring to Figure 3 The coarse-grained processing unit also includes a coarse-grained reconfigurable architecture core unit 308, and the fine-grained processing unit includes a Boolean processing array (BPA) 309 and a Boolean processing array shared memory 310. Wherein:

[0099] Boolean processing array 309 is used for fine-grained calculations;

[0100] The Boolean processing array shares memory 310 to store the data of the Boolean processing array;

[0101] The first initialization flow path 311 of the third layer is connected to the initialization flow output terminal of the processing unit array controller 303 and the initialization flow input terminal of the coarse-grained reconfigurable architecture core unit 308, respectively.

[0102] The two ends of the second initialization stream 312 of the third layer are respectively connected to the first initialization stream output end of the Boolean processing array interface 304 and the initialization stream input end of the Boolean processing array shared memory 310;

[0103] The two ends of the third initialization stream path 313 of the third layer are respectively connected to the second initialization stream output end of the Boolean processing array interface 304 and the initialization stream input end of the Boolean processing array 309.

[0104] The coarse-grained reconfigurable architecture core (CGRA Core) 308 mainly includes a Processing Element Array (PEA), global register files for global storage, and configuration memory for storing configuration streams. There are four PEAs, each mainly containing 4×4 PE (Processing Element) computing units for coarse-grained computation.

[0105] The Boolean processing array 309 contains 4×4 fine-grained bPEs (boolean processing elements) for fine-grained computation.

[0106] For example, the processing unit array controller 303 transmits the preprocessed coarse-grained initialization stream information to the coarse-grained reconfigurable architecture core unit 308 through the first initialization flow path 311 of the third layer, initializing the coarse-grained reconfigurable architecture core unit 308, thereby putting the computing unit in the initial stage of the next computing state. The Boolean processing array interface 304 further decouples the fine-grained initialization stream information into computing initialization stream information and storage initialization stream information, and sends the computing initialization stream information to the Boolean processing array 309 through the third initialization path 313 of the third layer, realizing the initialization of the computing state inside the Boolean processing array 309. At the same time, it stores the storage initialization stream information in the Boolean processing shared memory 310 through the second initialization path 312 of the third layer, so that the current storage space clears outdated storage or prepares storage information. Through the above components and the initialization flow paths between them, the initialization of neural network computing is realized.

[0107] Therefore, coarse-grained initialization is performed in the coarse-grained processing unit, and fine-grained decoupling is performed in the fine-grained processing unit. The fine-grained initialization flow information after decoupling is then processed in a fine-grained manner. Each initialization flow path operates in parallel. Through the initialization flow path of this embodiment, it is ensured that most components can perform initialization operations according to the coarse-grained and fine-grained calculation state requirements, thereby improving the efficiency of calculation and the correctness of results.

[0108] In one exemplary embodiment, the central processing unit 301 is also configured to output control flow information;

[0109] like Figure 4 As shown, the processing unit array interface 302 is also used to receive control flow information through the first layer control flow path 401, decouple the control flow information to obtain coarse-grained control flow information and fine-grained control flow information, and distribute them.

[0110] The processing unit array controller 303 is also used to receive coarse-grained control flow information from the processing unit array interface 302 through the first control flow path 402 of the second layer, and preprocess the coarse-grained control flow information so that the coarse-grained processing unit can perform coarse-grained processing on the preprocessed coarse-grained control flow information.

[0111] The Boolean processing array interface 304 is also used to receive fine-grained control flow information from the processing unit array interface 302 through the second control flow path 403 of the second layer, and to decouple and distribute the fine-grained control flow information at the granular level so that the fine-grained processing unit can perform fine-grained processing on the fine-grained control flow information.

[0112] For example, when the system is used for neural network computation, control flow information is issued from the central processing unit 301 and transmitted to the processing unit array interface 302 through the first-layer control flow path 401. The control flow information enters the processing unit array interface 302, achieving initial decoupling between coarse and fine granularity, dividing into coarse-grained control flow information and fine-grained control flow information. These are then transmitted to the processing unit array controller 303 through the first control flow path 402 of the second layer, and to the Boolean processing array interface 304 through the second control flow path 403 of the second layer, respectively. In the coarse-grained processing unit 201, the processing unit array controller 303 preprocesses the coarse-grained control flow information to ensure the overall coordination of the coarse-grained control flow, enabling the coarse-grained processing unit 201 to perform coarse-grained computation. In the fine-grained processing unit 202, the fine-grained control flow information enters the Boolean processing array interface 304, which performs a second, finer-grained decoupling and subsequent component information distribution operations, enabling the fine-grained processing unit 202 to perform fine-grained computation.

[0113] Furthermore, referring to Figure 4 The fine-grained processing unit also includes an instruction allocation unit 404, a Boolean processing array data transmission unit 405, and a Boolean processing array crossbar switch unit 406. Wherein:

[0114] Instruction allocation unit 404 is used to schedule fine-grained control flow information according to scheduling information;

[0115] Boolean processing array data transmission unit 405 is used to perform data transmission with coarse-grained processing unit 201;

[0116] The Boolean processing array cross switch unit 406 is used for data transfer between the Boolean processing array shared memory 310 and the Boolean processing array 309.

[0117] The two ends of the first control flow path 407 of the third layer are respectively connected to the control flow output terminal of the processing unit array controller 303 and the control flow input terminal of the coarse-grained reconfigurable architecture core unit 308;

[0118] The two ends of the second control flow path 408 of the third layer are respectively connected to the first control flow output terminal of the Boolean processing array interface 304 and the control flow input terminal of the Boolean processing array cross switch unit 406;

[0119] The two ends of the third control flow path 409 of the third layer are respectively connected to the second control flow output end of the Boolean processing array interface 304 and the control flow input end of the Boolean processing array data transmission unit 405;

[0120] The two ends of the fourth control flow path 410 of the third layer are respectively connected to the third control flow output terminal of the Boolean processing array interface 304 and the control flow input terminal of the instruction allocation unit 404.

[0121] Furthermore, referring to Figure 4 The coarse-grained processing unit 201 further includes a processing unit array data transmission unit 411, a processing unit array crossbar switch unit 412, a processing unit array configuration direct memory 413, and a processing unit array data direct memory 414. The fine-grained processing unit 202 further includes a Boolean processing array configuration unit 415. Wherein:

[0122] The processing unit array data transmission unit 411 is used to perform data transmission with the Boolean processing array data transmission unit 405;

[0123] The crossbar switch unit 412 of the processing unit array is used for data transmission between the shared memory of the processing unit array and the processing unit array of the coarse-grained reconfigurable architecture core unit 308;

[0124] The processing unit array is configured with direct memory access 413 to pull the configuration stream of hierarchical memory;

[0125] Processing unit array data direct memory access 414 is used to transfer data between hierarchical memory and processing unit array shared memory.

[0126] The two ends of the first control flow path 416 of the fourth layer are respectively connected to the first control flow output end of the coarse-grained reconfigurable architecture core unit 308 and the control flow input end of the processing unit array data transmission unit 411;

[0127] The two ends of the second control flow path 417 of the fourth layer are respectively connected to the second control flow output terminal of the coarse-grained reconfigurable architecture core unit 308 and the control flow input terminal of the processing unit array cross switch unit 412;

[0128] The two ends of the third control flow path 418 of the fourth layer are respectively connected to the third control flow output of the coarse-grained reconfigurable architecture core unit 308 and the control flow input of the processing unit array configuration direct memory access 413;

[0129] The two ends of the fourth control flow path 419 of the fourth layer are respectively connected to the fourth control flow output end of the coarse-grained reconfigurable architecture core unit 308 and the control flow input end of the processing unit array data direct memory access 414;

[0130] The two ends of the fifth control flow path 420 of the fourth layer are respectively connected to the fifth control flow output terminal of the coarse-grained reconfigurable architecture core unit 308 and the control flow input terminal of the Boolean processing array configuration unit 415;

[0131] The two ends of the sixth control flow path 421 of the fourth layer are respectively connected to the control flow output terminal of the instruction allocation unit 404 and the control flow input terminal of the Boolean processing array 309.

[0132] For example, after the processing unit array controller 303 performs the initial operation on the coarse-grained control flow information, the coarse-grained control flow information enters the coarse-grained reconfigurable architecture core unit 308, where it performs further coarse-grained calculations through its computing unit, and feeds back the controller's control flow to other components through the control flow path of the fourth layer. At the same time, the PE computing unit generates new control flow and distributes it to the various components of the last layer, including storage and information acquisition components, through the control flow path of the fourth layer.

[0133] The Boolean processing array interface 304 in the fine-grained processing unit 202 determines whether the flow is to storage control, computation control, or interconnect control based on the type of fine-grained control flow information. If it is storage control, the fine-grained control flow is transmitted to the Boolean processing array cross-connect unit 406 through the second control flow path 408 of the third layer, realizing data transmission between the shared memory of the Boolean processing array and the Boolean processing array. If it is computation control, the fine-grained control flow is transmitted to the instruction allocation unit 404 through the fourth control flow path 410 of the third layer, and the fine-grained control flow information is transmitted to the Boolean processing array 309 for fine-grained computation according to the instruction allocation situation. If it is interconnect control, the fine-grained control flow is transmitted to the Boolean processing array data transmission unit 405 through the third control flow path 409 of the third layer, for data transmission with the coarse-grained processing unit 201.

[0134] In the fine-grained processing unit 202, the Boolean processing array configuration unit 415 receives feedback information from the controller 303 and new control flow generated by the PE calculation unit from the coarse-grained reconfigurable architecture core unit 308 through the fifth control flow path 420 of the fourth layer; the Boolean processing array 309 receives fine-grained control flow information from the instruction allocation unit 404 through the sixth control flow path 421 of the fourth layer and performs fine-grained calculations on it.

[0135] Within the coarse-grained processing unit 201, the processing unit array data transmission unit 416 receives feedback information and new control flow information generated by the PE calculation unit from the coarse-grained reconfigurable architecture core unit 308 through the first control flow path 416 of the fourth layer, and performs data transmission with the Boolean processing array data transmission unit 405. The processing unit array cross switch unit 412 receives feedback information and new control flow information generated by the PE calculation unit from the coarse-grained reconfigurable architecture core unit 308 through the second control flow path 417 of the fourth layer, realizing data transmission between the shared memory of the processing unit array and the processing unit array of the coarse-grained reconfigurable architecture core unit 308. The processing unit array configuration direct memory access 413 receives feedback information and new control flow information generated by the PE calculation unit from the coarse-grained reconfigurable architecture core unit 308 through the third control flow path 418 of the fourth layer; the processing unit array data direct memory access 414 receives feedback information and new control flow information generated by the PE calculation unit from the coarse-grained reconfigurable architecture core unit 308 through the fourth control flow path 419 of the fourth layer, performing data transmission between the hierarchical memory and the shared memory of the processing unit array.

[0136] Therefore, by using the above-mentioned hierarchical control flow path to achieve the transmission of control flow information, and with each layer of control flow path operating in parallel, the accuracy of the flow direction, the correctness of the control timing and results are guaranteed, and the control efficiency is improved.

[0137] In one exemplary embodiment, the system further includes multiple layers of configuration paths. Each layer of configuration paths operates in parallel. For example... Figure 5 As shown, the coarse-grained processing unit also includes hierarchical memory 501 for storing configuration stream information.

[0138] The coarse-grained processing unit 201 is also used to receive coarse-grained configuration stream information from the hierarchical memory through the first configuration flow path 502 of the first layer, and to perform coarse-grained processing on the coarse-grained configuration stream information.

[0139] The fine-grained processing unit 202 is also used to receive fine-grained configuration stream information through the second configuration flow path 503 of the first layer, and to perform fine-grained processing on the fine-grained configuration stream information.

[0140] Furthermore, referring to Figure 5 The processing unit array configuration direct memory access 302 is also used to obtain coarse-grained configuration flow information of hierarchical memory 501 from the first configuration flow path 502 of the first layer; the Boolean processing array configuration unit 415 is also used to obtain and store fine-grained configuration flow information from the second configuration flow path 503 of the first layer.

[0141] Reference Figure 5The coarse-grained reconfigurable architecture core unit 308 is also used to receive coarse-grained configuration stream information from the configuration stream output of the processing unit array configuration direct memory access 302 through the first configuration stream path 504 of the second layer, and perform coarse-grained calculations on it; the instruction allocation unit 404 is also used to receive fine-grained configuration stream information from the configuration stream output of the Boolean processing array configuration unit 415 through the second configuration stream path 505 of the second layer, and schedule the fine-grained configuration stream information according to the scheduling information.

[0142] Furthermore, referring to Figure 5 The processing unit array controller is further configured to receive coarse-grained configuration stream information from the configuration stream output of the coarse-grained reconfigurable architecture core unit 308 through the first configuration stream path 506 of the third layer, and preprocess it so that the coarse-grained processing unit 201 can perform coarse-grained processing on the preprocessed coarse-grained configuration stream information; the Boolean processing array is further configured to receive fine-grained configuration stream information from the first configuration stream output of the instruction allocation unit 404 through the second configuration stream path 507 of the third layer, and perform fine-grained calculation on it; the fine-grained processing unit also includes an interconnection network 509, which is configured to receive fine-grained configuration stream information from the second configuration stream output of the instruction allocation unit 404 through the third configuration stream path 508 of the third layer, and transmit it as a data stream across the Boolean processing array.

[0143] The configuration flow path is divided into two categories vertically and three layers horizontally. The role of the configuration flow information is to realize the specific execution content of the component's execution state.

[0144] For example, through the first-layer configuration flow paths 502 and 503, the configuration flow information of the hierarchical memory 501 flows to the Boolean processing array configuration unit 415 and the processing unit array configuration direct memory access 302, respectively, thereby achieving decoupling of coarse and fine configuration flows. Through the second-layer configuration flow paths 504 and 505, the configuration flow in the coarse-grained processing unit 201 enters the coarse-grained reconfigurable architecture core unit 308 to first change the computation mode of the PE. In the fine-grained processing unit 202, the decoupled fine-grained configuration flow enters the instruction allocation unit 404 to implement the instructions and configuration. Through the third-layer configuration flow paths 506, 507, and 508, the subsequent configuration generated by the coarse-grained reconfigurable architecture core unit 308 is fed back to the processing unit array controller 303 to realize the overall configuration operation; the instruction allocation unit 404 ensures the spatiotemporal distribution of instructions for the PE on the Boolean processing array 309, and simultaneously configures the computing array interconnection network to realize data communication across the Boolean processing array.

[0145] Thus, by configuring the data path of the hierarchical flow, coarse-grained and fine-grained paths are separated, thereby improving configuration efficiency.

[0146] In a specific example, the overall architecture of the system is as follows: Figure 6 As shown, this architecture is characterized by its ability to achieve parallel computing at both fine and coarse granularities, and its reconfigurable nature makes the computation process controllable and flexible. The architecture is mainly divided into two parts: a fine-grained computing unit 202 (BPA Unit) using a Boolean processing array and a coarse-grained computing unit 201 (CGRA Unit) using a CGRA. The BPA Unit is responsible for fine-grained task operations, and the CGRA Unit is responsible for coarse-grained task operations.

[0147] Reference Figure 6 Different colored lines represent the flow paths of different information flows. Between components, blue lines represent control flow paths, green lines represent configuration flow paths, red lines represent initialization flow paths, and black lines represent data flow paths. Figure 6 In the diagram, the numbers next to the lines indicate specific information flow paths. Each initialization flow path operates in parallel, each control flow path operates in parallel, and each configuration flow path operates in parallel. Initialization information is processed layer by layer through multiple initialization flow paths, control information is processed layer by layer through multiple control flow paths, and configuration information is processed layer by layer through multiple configuration flow paths. Each layer of processing represents the same step of operation. As shown in the diagram, the first initialization flow path 305 indicates that initialization flow information is generated from the central processing unit (CPU) and sent to the processing unit array interface; this step is the first step of initialization.

[0148] Structurally, in Figure 6The right half of the structure houses the CGRA Unit. The Processing Element Array (PEA) interface is used for decoupling information flow. PEA configuration direct memory access is used to retrieve configuration streams from hierarchical memory, and PEA data direct memory access is used to transfer data between hierarchical memory and the shared memory of the PEA. The Boolean Processing Array cross-switch unit is used to transfer data between the Boolean Processing Array (PEA) and its shared memory. The PEA controller can control most of the CGRA Unit components and some BPA Unit components. The coarse-grained reconfigurable architecture core unit (CGRA Core) 308 mainly includes Processing Element Arrays (PEA), Global Register Files for global storage, and Configuration Memory for storing configuration streams. There are four PEAs, each containing 4×4 PE (Processing Element) computation units for coarse-grained computation. PEA configuration direct memory access uses internal DMA to receive the corresponding configuration stream information, stores it in CFGRegs, and checks the internal configuration status through StatusRegs. The data transmission unit of the processing unit array can realize data exchange with the BPA Unit. Its internal components mainly consist of a FIFO for storage and a MUX for determining the output direction.

[0149] The Boolean processing array within the BPA Unit is used for fine-grained computation and contains 4×4 fine-grained boolean processing elements (bPEs). An inter-connect network is used for data flow transmission across the Boolean processing arrays. An instruction allocation unit is responsible for matching configuration flows and scheduling control flows based on scheduling information. A Boolean processing array data transmission unit is used for data transmission with the PEA. The Boolean processing array shared memory is used to store bPE data. A Boolean processing array cross-connect unit enables data transmission between the Boolean processing arrays and their shared memory.

[0150] It should be noted that, Figures 3 to 6 The schematic diagram of the pathways between the components is a simplified illustration, showing only the initialization, control, and configuration pathways between the corresponding components, and is not limited to simple connections between the components. Therefore, in practical applications, these pathways may include other components such as registers to implement information flow transmission functions.

[0151] For example, adopt Figure 6The hybrid granularity reconfigurable computing system shown first stores the image in hierarchical memory when performing image convolution calculations. Then, it configures the functions and information transmission paths of each component through multi-layered configuration flow paths, performs hierarchical initialization settings for each component through multi-layered initialization flow paths, and sets instructions for each component through multi-layered control flow paths. Next, it performs coarse-to-fine granular data transmission, with each component executing its pre-defined tasks, including multiplication and accumulation operations. After the calculation is complete, the result is output. Flexible configuration of processing elements and data transmission paths enables efficient parallel computing. Compared to CGRA, it can complete image convolution tasks faster, meeting the needs of applications with high real-time requirements, such as real-time image recognition systems.

[0152] This application improves computational efficiency by setting up control paths, configuring paths, and initializing paths, thereby ensuring the synchronization of the computation process and the correctness of information flow guidance. It is applicable to fields such as digital large-scale integrated circuits, information paths, Boolean Processors, CGRA, and computer architecture.

[0153] In summary, by implementing the path design of control flow, configuration flow, and initialization flow, the separation and coordinated flow of coarse and fine-grained information flow paths are achieved. This allows components of different granularity units to receive information flow that matches their own granularity, thereby reducing the need for components to decouple and distinguish the granularity of information flow. They only need to receive information of the corresponding granularity, reducing the bandwidth overhead of the component ports of each component's information flow, thus reducing power consumption and mitigating the problem of reduced computing power due to heat. Therefore, it can improve the computing speed.

[0154] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this application.

[0155] The embodiments described above are merely illustrative of several implementation methods of this application, and while the descriptions are specific and detailed, they should not be construed as limiting the scope of this patent application. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of this application, and these all fall within the protection scope of this application. Therefore, the protection scope of this application should be determined by the appended claims.

Claims

1. A hybrid granularity reconfigurable computing system, characterized in that, The system includes a fine-grained processing unit, a coarse-grained processing unit, a multi-layer control flow path, and a multi-layer initialization flow path. The coarse-grained processing unit is used to decouple control flow information into coarse-grained control flow information and fine-grained control flow information, perform coarse-grained processing on the coarse-grained control flow information, and transmit the fine-grained control flow information to the fine-grained processing unit through the control flow path. The coarse-grained processing unit is further configured to decouple the initialization stream information into coarse-grained initialization stream information and fine-grained initialization stream information, perform coarse-grained processing on the coarse-grained initialization stream information, and transmit the fine-grained initialization stream information to the fine-grained processing unit through the initialization stream path. The fine-grained processing unit is used to receive fine-grained control flow information through the control flow path, receive fine-grained initialization flow information through the initialization flow path, and perform fine-grained processing on the fine-grained control flow information and the fine-grained initialization flow information respectively.

2. The system according to claim 1, characterized in that, The coarse-grained processing unit includes: The central processing unit is used to output initialization stream information; The processing unit array interface is used to receive the initialization flow information through the first-layer initialization flow path, decouple the initialization flow information to obtain coarse-grained initialization flow information and fine-grained initialization flow information, and distribute them; The processing unit array controller is used to receive the coarse-grained initialization stream information through the first initialization stream path of the second layer, and preprocess the coarse-grained initialization stream information so that the coarse-grained processing unit can perform coarse-grained processing on the preprocessed coarse-grained initialization stream information. The fine-grained processing unit includes: A Boolean processing array interface is used to receive the fine-grained initialization stream information through the second initialization stream path of the second layer, and to decouple and distribute the fine-grained initialization stream information at the granular level so that the fine-grained processing unit can perform fine-grained processing on the fine-grained initialization stream information.

3. The system according to claim 2, characterized in that, The coarse-grained processing unit also includes a coarse-grained reconfigurable architecture core unit; The fine-grained processing unit further includes: Boolean processing arrays are used for fine-grained computations. The Boolean processing array shares memory for storing the data of the Boolean processing array; The two ends of the first initialization flow path of the third layer are respectively connected to the initialization flow output terminal of the processing unit array controller and the initialization flow input terminal of the coarse-grained reconfigurable architecture core unit; The two ends of the second initialization stream path of the third layer are respectively connected to the first initialization stream output end of the Boolean processing array interface and the initialization stream input end of the Boolean processing array shared memory; The two ends of the third initialization stream of the third layer are respectively connected to the second initialization stream output of the Boolean processing array interface and the initialization stream input of the Boolean processing array.

4. The system according to claim 3, characterized in that, The central processing unit is also used to output control flow information; The processing unit array interface is also used to receive control flow information from the central processing unit through the first layer control flow path, decouple the control flow information to obtain coarse-grained control flow information and fine-grained control flow information, and distribute them. The processing unit array controller is further configured to receive coarse-grained control flow information from the processing unit array interface through the first control flow path of the second layer, and preprocess the coarse-grained control flow information so that the coarse-grained processing unit can perform coarse-grained processing on the preprocessed coarse-grained control flow information. The Boolean processing array interface is also used to receive fine-grained control flow information from the processing unit array interface through the second control flow path of the second layer, and to decouple and distribute the fine-grained control flow information at the granular level so that the fine-grained processing unit can perform fine-grained processing on the fine-grained control flow information.

5. The system according to claim 4, characterized in that, The fine-grained processing unit further includes: The instruction allocation unit is used to schedule fine-grained control flow information according to the scheduling information; A Boolean processing array data transmission unit is used to perform data transmission with the coarse-grained processing unit; A Boolean processing array cross switch unit is used for data transmission between the shared memory of the Boolean processing array and the Boolean processing array; The two ends of the first control flow path of the third layer are respectively connected to the control flow output terminal of the processing unit array controller and the control flow input terminal of the coarse-grained reconfigurable architecture core unit; The two ends of the second control flow path of the third layer are respectively connected to the first control flow output terminal of the Boolean processing array interface and the control flow input terminal of the Boolean processing array cross switch unit; The two ends of the third control flow path of the third layer are respectively connected to the second control flow output terminal of the Boolean processing array interface and the control flow input terminal of the Boolean processing array data transmission unit; The two ends of the fourth control flow path of the third layer are respectively connected to the third control flow output terminal of the Boolean processing array interface and the control flow input terminal of the instruction allocation unit.

6. The system according to claim 5, characterized in that, The coarse-grained processing unit further includes: A processing unit array data transmission unit is used to perform data transmission with the Boolean processing array data transmission unit; The processing unit array cross switch unit is used for data transmission between the shared memory of the processing unit array and the processing unit array of the core unit of the coarse-grained reconfigurable architecture. The processing unit array is configured with direct memory access to pull configuration streams from hierarchical memory; Direct memory access to the processing unit array is used to transfer data between the hierarchical memory and the shared memory of the processing unit array. The fine-grained processing unit further includes: A Boolean processing array configuration unit is used to store the configuration information of the fine-grained computing unit; The two ends of the first control flow path of the fourth layer are respectively connected to the first control flow output end of the coarse-grained reconfigurable architecture core unit and the control flow input end of the processing unit array data transmission unit; The two ends of the second control flow path of the fourth layer are respectively connected to the second control flow output terminal of the coarse-grained reconfigurable architecture core unit and the control flow input terminal of the processing unit array cross switch unit; The two ends of the third control flow path of the fourth layer are respectively connected to the third control flow output of the coarse-grained reconfigurable architecture core unit and the control flow input of the processing unit array configured with direct memory access; The two ends of the fourth control flow path of the fourth layer are respectively connected to the fourth control flow output of the coarse-grained reconfigurable architecture core unit and the control flow input of the processing unit array data direct memory access; The two ends of the fifth control flow path of the fourth layer are respectively connected to the fifth control flow output terminal of the coarse-grained reconfigurable architecture core unit and the control flow input terminal of the Boolean processing array configuration unit; The two ends of the sixth control flow path of the fourth layer are respectively connected to the control flow output terminal of the instruction allocation unit and the control flow input terminal of the Boolean processing array.

7. The system according to claim 1, characterized in that, The system further includes multi-layer configuration flow paths, and the coarse-grained processing unit further includes: Hierarchical memory is used to store configuration stream information; The coarse-grained processing unit is further configured to receive coarse-grained configuration stream information from the hierarchical memory through the first configuration flow path of the first layer, and perform coarse-grained processing on the coarse-grained configuration stream information. The fine-grained processing unit is further configured to receive fine-grained configuration stream information through the second configuration flow path of the first layer, and to perform fine-grained processing on the fine-grained configuration stream information.

8. The system according to claim 7, characterized in that, The coarse-grained processing unit further includes: The processing unit array is configured with direct memory access for obtaining coarse-grained configuration flow information of the layer memory from the first configuration flow path of the first layer; The fine-grained processing unit further includes: Boolean processing array configuration unit, used to obtain and store fine-grained configuration stream information from the second configuration stream path of the first layer.

9. The system according to claim 8, characterized in that, The coarse-grained processing unit further includes: The coarse-grained reconfigurable architecture core unit is used to receive coarse-grained configuration stream information from the configuration stream output terminal of the direct memory access configuration of the processing unit array through the first configuration stream path of the second layer, and to perform coarse-grained calculations on it. The fine-grained processing unit further includes: The instruction allocation unit is used to receive fine-grained configuration stream information from the configuration stream output of the Boolean processing array configuration unit through the second configuration stream path of the second layer, and to schedule the fine-grained configuration stream information according to the scheduling information.

10. The system according to claim 9, characterized in that, The coarse-grained processing unit further includes: The processing unit array controller is used to receive coarse-grained configuration stream information from the configuration stream output terminal of the coarse-grained reconfigurable architecture core unit through the first configuration stream path of the third layer, and preprocess it so that the coarse-grained processing unit can perform coarse-grained processing on the preprocessed coarse-grained configuration stream information. The fine-grained processing unit further includes: A Boolean processing array is used to receive fine-grained configuration stream information from the first configuration stream output of the instruction allocation unit through the second configuration stream path of the third layer, and to perform fine-grained calculations on it. An interconnected network is used to receive fine-grained configuration stream information from the second configuration stream output of the instruction allocation unit through the third configuration stream path of the third layer, and to transmit it as a data stream across the Boolean processing array.

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