Large-scale FPGA wiring method based on virtual division

Abstract

A large-scale FPGA (Field Programmable Gate Array) wiring method based on virtual division relates to the technical field of integrated circuit design, and mainly comprises the following steps: carrying out abstract modeling on FPGA physical layer resources to construct a virtual layer model; executing global wiring calculation on the virtual layer to generate a virtual layer logic path; deconstructing and mapping the resources on the logic path into physical layer resources; and carrying out physical layer wiring calculation on the physical layer resources deconstructed and mapped on the logic path. According to the method, through reasonable abstract modeling of physical layer resources and multi-layer wiring calculation, the defects of long wiring time, overlarge memory occupation and low efficiency in large-scale FPGA design are overcome, the wiring efficiency is improved, meanwhile, the wiring time and memory consumption are effectively reduced, and the iterative optimization overhead in the prior art is effectively reduced.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of integrated circuit design, and particularly relates to a large-scale FPGA wiring method based on virtual division. BACKGROUND

[0002] With the rapid development of FPGA technology, its scale is constantly expanding, and the challenges faced in the wiring stage are increasingly significant. Traditional FPGA wiring methods often consume a large amount of computing resources and time when dealing with large-scale integrated circuit design, and are difficult to meet the requirements of modern integrated circuit design for efficiency and performance. In particular, in the wiring process, the problems of net congestion, long wiring time and excessive memory occupation seriously restrict the efficiency of the entire wiring process.

[0003] In view of these challenges, researchers have proposed a series of improvement schemes. Among these methods, the path exploration algorithm centered on congestion negotiation is widely used in FPGA wiring due to its effectiveness. However, this algorithm still faces some significant limitations when dealing with large-scale designs: first, multiple iterations are needed to solve wiring resource conflicts; second, new wiring conflicts may be introduced in each iteration process, limiting the optimization effect. Therefore, how to realize efficient wiring of large-scale FPGA design while considering the wiring effect has become a key technical problem to be solved in the current integrated circuit field.

[0004] Several invention patents have been disclosed to improve the efficiency of large-scale FPGA wiring and reduce memory occupation, such as:

[0005] CN113657067A proposes a multi-strategy optimization-based super-large-scale integrated circuit multi-layer overall wiring method, which significantly improves the wiring capacity utilization and efficiency through dynamic adjustment of virtual capacity, adaptive expansion of wiring sub-region, and A* algorithm heuristic search strategies. Compared with the traditional Manhattan structure, this method uses an X-type grid and adds 45° and 135° winding directions to optimize the wiring result and avoid local optimal problems. However, it may increase the computational complexity when dealing with highly dense circuits, and the actual performance is affected by chip architecture and design constraints, which needs further verification of its stability and universality.

[0006] CN114065694A proposes a compression method for FPGA routing resource graphs. This method progressively compresses the initial multi-layered graph (DevGraph) into a single-layered two-dimensional graph (OneLayerGraph) to reduce problem size and optimize router runtime. This approach simplifies the graph structure through systematic operations on connectivity, driving attributes, and coordinate system transformations, resulting in faster and more accurate congestion assessment, which is beneficial for subsequent placement and detailed routing. While this compression method significantly accelerates congestion assessment and optimizes routing time, its reliance on complex transformations of the graph structure and coordinate system may increase computational complexity during initial design. Its general applicability requires further verification.

[0007] In summary, existing cabling technologies have the following drawbacks:

[0008] (i) Existing FPGA global routing algorithms have problems such as large mapping scale, large memory resource consumption and long routing time when dealing with large-scale designs, which seriously affect routing efficiency.

[0009] (ii) Existing FPGA routing technology performs indiscriminate global traversal adjustment of all signal types and routing resources, resulting in low efficiency of logic path optimization and increased routing iteration overhead due to redundant adjustment of non-logic paths. Summary of the Invention

[0010] Based on the above problems, the purpose of this invention is to provide a new routing method to solve the defects of long routing time, excessive memory consumption and low efficiency in large-scale FPGA design, improve routing efficiency, and effectively reduce routing time and memory consumption.

[0011] The technical solution adopted by this invention to achieve its objective is a large-scale FPGA routing method based on virtual partitioning, comprising the following steps:

[0012] S1. Abstract and model the FPGA physical layer resources to construct a virtual layer model. The physical layer resources include logic units (LC) and physical interconnects (Link). The virtual layer model includes virtual blocks (VB) and virtual interconnects (VL).

[0013] S2. Perform global routing calculations in the virtual layer to generate a virtual layer logical path, wherein the logical path is the shortest path between the virtual block VB where the signal origin is located and the virtual block VB where the signal destination is located.

[0014] S3. Deconstruct and map resources on the logical path to physical layer resources;

[0015] S4, performing physical layer routing calculation on the mapped physical layer resources decomposed on the logical path, that is, calculating the shortest path between the logical unit LC where the signal starting point is located and the logical unit LC where the signal ending point is located.

[0016] Further, the rules of the abstract modeling are as follows: the virtual block VB is obtained by aggregating the same type and same area logical units LC, the physical interconnection line Link group between adjacent virtual blocks VB is abstracted as a virtual interconnection line VL, and the virtual interconnection line VL capacity value is equal to the number of contained physical interconnection lines Link.

[0017] Further, the method for generating the virtual layer logical path in the step S2 is a shortest path tree algorithm.

[0018] Further, after performing the global routing calculation in the virtual layer, it is further judged whether the virtual interconnection line VL capacity is overloaded, if yes, returning to the step S2 to re-perform the global routing calculation in the virtual layer, if not, outputting the virtual layer routing result.

[0019] Further, after performing the physical layer routing calculation on the mapped physical layer resources decomposed on the logical path, it is further performed resource conflict verification on the routing result to judge whether there is a conflict line network;

[0020] If there is no conflict line network, the final routing result is outputted;

[0021] If there is a conflict line network, the conflict line network is disassembled and the physical layer routing is re-performed, and then the resource conflict verification is performed again to judge whether there is a conflict line network, if yes, returning to the step S2 to re-perform the global routing calculation in the virtual layer, if not, outputting the final routing result.

[0022] The beneficial effects of the present application are as follows:

[0023] By reasonably abstract modeling the physical layer resources and multi-level routing calculation, that is, firstly performing routing in the virtual layer to generate the shortest path between the virtual block VB where the signal starting point is located and the virtual block VB where the signal ending point is located, and then performing routing on the physical layer only on the mapped physical layer resources decomposed on the logical path, without indiscriminately performing global traversal adjustment on the FPGA, the routing efficiency is greatly improved, and the routing time and memory consumption are effectively reduced. If the routing effect is not as expected, the routing in the virtual layer is re-performed to guide the physical layer, and the iteration optimization overhead in the prior art is effectively reduced. BRIEF DESCRIPTION OF DRAWINGS

[0024] Figure 1 It is a schematic diagram of the FPGA physical layer resources of the embodiment of the present application;

[0025] Figure 2This is an abstract modeling diagram of an embodiment of the present invention;

[0026] Figure 3 This is a schematic diagram of the virtual layer abstract resource in an embodiment of the present invention;

[0027] Figure 4 This is a schematic diagram of the virtual layer routing results in an embodiment of the present invention;

[0028] Figure 5 This is a schematic diagram of resource expansion and physical layer routing results in an embodiment of the present invention;

[0029] Figure 6 This is a schematic diagram of the overall process of an embodiment of the present invention. Detailed Implementation

[0030] To better understand the above-mentioned objectives, features, and advantages of the present invention, the present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments.

[0031] Figure 6 This invention illustrates a specific implementation of a large-scale FPGA routing method based on virtual partitioning, comprising the following steps:

[0032] S1. Abstract and model the FPGA physical layer resources to construct a virtual layer model. The physical layer resources include logic units (LC) and physical interconnects (Link). The virtual layer model includes virtual blocks (VB) and virtual interconnects (VL).

[0033] like Figure 1 As shown, in this embodiment, the physical layer resources include 16 logical units and their physical interconnects. Logical unit LC101 is the signal start point, logical units LC102 and LC103 are the signal end points, and Link104, Link105, and Link106 are physical interconnect resources. Logical units of the same type and in the same region are aggregated into virtual blocks, i.e., LC groups (LC_X1Y1, LC_X1Y2, LC_X2Y1, LC_X2Y2) are aggregated into virtual block VB1 (see...). Figure 2 Virtual blocks VB2, VB3, and VB4 are constructed according to the same rules. For example... Figure 2 The abstract modeling method for the physical interconnects between virtual blocks is as follows:

[0034] Physical interconnects Link 104 (2 lines) are mapped to virtual interconnects VL 204 (capacity = 2);

[0035] Physical interconnects Link 105 (3 lines) are mapped to virtual interconnects VL 205 (capacity = 3);

[0036] The physical interconnection line Link 106 (2 lines) is mapped to the virtual interconnection line VL 206 (capacity = 2);

[0037] The final abstract modeling diagram is shown in FIG. 4, in which: the signal starting point corresponds to VB1, and the signal ending point corresponds to VB3 and VB4. Figure 3

[0038] S2, performing global routing calculation at the virtual layer, and generating a virtual layer logic path by using a shortest path tree algorithm, the logic path being the shortest path between the virtual block VB where the signal starting point is located and the virtual block VB where the signal ending point is located; specifically, taking the virtual block VB1 as the starting point and the virtual blocks VB3 and VB4 as the ending points, a virtual layer logic path is generated by using a shortest path tree algorithm; as shown in FIG. 5, the logic path obtained contains the virtual interconnection lines VL 401 and VL 402. Figure 4

[0039] After the global routing calculation at the virtual layer, it is further determined whether the virtual interconnection line capacity is overloaded, if yes, returning to step S2 to perform global routing calculation at the virtual layer again, and if not, outputting the virtual layer routing result.

[0040] S3, mapping the resources on the logic path to physical layer resources;

[0041] Specifically, the objects of the mapping include VB1, VB3, VB4 and VL 401, VL 402 on the virtual layer logic path;

[0042] Physical resource expansion: as shown in FIG. 6, the signal starting point is the logic unit LC 501, and the signal ending point is the logic unit LC 502 and LC 503. Figure 5

[0043] S4, performing physical layer routing calculation on the physical layer resources mapped on the logic path, that is, calculating the shortest path between the logic unit LC 501 where the signal starting point is located and the logic unit LC 502 and LC 503 where the signal ending point is located. As shown in FIG. 7, the final physical layer routing between the signal starting point and the signal ending point contains the physical interconnection lines Link 504, Link 505, Link 507 and Link 509; the logic units LC 506 and LC 508 are also involved on the logic path (that is, the resources involved between the signal starting point LC 501 and the signal ending point LC 502) Figure 5

[0044] After the physical layer routing calculation on the physical layer resources mapped on the logic path, the routing result is further verified for resource conflict to determine whether there is a conflict line network.

[0045] If there is no conflict line network, the final routing result is outputted. ​​​​

[0046] If there is a conflict net, then the conflict net is disassembled and the physical layer is rewired, and resource conflict verification is performed again to determine whether there is a conflict net. If there is still a conflict net, then the process returns to step S2, and global routing calculation is performed again at the virtual layer. If there is no conflict net, then the final routing result is output.

Claims

1. A large-scale FPGA routing method based on virtual partitioning, characterized in that, The method comprises the following steps: S1, abstractly modeling FPGA physical layer resources, constructing a virtual layer model, the physical layer resources comprising logic cells LC and physical interconnection lines Link, the virtual layer model comprising virtual blocks VB and virtual interconnection lines VL; S2, performing global routing calculation in the virtual layer to generate a virtual layer logic path, the logic path being the shortest path between the virtual block VB where the signal starting point is located and the virtual block VB where the signal ending point is located; S3, mapping the resources on the logic path to the physical layer resources; S4, performing physical layer routing calculation on the physical layer resources mapped on the logic path, i.e. calculating the shortest path between the logic cell LC where the signal starting point is located and the logic cell LC where the signal ending point is located.

2. The method of claim 1, wherein, The rules of the abstract modeling are as follows: the virtual block VB is obtained by aggregating logic cells LC of the same type and in the same region, the group of physical interconnection lines Link between adjacent virtual blocks VB is abstracted into a virtual interconnection line VL, and the capacity value of the virtual interconnection line VL is equal to the number of the physical interconnection lines Link contained.

3. The method of claim 1, wherein: The method for generating the virtual layer logic path in step S2 is the shortest path tree algorithm.

4. The method of claim 1, wherein: After performing the global routing calculation in the virtual layer, it is further determined whether the capacity of the virtual interconnection line VL is overloaded, if yes, returning to step S2 to perform the global routing calculation in the virtual layer again, if no, outputting the virtual layer routing result.

5. The method of claim 1, wherein: After performing the physical layer routing calculation on the physical layer resources mapped on the logic path, it is further determined whether there is a conflict line network in the routing result; if no, outputting the final routing result; if yes, performing disconnection of the conflict line network and performing the physical layer routing calculation again, then performing the resource conflict verification again, if there is still a conflict line network, returning to step S2 to perform the global routing calculation in the virtual layer again, if there is no conflict line network, outputting the final routing result.

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