An artificial intelligence-based communication chip layout defect automatic identification method

Abstract

This invention discloses an automatic defect identification method for communication chip layout based on artificial intelligence, comprising the following steps: parsing the communication chip layout design file; performing design rule checks and parameter extraction; constructing an improved NCA model and completing state initialization, generating a fast-scale update parameter set and a slow-scale update parameter set; performing iterative evolution based on the fast-scale update parameter set and the slow-scale update parameter set, outputting an intermediate representation set; conditionally modulating the update function of the improved NCA model; constructing a graph neural network topology consistency verification mechanism, generating a set of verified defect regions; performing defect discrimination and labeling, outputting a set of defect types, a defect distribution heatmap, and a set of defect coordinates. This invention improves the accuracy of communication chip layout defect identification and enhances cross-layer connectivity verification capabilities.

Description

Technical Field

[0001] This invention relates to the field of integrated circuit physical design, and in particular to an automatic identification method for layout defects in communication chips based on artificial intelligence. Background Technology

[0002] In the physical design of communication chips, automatic identification of layout defects is a crucial step in ensuring circuit performance and manufacturability. Current technologies primarily rely on design rule checks and image processing methods based on empirical rules for layout defect detection. These methods typically compare linewidths, spacing, via sizes, and connectivity using rule bases. However, as layout complexity and the number of layers increase, they tend to suffer from low detection efficiency, high false alarm rates, and insufficient adaptability to novel defects.

[0003] Furthermore, existing defect detection tools largely rely on static thresholds and single geometric rules for judgment, lacking the ability to model cross-layer topological relationships holistically. For the multi-layered interconnects and complex process constraints present in communication chips, traditional methods often fail to accurately capture the coupling relationship between local anomalies and global consistency, making it difficult to identify some defects in a timely manner. Simultaneously, existing methods lack refined output in defect localization and annotation, only providing rough violation alerts, which are insufficient to meet the needs of precise analysis and optimization.

[0004] Therefore, how to provide an automatic identification method for layout defects in communication chips based on artificial intelligence is a problem that urgently needs to be solved by those skilled in the art. Summary of the Invention

[0005] One objective of this invention is to propose an automatic defect identification method for communication chip layout based on artificial intelligence. This invention introduces an improved NCA model, combines a multi-layer image matrix set with a geometric topological constraint set for cell state evolution, utilizes a conditional variable set to modulate the update function to generate a candidate defect region set, and achieves cross-layer connectivity determination through a graph neural network topological consistency verification mechanism. Finally, it completes defect type labeling and coordinate heatmap output. This invention has the advantages of high identification accuracy, strong cross-layer topological consistency, and precise defect localization.

[0006] An automatic identification method for layout defects in communication chips based on artificial intelligence, according to an embodiment of the present invention, includes the following steps:

[0007] The layout design file of the communication chip is parsed, the layout data is transformed into a multi-layer image matrix set, and the geometric boundary set and inter-layer connection relationship diagram are extracted.

[0008] Based on a multi-layer image matrix set, design rule checks and parameter extraction are performed to generate a set of geometric topological constraints.

[0009] An improved NCA model was constructed and the state was initialized. The multi-layer image matrix set and the geometric topological constraint set were encoded into the cell state vector multi-channel input. The fast-scale update parameter set, the slow-scale update parameter set and the conditional variable set were initialized.

[0010] Based on the fast-scale and slow-scale parameter update sets, the cell state vector is iteratively evolved to generate an intermediate evolutionary representation set;

[0011] The update function of the improved NCA model is conditionally modulated using a set of conditional variables, and a set of candidate defect regions is generated by combining the set of evolutionary intermediate representations.

[0012] A graph neural network topology consistency verification mechanism is constructed. Taking the inter-layer connection graph and the candidate defect region set as input, the connectivity verification result set is calculated and the verified defect region set is output.

[0013] Based on the verified defect region set and geometric topological constraint set, defects are identified and labeled, generating a defect type set, a defect distribution heatmap, and a defect coordinate set.

[0014] Optionally, the generation of the multi-layer image matrix set, geometric boundary set, and inter-layer connection graph includes:

[0015] Receive the layout design file of the communication chip and parse the layer number, layer type and geometric shape data;

[0016] The geometric data is mapped to the corresponding layer according to the layer number, coordinate normalization and unit conversion are performed, each layer is converted into a two-dimensional image matrix and collected into a multi-layer image matrix set, including the metal layer image matrix, the via layer image matrix and the barrier layer image matrix.

[0017] Based on geometric shape data, the boundary is calculated, and line segment boundaries, arc segment boundaries, and polygon boundaries are extracted and merged into a set of geometric boundaries.

[0018] Based on the positional relationship between the via layer and the metal layer, the cross-layer contact area and connection path are detected, and an interlayer connection relationship diagram is constructed.

[0019] Optionally, the generation of the geometric topological constraint set includes:

[0020] Based on a multi-layer image matrix set, a process rule file is loaded and a rule set is generated, which includes line width rules, spacing rules, via diameter rules, and inter-layer connection rules.

[0021] Based on the metal layer image matrix, the centerline width is calculated around the geometric boundary set, and verification is performed according to the line width rules to generate line width parameters;

[0022] Based on the metal layer image matrix and the barrier layer image matrix, the minimum distance between adjacent geometric boundaries is calculated, and a verification is performed according to the spacing rules to generate spacing parameters.

[0023] Based on the through-hole layer image matrix, the geometric boundaries of the through-holes are identified and the equivalent diameter is calculated. Verification is performed according to the through-hole diameter rules to generate through-hole diameter parameters.

[0024] Based on the inter-layer connection graph, cross-layer connection paths are identified and connectivity checks are performed. Inter-layer connectivity parameters are generated according to the inter-layer connection rules.

[0025] By summarizing line width parameters, spacing parameters, through-hole diameter parameters, and inter-layer connectivity parameters, a set of geometric topological constraints is constructed.

[0026] Optionally, the construction of the improved NCA model includes:

[0027] Based on a multi-layer image matrix set and a geometric topological constraint set, the channel order and length of the multi-channel input of the cell state vector are determined.

[0028] The set of multi-layer image matrices is encoded into the image channels of the cell state vector multi-channel input, the set of geometric topological constraints is encoded into the parameter channels of the cell state vector multi-channel input, and coordinate alignment and scale normalization are performed.

[0029] An improved NCA model is constructed, in which the cell state vector is initialized with the initial values ​​of the multi-channel input of the cell state vector;

[0030] Initialize the fast-scale update parameter set, and configure the iteration step number, neighborhood perception range and update sparsity probability as parameter elements into the set;

[0031] Initialize the slow-scale update parameter set, and configure the weight coefficients and gating thresholds as parameter elements into the set;

[0032] Based on the layer number and the set of geometric topology constraints, construct the process layer identifier variable and the scalar code of the geometric topology constraint, and merge them to generate a set of conditional variables.

[0033] Optionally, the generation of the evolutionary intermediate representation set includes:

[0034] Based on a multi-layer image matrix set and a geometric boundary set, neighborhood features are extracted, and a fast-scale update parameter set and a slow-scale update parameter set are loaded to configure the update process of the cell state vector.

[0035] The neighborhood features represent the pixel value distribution, geometric boundary direction information, and local topological relationships within a preset neighborhood range around the current position of the cell state vector;

[0036] In the fast-scale update stage, the local neighborhood update is performed on the cell state vector using the neighborhood features and geometric boundary set as input, outputting and accumulating the local defect response map, while updating the cell state vector.

[0037] Specifically, within the current position of the cell state vector and its neighborhood, based on the iteration step number, neighborhood perception range, and update sparsity probability set by the fast-scale update parameter set, the cell state vector is sampled to determine the update position before each iteration according to the update sparsity probability. The pixel value distribution and geometric boundary direction information contained in the neighborhood features are extracted. The extracted neighborhood features are input into the local update function of the improved NCA model. The state change amount at each position in the neighborhood is calculated through the convolution kernel weights, and the state change amount is superimposed on the corresponding cell state vector channel to generate the updated cell state vector.

[0038] During the slow-scale update phase, the cell state vector is updated globally with the inter-layer connectivity graph as input, and the global topological consistency graph is output and accumulated, while the cell state vector is updated.

[0039] Specifically, before each slow-scale update, the weight coefficients and gating thresholds in the slow-scale update parameter set are loaded. Under the constraints of the inter-layer connectivity graph, cross-layer connectivity aggregation is performed on all cell state vectors. The global consistency value of each cell position is calculated by combining the inter-layer connectivity parameters in the geometric topology constraint set. The global consistency value is compared with the gating threshold to filter out low consistency positions. For the positions that pass the filtering, a global consistency correction term is added to the parameter channel of the cell state vector and written back to the updated cell state vector. The global consistency value obtained from each slow-scale update is normalized, mapped to image coordinates, and accumulated in the iterative order to form a global topological consistency graph.

[0040] After the fast-scale update phase and the slow-scale update phase are completed, the latest cell state vector, the local defect response map, and the global topological consistency map are combined. The multi-channel content of the latest cell state vector is used as the basic representation. The local defect response map and the global topological consistency map are aligned and mapped to the corresponding positions according to the spatial coordinates and layer numbers. The three inputs are normalized and fused based on the geometric topological constraint set to generate a three-dimensional tensor structure containing local defect sensitivity, global topological consistency index and cell state evolution trajectory. This three-dimensional tensor structure is used as the intermediate representation set for evolution.

[0041] Optionally, the generation of the candidate defect region set includes:

[0042] Establish a parameter binding relationship between the set of conditional variables and the update function of the improved NCA model, and inject the set of conditional variables into the weight coefficients, gate vectors and normalization factors of the update function;

[0043] The spatial coordinates and layer numbers of the intermediate evolutionary representation set are aligned with the original local defect response map and the original global topology consistency map. The pixel distributions of the intermediate evolutionary representation set, the original local defect response map, and the original global topology consistency map are then stitched together into a unified fusion feature tensor.

[0044] Using the fused feature tensor as input, the update function is called to calculate the defect response intensity under the modulation of the conditional variable set, and the defect confidence map is output.

[0045] Based on the process level identifier variable and geometric topology constraint scalar encoding in the conditional variable set, a segmentation threshold parameter is set, and threshold segmentation and connected component analysis are performed on the defect confidence map to generate a candidate defect region set.

[0046] Morphological refinement and overlap resolution are performed on the candidate defect region set to finally output a candidate defect region set with clear boundaries and no redundant overlap.

[0047] Optionally, the generation of the set of defective regions after verification includes:

[0048] Using the inter-layer connection graph and the set of candidate defect regions as input, a graph neural network topology consistency verification mechanism is constructed, including an input layer, a message passing layer, an aggregation layer, and an output layer.

[0049] Based on the candidate defect region set, a node feature matrix is ​​generated through geometric feature extraction and attribute encoding. Based on the inter-layer connection graph, an edge feature matrix is ​​generated through topological relationship parsing and edge attribute encoding.

[0050] The input layer receives the node feature matrix and the edge feature matrix;

[0051] In the message passing layer and aggregation layer, process-level identifier variables and geometric topology constraint scalar codes of conditional variable sets are introduced to modulate the weight coefficients, gating vectors and aggregation weights of the update function, generating node embedding representations and graph embedding matrices.

[0052] In the output layer, based on the connectivity threshold parameter, the connectivity of the node embedding representation is determined, and a set of connectivity verification results is generated by combining the graph embedding matrix.

[0053] The connectivity threshold parameter is obtained by mapping the set of geometric topological constraints to the set of conditional variables;

[0054] Based on the connectivity verification result set, filter the normally connected regions, output the abnormally connected regions, and form a set of defective regions after verification.

[0055] Optionally, the generation of the defect type set, defect distribution heatmap, and defect coordinate set includes:

[0056] Using the set of verified defect regions and the set of geometric topological constraints as input, a one-to-one correspondence between regions and parameters is established. The line width parameter, spacing parameter, through-hole diameter parameter and interlayer connectivity parameter values ​​of each region are extracted, and the parameter deviation is calculated and recorded as region records.

[0057] Based on the parameter deviation in the region record, perform type discrimination, output type labels, and construct a defect type set;

[0058] The type label is bound to the region boundary, and the layer number is bound to the parameter deviation to generate a defect coordinate set, which includes the region centroid coordinates and the boundary vertex coordinates.

[0059] The parameter deviation is mapped to the image grid according to spatial coordinates, and the intensity distribution is generated by interpolation mapping and Gaussian smoothing to form a defect distribution heatmap.

[0060] Summarize the defect type set, defect distribution heatmap, and defect coordinate set.

[0061] The beneficial effects of this invention are:

[0062] First, this invention constructs an improved NCA model to achieve joint modeling of multi-layer image matrix sets and geometric topological constraint sets. It considers both local features and global topological information during the evolution of cell state vectors, thereby improving the accuracy and completeness of communication chip layout defect identification.

[0063] Secondly, this invention introduces a set of conditional variables into the update function to adaptively modulate the convolution kernel weights and biases, enabling the model to dynamically adjust the update mechanism for different process levels and geometric rules, effectively reducing the false alarm rate and false negative rate of traditional methods in complex layout scenarios.

[0064] Furthermore, this invention constructs a graph neural network topology consistency verification mechanism to jointly determine the candidate defect region set and the inter-layer connectivity graph, which solves the problem of difficulty in accurately judging cross-layer connectivity anomalies in the prior art, thereby ensuring the reliability and robustness of the identification results.

[0065] Finally, this invention generates a set of defect types, a heat map of defect distribution, and a set of defect coordinates during the defect identification and labeling stage, thereby achieving refined defect location and result output, and providing an efficient and reliable reference for subsequent process optimization and design correction. Attached Figure Description

[0066] The accompanying drawings are provided to further illustrate the invention and form part of the specification. They are used in conjunction with embodiments of the invention to explain the invention and do not constitute a limitation thereof. In the drawings:

[0067] Figure 1 This is an overall flowchart of an artificial intelligence-based automatic identification method for layout defects in communication chips proposed in this invention.

[0068] Figure 2 This is a schematic diagram of the structure of the improved NCA model proposed in this invention in the multi-channel input and iterative evolution of cell state vectors;

[0069] Figure 3 This is a schematic diagram of the structure of the graph neural network topology consistency verification mechanism proposed in this invention in the joint determination of candidate defect region set and inter-layer connection relationship graph. Detailed Implementation

[0070] The present invention will now be described in further detail with reference to the accompanying drawings. These drawings are simplified schematic diagrams, illustrating only the basic structure of the invention, and therefore only show the components relevant to the invention.

[0071] refer to Figure 1-3 An automatic identification method for layout defects in communication chips based on artificial intelligence includes the following steps:

[0072] The layout design file of the communication chip is parsed. The GDSII layout file parsing technology is used to convert the layout data into a multi-layer image matrix set and extract the geometric boundary set and the inter-layer connection relationship diagram.

[0073] Based on a multi-layer image matrix set, design rule checks and parameter extraction are performed to generate a set of geometric topological constraints, which includes line width parameters, spacing parameters, via diameter parameters, and inter-layer connectivity parameters.

[0074] An improved NCA model was constructed and the state was initialized. The multi-layer image matrix set and the geometric topological constraint set were encoded into the cell state vector multi-channel input. The fast-scale update parameter set, the slow-scale update parameter set and the conditional variable set were initialized.

[0075] Based on the fast-scale update parameter set and the slow-scale update parameter set, the cell state vector is iteratively evolved. The fast-scale update calculates the local defect response map based on the neighborhood features and geometric boundary set, while the slow-scale update calculates the global topological consistency map based on the inter-layer connection relationship map, generating an evolutionary intermediate representation set.

[0076] The update function of the improved NCA model is conditionally modulated using a set of conditional variables. By combining the set of evolutionary intermediate representations, the local defect response map, and the global topological consistency map, a set of candidate defect regions is generated.

[0077] Based on graph neural network topology consistency verification technology, the inter-layer connection graph and the candidate defect region set are used as inputs to calculate the connectivity verification result set and output the verified defect region set.

[0078] Based on the verified defect region set and geometric topological constraint set, defects are identified and labeled, generating a defect type set, a defect distribution heatmap, and a defect coordinate set.

[0079] In this embodiment, the generation of the multi-layer image matrix set, the geometric boundary set, and the inter-layer connection graph includes:

[0080] Receive the layout design file of the communication chip, call the GDSII layout file parsing technology, and parse the layer number, layer type and geometric shape data;

[0081] The GDSII layout file parsing technology decodes the layout data file stored in binary stream mode into layer number information, layer type information and geometric shape information, and recovers geometric objects such as polygons, rectangles and paths based on the coordinate data recorded in the file. At the same time, it extracts the hierarchical structure relationship between different layers, which is used as input data to construct a multi-layer image matrix set.

[0082] Geometric data is mapped to the corresponding layer according to the layer number, coordinate normalization and unit conversion are performed, each layer is converted into a two-dimensional image matrix and collected into a multi-layer image matrix set, which includes a metal layer image matrix, a via layer image matrix and a barrier layer image matrix.

[0083] Based on geometric shape data, the boundary is calculated, and line segment boundaries, arc segment boundaries, and polygon boundaries are extracted and merged into a set of geometric boundaries.

[0084] Based on the positional relationship between the via layer and the metal layer, the cross-layer contact area and connection path are detected, and an interlayer connection relationship diagram is constructed;

[0085] Perform consistency checks on the multi-layer image matrix set, geometric boundary set, and inter-layer connection graph.

[0086] In this embodiment, the generation of the geometric topological constraint set includes:

[0087] Based on a multi-layer image matrix set, a process rule file is loaded and a rule set is generated, which includes line width rules, spacing rules, via diameter rules, and inter-layer connection rules.

[0088] The process rule document is specifically a set of design rules provided by the semiconductor manufacturing process, which includes the lower limit of line width, the lower limit of spacing, the range of via diameter, and the cross-layer connection constraint parameters corresponding to different layer numbers. It defines geometric size restrictions, inter-layer interaction conditions, and tolerance ranges in the form of rule tables or scripts to guide the execution of line width calculation, spacing calculation, via diameter calculation, and inter-layer connectivity verification.

[0089] Based on the metal layer image matrix, the centerline width is calculated around the geometric boundary set, and verification is performed according to the line width rules to generate line width parameters;

[0090] Based on the metal layer image matrix and the barrier layer image matrix, the minimum distance between adjacent geometric boundaries is calculated, and a verification is performed according to the spacing rules to generate spacing parameters.

[0091] Based on the through-hole layer image matrix, the geometric boundaries of the through-holes are identified and the equivalent diameter is calculated. Verification is performed according to the through-hole diameter rules to generate through-hole diameter parameters.

[0092] Based on the inter-layer connection graph, cross-layer connection paths are identified and connectivity checks are performed. Inter-layer connectivity parameters are generated according to the inter-layer connection rules.

[0093] By summarizing line width parameters, spacing parameters, through-hole diameter parameters, and inter-layer connectivity parameters, a set of geometric topological constraints is constructed.

[0094] In this embodiment, the construction of the improved NCA model includes:

[0095] Based on a multi-layer image matrix set and a geometric topological constraint set, the channel order and length of the multi-channel input of the cell state vector are determined.

[0096] The cell state vector multi-channel refers to the state vector corresponding to each cell position in the improved NCA model being composed of multiple channels. These channels include image channels from a multi-layer image matrix set and parameter channels from a geometric topological constraint set, which are used to simultaneously characterize local geometric features, hierarchical process information and design rule parameters, thereby providing complete input for subsequent iterative evolution.

[0097] The metal layer image matrix, via layer image matrix, and barrier layer image matrix in the multi-layer image matrix set are encoded into image channels in the cell state vector multi-channel input. The line width parameter, spacing parameter, via diameter parameter, and inter-layer connectivity parameter in the geometric topology constraint set are encoded into parameter channels in the cell state vector multi-channel input. Coordinate alignment and scale normalization are then performed.

[0098] An improved NCA model was constructed, and state initialization was completed by initializing the cell state vector to the initial values ​​of the multi-channel input of the cell state vector.

[0099] Initialize the fast-scale update parameter set, and configure the iteration step number, neighborhood perception range and update sparsity probability as parameter elements into the set for the execution of local neighborhood updates;

[0100] Initialize the slow-scale update parameter set, and configure the weight coefficients and gating thresholds as parameter elements into the set for the execution of global topology consistency calculation;

[0101] Based on the layer number and the set of geometric topology constraints, process layer identifier variables and geometric topology constraint scalar codes are constructed, merged to generate a set of conditional variables, and the set of conditional variables is bound to the update function of the improved NCA model along with the fast-scale update parameter set and the slow-scale update parameter set.

[0102] The generation of the conditional variable set specifically involves: establishing process level identifier variables based on the parsed layer numbers, mapping different layer numbers to corresponding level coding vectors; normalizing and converting line width parameters, spacing parameters, via diameter parameters, and inter-layer connectivity parameters in the geometric topology constraint set into constraint scalar codes; concatenating the process level identifier variables and geometric topology constraint scalar codes along the channel dimension and correcting for dimensional consistency, outputting the conditional variable set, which includes process level identifier variable channels and geometric topology constraint scalar code channels.

[0103] In this embodiment, the generation of the evolutionary intermediate representation set includes:

[0104] Based on a multi-layer image matrix set and a geometric boundary set, neighborhood features are extracted, and a fast-scale update parameter set and a slow-scale update parameter set are loaded to configure the update process of the cell state vector.

[0105] The neighborhood feature represents the pixel value distribution, geometric boundary direction information, and local topological relationship within a preset neighborhood range around the current position of the cell state vector. It is used to describe the geometric shape and structural changes in the local area and to provide input information for local defect detection.

[0106] In the fast-scale update stage, the cell state vector is updated locally using the neighborhood features and geometric boundary set as input, and the local defect response map is output and accumulated. At the same time, the cell state vector is updated for subsequent slow-scale updates.

[0107] Specifically, within the current position of the cell state vector and its neighborhood, based on the iteration step number, neighborhood perception range, and update sparsity probability set by the fast-scale update parameter set, the cell state vector is sampled to determine the update position before each iteration according to the update sparsity probability. The pixel value distribution and geometric boundary direction information contained in the neighborhood features are extracted. The extracted neighborhood features are input into the local update function of the improved NCA model. The state change amount at each position in the neighborhood is calculated through the convolution kernel weights, and the state change amount is superimposed on the corresponding cell state vector channel to generate the updated cell state vector.

[0108] After each local neighborhood update, based on the process level features and geometric topology constraint parameters recorded in the cell state vector, the probability values ​​of regions inconsistent with the standard rules are calculated, and these probability values ​​are mapped to the pixel intensity distribution in the local defect response map. After multiple rounds of iteration and accumulation, a complete local defect response map is output.

[0109] In the slow-scale update phase, the cell state vector is updated globally with the inter-layer connectivity graph as input, and the global topological consistency graph is output and accumulated. At the same time, the cell state vector is updated for the next round of fast-scale update.

[0110] Specifically, before each slow-scale update, the weight coefficients and gating thresholds in the slow-scale update parameter set are loaded. Under the constraints of the inter-layer connectivity graph, cross-layer connectivity aggregation is performed on all cell state vectors. The global consistency value of each cell position is calculated by combining the inter-layer connectivity parameters in the geometric topology constraint set. The global consistency value is compared with the gating threshold to filter out low consistency positions. For the positions that pass the filtering, a global consistency correction term is added to the parameter channel of the cell state vector and written back to the updated cell state vector. The global consistency value obtained from each slow-scale update is normalized, mapped to image coordinates, and accumulated in the iterative order to form a global topological consistency graph.

[0111] After the fast-scale update phase and the slow-scale update phase are completed, the latest cell state vector, the local defect response map, and the global topological consistency map are combined. The multi-channel content of the latest cell state vector is used as the basic representation. The local defect response map and the global topological consistency map are aligned and mapped to the corresponding positions according to the spatial coordinates and layer numbers. The three inputs are normalized and fused based on the geometric topological constraint set to generate a three-dimensional tensor structure containing local defect sensitivity, global topological consistency index and cell state evolution trajectory. This three-dimensional tensor structure is used as the intermediate representation set for evolution.

[0112] In this embodiment, the generation of the candidate defect region set includes:

[0113] Establish a parameter binding relationship between the set of conditional variables and the update function of the improved NCA model, and inject the set of conditional variables into the weight coefficients, gate vectors and normalization factors of the update function;

[0114] The spatial coordinates and layer numbers of the evolutionary intermediate representation set are aligned with the original local defect response map and the original global topological consistency map. The cell state vector, local defect sensitivity and global topological consistency index of the evolutionary intermediate representation set are concatenated with the pixel distribution of the original local defect response map and the original global topological consistency map to form a unified fusion feature tensor.

[0115] Using the fused feature tensor as input, the update function is called to calculate the defect response intensity under the modulation of the conditional variable set, and the defect confidence map is output.

[0116] Specifically, when the fused feature tensor is input into the update function, the kernel weights and biases of the update function are first modulated based on the process level identifier variable and the geometric topology constraint scalar encoding in the conditional variable set. This includes selecting the corresponding kernel sub-weight matrix based on the process level identifier variable, adjusting the channel weight coefficients of the kernel based on the geometric topology constraint scalar encoding, dynamically correcting the bias value based on the fast-scale and slow-scale update parameter sets, and introducing a gating vector during the calculation process to achieve weight sparsity control, enabling the update function to be adaptive under different process levels and geometric rules. Subsequently, the cell state vector channels, local defect response maps, and global topology consistency maps contained in the fused feature tensor are input into the update function layer by layer to calculate the defect response intensity value at each pixel location. Finally, based on the normalization mapping technique, the defect response intensity value is converted into a probability distribution to generate a pixel-level defect confidence map, which is used to characterize the probability that each location in the communication chip layout belongs to a defect region.

[0117] Based on the process level identifier variable and geometric topology constraint scalar encoding in the conditional variable set, a segmentation threshold parameter is set, and threshold segmentation and connected component analysis are performed on the defect confidence map to generate a candidate defect region set.

[0118] The segmentation threshold parameter distinguishes the defect sensitivity levels of different metal layers, via layers and barrier layers based on the process level identifier variable, and sets the upper and lower limits of the threshold in combination with the line width parameter, spacing parameter and via diameter parameter in the geometric topology constraint scalar encoding. Different levels and rules correspond to different threshold ranges to ensure that the defect judgment criteria are consistent with the process design rules.

[0119] The threshold segmentation and connected component analysis are performed as follows: First, the pixel intensity in the defect confidence map is compared with the segmentation threshold parameter to generate a binarized defect candidate map; then, region clustering is performed in the binarized defect candidate map based on the pixel connectivity principle, and spatially adjacent high-confidence pixels are aggregated into connected components; further, isolated regions that do not meet the connectivity constraints are filtered out based on the inter-layer connectivity graph, and finally, a set of candidate defect regions that conform to the process rules is output.

[0120] Morphological refinement and overlap resolution are performed on the candidate defect region set to finally output a candidate defect region set with clear boundaries and no redundant overlap.

[0121] The morphological refinement and overlap resolution include performing erosion and dilation operations on the boundary of each defect region in the candidate defect region set to remove isolated noise points and smooth the region boundaries, making the defect region outline closer to the real geometric shape; then performing opening and closing operations on the defect regions at different scales to eliminate local burrs and small-area artifacts while maintaining the overall connectivity of the defect regions; on this basis, overlap resolution is performed on candidate defect regions that overlap or highly intersect in spatial location. The overlap resolution process involves calculating the overlap rate of intersecting regions. When the overlap rate is higher than a set threshold, the overlapping regions are merged into a single defect region. When the overlap rate is lower than the set threshold, the independent regions are retained. Finally, a set of candidate defect regions with clear boundaries and no redundant overlap is output.

[0122] In this embodiment, the generation of the verified defect region set includes:

[0123] A graph neural network topology consistency verification mechanism is constructed using the inter-layer connection graph and the candidate defect region set as input. The graph neural network topology consistency verification mechanism includes an input layer, a message passing layer, an aggregation layer, and an output layer.

[0124] Based on the candidate defect region set, a node feature matrix is ​​generated through geometric feature extraction and attribute encoding. The node feature matrix includes area, perimeter, layer number, centroid coordinates, and local parameters calculated based on the geometric topological constraint set. Based on the inter-layer connection graph, an edge feature matrix is ​​generated through topological relationship parsing and edge attribute encoding. The edge feature matrix includes cross-layer connection type, geometric distance, and connection direction.

[0125] The input layer receives the node feature matrix and the edge feature matrix, providing an input representation for the connectivity verification calculation of the subsequent message passing layer and aggregation layer;

[0126] In the message passing layer and aggregation layer, process level identifier variables and geometric topology constraint scalar codes of conditional variable sets are introduced to modulate the weight coefficients, gating vectors and aggregation weights of the update function, so that the graph neural network topology consistency verification mechanism can dynamically adjust the message passing process according to different process levels and geometric topology constraints, and generate node embedding representations and graph embedding matrices.

[0127] In the output layer, based on the connectivity threshold parameter, the connectivity of the node embedding representation is determined, and a connectivity verification result set is generated by combining the graph embedding matrix, and indexed and mapped with the candidate defect region set.

[0128] The connectivity threshold parameter is obtained by mapping the set of geometric topological constraints to the set of conditional variables;

[0129] Based on the connectivity verification result set, filter the normally connected regions, output the abnormally connected regions, and form a set of defective regions after verification.

[0130] In this embodiment, the generation of the defect type set, the defect distribution heatmap, and the defect coordinate set includes:

[0131] Using the set of verified defect regions and the set of geometric topological constraints as input, a one-to-one correspondence between regions and parameters is established. The line width parameter, spacing parameter, through-hole diameter parameter and interlayer connectivity parameter values ​​of each region are extracted, and the parameter deviation is calculated and recorded as region records.

[0132] Based on the parameter deviation in the area record, perform type discrimination. Deviation from the upper and lower limits of line width is judged as line width violation, deviation from the lower limit of spacing is judged as spacing violation, deviation from the diameter range of through hole is judged as through hole diameter violation, and violation of inter-layer connectivity parameter is judged as connectivity anomaly. Output type labels and construct a defect type set.

[0133] The type label is bound to the region boundary, and the layer number is bound to the parameter deviation to generate a defect coordinate set, which includes the region centroid coordinates and the boundary vertex coordinates.

[0134] The parameter deviation is mapped to the image grid according to spatial coordinates, and the intensity distribution is generated by interpolation mapping and Gaussian smoothing to form a defect distribution heatmap.

[0135] Summarize and output the defect type set, defect distribution heatmap, and defect coordinate set.

[0136] Example 1:

[0137] To verify the feasibility of this invention in practice, it was applied to the automatic identification of layout defects in communication chips. In actual chip design processes, as process nodes shrink and the number of layout layers increases, traditional defect detection methods relying on rule bases and static thresholds often suffer from insufficient efficiency, high false alarm rates, and difficulty in accurately identifying cross-layer defects when faced with complex layout data. This invention introduces an improved NCA model and a graph neural network topology consistency verification mechanism to automatically model and iteratively calculate layout data, achieving high efficiency and reliability in defect identification.

[0138] In the application scenario, the test samples came from the layout design file of a communication chip. This file contained 11 metal layers, 2 via layers, and 1 barrier layer, with a layout data volume of 8GB, including over 1.4 million geometric shapes and approximately 370,000 cross-layer connectivity relationships. Using GDSII layout file parsing technology, this layout data was converted into a multi-layer image matrix set, simultaneously extracting geometric boundary information and inter-layer connectivity relationships. The extracted linewidth parameters, spacing parameters, via diameter parameters, and inter-layer connectivity parameters were checked against design rules to construct a complete set of geometric topological constraints. Based on this input, this invention constructed an improved NCA model, performing local defect response calculation and global topological consistency modeling on the layout data. Then, the update function was adaptively modulated using a set of conditional variables to generate a set of candidate defect regions. After entering the graph neural network topological consistency verification mechanism, the candidate defect regions were jointly judged with the inter-layer connectivity relationships, ultimately outputting a verified set of defect regions. Based on this, defect type labeling, defect distribution heatmap drawing, and defect coordinate set generation were completed.

[0139] During the experiment, to verify the improvement effect of the present invention compared with traditional methods, three evaluation indicators were selected, including defect identification accuracy, defect false alarm rate, and defect localization deviation. The experimental comparison method was the traditional rule-based DRC method and the artificial intelligence method proposed in this invention. Tests were conducted under the same dataset and hardware environment. Each method processed 1.4 million geometric figures and 370,000 cross-layer connections, and the final identification results and statistical data were recorded.

[0140] The experimental results are shown in the table below:

[0141] Table 1 Comparison of Communication Chip Layout Defect Identification Performance

[0142]

[0143] As shown in Table 1, the present invention achieves a defect identification accuracy of 91.4%, a significant improvement over the 82.3% of the traditional rule-based method, indicating that the present invention can better capture potential defects in complex graph environments. Regarding the false alarm rate, the present invention has a false alarm rate of 2.9%, significantly lower than the 11.6% of the traditional method, greatly reducing unnecessary manual review and improving overall detection efficiency. In terms of defect localization deviation, the average deviation of the present invention is 0.65 micrometers, better than the 0.82 micrometers of the traditional method, indicating higher precision in coordinate output and defect annotation. Regarding processing time, the present invention takes 105 minutes, 23 minutes less than the 128 minutes of the traditional method, demonstrating the efficiency advantage of iterative evolution and parallel processing mechanisms. In terms of cross-layer connectivity defect detection rate, the present invention achieves 92.1%, higher than the 81.7% of the traditional method, proving that after introducing the graph neural network topology consistency verification mechanism, the present invention can more accurately identify cross-layer connectivity anomalies, thereby significantly improving the reliability of the detection results.

[0144] Comparative analysis reveals that the advantages of the method in this invention are mainly reflected in three aspects. First, the improved NCA model can perform multi-channel input modeling of the layout and improves the accuracy and comprehensiveness of identification through the joint evolution mechanism of fast and slow scales. Second, the introduction of the conditional variable set enables the update function to have adaptive modulation capabilities, maintaining stable detection performance under different process levels and geometric rules, thereby effectively reducing the false alarm rate. Third, the graph neural network topology consistency verification mechanism ensures that cross-layer connectivity anomalies can be accurately identified, fundamentally making up for the shortcomings of traditional methods in detecting complex topological defects.

[0145] The above description is only a preferred embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any equivalent substitutions or modifications made by those skilled in the art within the scope of the technology disclosed in the present invention, based on the technical solution and inventive concept of the present invention, should be covered within the scope of protection of the present invention.

Claims

1. An automatic identification method for layout defects in communication chips based on artificial intelligence, characterized in that, Includes the following steps: The layout design file of the communication chip is parsed, the layout data is transformed into a multi-layer image matrix set, and the geometric boundary set and inter-layer connection relationship diagram are extracted. Based on a multi-layer image matrix set, design rule checks and parameter extraction are performed to generate a set of geometric topological constraints. An improved NCA model was constructed and the state was initialized. The multi-layer image matrix set and the geometric topological constraint set were encoded into the cell state vector multi-channel input. The fast-scale update parameter set, the slow-scale update parameter set and the conditional variable set were initialized. The improved NCA model is an iterative evolution model built on the basis of the traditional NCA model. It represents the communication chip layout data as cell state vectors and drives the cell state vectors to update in the spatial neighborhood round by round through the update function until convergence and output. The improved NCA model introduces a dual-scale update mechanism with multi-channel input of cell state vectors, fast-scale update parameter set and slow-scale update parameter set, and constructs a conditional variable set to conditionally modulate the update function: the multi-channel input of cell state vectors encodes the multi-layer image matrix set into image channels and the geometric topological constraint set into parameter channels. Fast-scale update and slow-scale update are used to perform local neighborhood update and global topological consistency update on cell state vectors to generate an evolutionary intermediate representation set. The conditional variable set is generated by merging the process level identifier variable and the geometric topological constraint scalar encoding and is injected into the update function to drive the update function to adaptively execute iterative evolution under different process levels and geometric topological constraints. The fast-scale update parameter set is a set of parameters used to perform local neighborhood update. It consists of the number of iteration steps, the neighborhood sensing range, and the update sparsity probability. It controls the number of iterations, the neighborhood sampling range, and the sampling sparsity control of the update position during the local neighborhood update stage. The slow-scale update parameter set is a set of parameters used to perform global topology consistency update. It consists of weight coefficients and gating thresholds. In the global topology consistency update stage, cross-layer connectivity aggregation is performed in combination with the weight coefficients, and global consistency values ​​are filtered out in combination with the gating thresholds. The conditional variable set is a set of variables used to conditionally modulate the update function of the improved NCA model. It is generated by merging process level identifier variables and geometric topology constraint scalar codes. The conditional variable set is injected with the weight coefficients, gating vectors and normalization factors of the update function, driving the update function to adaptively modulate under different process levels and geometric rules. Based on the fast-scale and slow-scale parameter update sets, the cell state vector is iteratively evolved to generate an intermediate evolutionary representation set; The update function of the improved NCA model is conditionally modulated using a set of conditional variables, and a set of candidate defect regions is generated by combining the set of evolutionary intermediate representations. A graph neural network topology consistency verification mechanism is constructed. Taking the inter-layer connection graph and the candidate defect region set as input, the connectivity verification result set is calculated and the verified defect region set is output. Based on the verified defect region set and geometric topological constraint set, defects are identified and labeled, generating a defect type set, a defect distribution heatmap, and a defect coordinate set.

2. The method for automatic identification of layout defects in communication chips based on artificial intelligence according to claim 1, characterized in that, The generation of the multi-layer image matrix set, geometric boundary set, and inter-layer connection graph includes: Receive the layout design file of the communication chip and parse the layer number, layer type and geometric shape data; The geometric data is mapped to the corresponding layer according to the layer number, coordinate normalization and unit conversion are performed, each layer is converted into a two-dimensional image matrix and collected into a multi-layer image matrix set, including the metal layer image matrix, the via layer image matrix and the barrier layer image matrix. Based on geometric shape data, the boundary is calculated, and line segment boundaries, arc segment boundaries, and polygon boundaries are extracted and merged into a set of geometric boundaries. Based on the positional relationship between the via layer and the metal layer, the cross-layer contact area and connection path are detected, and an interlayer connection relationship diagram is constructed.

3. The method for automatic identification of layout defects in communication chips based on artificial intelligence according to claim 1, characterized in that, The generation of the set of geometric topological constraints includes: Based on a multi-layer image matrix set, a process rule file is loaded and a rule set is generated, which includes line width rules, spacing rules, via diameter rules, and inter-layer connection rules. Based on the metal layer image matrix, the centerline width is calculated around the geometric boundary set, and verification is performed according to the line width rules to generate line width parameters; Based on the metal layer image matrix and the barrier layer image matrix, the minimum distance between adjacent geometric boundaries is calculated, and a verification is performed according to the spacing rules to generate spacing parameters. Based on the through-hole layer image matrix, the geometric boundaries of the through-holes are identified and the equivalent diameter is calculated. Verification is performed according to the through-hole diameter rules to generate through-hole diameter parameters. Based on the inter-layer connection graph, cross-layer connection paths are identified and connectivity checks are performed. Inter-layer connectivity parameters are generated according to the inter-layer connection rules. By summarizing line width parameters, spacing parameters, through-hole diameter parameters, and inter-layer connectivity parameters, a set of geometric topological constraints is constructed.

4. The method for automatic identification of layout defects in communication chips based on artificial intelligence according to claim 1, characterized in that, The construction of the improved NCA model includes: Based on a multi-layer image matrix set and a geometric topological constraint set, the channel order and length of the multi-channel input of the cell state vector are determined. The set of multi-layer image matrices is encoded into the image channels of the cell state vector multi-channel input, the set of geometric topological constraints is encoded into the parameter channels of the cell state vector multi-channel input, and coordinate alignment and scale normalization are performed. Perform state initialization of the improved NCA model, initializing the cell state vector to the initial values ​​of the cell state vector multi-channel input; Initialize the fast-scale update parameter set, and configure the iteration step number, neighborhood perception range and update sparsity probability as parameter elements into the set; Initialize the slow-scale update parameter set, and configure the weight coefficients and gating thresholds as parameter elements into the set; Based on the layer number and the set of geometric topology constraints, construct the process layer identifier variable and the scalar code of the geometric topology constraint, and merge them to generate a set of conditional variables.

5. The method for automatic identification of layout defects in communication chips based on artificial intelligence according to claim 1, characterized in that, The generation of the evolutionary intermediate representation set includes: Based on a multi-layer image matrix set and a geometric boundary set, neighborhood features are extracted, and a fast-scale update parameter set and a slow-scale update parameter set are loaded to configure the update process of the cell state vector. The neighborhood features represent the pixel value distribution, geometric boundary direction information, and local topological relationships within a preset neighborhood range around the current position of the cell state vector; In the fast-scale update stage, the local neighborhood update is performed on the cell state vector using the neighborhood features and geometric boundary set as input, outputting and accumulating the local defect response map, while updating the cell state vector. Specifically, within the current position of the cell state vector and its neighborhood, based on the iteration step number, neighborhood perception range, and update sparsity probability set by the fast-scale update parameter set, the cell state vector is sampled to determine the update position before each iteration according to the update sparsity probability. The pixel value distribution and geometric boundary direction information contained in the neighborhood features are extracted. The extracted neighborhood features are input into the local update function of the improved NCA model. The state change amount at each position in the neighborhood is calculated through the convolution kernel weights, and the state change amount is superimposed on the corresponding cell state vector channel to generate the updated cell state vector. During the slow-scale update phase, the cell state vector is updated globally with the inter-layer connectivity graph as input, and the global topological consistency graph is output and accumulated, while the cell state vector is updated. Specifically, before each slow-scale update, the weight coefficients and gating thresholds in the slow-scale update parameter set are loaded. Under the constraints of the inter-layer connectivity graph, cross-layer connectivity aggregation is performed on all cell state vectors. The global consistency value of each cell position is calculated by combining the inter-layer connectivity parameters in the geometric topology constraint set. The global consistency value is compared with the gating threshold to filter out low consistency positions. For the positions that pass the filtering, a global consistency correction term is added to the parameter channel of the cell state vector and written back to the updated cell state vector. The global consistency value obtained from each slow-scale update is normalized, mapped to image coordinates, and accumulated in the iterative order to form a global topological consistency graph. After the fast-scale update phase and the slow-scale update phase are completed, the latest cell state vector, local defect response map and global topological consistency map are combined. The multi-channel content of the latest cell state vector is used as the basic representation. The local defect response map and the global topological consistency map are aligned and mapped to the corresponding positions according to the spatial coordinates and layer number. Based on the geometric topological constraint set, the latest cell state vector, local defect response map and global topological consistency map are normalized and fused to generate a three-dimensional tensor structure containing local defect sensitivity, global topological consistency index and cell state evolution trajectory. This three-dimensional tensor structure is used as the intermediate representation set for evolution.

6. The method for automatic identification of layout defects in communication chips based on artificial intelligence according to claim 1, characterized in that, The generation of the candidate defect region set includes: Establish a parameter binding relationship between the set of conditional variables and the update function of the improved NCA model, and inject the set of conditional variables into the weight coefficients, gate vectors and normalization factors of the update function; The spatial coordinates and layer numbers of the intermediate evolutionary representation set are aligned with the original local defect response map and the original global topology consistency map. The pixel distributions of the intermediate evolutionary representation set, the original local defect response map, and the original global topology consistency map are then stitched together into a unified fusion feature tensor. Using the fused feature tensor as input, the update function is called to calculate the defect response intensity under the modulation of the conditional variable set, and the defect confidence map is output. Based on the process level identifier variable and geometric topology constraint scalar encoding in the conditional variable set, a segmentation threshold parameter is set, and threshold segmentation and connected component analysis are performed on the defect confidence map to generate a candidate defect region set. Morphological refinement and overlap resolution are performed on the candidate defect region set to finally output a candidate defect region set with clear boundaries and no redundant overlap.

7. The method for automatic identification of layout defects in communication chips based on artificial intelligence according to claim 1, characterized in that, The generation of the verified defect region set includes: Using the inter-layer connection graph and the set of candidate defect regions as input, a graph neural network topology consistency verification mechanism is constructed, including an input layer, a message passing layer, an aggregation layer, and an output layer. Based on the candidate defect region set, a node feature matrix is ​​generated through geometric feature extraction and attribute encoding. Based on the inter-layer connection graph, an edge feature matrix is ​​generated through topological relationship parsing and edge attribute encoding. The input layer receives the node feature matrix and the edge feature matrix; In the message passing layer and aggregation layer, process-level identifier variables and geometric topology constraint scalar codes of conditional variable sets are introduced to modulate the weight coefficients, gating vectors and aggregation weights of the update function, generating node embedding representations and graph embedding matrices. In the output layer, based on the connectivity threshold parameter, the connectivity of the node embedding representation is determined, and a set of connectivity verification results is generated by combining the graph embedding matrix. The connectivity threshold parameter is obtained by mapping the set of geometric topological constraints to the set of conditional variables; Based on the connectivity verification result set, filter the normally connected regions, output the abnormally connected regions, and form a set of defective regions after verification.

8. The method for automatic identification of layout defects in communication chips based on artificial intelligence according to claim 1, characterized in that, The generation of the defect type set, defect distribution heatmap, and defect coordinate set includes: Using the set of verified defect regions and the set of geometric topological constraints as input, a one-to-one correspondence between regions and parameters is established. The line width parameter, spacing parameter, through-hole diameter parameter and interlayer connectivity parameter values ​​of each region are extracted, and the parameter deviation is calculated and recorded as region records. Based on the parameter deviation in the region record, perform type discrimination, output type labels, and construct a defect type set; By binding the type label with the region boundary and the layer number with the parameter deviation, a defect coordinate set is generated, which includes the region centroid coordinates and the boundary vertex coordinates. The parameter deviation is mapped to the image grid according to spatial coordinates, and the intensity distribution is generated by interpolation mapping and Gaussian smoothing to form a defect distribution heatmap. Summarize the defect type set, defect distribution heatmap, and defect coordinate set.

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