Chip positioning method and system and chip position correction device
By identifying and fitting feature lines in the longitudinal and transverse regions on the chip, and using angle bisectors to determine the chip's actual position and angle, the problem of inaccurate chip positioning in existing technologies is solved, achieving higher positioning accuracy and lower pose error.
Patent Information
- Application Number
- CN202511584534.8
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-10-31
- Publication Date
- 2025-12-12
AI Technical Summary
In existing technologies, chip positioning accuracy is not precise enough, especially when the number of marker points is limited or they are obscured or damaged, resulting in inaccurate chip positioning.
By acquiring chip images, identifying target feature regions, fitting feature lines within the longitudinal and transverse regions, determining the actual position and angle of the chip using angle bisectors, and using protrusion features formed in the same process step as the positioning basis, the angle error is balanced and the pose error is reduced.
It improves the accuracy of chip positioning, ensures the chip's accuracy in actual position and angle, avoids the problem of poor positioning accuracy caused by unclear or limited number of marker points, and reduces pose error.
Smart Images
Figure CN121120782A_ABST
Abstract
Description
Technical Field
[0001] This application relates to the field of chip positioning technology, and in particular to a chip positioning method, system and chip position correction device. Background Technology
[0002] In this field, most chip equipment uses the chip's own markers for visual positioning. These markers are specially designed points during chip manufacturing, typically in the form of a cross, circle, or L, and there are usually two or more of them. These shapes provide a macroscopic reference with known dimensions and shape.
[0003] Generally, visual positioning identifies two or more (usually less than four) Mark points and uses a certain algorithm to fit the position (X, Y) and rotation angle (θ) of the chip's center point.
[0004] However, the above-mentioned visual positioning method is a relatively macroscopic visual positioning. Since the number of these markers is limited and they may be obscured or damaged in some cases, the chip position obtained through these markers is not accurate enough. Summary of the Invention
[0005] One objective of the first aspect of this application is to provide a chip positioning method that can improve chip positioning accuracy.
[0006] A further objective of this application is to further reduce pose error.
[0007] A second aspect of this application aims to provide a chip positioning system for performing the above-described chip positioning method.
[0008] One objective of the third aspect of this application is to provide a chip position correction device including the above-described chip positioning system.
[0009] Specifically, according to one aspect of this application, a chip positioning method is provided, comprising: Obtain a chip image of the chip to be located; The target feature region on the chip image is identified according to a preset feature region, and the target feature region is matched with the preset feature region; The fitted feature region on the chip image is determined based on the location information of the target feature region. The fitted feature region has a preset feature correspondence with the target feature region. The fitted feature region includes two vertical regions and two horizontal regions. Each vertical region includes multiple second features protruding on the chip to be located. Each horizontal region includes multiple third features protruding on the chip to be located. A vertical line is correspondingly fitted to multiple second features in each of the vertical regions, and a horizontal line is correspondingly fitted to multiple third features in each of the horizontal regions. Draw the angle bisectors of the two vertical lines as the first fitting line, and draw the angle bisectors of the two horizontal lines as the second fitting line; The actual position and actual angle of the chip are obtained based on the position and angle of the first and second fitted lines.
[0010] Optionally, the target feature area is provided with a plurality of raised first features, wherein the first feature, the second feature and the third feature are one or more of solder balls, ball grid arrays and pads on the chip to be positioned.
[0011] Optionally, the first feature, the second feature, and the third feature are formed in the same process step.
[0012] Optionally, the length of the longitudinal region is greater than 1 / 2 of the longitudinal dimension of the chip to be positioned, and the length of the transverse region is greater than 1 / 2 of the transverse dimension of the chip to be positioned.
[0013] Optionally, the first fitted line is the square of the angle between the two vertical lines, and the second fitted line is the angle bisector of the two horizontal lines.
[0014] Optionally, the step of obtaining a chip image of the chip to be located may include: Preset feature regions on the acquisition template.
[0015] Optionally, the step of fitting a vertical line to the plurality of second features in each of the longitudinal regions includes: The second feature, whose distance from the center to the longitudinal centerline of the longitudinal region is less than a preset value, is taken as the target feature; The vertical line is fitted based on the center position of all the target features.
[0016] Optionally, the step of obtaining the actual position and actual angle of the chip to be positioned based on the position and angle of the first and second fitted lines includes: The actual position of the chip is determined based on the intersection of the first and second fitted lines. Calculate the first angular deviation between the first fitted line and the target longitudinal direction; Calculate the second angular deviation between the second fitted line and the target laterally; The actual angle of the chip is determined by the average of the first angle deviation and the second angle deviation.
[0017] In particular, according to another aspect of this application, a chip positioning system is also provided, including a memory and a controller, wherein the memory is used to store a computer program, and the controller is used to execute the computer program in the memory to implement the chip positioning method described in any of the above claims.
[0018] In particular, according to another aspect of this application, a chip position correction device is also provided, including an image acquisition unit, a motion mechanism, and the aforementioned chip positioning system. The image acquisition unit is used to acquire a chip image of the chip and send it to the chip positioning system. The chip positioning system is used to calculate the actual position and actual angle of the chip and send them to the motion mechanism. The motion mechanism is used to drive the chip to adjust to the target position and target angle.
[0019] This application provides a chip positioning method that uses a batch of raised features on the chip as the initial positioning basis, avoiding the problem of poor positioning accuracy caused by unclear or limited original positioning marks on the chip. Furthermore, by using the angle bisectors of the vertical lines fitted by the first features in two vertical regions and the angle bisectors of the horizontal lines fitted by the second features in two horizontal regions as the final positioning references, angular errors in both directions can be balanced, resulting in a more accurate determined actual angle. Using two angle bisectors to determine the actual position of the chip is more accurate than determining the actual position of the chip using a single reference point.
[0020] Furthermore, by using chip features formed in the same process step as the first, second, and third features, pose errors caused by different process steps can be avoided, thereby further reducing pose errors and improving the accuracy of the actual position and angle of the final chip.
[0021] Furthermore, by selecting feature groups with longer occupancy as positioning features, the problem of decreased positioning accuracy due to a small number of features or single-point errors can be avoided.
[0022] Furthermore, by taking the average of the first angular deviation between the first fitted line and the target longitudinal direction and the second angular deviation between the second fitted line and the target transverse direction as the chip's angular deviation, the angular error can be further reduced and the positioning accuracy improved. Attached Figure Description
[0023] Figure 1 This is a flowchart of a chip positioning method according to an embodiment of this application; Figure 2 This is a schematic flowchart of a chip positioning method according to an embodiment of this application; Figure 3 This is a schematic diagram of a chip positioning method according to an embodiment of this application; Figure 4 This is a connection block diagram of a chip positioning system according to an embodiment of this application; Figure 5 This is a connection block diagram of a chip position correction device according to an embodiment of this application; Figure label: 100-Chip image, 110-Target feature region, 10-First feature, 120-Vertical region, 20-Second feature, 130-Horizontal region, 30-Third feature, 300-Chip positioning system, 310-Memory, 320-Controller, 400-Image acquisition unit, 500-Motion mechanism. Detailed Implementation
[0024] To make the above-mentioned objectives, features, and advantages of this application more apparent and understandable, the specific embodiments of this application will be described in detail below with reference to the accompanying drawings. It should be understood that the specific embodiments described herein are for illustrative purposes only and are not intended to limit the scope of this application. Furthermore, it should be noted that, for ease of description, only the parts relevant to this application are shown in the accompanying drawings, not the entire structure. Based on the embodiments in this application, all other embodiments obtained by those skilled in the art without inventive effort are within the scope of protection of this application.
[0025] The term “exemplary” as used herein means “serving as an example, embodiment, or illustration.” Any embodiment illustrated herein as “exemplary” is not necessarily to be construed as superior to or better than other embodiments.
[0026] Furthermore, to better illustrate this application, numerous specific details are provided in the following detailed description. Those skilled in the art should understand that this application can be implemented without certain specific details. In some instances, methods, means, components, and circuits well known to those skilled in the art have not been described in detail in order to highlight the spirit of this disclosure.
[0027] It should be understood that the term "and / or" in this article is merely a description of the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent: A existing alone, A and B existing simultaneously, or B existing alone. Additionally, the character " / " in this article indicates that the preceding and following related objects have an "or" relationship.
[0028] In this application's embodiments, "multiple" refers to two or more. The descriptions of "first," "second," etc., appearing in this application's embodiments are merely illustrative and for distinguishing the described objects; they have no order and do not indicate a specific limitation on the number in this application's embodiments, nor do they constitute any limitation on the embodiments of this application.
[0029] The chip positioning method of this application is used to accurately position the actual pose (including position and angle) of the chip on the stage, so as to adjust the chip according to the difference between the actual pose and the target pose (including position and angle). That is, the chip is adjusted from the actual pose to the target pose by using a motion mechanism (such as a chip alignment mechanism) so as to enable subsequent precise operation of the chip, such as detection or processing. This application does not limit the application scenarios of the positioning method.
[0030] Figure 1 This is a flowchart of a chip positioning method according to an embodiment of this application. Figure 2 This is a schematic flowchart illustrating a chip positioning method according to an embodiment of this application. Figure 2 Only the features within the target feature region 110 and the fitted feature regions (120, 130) are shown, while the features of other regions on the chip image 100 are hidden. Figure 3 This is a schematic diagram of a chip positioning method according to an embodiment of this application. Figure 1 As shown, in one embodiment, the chip positioning method includes: Step S100: Obtain chip image 100 of the chip to be located; Step S200: Identify the target feature region 110 on the chip image 100 according to the preset feature region, and match the target feature region 110 with the preset feature region; Step S300: Determine the fitting feature region on the chip image 100 based on the position information of the target feature region 110. The fitting feature region and the target feature region 110 have a preset feature correspondence. The fitting feature region includes two vertical regions 120 and two horizontal regions 130. See [link to relevant documentation] Figure 2 In (a), each longitudinal region 120 includes a plurality of second features 20 protruding on the chip to be positioned, and each transverse region 130 includes a plurality of third features 30 protruding on the chip to be positioned. Step S400: Fit vertical lines to the second feature 20 in each vertical region 120, and fit horizontal lines to the third feature 30 in each horizontal region 130. (See vertical lines for reference.) Figure 2 In (b) of the text, K1 and K2 are shown in the horizontal line. Figure 2 K3 and K4 in (b); Step S500: Fit the first fitting line V1 based on the two vertical lines, and fit the second fitting line V2 based on the two horizontal lines. See [link to relevant documentation]. Figure 2 (c) in the middle; Step S600: Obtain the actual position and actual angle of the chip based on the position and angle of the first fitting line V1 and the second fitting line V2.
[0031] In step S100, the image 100 of the chip can be captured by the camera. After the image is captured, some conventional preprocessing can be performed on the image, such as enhancing contrast and filtering noise reduction, to improve the image quality.
[0032] See Figure 2 In step (a), the preset feature region and target feature region 110 in step S200 are easily identifiable and unique regions on the chip, or they can be chip type-related regions, such as regions with a special shape that only exist on this type of chip. Multiple first features 10 can be set within the target feature region 110, and these multiple first features 10 are arranged in a special shape, with only one target feature region 110 for this chip. The first feature 10, second feature 20, and third feature 30 can be common protrusion features on the chip, such as one or more of solder balls, ball grid arrays (BGA), and pads (PADs) on the chip. Of course, they can also be other features easily identifiable by the camera; there are no restrictions here. The protrusion features included in the first feature 10, second feature 20, and third feature 30 can be the same or different, and can include one type of protrusion feature or multiple types of protrusion features; there are no restrictions here.
[0033] Here, the preset feature region can be an image region acquired in advance before step S100. For example, a template with a preset feature region is made. The preset feature region has the same shape as the target feature region 110. Then, the preset feature region on the template is acquired and saved. After the chip image 100 of the chip is acquired in step S100, the region with the same shape as the preset feature region is identified. This region is the target feature region 110 on the chip image 100.
[0034] In step S300, for a specific chip, the relative positional relationships between various features on its surface are determined and can be obtained in advance. Therefore, the position of the fitted feature region can be obtained based on the position of the target feature region 110, for example... Figure 2 In the target feature region 110, there is a first bump group, and a second bump group, a third bump group, a fourth bump group, and a fourth bump group are respectively located on the left and right sides of the first bump group. The relative positional relationship between these bump groups and the first bump group is determined. Each bump group is made according to the design requirements. Therefore, the positions of the second bump group, the third bump group, the third bump group, and the fourth bump group can be calculated based on the position of the first bump group. This determines the position of the regions corresponding to the second bump group, the third bump group, the third bump group, and the fourth bump group, respectively. That is, the positional information of the two vertical regions 120 and the two horizontal regions 130 mentioned above.
[0035] In step S500, the first fitting line V1 is the square line of the angle between the two vertical lines, and the second fitting line V2 is the angle bisector of the two horizontal lines.
[0036] like Figure 3 As shown, the dashed rectangle 200 represents the chip's outline at the target position and angle, while the solid rectangle represents the outline of the chip currently being located. When the chip is at the target position and angle, the first fitted line V1 should align with... Figure 3 The dotted line V0 in the figure coincides with the second fitted line L1. Figure 3 The dotted line L0 in the diagram coincides with the intersection point D1 of the first fitted line V1 and the second fitted line L1. The intersection point D1 should also coincide with the intersection point D0 of the dotted line V0 and the dotted line L0. The dotted line L0, the dotted line V0, and the intersection point D0 determine the target position and target angle of the chip. Once the actual first fitted line V1, the second fitted line L1, and the intersection point D1 of the chip are obtained, the amount of rotation and / or movement required by the chip can be determined. For example, the chip can be moved from position D1 to position D0 by a motion mechanism, and the chip can be rotated to the position where the first fitted line V1 coincides with the straight line V0.
[0037] The chip positioning method in this embodiment uses a batch of raised features on the chip as the original positioning basis, which avoids the problem of poor positioning accuracy caused by unclear or limited original positioning marks on the chip. Furthermore, by using the angle bisectors of the vertical lines fitted by the first feature 10 in the two vertical regions 120 and the angle bisectors of the horizontal lines fitted by the second feature 20 in the two horizontal regions 130 as the final positioning references, the angular errors in the two directions can be balanced, making the determined actual angle more accurate. Using two angle bisectors to determine the actual position of the chip is more accurate than determining the actual position of the chip using a single reference point.
[0038] In one embodiment, the first feature 10, the second feature 20, and the third feature 30 are formed in the same process step. For example, the first feature 10, the second feature 20, and the third feature 30 are bump balls formed in a single solder paste printing process.
[0039] This embodiment uses chip features formed in the same process step as the first feature 10, the second feature 20 and the third feature 30 to avoid pose errors caused by different process steps, thereby further reducing pose errors and improving the accuracy of the actual position and actual angle of the final chip.
[0040] To avoid a decrease in accuracy due to single-point errors, feature groups with larger lengths should be selected when choosing the fitting feature region.
[0041] When a chip has multiple sets of feature groups arranged vertically and multiple sets of feature groups arranged horizontally, the feature group with the larger length can be selected. For example, the chip includes multiple first protrusion feature groups and multiple second protrusion feature groups. The first protrusion feature group includes multiple protrusion features arranged vertically, and the second protrusion feature group includes multiple protrusion features arranged horizontally. In one embodiment, the length of the vertical region 120 is greater than half of the vertical dimension of the chip to be positioned, to ensure that the vertical region 120 has a certain length of second features 20 arranged vertically, and the length of the horizontal region 130 is greater than half of the horizontal dimension of the chip to be positioned, to ensure that the horizontal region 130 has a certain length of third features 30 arranged horizontally. In another embodiment, the vertical region 120 is the longest among the multiple first protrusion feature groups, and the horizontal region 130 is the longest among the multiple second protrusion feature groups. It should be noted that the selection of the vertical region 120 and the horizontal region 130 should be performed in advance. After selection, each time the chip positioning method is executed, the fitting feature region is the region on the chip to be positioned that has a preset feature correspondence with the target feature region.
[0042] This embodiment selects feature groups with longer occupancy as positioning features, which can avoid the problem of decreased positioning accuracy caused by a small number of features and single-point errors.
[0043] In step S430, the preset size information includes width and length. Taking a vertical region 120 as an example, the length of the vertical region 120 at least covers all aligned second features 20. The width of the vertical region 120 can be slightly larger than the lateral dimension of the second features 20. For example, when the second features 20 are all bumps, the width of the vertical region 120 can be 1-1.2 times the diameter of the bump.
[0044] In one embodiment, step S500, the step of fitting the vertical line, includes: Step S510: Select the second feature 20 whose distance from the center to the longitudinal centerline of the longitudinal region 120 is less than a preset value as the target feature; Step S520: Fit vertical lines based on the center positions of all target features.
[0045] In step S510, the longitudinal center line of the longitudinal region 120 can be drawn first. Then, the center point of each second feature 20 in the longitudinal region 120 is extracted. Then, the second features 20 whose center point is greater than or equal to the longitudinal center line by a preset value are removed. The remaining second features 20 are used as target features for vertical fitting. The preset value here can be set according to the accuracy requirements.
[0046] In step S520, a commonly used straight line fitting algorithm can be used to fit the vertical line. In this embodiment, the least squares method is used for fitting. In other embodiments, weighted least squares method or median regression or other fitting algorithms can also be used.
[0047] The fitting method for horizontal lines is the same as that for vertical lines, so it will not be repeated here.
[0048] In one embodiment, step S700 includes: Step S710: Determine the actual position of the chip based on the intersection of the first and second fitted lines; Step S720: Calculate the first angular deviation between the first fitted line and the target longitudinal direction; Step S730: Calculate the second angular deviation between the second fitted line and the target laterally; Step S740: Calculate the actual angle of the chip based on the average of the first angle deviation and the second angle deviation.
[0049] like Figure 3 As shown, the target's longitudinal direction is the direction of line V0, and the target's transverse direction is the direction of line L0. The first angular deviation is the included angle R1, and the second angular deviation is the included angle R2. In this embodiment, the average of R1 and R2 is taken as the angular difference between the chip and the template. The chip is then rotated by this angular difference. Figure 3 As shown, assuming R1 is 1° and R2 is 0.8°, the angle difference is taken as 0.9°, and the chip is controlled accordingly. Figure 3 Rotating the chip counterclockwise by 0.9° achieves angle correction.
[0050] This embodiment uses the average of the first angular deviation between the first fitted line and the target longitudinal direction and the second angular deviation between the second fitted line and the target transverse direction as the chip's angular deviation, which can further reduce angular error and improve positioning accuracy.
[0051] Figure 4 This is a connection block diagram of a chip positioning system 300 according to an embodiment of this application. Figure 4 As shown, this application also provides a chip positioning system 300, including a memory 310 and a controller 320. The memory 310 is used to store a computer program, and the controller 320 is used to implement the chip positioning method described above when executing the computer program on the memory 310.
[0052] The controller 320 can be a central processing unit (CPU). The controller 320 can also be other general-purpose controllers 320, digital signal processors (DSPs), application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, or combinations of the above types of chips.
[0053] The memory 310, as a non-transitory computer-readable storage medium, can be used to store non-transitory software programs, non-transitory computer-executable programs, and modules, such as the movement trajectory adjustment method in this embodiment of the invention. The controller 320 executes various functional applications and data processing, i.e., the movement trajectory adjustment method, by running the non-transitory software programs, instructions, and modules stored in the memory 310.
[0054] Those skilled in the art will understand that all or part of the processes in the methods of the above embodiments can be implemented by a computer program instructing related hardware. The program can be stored in a computer-readable storage medium, and when executed, it can include the processes of the embodiments of the methods described above. The storage medium can be a magnetic disk, optical disk, read-only memory (ROM), random access memory (RAM), flash memory 310, hard disk drive (HDD), or solid-state drive (SSD), etc.; the storage medium can also include combinations of the above types of memory 310.
[0055] Figure 5 This is a connection block diagram of a chip position correction device according to one embodiment of this application. Figure 5 As shown, this application also provides a chip position correction device, including an image acquisition unit 400, a motion mechanism 500 and the aforementioned chip positioning system 300. The image acquisition unit 400 is used to acquire a chip image 100 of the chip and send it to the chip positioning system 300. The chip positioning system 300 is used to calculate the actual position and actual angle of the chip and send them to the motion mechanism 500. The motion mechanism 500 is used to drive the chip to adjust to the target position and target angle.
[0056] In this embodiment, after obtaining high-precision chip position and angle information through the chip positioning system 300, the displacement difference between the actual position and the target position of the chip, and the angle difference between the actual angle and the target angle of the chip can be calculated. Then, the displacement difference and angle difference are sent to the motion mechanism 500. The motion mechanism 500 drives the chip to translate and rotate until the chip is at the target position and target angle, thereby completing the chip position correction.
[0057] The embodiments described above are merely illustrative of several implementation methods of this application, and while the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the patent application. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of this application, and these all fall within the protection scope of this application. Therefore, the protection scope of this patent application should be determined by the appended claims.
Claims
1. A chip positioning method, characterized in that, include: Obtain a chip image of the chip to be located; The target feature region on the chip image is identified according to a preset feature region, and the target feature region is matched with the preset feature region; The fitted feature region on the chip image is determined based on the location information of the target feature region. The fitted feature region and the target feature region have a preset feature correspondence relationship. The fitted target feature region includes two vertical regions and two horizontal regions. Each vertical region includes multiple second features protruding on the chip to be located. Each horizontal region includes multiple third features protruding on the chip to be located. A vertical line is correspondingly fitted to multiple second features in each of the vertical regions, and a horizontal line is correspondingly fitted to multiple third features in each of the horizontal regions. A first fitting line is obtained by fitting the two vertical lines, and a second fitting line is obtained by fitting the two horizontal lines. The actual position and actual angle of the chip to be positioned are obtained based on the position and angle of the first and second fitted lines.
2. The chip positioning method according to claim 1, characterized in that, The target feature area is provided with a plurality of raised first features, and the first feature, the second feature and the third feature are one or more of solder balls, ball grid arrays and pads on the chip to be positioned.
3. The chip positioning method according to claim 2, characterized in that, The first feature, the second feature, and the third feature are formed in the same process step.
4. The chip positioning method according to claim 1, characterized in that, The length of the longitudinal region is greater than 1 / 2 of the longitudinal dimension of the chip to be positioned, and the length of the transverse region is greater than 1 / 2 of the transverse dimension of the chip to be positioned.
5. The chip positioning method according to claim 1, characterized in that, The first fitted line is the square angle line of the two vertical lines, and the second fitted line is the angle bisector of the two horizontal lines.
6. The chip positioning method according to any one of claims 1-5, characterized in that, The steps preceding the acquisition of a chip image of the chip to be located also include: Preset feature regions on the acquisition template.
7. The chip positioning method according to any one of claims 1-5, characterized in that, The step of fitting a vertical line to the plurality of second features in each of the said vertical regions includes: The second feature, whose distance from the center to the longitudinal centerline of the longitudinal region is less than a preset value, is taken as the target feature; The vertical line is fitted based on the center position of all the target features.
8. The chip positioning method according to any one of claims 1-5, characterized in that, The steps for obtaining the actual position and actual angle of the chip to be positioned based on the position and angle of the first and second fitted lines include: The actual position of the chip is determined based on the intersection of the first and second fitted lines. Calculate the first angular deviation between the first fitted line and the target longitudinal direction; Calculate the second angular deviation between the second fitted line and the target laterally; The actual angle of the chip is determined by the average of the first angle deviation and the second angle deviation.
9. A chip positioning system, characterized in that, The device includes a memory and a controller, wherein the memory is used to store a computer program, and the controller is used to execute the computer program in the memory to implement the chip positioning method according to any one of claims 1-8.
10. A chip position correction device, characterized in that, The device includes an image acquisition unit, a motion mechanism, and the chip positioning system of claim 9. The image acquisition unit is used to acquire a chip image of the chip to be positioned and send it to the chip positioning system. The chip positioning system is used to calculate the actual position and actual angle of the chip to be positioned and send it to the motion mechanism. The motion mechanism is used to drive the chip to be positioned to adjust to the target position and target angle.