Display device

Abstract

This application belongs to the field of display technology, specifically relating to a display device, including: a logic component; an array substrate connected to the logic component, the array substrate having a display area and a non-display area located around the display area, a display signal line provided in the display area, and an induction coil provided in the non-display area. The induction coil is configured to cooperate with an external charging coil to supply power to the logic component. When the logic component receives screen information, it provides a display signal to the display signal line using the power supplied by the induction coil. This application, by using an induction coil on the array substrate in cooperation with an external charging coil to supply power to the logic component, achieves a thinner and lighter display device with lower production costs compared to designs that incorporate a battery within the display device and an induction coil on the logic component.

Description

Technical Field

[0001] This application belongs to the field of display technology, and specifically relates to a display device. Background Technology

[0002] Currently, electronic tags and other display devices on the market all require batteries. Whether it is a button battery or lithium batteries and polymer batteries of various shapes, they will increase the size of the display device and make the internal structure of the display device complex. Summary of the Invention

[0003] The purpose of this application is to solve the problems in related technologies, such as the increased size of display devices and the complexity of their internal structures due to batteries.

[0004] This application provides a display device, including: a logic component; an array substrate connected to the logic component, the array substrate having a display area and a non-display area located around the display area, a display signal line provided in the display area, and an induction coil provided in the non-display area, the induction coil being configured to cooperate with an external charging coil to supply power to the logic component, and the logic component providing a display signal to the display signal line under the power supplied by the induction coil when receiving screen information.

[0005] In one exemplary embodiment of this application, a display control line is provided in the non-display area. The display control line is connected to the display signal line and is configured to transmit the display signal provided by the logic component to the display signal line. The induction coil includes at least a first coil, which includes a plurality of main traces and bridging traces. The main traces are disposed on the same layer as the display control line and are spaced apart. The bridging traces are located on different layers from the main traces and the display control line and overlap in the stacking direction of the array substrate. The bridging traces are connected to the main traces located on both sides of the display control line through conductive vias.

[0006] In one exemplary embodiment of this application, the line width of the bridging trace is greater than the line width of the main trace.

[0007] In one exemplary embodiment of this application, the induction coil includes at least a first coil and a second coil located on different layers. The first end and the second end of the first coil are respectively connected to the logic component. The first end and the second end of the second coil are respectively connected to the first end and the second end of the first coil through a conductive via structure.

[0008] In one exemplary embodiment of this application, the display device further includes a first switch and a second switch; the induction coil includes at least a first coil and a second coil located on different layers, a first end of the first coil and the logic component are connected to a first node, a second end of the first coil and the logic component are connected to a second node, a first end of the second coil is connected to the first node through the first switch, and a second end of the second coil is connected to the second node through the second switch, wherein the first switch and the second switch are configured to turn on or off according to the target power required by the logic component.

[0009] In one exemplary embodiment of this application, a compensation module is provided in the non-display area. The compensation module includes a compensation coil, the size of which is smaller than that of the induction coil. The compensation coil is configured to cooperate with an external start-up charging coil to generate a drive signal. The first switch and the second switch are configured to be turned on under the drive signal, so that the second coil cooperates with the external start-up charging coil to output power to the second node to supply power to the logic component.

[0010] In one exemplary embodiment of this application, the compensation module further includes a sustaining capacitor and a third switch. The first end of the sustaining capacitor, the first end of the compensation coil, and the first end of the third switch are all connected to a third node, which is grounded. The second end of the sustaining capacitor, the second end of the compensation coil, the control terminal of the first switch, the control terminal of the second switch, and the second end of the third switch are all connected to a fourth node. The control terminals of the first switch and the second switch are configured to receive the drive signal, and the control terminal of the third switch is configured to receive a short-circuit signal of the logic component when the logic component reaches the target charge level, so that the first and second ends of the sustaining capacitor are connected.

[0011] In one exemplary embodiment of this application, the compensation module further includes a rectifier tube, and the second end of the compensation coil is connected to the fourth node through the rectifier tube.

[0012] In one exemplary embodiment of this application, the orthographic projection of the first coil on the array substrate coincides with the orthographic projection of the second coil on the array substrate.

[0013] In one exemplary embodiment of this application, a display control line is provided in the non-display area, the display control line is connected to the display signal line, and the display control line is configured to transmit the display signal provided by the logic component to the display signal line; the display signal line is a scan line, and the display control line and the first coil are disposed on the same layer as the scan line.

[0014] The display device of this application has at least the following beneficial effects:

[0015] The display device of this application includes a logic component and an array substrate. The array substrate is connected to the logic component and has a display area and a non-display area. The display area contains display signal lines, and the non-display area contains an induction coil. The induction coil can be configured to cooperate with an external charging coil to supply power to the logic component. When the logic component receives screen information, it provides a display signal to the display signal lines using the power supplied by the induction coil, enabling the display device to refresh in real time. By using an induction coil in cooperation with an external charging coil to supply power to the logic component, compared to designing a battery within the display device, the internal space occupied by the battery can be reduced, thereby allowing for a thinner display device and effectively reducing manufacturing costs and size. Furthermore, by using an induction coil in cooperation with an external charging coil to supply power to the logic component, compared to placing the induction coil within the logic component, the design size of the logic component can be reduced, lowering its manufacturing cost.

[0016] Other features and advantages of this application will become apparent from the following detailed description, or may be learned in part from practice of this application.

[0017] It should be understood that the above general description and the following detailed description are exemplary and explanatory only, and do not limit this application. Attached Figure Description

[0018] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this application and, together with the description, serve to explain the principles of this application. It is obvious that the drawings described below are merely some embodiments of this application, and those skilled in the art can obtain other drawings based on these drawings without any inventive effort.

[0019] Figure 1 This paper illustrates a schematic diagram of the connection between a logic component and an array substrate provided in some embodiments of this application.

[0020] Figure 2 This paper illustrates a schematic diagram of a structure with sensing traces in a non-display area provided in some embodiments of this application.

[0021] Figure 3 A cross-sectional schematic diagram of the bridging wire, bridging induction coil, and connecting trace provided in some embodiments of this application is shown.

[0022] Figure 4 The diagram shows a structural schematic of the bridging wiring section and the bridging main body wiring section provided in some embodiments of this application.

[0023] Figure 5 This paper shows a schematic diagram of the structure provided in some embodiments of the present application, in which the induction coil and the data line are arranged on the same layer.

[0024] Figure 6 The diagram shows a schematic of the structure of an induction coil using a first coil and a second coil, provided in some embodiments of this application.

[0025] Figure 7 A schematic diagram of the structure of the second coil multiplexing bridging routing section provided in some embodiments of this application is shown.

[0026] Figure 8 A schematic diagram of the structure in which the first coil and the second coil are interleaved, provided in some embodiments of this application, is shown.

[0027] Figure 9 A cross-sectional schematic diagram of the interlaced first and second coils provided in some embodiments of this application is shown.

[0028] Figure 10 A schematic diagram of the structure of an external start-up charging coil provided in some embodiments of this application is shown.

[0029] Figure 11 The diagram shows a structural schematic of the compensation module, the first switch, and the second switch connection provided in some embodiments of this application.

[0030] Explanation of reference numerals in the attached figures:

[0031] 100. Display device; 110. Array substrate; 111. Substrate; 1110. Display area; 1111. Non-display area; 112. Induction coil; 1120. First coil; 11200. Main body wiring section; 11201. Bridging wiring section; 11202. Conductive via section; 1121. Second coil; 113. Display control line; 114. Bridging line; 115. Connection trace; 120. Logic component; 130. Driver chip; 140. Flexible circuit board; 141, conductive pin; 150, electronic ink layer; 160, housing; 170, cover plate; 180, first switch; 190, second switch; 1000, compensation module; 1010, compensation coil; 1011, holding capacitor; 1012, third switch; 1013, rectifier tube; 200, external charging coil; 300, external start-up charging coil; A, first node; B, second node; C, third node; D, fourth node. Detailed Implementation

[0032] Exemplary embodiments will now be described more fully with reference to the accompanying drawings. However, these exemplary embodiments can be implemented in many forms and should not be construed as limited to the examples set forth herein; rather, these embodiments are provided to make this application more comprehensive and complete, and to fully convey the concept of the exemplary embodiments to those skilled in the art.

[0033] In this application, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of this application, "multiple" means two or more, unless otherwise explicitly specified.

[0034] In this application, unless otherwise expressly specified and limited, the term "connection" and other such terms should be interpreted broadly. For example, it can refer to a fixed connection, a detachable connection, or an integral connection; it can refer to a mechanical connection or an electrical connection; it can refer to a direct connection or an indirect connection through an intermediate medium; it can refer to the internal communication of two components or the interaction between two components. Those skilled in the art can understand the specific meaning of the above terms in this application according to the specific circumstances.

[0035] Furthermore, the described features, structures, or characteristics can be combined in any suitable manner in one or more embodiments. Numerous specific details are provided in the following description to give a thorough understanding of embodiments of this application. However, those skilled in the art will recognize that the technical solutions of this application can be practiced without one or more of the specific details, or other methods, components, apparatuses, steps, etc., can be employed. In other instances, well-known methods, apparatuses, implementations, or operations are not shown or described in detail to avoid obscuring various aspects of this application.

[0036] See Figure 1 As shown, this application provides a display device 100, which can be an electronic tag, wearable device, etc. The display device 100 may include an array substrate 110 and a logic component 120. The logic component 120 is disposed on one side of the array substrate 110 and can be electrically connected to the array substrate 110.

[0037] In this embodiment, the array substrate 110 may include a substrate 111 and an induction coil 112 disposed on the substrate 111. The substrate 111 may be a glass substrate, but is not limited to it; it may also be a substrate of other materials, such as PI material. The substrate 111 may have a display area 1110 and a non-display area 1111 located around the display area 1110. The display area 1110 has display signal lines (not shown in the figure). The display area 1110 can display an image, and the non-display area 1111 can be used to arrange the induction coil 112, the driver chip 130 described later, and the display control line 113.

[0038] See Figure 2 As shown, the induction coil 112 may include a first coil 1120, which can generate electromagnetic induction with the external charging coil 200 to form an induced current on the first coil 1120, and use this induced current to supply power to the logic component 120.

[0039] It is understandable that placing the induction coil 112 in the non-display area 1111 can reduce or eliminate as much as possible the interference of the induction coil 112 on the display signal line in the display area 1110, ensure the normal transmission of the display signal line signal, thereby ensuring the normal movement of electrophoretic particles in the electronic ink layer 150 and ensuring the normal display of the display device 100.

[0040] Among them, see Figure 1 and Figure 2 As shown, the logic component 120 can be disposed on one side of the array substrate 110 and electrically connected to the opposite ends of the induction coil 112. That is, when the first coil 1120 and the external charging coil 200 electromagnetically induce a current, this induced current can serve as a power supply for the logic component 120. In this way, by using the induced current generated by the first coil 1120 to power the logic component 120, compared to the solution of designing a battery inside the display device 100, the internal space occupied by the battery in the display device 100 can be reduced, thereby thinning the display device 100 and effectively reducing the manufacturing cost and size of the display device 100. In addition, by using the first coil 1120 and the external charging coil 200 to power the logic component 120, compared to the solution of placing the first coil in the logic component 120, the design size of the logic component 120 can be reduced, and the manufacturing cost of the logic component 120 can be lowered.

[0041] In this embodiment, the first coil 1120 may be arranged in multiple turns around the display area 1110 to generate a sufficiently large induced current to power the logic component 120.

[0042] For example, see Figure 2 and Figure 3 As shown, the first coil 1120 has a start end (not shown in the figure) and a tail end (not shown in the figure). The start end is electrically connected to the logic component 120. The first coil 1120 can be arranged along the outer contour of the display area 1110 and is arranged around the display area 1110 by at least two turns (or three, four or five turns). That is, the first coil 1120 is formed around the display area 1110 in the non-display area 1111. The tail end is located in the inner loop of the first coil 1120 and crosses multiple turns of the first coil 1120 through the bridging wire 114 described below to connect with the logic component 120 so as to transfer the induced current generated on the first coil 1120 to the logic component 120 and supply power to the logic component 120.

[0043] Of course, in some embodiments, the first coil 1120 may also have one turn of the first coil 1120, which surrounds the display area 1110.

[0044] In the embodiments of this application, see Figure 4 As shown, the non-display area 1111 may include a display control line 113. The display control line 113 may be arranged on the same layer as the display signal line in the display area 1110 and connected to the display signal line. The display control line 113 may be configured to transmit the display signal provided by the logic component 120 to the display signal line for screen display refresh.

[0045] In this embodiment, the first coil 1120 can be disposed on the same layer as the display control line 113. The first coil 1120 may include multiple main trace portions 11200 and bridging trace portions 11201. The main trace portions 11200 are disposed on the same layer as the display control line 113 and are spaced apart. The bridging trace portions 11201 are disposed on different layers from the main trace portions 11200 and the display control line 113, and overlap in the stacking direction of the array substrate 110. The bridging trace portions 11201 can be connected to the main trace portions 11200 located on both sides of the display control line 113 through conductive via portions 11202, so that the first coil 1120 is a connected line, which can supply power to the logic component 120 by the induced current generated by the first coil 1120.

[0046] It is worth mentioning that if there are traces affecting the first coil 1120 in the circumferential direction of the first coil 1120, the main body traces 11200 separated by the bridging traces 11201 can be bridged, and it is not limited to the display control line 113.

[0047] In this embodiment, the line width of the bridging trace 11201 is greater than the line width of the main trace 11200. By making the line width of the bridging trace 11201 greater than the line width of the main trace 11200, the connection stability of the main traces 11200 at both ends of the display control line 113 can be increased, and the bridging trace 11201 can be prevented from breaking at the display control line 113.

[0048] See Figure 2 and Figure 3 As shown, the array substrate 110 may also include a bridging wire 114, which may be located on a different layer from the first coil 1120. One end of the bridging wire 114 may be electrically connected to the logic component 120, and the other end may cross the multiple turns of the first coil 1120 surrounding the display area 1110 to connect to the tail end of the first coil 1120 located in the inner circle, thereby electrically connecting the tail end of the first coil 1120 to the logic component 120 to supply power to the logic component 120.

[0049] It should be noted that both the bridging wire 114 and the first coil 1120 can use metallic traces, such as molybdenum-based alloys (Mo / Ti) or copper-based alloys (Cu / Mo). An insulating layer can be provided between the bridging wire 114 and the first coil 1120 to reduce interference between them. The bridging wire 114 can be connected to the tail end of the first coil 1120 through a via structure on the insulating layer to introduce the induced current in the first coil 1120 into the logic component 120, thereby supplying power to the logic component 120.

[0050] Furthermore, the bridging wire 114 can be disposed on the same layer as the bridging wiring section 11201, that is, the bridging wire 114 is manufactured at the same time as the bridging wiring section 11201, thereby reducing the manufacturing cost of the bridging wire 114 and improving the manufacturing efficiency of the display device 100.

[0051] In this application, "same-layer configuration" refers to a layer structure formed using the same film deposition process to create a film layer for a specific pattern, and then using the same mask to form a single patterning process. That is, one patterning process corresponds to one mask (also called a photomask). Depending on the specific pattern, a single patterning process may include multiple exposure, development, or etching processes, and the specific pattern in the formed layer structure can be continuous or discontinuous. These specific patterns may also be at different heights or have different thicknesses. This simplifies the manufacturing process, saves manufacturing costs, and improves production efficiency.

[0052] In this embodiment, the display area 1110 is further provided with scan lines and data lines. The scan lines extend in the row direction, and the data lines extend in the column direction. The scan lines and data lines are on different layers and are insulated from each other. Both the scan lines and data lines can be made of metal or alloy materials, such as molybdenum, aluminum, and titanium, to ensure good conductivity. However, they are not limited to these materials and can also be made of other materials with good conductivity.

[0053] In this embodiment, the display signal line can be a scan line. The first coil 1120 and the display control line 113 can be arranged in the same layer as the scan line. By arranging the first coil 1120 in the same layer as the scan line, the first coil 1120 can be closer to the lower surface of the substrate 111, and the distance between it and the external charging coil 200 is shorter. The interference experienced between the first coil 1120 and the external charging coil 200 is less, which can improve the energy transfer efficiency between the external charging coil 200 and the first coil 1120 and reduce the energy loss between the first coil 1120 and the external charging coil 200. In addition, by arranging the display control line 113, the first coil 1120 and the scan line in the same layer, the display control line 113 and the first coil 1120 can be fabricated at the same time as the scan line, without the need to use additional fabrication processes to fabricate the first coil 1120, which can reduce the manufacturing cost of the display device 100.

[0054] In other embodiments of this application, see Figure 5 As shown, the display signal line can also be a data line. The display control line 113 and the first coil 1120 can also be arranged on the same layer as the data line to reduce the impact on the scan line layer routing and the routing of the driver chip 130 below. Compared to the scheme where the first coil 1120 is arranged on the same layer as the scan line, this reduces the number of bridging traces 11201 and conductive vias 11202, lowering production costs. After the display control line 113, the first coil 1120, and the data line are arranged on the same layer, the first coil 1120 can bridge broken main traces 11200 using bridging traces 11201 (which is on a different layer than the data line) to cross data lines or other signal lines on the same layer, making the first coil 1120 a connected circuit. The bridging line 114 and the bridging trace 11201 can be arranged on the same layer as the scan line.

[0055] In this embodiment, a pixel electrode is further provided within the display area. Data signals on the data lines are transmitted to the pixel electrode via a scan line input signal, and the pixel electrode controls the movement of electrophoretic particles in the electrophoretic solution, as described below. The pixel electrode can be a transparent electrode; for example, it can be made of ITO (indium tin oxide) material to improve light transmittance, but it is not limited to this and can also be made of other transparent conductive materials.

[0056] In the embodiments of this application, see Figure 3 As shown, the bridging trace 11201 and bridging wire 114 can be arranged on the same layer as the data line. That is, while preparing the data line, the bridging wire 114 and bridging trace 11201 are formed in the non-display area 1111 to cross the first coil 1120 which is arranged with multiple turns around the display area 1110 and the main trace 11200 on both sides of the display control line 113. It is connected to the tail end of the first coil 1120 through the via structure on the gate insulation layer and to the main trace 11200 located on both sides of the display control line 113 through the conductive via 11202.

[0057] Understandably, see Figure 4 As shown, the via structure and conductive via portion 11202 on the gate insulating layer can be fabricated before the data line is fabricated.

[0058] In different embodiments of this application, the bridging wire 114 and the bridging trace 11201 can also be disposed on the same layer as the pixel electrode. That is, the bridging wire 114 and the bridging trace 11201 can be disposed on the same layer as the pixel electrode, so that the bridging wire 114 and the bridging trace 11201 can be fabricated at the same time as the pixel electrode, which can improve manufacturing efficiency and save manufacturing costs.

[0059] In other embodiments of this application, the bridging line 114 may also be a separately configured metal trace, which may be configured on a different layer from the scan lines, data lines, and pixel electrodes. That is, as long as the bridging line 114 can cross the first coil 1120 configured around the display area 1110 and connect to the tail end located in the inner circle.

[0060] In some other embodiments of this application, the bridging routing section 11201 may also be disposed on a different layer from the bridging line 114, as long as the bridging routing section 11201 can connect the main routing sections 11200 on both sides of the display control line 113.

[0061] In other words, the bridging wiring section 11201 can be set on the same layer as the bridging wiring section 114 or on a different layer, depending on the specific design of different embodiments.

[0062] In the embodiments of this application, see Figure 2 and Figure 3As shown, the non-display area 1111 also includes a connection trace 115 disposed on the same layer as the first coil 1120. One end of the connection trace 115 is electrically connected to the logic component 120, and the other end is connected to the end of the bridging wire 114 away from the tail end through a via structure (not shown in the figure). Since the connection trace 115 is disposed on the same layer as the first coil 1120, the connection trace 115 is closer to the surface of the substrate 111 than the bridging wire 114. The number of via layers connecting the connection trace 115 to the logic component 120 is less, which can simplify the connection method between the first coil 1120 and the logic component 120, reduce the number of vias, and thus reduce the manufacturing cost.

[0063] In some embodiments of this application, the induction coil 112 may further include a first coil 1120 and a second coil 1121 located on different layers. The first end and the second end of the first coil 1120 are respectively connected to the logic component 120, and the first end and the second end of the second coil 1121 are respectively connected to the first end and the second end of the first coil 1120 through conductive via structures, so that both the second coil 1121 and the first coil 1120 are connected to the logic component 120.

[0064] In some embodiments of this application, the orthographic projection of the first coil 1120 on the substrate 111 coincides with the orthographic projection of the second coil 1121 on the substrate 111. That is, this embodiment uses a double-layer circuit with common routing and winding, which can reduce impedance while allowing the induction coil 112 to carry a larger induced current, resulting in higher energy transmission efficiency and reduced efficiency loss.

[0065] It is worth mentioning that, see Figure 8 and Figure 9 As shown, the orthographic projection of the first coil 1120 on the array substrate 110 can also lie between the orthographic projections of the adjacent second coil 1121 on the array substrate 110. In this way, by interleaving the first coil 1120 and the second coil 1121, the shielding effect of the first coil 1120 or the second coil 1121 located on the bottom side on the second coil 1121 or the first coil 1120 located above it and the external charging coil 200 can be reduced, ensuring that the second coil 1121 or the first coil 1120 located on the upper side can also generate induced current with the external charging coil 200, thus increasing the induced current generated by the induction coil 112. By interleaving the first coil 1121 and the second coil 1121, more induction coils 112 can also be arranged.

[0066] In some embodiments of this application, the bridging trace 11201 can be disposed on the same layer as the second coil 1121, so that the second coil 1121 can be reused as the bridging trace 11201, which saves the design of the bridging trace 11201, increases the current, and saves manufacturing costs.

[0067] In other embodiments of this application, the bridging wiring section 11201 may also be disposed on a different layer from the first coil 1120 and the second coil 1121, and the main wiring section 11200 on both sides of the display control line 113 may be connected by other metal layers.

[0068] It is understandable that if the display control line 113 and the second coil 1121 are arranged on the same layer, the first coil 1120 can be reused as a bridging trace 11201 to connect the second coils 1121 located on both sides of the display control line 113. That is, when there is a trace affecting the first coil 1120 or the second coil 1121 in the winding direction of the induction coil 112, the second coil 1121 or the first coil 1120 arranged in a single layer can be used as a bridging trace 11201 to bridge the broken first coil 1120 and second coil 1121, and it is not limited to the display control line 113. The first coil 1120 and the second coil 1121 can be each other's bridging traces 11201, ensuring that the first coil 1120 and the second coil 1121 form a connected circuit, and while ensuring the generation of induced current, it can also reduce production costs.

[0069] In some embodiments of this application, the line width of the bridging wiring portion 11201 is greater than the line width of the main wiring portion 11200, so as to reduce the resistance difference between the second coil 1121 at the bridging wiring portion 11201 and the resistance difference between the double-layered first coil 1120 and the second coil 1121, and ensure that the resistance is uniformly set at all points on the induction coil 112.

[0070] For example, the line width of the bridging wiring section 11201 is twice the line width of the main wiring section 11200 to ensure uniform resistance at any point on the induction coil 112 and to ensure stable induced current.

[0071] In some embodiments of this application, the first coil 1120 can be disposed on the same layer as the scan line, and the second coil 1121 can be disposed on the same layer as the data line, so that the first coil 1120 and the second coil 1121 are formed in the non-display area while the scan line and the data line are being prepared, thereby reducing the production cost of the induction coil 112.

[0072] In other embodiments of this application, see Figure 10 and Figure 11As shown, the display device 100 may further include a first switch 180 and a second switch 190. The induction coil 112 includes a first coil 1120 and a second coil 1121 located on different layers. The first end of the first coil 1120 and the logic component 120 are connected to a first node A, and the second end of the first coil 1120 and the logic component 120 are connected to a second node B. The first end of the second coil 1121 is connected to the first node A through the first switch 180, and the second end of the second coil 1121 is connected to the second node B through the second switch 190. The first switch 180 and the second switch 190 are configured to turn on or off according to the target power required by the logic component 120.

[0073] In other embodiments of this application, the first switch 180 and the second switch 190 may be a first transistor and a second transistor, respectively, and the first transistor and the second transistor are turned on or off by a signal indicating the target power required by the logic component 120. That is, the control terminals of the first transistor and the second transistor are connected to the signal indicating the target power required by the logic component 120.

[0074] For example, if the logic component 120 requires a large target power, the first transistor and the second transistor are turned on under the action of the first drive signal, so that the second coil 1121 and the first coil 1120 are used simultaneously to generate induced current with the external charging coil 200, and the induced current of the first coil 1120 and the second coil 1121 is output through the second node B to transmit the induced current in the second node B to the logic component 120 to supply power to the logic component 120. By utilizing the first coil 1120 and the second coil 1121 to generate induced current simultaneously, the induction coil 112 can generate a larger induced current, so as to ensure that the logic component 120 can work normally when the display device 100 requires a large power.

[0075] If the target power required by the logic component 120 is small, the first transistor and the second transistor can be disconnected under the action of the second drive signal, thereby disconnecting the second coil 1121 from the first coil 1120. Only the first coil 1120 and the external charging coil 200 are used to generate an induced current. This induced current generated by the first coil 1120 is transmitted to the logic component 120 through the second node B to supply power to the logic component 120. By utilizing only the first coil 1120 to generate the induced current, it can be ensured that the logic component 120 can operate normally under low current conditions.

[0076] In some other embodiments of this application, a compensation module 1000 may also be provided in the non-display area 1111. The compensation module 1000 may include a compensation coil 1010. The size of the compensation coil 1010 is smaller than the size of the induction coil 112, so as to reduce the amount of non-display area 1111 occupied by the compensation coil 1010, and ensure that the induction coil 112 has sufficient area for setting.

[0077] In other embodiments of this application, see Figure 11 As shown, the compensation coil 1010 is configured to cooperate with the external start-up charging coil 300 to generate a drive signal. The drive signal is transmitted via a drive line to the control terminals of the first transistor and the second transistor. The first transistor is configured to connect the first end of the second coil 1121 to the first node A under the drive signal, and the second transistor is configured to connect the second end of the second coil 1121 to the second node B under the drive signal. Thus, the drive signal generated by the compensation module 1000 produces a first drive signal or a second drive signal for the first and second transistors, causing them to turn on or off. By independently driving the first and second transistors with the compensation module 1000, the on / off state of the first and second transistors is not affected by other signals, allowing for independent control of both transistors, and enabling rapid response from both.

[0078] In other embodiments of this application, see Figure 11 As shown, the compensation module 1000 may further include a sustaining capacitor 1011 and a third switch 1012. The first end of the sustaining capacitor 1011, the first end of the compensation coil 1010, and the first end of the third switch 1012 are all connected to a third node C, which is grounded. The second end of the sustaining capacitor 1011, the second end of the compensation coil 1010, the control terminal of the first transistor, and the control terminal of the second transistor are all connected to a fourth node D. The control terminals of the first and second transistors are configured to receive drive signals. The control terminal of the third switch 1012 is configured to receive a short-circuit signal transmitted by the logic component 120 when the logic component 120 reaches the target charge level, thereby connecting the first and second ends of the sustaining capacitor 1011 to ground the sustaining capacitor 1011. This removes the voltage at the control terminals of the first and second transistors, causing the first and second transistors to turn off. Only the induced current generated by the first coil 1120 and the external charging coil 200 supplies power to the logic component 120, adapting to situations where the target charge required by the logic component 120 is low.

[0079] In other embodiments of this application, the third switch 1012 may be a third transistor. When the third transistor receives a short-circuit signal from the logic component 120, it turns on to connect the first and second terminals of the sustaining capacitor 1011 and ground it, thereby removing the voltage on the sustaining capacitor 1011 and the control terminals of the first switch 180 and the second switch 190, so as to disconnect the second coil 1121 from the first coil 1120. The first coil 1120 generates an induced current with the external charging coil 200.

[0080] It is understandable that the control terminals of the first transistor and the second transistor can be connected to the fourth node D via switch traces to transmit drive signals to the control terminals of the first transistor and the second transistor.

[0081] In other embodiments of this application, see Figure 11 As shown, the compensation module 1000 also includes a rectifier tube 1013, and the second end of the compensation coil 1010 is connected to the fourth node D through the rectifier tube 1013. The rectifier tube 1013 can convert the alternating current generated by the compensation coil 1010 into direct current, so that the first transistor and the second transistor can be turned on smoothly, ensuring that the first coil 1120 and the second coil 1121 can be turned on when the amount of electricity is large.

[0082] It should be understood that the compensation coil 1010 can generate an AC drive signal with the external start-up charging coil 300. After rectification by the rectifier diode 1013, the AC drive signal is converted into a DC drive signal. The DC drive signal charges the sustaining capacitor 1011. During the charging process of the sustaining capacitor 1011, the drive signal is transmitted to the control terminals of the first transistor and the second transistor through the switch wiring to control the first transistor and the second transistor to conduct, thereby connecting the second coil 1121 with the first coil 1120. The first coil 1120 and the second coil 1121 simultaneously generate induced current with the external charging coil 200, providing a large induced current for the logic component 120. When the logic component 120 reaches the target charge, a short-circuit signal is input to the third transistor to turn it on, connecting the first terminal and the second terminal of the sustaining capacitor 1011 and grounding it, removing the voltage at the control terminals of the first transistor and the second transistor, and using the first coil 1120 to continuously supply power to the logic component 120.

[0083] In the embodiments of this application, see Figure 2As shown, the display device 100 may further include a driver chip 130 disposed on the substrate 111. The driver chip 130 may be electrically connected to the logic component 120 and the display control line 113 disposed in the non-display area 1111. The logic component 120 transmits screen signals to the driver chip 130. The driver chip 130 provides scanning signals to the display signal lines in the display area 1110 through the display control line 113 according to the screen signals, so as to drive the driving transistors in the sub-pixels to turn on or off, thereby driving the movement of electrophoretic particles in the electronic ink layer 150 in the display area 1110.

[0084] Understandably, the driver chip 130 can be fixed to the pins on the substrate 111 using anisotropic conductive adhesive (ACF) to achieve vertical conductivity and lateral insulation.

[0085] In some embodiments of this application, see Figure 2 As shown, the first coil 1120 surrounds the display area 1110 and the driver chip 130, which can reduce the bridging area of ​​the display control line 113 emitted by the first coil 1120 and the driver chip 130, making the first coil 1120 more continuous, reducing the number of bridging traces 11201, and thus reducing manufacturing costs.

[0086] In the embodiments of this application, see Figure 1 As shown, the logic component 120 can be disposed on the back side of the array substrate 110 so that the logic component 120 and the array substrate 110 are arranged sequentially in the display direction, which can expand the display area of ​​the display side of the display device 100 and thus improve the display screen.

[0087] In the embodiments of this application, see Figure 1 and Figure 2 As shown, the display device 100 may further include a flexible circuit board 140 capable of reverse power supply. The logic component 120 is connected to the driver chip 130 and the first coil 1120 on the array substrate 110 via the flexible circuit board 140.

[0088] The flexible circuit board 140 may include a pin array, one end of which is connected to the logic component 120 and the other end of which is connected to the array substrate 110.

[0089] For example, see Figure 2 As shown, the substrate 111 has a bonding area at its edge, and the pin array includes multiple conductive pins 141 (Pin) spaced apart from each other. The end of the conductive pin 141 away from the logic component 120 is connected to the pin on the glass substrate through anisotropic conductive adhesive to electrically connect with the driver chip 130, thereby transmitting screen signals to the driver chip 130 to control the scan signals and data signals on the scan lines and data lines, thereby controlling the movement of electrophoretic particles.

[0090] In the embodiments of this application, see Figure 2 As shown, the pin array in the flexible circuit board 140 includes two conductive pins 141. These pins can be located at opposite edges of the flexible circuit board 140. One end of one conductive pin 141 can be connected to the logic component 120, and the other end can be connected to the beginning of the first coil 1120. One end of the other conductive pin 141 is connected to the logic component 120, and the other end is connected to the aforementioned connection trace 115, so as to guide the induced current in the first coil 1120 into the logic component 120 to supply power to the logic component 120.

[0091] It is understood that logic component 120 may include a rectifier circuit (not shown), a voltage regulator circuit (not shown), a power management chip (not shown), and a controller (not shown). The controller is electrically connected to the power management chip, and the power management chip is connected to conductive pins 141 on the flexible circuit board 140 via the voltage regulator circuit and the rectifier circuit, and then electrically connected to the induction coil 112. The alternating current of the induced current is converted to direct current by the rectifier bridge in the rectifier circuit, and then the direct current is transmitted to the power management chip through the voltage regulator circuit. The voltage regulator circuit can maintain the stability of the output voltage when the input voltage fluctuates or the load changes. The power management chip can transmit the direct current to the controller to power the controller, and then provide image signals to the driver chip 130 to adjust the display screen.

[0092] In some embodiments of this application, the display device 100 may also include a boost module (not shown in the figure). The boost module may be disposed in the non-display area 1111 of the array substrate 110 or in the logic component 120. One end of the boost module is connected to the tail end of the first coil 1120, and the other end is connected to the rectifier circuit. The boost module can boost the voltage generated by the first coil 1120, so that the first coil 1120 with the fewest turns can meet the power supply of the logic component 120. This can save the space occupied by the first coil 1120 in the non-display area 1111, reduce the space occupied in the non-display area 1111, and further realize a narrow bezel design.

[0093] It should be noted that the boost module can use a charge pump boost scheme, which utilizes capacitor charging and discharging to achieve voltage multiplication.

[0094] In addition, the logic component 120 may also include an energy storage element (not shown in the figure), which is charged by the induced current generated by the first coil 1120 in cooperation with the external charging coil 200, so that when the external charging coil 200 is de-energized, the energy storage element can still provide power to the logic component 120 to realize the display.

[0095] In the embodiments of this application, see Figure 1 As shown, the display device 100 may further include an electronic ink layer 150. The electronic ink layer 150 is disposed above the array substrate 110 and is disposed opposite to the array substrate 110. The electronic ink layer 150 may include multiple microcapsule structures (not shown) or multiple microcup structures (not shown), each microcapsule structure / microcup structure corresponding one-to-one with a sub-pixel in the display area 1110. Each microcapsule structure / microcup structure includes black electrophoretic particles and white electrophoretic particles. By adjusting the voltage of the pixel electrode in the sub-pixel, the movement direction of the black electrophoretic particles and white electrophoretic particles is controlled, thereby realizing the display image.

[0096] In this application, the logic component 120 can draw power from the induction coil 112 on the array substrate 110 through the flexible circuit board 140. After drawing power, it receives the screen signal via Bluetooth or WiFi. After processing by the logic component 120, it is transmitted to the driver chip 130 through the flexible circuit board 140, thereby controlling the signals of the scan line and data line, thereby controlling the voltage of the pixel electrode, thereby controlling the movement of electrophoretic particles in the electronic ink layer 150, and finally starting the bistable screen refresh.

[0097] In the embodiments of this application, please refer to Figure 1 As shown, the display device 100 may further include a housing 160, which may have a first receiving cavity and a second receiving cavity. A logic component 120 is disposed in the first receiving cavity (not shown), and an array substrate 110 and an electronic ink layer 150 may be disposed in the second receiving cavity (not shown). An external induced power supply may be disposed on the side of the housing 160 opposite to the display and corresponding to the array substrate 110, serving as the transmitter of the induced current.

[0098] In the embodiments of this application, please refer to Figure 1 As shown, the display device 100 may also include a cover plate 170. The cover plate 170 is disposed on the upper surface of the housing 160 to seal the second receiving cavity, thereby preventing impurities from entering the electronic ink layer 150 and the array substrate 110, and thus protecting the electronic ink layer 150 and the array substrate 110.

[0099] In the description of this specification, references to terms such as "some embodiments," "exemplarily," etc., indicate that a specific feature, structure, material, or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of this application. The illustrative expressions of the above terms in this specification do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in a suitable manner in any one or more embodiments or examples. Moreover, without contradiction, those skilled in the art can combine and integrate the different embodiments or examples described in this specification, as well as the features of different embodiments or examples.

[0100] Although embodiments of this application have been shown and described above, it is understood that the above embodiments are exemplary and should not be construed as limiting this application. Those skilled in the art can make changes, modifications, substitutions and variations to the above embodiments within the scope of this application. Therefore, any changes or modifications made in accordance with the claims and description of this application should fall within the scope of this patent application.

Claims

1. A display device, characterized by comprising: The display device comprises: a logic component; an array substrate connected with the logic component, the array substrate having a display area and a non-display area located at the periphery of the display area, the display area being provided with display signal lines, and the non-display area being provided with an induction coil configured to cooperate with an external charging coil to supply power to the logic component, the logic component providing display signals to the display signal lines under the power provided by the induction coil when receiving picture information; the display device further comprises a first switch and a second switch; the induction coil comprises at least a first coil and a second coil located at different layers, a first end of the first coil and the logic component being connected to a first node, a second end of the first coil and the logic component being connected to a second node, a first end of the second coil being connected to the first node through the first switch, and a second end of the second coil being connected to the second node through the second switch, the first switch and the second switch being configured to be turned on or off according to a target power required by the logic component.

2. The display device according to claim 1, the non-display area being provided with a display control line, the display control line being connected with the display signal line, and the display control line being configured to transmit the display signals provided by the logic component to the display signal line; the induction coil comprises at least a first coil, the first coil comprising a plurality of main wiring portions and a bridge wiring portion, the main wiring portions being provided in the same layer as the display control line and having a spacing, and the bridge wiring portion being located at different layers from the main wiring portions and the display control line and having an overlap in the stacking direction of the array substrate, and the bridge wiring portion being connected with the main wiring portions located on both sides of the display control line through a conductive via portion.

3. The display device according to claim 2, wherein The line width of the bridge wiring portion is greater than the line width of the main wiring portion.

4. The display device according to claim 1, wherein The non-display area is provided with a compensation module, the compensation module comprising a compensation coil, the compensation coil having a size smaller than that of the induction coil, and the compensation coil being configured to cooperate with an external starting charging coil to generate a driving signal; the first switch and the second switch are configured to be turned on under the driving of the driving signal, so that the second coil cooperates with the external starting charging coil to output power to the second node to supply power to the logic component.

5. The display device according to claim 4, wherein The compensation module further comprises a maintenance capacitor and a third switch, a first end of the maintenance capacitor, a first end of the compensation coil and a first end of the third switch are all connected with a third node, and the third node is grounded; a second end of the maintenance capacitor, a second end of the compensation coil, a control end of the first switch, a control end of the second switch and a second end of the third switch are all connected with a fourth node, the control end of the first switch and the control end of the second switch are configured to receive the driving signal, and the control end of the third switch is configured to receive a short-circuit signal of the logic component when the logic component reaches a target power, so that the first end and the second end of the maintenance capacitor are connected.

6. The display device according to claim 5, wherein The compensation module further comprises a rectifier tube, and a second end of the compensation coil is connected to the fourth node through the rectifier tube.

7. The display device according to claim 1, wherein The first coil and the second coil are arranged on the array substrate.

8. The display device according to claim 1, wherein The non-display area is provided with a display control line, the display control line is connected with the display signal line, and the display control line is configured to transmit the display signal provided by the logic component to the display signal line. The display signal line is a scanning line, and the display control line and the first coil are arranged in the same layer as the scanning line.

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