Display driving circuit, driving chip and display device

Abstract

The application discloses a display driving circuit, a driving chip and a display device. The display driving circuit comprises a first transistor and a second transistor, the ratio of the current flowing through the first transistor to the current flowing through the second transistor is A; a third transistor and a fourth transistor, the ratio of the current flowing through the third transistor to the current flowing through the fourth transistor is N; a fifth transistor and a sixth transistor, the ratio of the current flowing through the fifth transistor to the current flowing through the sixth transistor is B, wherein, in a small signal stage, the current establishment speed is related to the equivalent transconductance of the first transistor; the equivalent transconductance is directly proportional to the product of B and N, and inversely proportional to A. The display driving circuit, the driving chip and the display device improve the current establishment speed.

Description

Technical Field

[0001] This invention relates to the field of display technology, and in particular to a display driving circuit, a driving chip, and a display device. Background Technology

[0002] In existing display technologies, the brightness of a display device is directly proportional to the amount of current flowing through the pixels. Therefore, the core task of the display driver chip, which provides the driving signals to the display device, is to generate and output a highly accurate and stable driving current to each pixel unit.

[0003] When the output current of a display driver chip needs to switch from one grayscale value to another, the output current does not jump to the target value instantaneously. Due to the presence of the load capacitance, the output current needs to undergo a transient response process before it finally stabilizes at the target current value. This time, from the issuance of the initial switching command to the output current reaching and stabilizing within a predetermined error range near the target current value, is called the current settling time. Current settling speed (time) is a crucial dynamic parameter for measuring the performance of current-driven display driver chips.

[0004] Under the existing architecture, the current build-up speed (time) is limited by the loop bandwidth and slew rate. When the current build-up speed is affected, it will affect the brightness of the display. To achieve the same brightness, a larger channel current must be turned on, which will waste power.

[0005] Therefore, there is a need for a new display driver circuit, driver chip, and display device that can overcome at least one of the above problems. Summary of the Invention

[0006] In view of the above problems, the purpose of the present invention is to provide a display driving circuit, a driving chip and a display device, and in particular a technology to improve the current build-up speed of the display driving chip, thereby improving the current build-up speed.

[0007] According to one aspect of the present invention, a display driving circuit is provided, comprising:

[0008] The ratio of the current flowing through the first transistor to the current flowing through the second transistor is A;

[0009] The ratio of the current flowing through the third transistor to the current flowing through the fourth transistor is N;

[0010] The ratio of the current flowing through the fifth transistor to the current flowing through the sixth transistor is B.

[0011] In the small-signal phase, the current build-up rate is related to the equivalent transconductance of the first transistor; the equivalent transconductance is proportional to the product of B and N and inversely proportional to A.

[0012] Optionally, the first transistor is a P-type MOS transistor, and the second transistor is a P-type MOS transistor; the gate and drain of the first transistor are shorted, and the gate of the second transistor is connected to the gate of the first transistor;

[0013] The third transistor is an N-type MOS transistor, and the fourth transistor is an N-type MOS transistor; the drain of the third transistor is connected to the drain of the first transistor, and the gate of the fourth transistor is shorted to the drain.

[0014] The fifth transistor is an N-type MOS transistor, and the sixth transistor is an N-type MOS transistor; the gate of the fifth transistor is connected to the gate of the sixth transistor.

[0015] Optionally, the drain of the second transistor is connected to the drain of the sixth transistor, and the gate and drain of the sixth transistor are shorted to form a diode connection.

[0016] Optionally, the sources of the third transistor, the fourth transistor, the fifth transistor, and the sixth transistor are all grounded.

[0017] Optionally, the first transistor is a P-type MOS transistor; the display driving circuit further includes capacitors and a switching network;

[0018] The capacitor is connected between the gate of the first transistor and the reference voltage;

[0019] The switching network configures the first transistor as a diode connection during the sampling phase and charges the capacitor;

[0020] During the hold phase, the switching network configures the first transistor and the third transistor as a common-source amplifier.

[0021] Optionally, the switching network includes:

[0022] A first switch is disposed between the gate and the drain of the first transistor;

[0023] A second switch is disposed between the drain of the first transistor and the drain of the third transistor;

[0024] A third switch, wherein the third switch is disposed between the capacitor and the reference voltage; and

[0025] A fourth switch is disposed between the gate of the first transistor and the capacitor.

[0026] Optionally, during the sampling phase, the first switch is closed, the third switch is closed, the second switch is open, and the fourth switch is open.

[0027] During the holding phase, the first switch is open, the third switch is open, the second switch is closed, and the fourth switch is closed.

[0028] Optionally, the display driving circuit further includes:

[0029] The setting module is used to set the values ​​of N, A, and B.

[0030] According to another aspect of the present invention, a chip is provided, comprising:

[0031] The display driver circuit described above.

[0032] According to another aspect of the present invention, a display device is provided, comprising:

[0033] Display panel; and

[0034] The display driving circuit described above is connected to the display panel to drive the display panel to display.

[0035] The display driving circuit, driving chip, and display device provided by the present invention are equipped with appropriate current scaling factors A, N, and B, which significantly improves the current build-up speed.

[0036] Furthermore, by optimizing the current replication ratio, especially the current control during the sampling and holding phases, the charge conservation characteristic of the capacitor can rapidly raise the gate voltage of the first transistor when the initial VCR potential is AVDD in the early stage of the holding phase, causing the first transistor to turn off, which in turn causes the second, sixth, and fifth transistors to turn off as well. As the VCR potential gradually decreases, the gate voltage of the first transistor gradually recovers, and the first transistor begins to conduct, which in turn causes the second, sixth, and fifth transistors to gradually conduct as well, ultimately forming a stable current output. This significantly improves the current build-up speed, especially during the large signal phase.

[0037] Furthermore, by optimizing the equivalent transconductance of the first transistor, the loop bandwidth was improved, which not only increased the current build-up speed but also enhanced the circuit's response speed and stability.

[0038] Furthermore, the current ratio flowing through each transistor was set to ensure accurate current replication and transmission, thereby enabling the entire circuit to maintain a stable current output during both the sampling and holding phases, thus improving the reliability and accuracy of the circuit.

[0039] Furthermore, during the sampling phase, the first transistor is configured as a diode, and the gate voltage is determined by the current of the third transistor. The amount of charge stored in the capacitor is (Vgate - VCRES)·Cap. During the hold phase, the first and third transistors form a common-source amplifier. By utilizing the charge conservation characteristics of the capacitor, the gate voltage of the first transistor is controlled, thereby affecting the current build-up speed and stability of the entire circuit. This design not only improves the current build-up speed but also enhances the stability and reliability of the circuit.

[0040] Furthermore, by reasonably setting the current scaling factors A, N, and B, the first, second, fifth, and sixth transistors are all turned off in the initial stage of the holding phase, and the current flowing through the third transistor is N·IREF. This reduces unnecessary current loss and effectively reduces the power consumption of the circuit while improving the current build-up speed and loop bandwidth.

[0041] Furthermore, by flexibly setting the current scaling factors A, N, and B, the circuit can adapt to different application scenarios and requirements; this flexibility not only improves the versatility of the circuit, but also makes the circuit perform better under different operating conditions. Attached Figure Description

[0042] The above and other objects, features and advantages of the present invention will become more apparent from the following description of embodiments of the invention with reference to the accompanying drawings, in which:

[0043] Figure 1 A schematic diagram of the display driving circuit according to Embodiment 1 of the present invention is shown;

[0044] Figure 2 A schematic diagram of the display driving circuit according to Embodiment 2 of the present invention is shown;

[0045] Figure 3 A schematic diagram of the equivalent transconductance of a display driving circuit according to Embodiment 2 of the present invention is shown. Detailed Implementation

[0046] Various embodiments of the invention will now be described in more detail with reference to the accompanying drawings. In the various drawings, the same elements are indicated by the same or similar reference numerals. For clarity, the various parts in the drawings are not drawn to scale. Furthermore, certain well-known parts may not be shown in the drawings.

[0047] The specific embodiments of the present invention will be described in further detail below with reference to the accompanying drawings and examples. Many specific details of the invention, such as the structure, materials, dimensions, processing techniques, and methods of the components, are described below to provide a clearer understanding of the invention. However, as those skilled in the art will understand, the invention may be implemented without following these specific details.

[0048] It should be understood that when describing the structure of a component, when referring to a layer or region as being "above" or "on top of" another layer or region, it can mean that it is directly above the other layer or region, or that it contains other layers or regions between it and the other layer or region. Furthermore, if the component is flipped over, that layer or region will be located "below" or "under" the other layer or region.

[0049] According to one aspect of the present invention, a display driving circuit is provided. The display driving circuit includes a first to a sixth transistor.

[0050] Specifically, the ratio of the current flowing through the first transistor to the current flowing through the second transistor is A; the ratio of the current flowing through the third transistor to the current flowing through the fourth transistor is N; and the ratio of the current flowing through the fifth transistor to the current flowing through the sixth transistor is B. Optionally, the ratio of the current flowing through the second transistor to the fourth transistor is set according to the actual circuit (requirements); the ratio of the current flowing through the fourth transistor to the sixth transistor is set according to the actual circuit (requirements). Optionally, N, A, and B are specific values ​​or a range of values.

[0051] In the small-signal phase, the current build-up rate is related to the equivalent transconductance (ETD) of the first transistor; the ETD is directly proportional to the product of B and N, and inversely proportional to A. The current build-up process of a display driver chip includes starting from an initial state, gradually adjusting the current from an initial value (e.g., 0) to approach and eventually stabilize at the target value. The current build-up process of a display driver chip includes a large-signal phase and a small-signal phase. The large-signal phase is the initial stage of the current build-up process, where the current is rapidly increased to approach the target value as closely as possible. The small-signal phase is the stage where, after the current approaches the target value, the current is precisely adjusted to that target value.

[0052] Figure 1 A schematic diagram of the display driving circuit according to Embodiment 1 of the present invention is shown. Figure 1 As shown, the first transistor (MP3) is a P-type MOS transistor, and the second transistor (MP4) is a P-type MOS transistor. The gate and drain of the first transistor are shorted, and the gate of the second transistor is connected to the gate of the first transistor. Optionally, the first transistor (MP3) is connected to the current output terminal (i.e., the output port after current is established).

[0053] The third transistor (MN1) is an N-type MOS transistor, and the fourth transistor (MN2) is an N-type MOS transistor. The drain of the third transistor is connected to the drain of the first transistor, and the gate of the fourth transistor is shorted to the drain.

[0054] The fifth transistor (MN3) is an N-type MOS transistor, and the sixth transistor (MN4) is an N-type MOS transistor. The gate of the fifth transistor is connected to the gate of the sixth transistor.

[0055] Optionally, the drain of the second transistor is connected to the drain of the sixth transistor, and the gate and drain of the sixth transistor are shorted to form a diode connection.

[0056] Optionally, the sources of the third transistor, the fourth transistor, the fifth transistor, and the sixth transistor are all grounded.

[0057] In an optional embodiment of the present invention, the display driving circuit further includes a setting module. The setting module is used to set the values ​​(ranges) of N, A, and B (respectively).

[0058] Figure 2 A schematic diagram of the display driving circuit according to Embodiment 2 of the present invention is shown. Figure 2 As shown, the display driving circuit according to Embodiment 2 of the present invention further includes a capacitor (Cap) and a switching network.

[0059] Specifically, the first transistor (MP3) is a P-type MOS transistor. A capacitor is connected between the gate of the first transistor and the reference voltage (Vref).

[0060] During the sampling phase, the switching network configures the first transistor (MP3) as a diode connection and charges the capacitor (Cap). During the hold phase, the switching network configures the first transistor (MP3) and the third transistor (MN1) as a common-source amplifier.

[0061] Optionally, the switching network includes a first switch S1, a second switch S2, a third switch S3, and a fourth switch S4. The first switch S1 is disposed between the gate and drain of the first transistor (MP3). The second switch S2 is disposed between the drain of the first transistor (MP3) and the drain of the third transistor (MN1). The third switch S3 is disposed between the capacitor (Cap) and the reference voltage (Vref). The fourth switch S4 is disposed between the gate of the first transistor (MP3) and the capacitor (Cap).

[0062] Optionally, during the sampling phase, the first switch S1 is closed (conducting), the third switch S3 is closed, the second switch S2 is open (not conducting), and the fourth switch S4 is open. During the holding phase, the first switch S1 is open, the third switch S3 is open, the second switch S2 is closed, and the fourth switch S4 is closed.

[0063] Combination Figure 2 As shown, in a specific embodiment of the present invention, the sum of the currents flowing through the fifth transistor (MN3) and the fourth transistor (MN2) is IREF (e.g., the current provided by a current source), and the current ratios of each branch are as follows: Figure 2 The current ratio flowing through the first transistor (MP3) and the second transistor (MP4) is set to A:1 (I_MP3:I_MP4=A:1); the current ratio flowing through the fourth transistor (MN2) and the third transistor (MN1) is 1:N (I_MN2:I_MN1=1:N); and the current ratio flowing through the sixth transistor (MN4) and the fifth transistor (MN3) is 1:B (I_MN4:I_MN3=1:B).

[0064] The current flowing through the fourth transistor (MN2) is set to I_MN2 = I. Therefore, the current flowing through the third transistor (MN1) is I_MN1 = N·I, the current flowing through the second transistor (MP4) is I_MP4 = N·I / A, and the current flowing through the sixth transistor (MN4) is I_MN4 = B·N·I / A. Specifically, during the sampling phase, the first switch S1 and the third switch S3 are closed, while the second switch S2 and the fourth switch S4 are open. At this time, the first transistor (MP3) is connected in diode form, and its gate voltage (Vgate) is determined by the current of the third transistor (MN1). The charge stored in the capacitor Cap is (Vgate - VCRES)·Cap, where VCRES is, for example, the capacitor voltage during the sampling phase. Simultaneously, the second transistor (MP4) replicates the current of the first transistor (MP3) at a ratio of 1:A, and the fifth transistor (MN3) replicates the current of the sixth transistor (MN4) at a ratio of B:1. The third transistor (MN1) replicates the current of the fourth transistor (MN2) at a ratio of N:1.

[0065] During the hold phase, the first switch S1 and the third switch S3 are open, while the second switch S2 and the fourth switch S4 are closed. The first transistor (MP3) and the third transistor (MN1) form a common-source amplifier, with the gate of the first transistor (MP3) as the input and the drain of the first transistor (MP3) as the output. At the beginning of the hold phase, the initial value of the VCR (capacitor reference voltage) potential is AVDD (supply voltage). Due to the conservation of charge in the capacitor (Cap), the Vgate potential at the gate of the first transistor (MP3) is raised, causing the first transistor (MP3) to turn off. Therefore, the second transistor (MP4), the sixth transistor (MN4), and the fifth transistor (MN3) are all turned off, and the current flowing through the third transistor (MN1) is N·IREF.

[0066] Because the initial value of VCR potential is AVDD in the early stage of the hold phase, the charge conservation of the capacitor (Cap) will raise the Vgate potential of the first transistor (MP3), causing the first transistor (MP3) to turn off. Therefore, in the early stage of loop establishment, it is in the large signal phase, and the establishment speed of Vgp2 determines the establishment speed of the output current IOUT. In the large signal phase, the pull-down speed of Vgp2 (the node voltage at the gp2 node in the diagram) is determined by the magnitude of the current value of the third transistor (MN1), that is, the slew rate is IMN1 / C1 = N·IREF / C1.

[0067] Furthermore, Figure 3 A schematic diagram of the equivalent transconductance of a display driving circuit according to Embodiment 2 of the present invention is shown. (In conjunction with...) Figure 2 and Figure 3 As shown, the build-up speed of Vgp2 in the small-signal stage is determined by the loop bandwidth, which is related to the gm (transconductance) of the first transistor (MP3). Figure 3 The equivalent gm (transconductance) of the loop in the structure shown is (BN / A+1)·gm3, and the specific calculation method is as follows:

[0068] When the gate of the first transistor (MP3) experiences a voltage change of DeltaV, the first transistor (MP3) experiences a current change of gm3·DeltaV. Therefore, the second transistor (MP4) experiences a current change of gm3·DeltaV / A. Consequently, the fifth transistor (MN3) experiences a current change of B·gm3·DeltaV / A. The fourth transistor (MN2) experiences a current of the same magnitude but opposite direction to that of the fifth transistor (MN3). Therefore, the third transistor (MN1) experiences a current change of BN·gm3·DeltaV / A. Thus, the iout current is (BN / A+1)·gm3·DeltaV. The equivalent transconductance (Gm) is calculated as Gm = iout / DeltaV = (BN / A+1)·gm3. The architecture shown in this application has a large bandwidth and fast speed during the small-signal setup phase of the loop.

[0069] When the loop consisting of the seventh transistor (MP1), the eighth transistor (MP2), the first transistor (MP3), and the third transistor (MN1) reaches stability, the gate voltage of the first transistor (MP3) remains consistent with the gate voltage during the sampling phase, which is still Vgate. Since the charge stored in the capacitor (Cap) remains unchanged during the sampling and holding phases, the drain voltage VCR of the eighth transistor (MP2) is equal to VCRES at this time. Therefore, the eighth transistor (MP2) can accurately replicate the current value of the ninth transistor (MP0), thereby achieving constant current output.

[0070] Optionally, the seventh transistor is a P-type MOSFET, the eighth transistor is a P-type MOSFET, and the ninth transistor is a P-type MOSFET. The gate of the seventh transistor (MP1) is connected to the drain of the first transistor (MP3) via the fourth switch S4. The gate of the seventh transistor (MP1) is also connected to the gate of the first transistor (MP3) via the fourth switch S4 and the third switch S3 in sequence. The drain of the seventh transistor (MP1) is connected to the LED as an output terminal (IOUT). The source of the seventh transistor (MP1) is connected to the drain of the eighth transistor (MP2) via the second switch S2. The gate of the eighth transistor (MP2) is connected to the gate of the ninth transistor (MP0). The source of the eighth transistor (MP2) is connected to the source of the first transistor (MP3).

[0071] When the values ​​of N, A, and B are set (configured) appropriately, the scheme presented in this application achieves excellent oscillation performance. Combined with... Figure 2 As shown, listing the KCL equations for node Vnode1 yields:

[0072] IREF=BNI / A+I formula (1)

[0073] Let the total power consumption of the entire loop be Itotal, then we can obtain:

[0074] Itotal=NI+NI / A+IREF formula (2)

[0075] Substituting formula (2) into formula (1) yields:

[0076] Itotal=[(A+1)·N / (BN+A)]·IREF+ IREF formula (3)

[0077] We can assume that the current value of IREF is 1u, B=2, A=4, and N=8.

[0078] Then it can be calculated Figure 2 The total power consumption of the architecture within the dashed box is:

[0079] Itotal = 3μA;

[0080] Equivalent Gm = (BN / A+1)·gm3 = 5·gm3;

[0081] SR = N·IREF / C1 = 8 / C1;

[0082] The current value of the PM3 branch is 1.6μA.

[0083] In the above formula, gm3 represents the result of PM3 current being 1.6μA.

[0084] As can be seen from the above formula, the architecture described in this application has excellent performance in terms of both slew rate and transconductance, and the current build-up speed of the architecture described in this application is rapid.

[0085] According to another aspect of the present invention, a (driving) chip is provided. This chip includes the display driving circuit described above. This chip is used, for example, for driving a display device.

[0086] According to another aspect of the present invention, a display device is provided. The display device includes a display panel and a display driving circuit as described above. The display driving circuit is connected to the display panel to drive the display panel to display. Optionally, the display panel includes at least one selected from cathode ray tube display panels, digital light processing display panels, liquid crystal display panels, light-emitting diode display panels, organic light-emitting diode display panels, quantum dot display panels, Micro-LED display panels, Mini-LED display panels, field emission display panels, plasma display panels, electrophoretic display panels, and electrowetting display panels.

[0087] It should be noted that, in this document, relational terms such as "first" and "second" are used merely to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element.

[0088] As described above, these embodiments of the present invention do not exhaustively cover all details, nor do they limit the invention to the specific embodiments described. Clearly, many modifications and variations can be made based on the above description. This specification selects and specifically describes these embodiments to better explain the principles and practical applications of the invention, thereby enabling those skilled in the art to effectively utilize the invention and its modifications. The invention is limited only by the claims and their full scope and equivalents.

Claims

1. A display driving circuit, comprising: a first transistor and a second transistor, a ratio of a current flowing through the first transistor to a current flowing through the second transistor being A; a third transistor and a fourth transistor, a ratio of a current flowing through the third transistor to a current flowing through the fourth transistor being N; a fifth transistor and a sixth transistor, a ratio of a current flowing through the fifth transistor to a current flowing through the sixth transistor being B, wherein, in a small signal stage, a speed of establishing the current is related to an equivalent transconductance of the first transistor, the equivalent transconductance being proportional to a product of B and N and inversely proportional to A; the first transistor is a P-type MOS transistor, and the second transistor is a P-type MOS transistor; a gate of the first transistor is connected to a drain of the first transistor via a switch, and a gate of the second transistor is connected to the gate of the first transistor; the third transistor is an N-type MOS transistor, and the fourth transistor is an N-type MOS transistor; a drain of the third transistor is connected to the drain of the first transistor, and a gate of the fourth transistor is shorted to a drain of the fourth transistor; the fifth transistor is an N-type MOS transistor, and the sixth transistor is an N-type MOS transistor; a gate of the fifth transistor is connected to a gate of the sixth transistor; a drain of the second transistor is connected to a drain of the sixth transistor, and a gate of the sixth transistor is shorted to the drain of the sixth transistor to form a diode connection; a source of the third transistor, a source of the fourth transistor, a source of the fifth transistor, and a source of the sixth transistor are all grounded; a gate of the third transistor is connected to a gate of the fourth transistor, and a drain of the fourth transistor is connected to a drain of the fifth transistor.

2. The display drive circuit of claim 1, wherein, the first transistor is a P-type MOS transistor; and the display driving circuit further comprises a capacitor and a switch network; the capacitor is connected between a gate of the first transistor and a reference voltage; the switch network configures the first transistor as a diode connection in a sampling stage and charges the capacitor; the switch network configures the first transistor and the third transistor as a common source amplifier in a holding stage.

3. The display drive circuit of claim 2, wherein, the switch network comprises: a first switch disposed between a gate and a drain of the first transistor; a second switch disposed between the drain of the first transistor and a drain of the third transistor; a third switch disposed between the capacitor and the reference voltage; and a fourth switch disposed between the gate of the first transistor and the capacitor.

4. The display drive circuit of claim 3, wherein, in the sampling stage, the first switch is closed, the third switch is closed, the second switch is open, and the fourth switch is open; in the holding stage, the first switch is open, the third switch is open, the second switch is closed, and the fourth switch is closed.

5. The display drive circuit of claim 1, wherein, the display driving circuit further comprises: a setting module configured to set a value of the N, a value of the A, and a value of the B. 6.A chip, comprising: the display driving circuit according to any one of claims 1-5. 7.A display device, comprising: A display panel; And The display driving circuit according to any one of claims 1-5, which is connected with the display panel to drive the display panel to display.

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