Display panel, driving method thereof and display device

Abstract

The embodiment of the invention provides a display panel, a driving method thereof and a display device, the display panel comprises a plurality of sub-pixels, each sub-pixel comprises a pixel circuit and a light-emitting device which are electrically connected, the sub-pixels in the ith row comprise a plurality of sub-pixels arranged in the first direction, the sub-pixels in the multiple rows are arranged in the second direction, the second direction intersects with the first direction, i is any positive integer; one work cycle of the pixel circuit comprises a reset stage, a data writing stage and a light emitting stage, in the reset stage and / or the data writing stage of the (i + 1) th row of sub-pixels, the i th row of sub-pixels are in the light emitting stage, and the (i + 2) th row of sub-pixels are in the light emitting stage. According to the display panel and the display device, multiple rows of sub-pixels in the same area cannot be darkened at the same time, the dark state significance of dark state sub-pixel rows can be reduced, the brightness difference recognized by human eyes is weakened, and the eye protection function of the display panel is achieved.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of display, in particular to a display panel, a driving method thereof and a display device. BACKGROUND

[0002] With the development of display technology, consumers have higher and higher requirements for the performance of display panels, especially the eye protection requirements of display panels. However, in the prior art, when the display panel displays a frame picture, the brightness fluctuation in the frame picture is relatively obvious, which is not conducive to eye protection. Therefore, a solution is urgently needed. SUMMARY

[0003] In view of this, the embodiments of the present application provide a display panel, a driving method thereof and a display device to solve the above problems.

[0004] In a first aspect, the embodiments of the present application provide a display panel, comprising a plurality of sub-pixels, each sub-pixel comprising a pixel circuit and a light emitting device connected electrically, the i-th row of sub-pixels comprising a plurality of sub-pixels arranged along a first direction, and a plurality of rows of sub-pixels arranged along a second direction, the second direction intersecting the first direction, wherein i is any positive integer. One working cycle of the pixel circuit comprises a reset phase, a data writing phase and a light emitting phase, in the reset phase and / or the data writing phase of the (i+1)-th row of sub-pixels, the i-th row of sub-pixels is in the light emitting phase, and the (i+2)-th row of sub-pixels is in the light emitting phase.

[0005] In a second aspect, based on the same inventive concept, the embodiments of the present application provide a driving method of a display panel, the display panel comprising a plurality of sub-pixels, the i-th row of sub-pixels comprising a plurality of sub-pixels arranged along a first direction, and a plurality of rows of sub-pixels arranged along a second direction, the second direction intersecting the first direction, wherein i is any positive integer; the method comprising: In a frame picture of the display panel, in a period when the (i+1)-th row of sub-pixels does not emit light, the i-th row of sub-pixels is driven to emit light, and the (i+2)-th row of sub-pixels is driven to emit light.

[0006] In a third aspect, based on the same inventive concept, the embodiments of the present application provide a display device comprising the display panel provided in the first aspect.

[0007] In the embodiment of the present application, in the reset stage and / or data writing stage of the (i+1)th row of sub-pixels, the i th row of sub-pixels is set to be in the light-emitting stage t3, and the (i+2)th row of sub-pixels is set to be in the light-emitting stage t3. Therefore, when the (i+1)th row of sub-pixels is in the dark state for at least part of the period, the two rows of sub-pixels adjacent to the (i+1)th row of sub-pixels and located on the opposite sides of the (i+1)th row of sub-pixels can be in the light-emitting state. Thus, the multiple rows of sub-pixels in the same region are prevented from being darkened at the same time, the dark state of the (i+1)th row of sub-pixels is reduced in obviousness, the difference between the light and the dark recognized by the human eye is weakened, the harm of the picture to the human eye is reduced, and the eye protection function of the display panel is realized. BRIEF DESCRIPTION OF DRAWINGS

[0008] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings required in the embodiments will be briefly introduced below. Obviously, the drawings in the following description are only some embodiments of the present application, and other drawings can be obtained by those skilled in the art without creative labor.

[0009] Figure 1 A schematic diagram of a display panel provided in the embodiment of the present application; Figure 2 A schematic diagram of a pixel circuit provided in the embodiment of the present application; Figure 1 A schematic diagram of a pixel circuit provided in the embodiment of the present application; Figure 3 A timing diagram of the pixel circuit shown in FIG. 2; Figure 2 A driving timing diagram of a display panel provided in the embodiment of the present application; Figure 4 A driving timing diagram of a display panel provided in the related art; Figure 5 A light and dark schematic diagram of a display picture in the related art; Figure 6 A light and dark schematic diagram of a display picture provided in the embodiment of the present application; Figure 7 A driving timing diagram of a display panel provided in the embodiment of the present application; Figure 8 A driving sequence schematic diagram of a display panel provided in the embodiment of the present application; Figure 9 A driving sequence schematic diagram of a display panel provided in the embodiment of the present application; Figure 10 A timing diagram of a driving group provided in the embodiment of the present application; Figure 11 Figure 10 A driving timing diagram of a display panel provided in the embodiment of the present application; Figure 12 A driving timing diagram of a display panel provided in the embodiment of the present application; Figure 13 ​A schematic diagram of a display panel provided by an embodiment of the present application is shown in FIG. 1. Figure 14 For Figure 13 A cascade sequence diagram of the shift register unit is shown in FIG. 3. Figure 15 A schematic diagram of a display device provided by an embodiment of the present application is shown in FIG. 4. DETAILED DESCRIPTION

[0010] In order to better understand the technical solutions of the present application, the embodiments of the present application are described in detail below with reference to the accompanying drawings.

[0011] It should be clear that the described embodiments are only some of the embodiments of the present application, but not all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art without creative labor fall within the scope of protection of the present application.

[0012] The terms used in the embodiments of the present application are only for the purpose of describing the specific embodiments, and are not intended to limit the present application. The singular forms "a", "an" and "the" used in the embodiments of the present application and the appended claims are also intended to include the plural forms, unless the context clearly indicates otherwise.

[0013] It should be understood that the term "and / or" used herein is only to describe the association relationship of the associated objects, which means that there can be three relationships, for example, A and / or B, which can represent the three cases of A alone, A and B together, and B alone. In addition, the character " / " in this paper generally indicates that the associated objects before and after are in an "or" relationship.

[0014] Various modifications and changes can be made to the present application without departing from the spirit or scope of the present application, which will be apparent to those skilled in the art. Therefore, the present application is intended to cover the modifications and changes of the present application falling within the scope of the corresponding claims (claimed technical solutions) and their equivalents. It should be noted that the embodiments provided by the embodiments of the present application can be combined with each other without contradiction.

[0015] Figure 1 A schematic diagram of a display panel provided by an embodiment of the present application is shown in FIG. 1, Figure 2 For Figure 1 A schematic diagram of a pixel circuit is shown in FIG. 2, Figure 3 For Figure 2 A timing diagram of the pixel circuit shown in FIG. 2 is shown in FIG. 3.

[0016] The present application provides a display panel 01, as shown in FIG. 1. Figure 1As shown, the display panel 01 includes a plurality of sub-pixels 10, each of which includes a pixel circuit 11 and a light emitting device 12 electrically connected, and the pixel circuit 11 is configured to drive the light emitting device 12 to emit light. The light emitting device 12 can be an organic light emitting diode (OLED), a sub-millimeter light emitting diode (Mini-LED), or a micro light emitting diode (Micro-LED, which is not limited in the present application.

[0017] The i-th row of sub-pixels 10_i includes a plurality of sub-pixels 10 arranged along a first direction X, and a plurality of rows of sub-pixels 10 are arranged along a second direction Y, the second direction Y intersects the first direction X, wherein i is any positive integer.

[0018] That is, a plurality of sub-pixels 10 arranged along the first direction X can constitute a row of sub-pixels, which can also be referred to as a sub-pixel row, and a plurality of sub-pixel rows are arranged along the second direction Y.

[0019] For example, the first direction X is the row direction of the display panel 01, and the second direction Y is the column direction of the display panel 01.

[0020] In combination with Figure 2 and Figure 3 As shown, one working period T of the pixel circuit 11 includes a reset phase t1, a data writing phase t2, and a light emitting phase t3. The data writing phase t2 is performed after the reset phase t1, and the light emitting phase t3 is performed after the data writing phase t2. In the reset phase t1 and the data writing phase t2, the light emitting device 12 does not emit light, i.e., the sub-pixel 10 does not emit light. In the light emitting phase t3, the light emitting device 12 emits light, i.e., the sub-pixel 10 emits light.

[0021] In the same row of sub-pixels 10, the working states of the pixel circuits 11 can be the same. That is, the pixel circuits 11 in the same row of sub-pixels 10 can all be in the reset phase t1, or all be in the data writing phase t2, or all be in the light emitting phase t3.

[0022] In combination with Figure 3 and Figure 4 As shown, Figure 4 A driving timing diagram of a display panel provided by an embodiment of the present application is shown. In the reset phase t1 and / or the data writing phase t2 of the i+1-th row of sub-pixels 10_i+1, the i-th row of sub-pixels 10_i is in the light emitting phase t3, and the i+2-th row of sub-pixels 10_i+2 is in the light emitting phase t3.

[0023] That is, in one frame of the display panel 01, in the period when the i+1th row of sub-pixels 10_i+1 at least partially do not emit light, the i th row of sub-pixels 10_i (the row of sub-pixels above the i+1th row of sub-pixels 10_i+1) and the i+2th row of sub-pixels 10_i+2 (the row of sub-pixels below the i+1th row of sub-pixels 10_i+1) all emit light.

[0024] The present inventors have found through research that, as shown in Figure 5 Figure 5 A driving timing diagram of a display panel provided by the related art is shown in the related art. In the related art, the display panel 01 drives each row of sub-pixels 10 in order along the second direction Y during the display of one frame of image, for example, as shown in Figure 1 Figure 2 Figure 3 and Figure 5 , the 1st row of sub-pixels, the 2nd row of sub-pixels, …, the i th row of sub-pixels 10_i, the i+1th row of sub-pixels 10_i+1, and the i+2th row of sub-pixels 10_i+2 enter the reset stage t1, the data writing stage t2, and the light emitting stage t3 in stages. When one row of sub-pixels starts to perform the data writing stage t2, the next row of sub-pixels is still performing the reset stage t1.

[0025] Based on this driving mode, as shown in Figure 3 and Figure 5 , it can be seen that at any moment when the i+1th row of sub-pixels 10_i+1 is in the reset stage t1 and the data writing stage t2, at least one of the i th row of sub-pixels 10_i and the i+2th row of sub-pixels 10_i+2 is not in the light emitting stage t3. For example, as shown in Figure 5 at the starting moment when the i+1th row of sub-pixels 10_i+1 is in the data writing stage t2, the i th row of sub-pixels 10_i is in the data writing stage t2, and the i+2th row of sub-pixels 10_i+2 is in the reset stage t1.

[0026] This results in that in one frame of image, several adjacent rows of sub-pixels in the same region will be darkened at the same time, as shown in Figure 6 Figure 6 A bright and dark display image in the related art is shown. When a fast camera (shutter speed <1 / 8000s) is used to take a picture of the image, it can be seen that there is a clear black bar in the display image, which represents the dark state of the row of sub-pixels. Thus, the bright and dark fluctuations within one frame are obvious, which is not conducive to eye protection. ​​​​In the embodiment, during the reset stage t1 and / or the data writing stage t2 of the (i+1)th row of sub-pixels 10_i+1, the i th row of sub-pixels 10_i is in the light-emitting stage t3, and the (i+2)th row of sub-pixels 10_i+2 is in the light-emitting stage t3. During at least part of the dark state of the (i+1)th row of sub-pixels 10_i+1, the two rows of sub-pixels adjacent to the (i+1)th row of sub-pixels 10_i+1 on the opposite sides thereof can be in the light-emitting state, so as to facilitate the same area of multiple rows of sub-pixels not to be darkened at the same time, reduce the obviousness of the dark state of the (i+1)th row of sub-pixels 10_i+1, weaken the light-dark difference recognized by the human eye, thereby reducing the harm of the picture to the human eye, and realizing the eye protection function of the display panel.

[0027] For example, as shown in Figure 7 , Figure 7 , a display picture bright-dark schematic diagram provided by the embodiment can be seen when a fast camera (shutter speed <1 / 8000s) is used to take a picture Figure 7 , the color of the black bar is obviously lighter than Figure 6 , the color of the black bar. The embodiment can effectively improve the flicker in the frame picture and improve the protection function for the human eye.

[0028] It should be noted that in some other embodiments, one working cycle of the pixel circuit 11 can further include other stages, such as a bias adjustment stage, and the like, as long as the pixel circuit 11 is not in the light-emitting stage t3, the sub-pixel 10 is in the dark state. In the embodiment, at any moment when the (i+1)th row of sub-pixels 10_i+1 is in the dark state, the two rows of sub-pixels 10 adjacent to the (i+1)th row of sub-pixels 10_i+1 on the opposite sides thereof are in the light-emitting stage t3, so as to reduce the flicker degree in a frame picture to a greater extent, and further improve the eye protection ability of the display panel.

[0029] Figure 8 Another driving timing diagram of the display panel provided by the embodiment is provided.

[0030] In one embodiment of the present application, in combination with Figure 1 , Figure 2 , Figure 3 and Figure 8 , during the reset stage t1 and / or the data writing stage t2 of the (i+1)th row of sub-pixels 10_i+1, at least two rows of sub-pixels adjacent to the (i+1)th row of sub-pixels 10_i+1 on one side thereof are in the light-emitting stage t3, and at least two rows of sub-pixels adjacent to the (i+1)th row of sub-pixels 10_i+1 on the other side thereof are in the light-emitting stage t3.

[0031] That is, at least the i-th row of sub-pixels 10_i and the i-1-th row of sub-pixels 10_i-1 are in the light-emitting phase t3 at the reset phase t1 and / or the data writing phase t2 of the i+1-th row of sub-pixels 10_i+1, and at least the i+2-th row of sub-pixels 10_i+2 and the i+3-th row of sub-pixels 10_i+3 are in the light-emitting phase t3. In this embodiment, i≥2.

[0032] In the reset phase t1 and / or the data writing phase t2 of the i+1-th row of sub-pixels 10_i+1, at least two rows of sub-pixels located on one side of the i+1-th row of sub-pixels 10_i+1 and adjacent to the i+1-th row of sub-pixels 10_i+1 are in the light-emitting phase t3, and at least two rows of sub-pixels located on the other side of the i+1-th row of sub-pixels 10_i+1 and adjacent to the i+1-th row of sub-pixels 10_i+1 are in the light-emitting phase t3, so that at least the upper two rows of sub-pixels and the lower two rows of sub-pixels of the i+1-th row of sub-pixels 10_i+1 are in the light-emitting state during at least part of the dark state of the i+1-th row of sub-pixels 10_i+1, which is conducive to further reducing the dark state obviousness of the i+1-th row of sub-pixels 10_i+1, thereby further weakening the bright-dark difference recognized by the human eye and improving the eye protection function of the display panel 01.

[0033] In order to facilitate understanding of the technical solutions of the present application, the structure and working process of the pixel circuit shown in Figure 2 and Figure 3 will be briefly described below. Figure 2

[0034] As shown in Figure 2 , the pixel circuit 11 includes a drive transistor Md, a power voltage writing module 111, and a light-emitting control module 112. The input end of the power voltage writing module 111 is electrically connected with the first power signal line DL1, the output end is electrically connected with the first electrode of the drive transistor Md, and the control end is electrically connected with the light-emitting control signal line EM. The power voltage writing module 111 is used to transmit the first power voltage PVDD transmitted by the first power signal line DL1 to the first electrode of the drive transistor Md.

[0035] The input end of the light-emitting control module 112 is electrically connected with the second electrode of the drive transistor Md, the output end is electrically connected with the first electrode of the light-emitting device 12, and the control end is electrically connected with the light-emitting control signal line EM. The signal transmitted by the light-emitting control signal line EM controls the switching state of the power voltage writing module 111 and the light-emitting control module 112. The second electrode of the light-emitting device 12 can receive the second power voltage PVEE.

[0036] Among them, the first electrode of the light-emitting device 12 can be its anode, and the second electrode of the light-emitting device 12 can be its cathode.

[0037] ​In the light emitting stage t3, the light emitting control signal line EM transmits an enable signal, and the power voltage writing module 111 and the light emitting control module 112 are both in an open state.

[0038] In the reset stage t1 and the data writing stage t2, the light emitting control signal line EM transmits a non-enable signal, and the power voltage writing module 111 and the light emitting control module 112 are both in a closed state.

[0039] As shown in the example, Figure 2 The power voltage writing module 111 includes a first transistor M1, the first electrode of the first transistor M1 is electrically connected with the first power voltage signal line DL1, the second electrode is electrically connected with the first electrode of the driving transistor Md, and the gate electrode is electrically connected with the light emitting control signal line EM.

[0040] The light emitting control module 112 includes a second transistor M2, the first electrode of the second transistor M2 is electrically connected with the second electrode of the driving transistor Md, the second electrode is electrically connected with the first electrode of the light emitting device 12, and the gate electrode is electrically connected with the light emitting control signal line EM.

[0041] As shown in the example, Figure 3 In the light emitting stage t3, the light emitting control signal line EM transmits an enable signal (such as a low level signal), the first transistor M1 and the second transistor M2 are open, the pixel circuit 11 transmits a driving current to the light emitting device 12, and the light emitting device 12 is driven to emit light. That is, the sub-pixel 10 emits light.

[0042] In the reset stage t1 and the data writing stage t2, the light emitting control signal line EM transmits a non-enable signal (such as a high level signal), the first transistor M1 and the second transistor M2 are closed, the pixel circuit 11 stops providing a driving current to the light emitting device 12, and the light emitting device 12 does not emit light. That is, the sub-pixel 10 does not emit light, and the sub-pixel 10 is in a dark state.

[0043] It should be noted that the same sub-pixel row can be connected with the same light emitting control signal line EM, and Figure 4 , Figure 8 In the timing diagram shown in the example, in the period when the light emitting control signal line EM connected with the sub-pixel row transmits a non-enable signal (such as a high level signal), the sub-pixels in the row do not emit light and are in a dark state.

[0044] Further, as shown in the example, Figure 2As shown, the pixel circuit 11 further comprises a first reset module 113, a data writing module 114, a threshold value grabbing module 115 and a second reset module 116. The input end of the first reset module 113 is electrically connected with the first reset voltage signal line SL1, the output end is electrically connected with the gate of the driving transistor Md, and the control end is electrically connected with the first scan line S1. The first reset module 113 is used for transmitting the first reset voltage Vref1 on the first reset voltage signal line SL1 to the gate of the driving transistor Md, so as to reset the gate of the driving transistor Md.

[0045] The input end of the data writing module 114 is electrically connected with the data signal line DL2, the output end is electrically connected with the first electrode of the driving transistor Md, and the control end is electrically connected with the second scan line S2. The data writing module 114 is used for transmitting the data voltage Vdata on the data signal line DL2 to the first electrode of the driving transistor Md.

[0046] The input end of the threshold value grabbing module 115 is electrically connected with the second electrode of the driving transistor Md, the output end is electrically connected with the gate of the driving transistor Md, and the control end is electrically connected with the second scan line S2. The threshold value grabbing module 115 is used for compensating the threshold voltage of the driving transistor Md to the gate of the driving transistor Md.

[0047] The input end of the second reset module 116 is electrically connected with the second reset voltage signal line SL2, the output end is electrically connected with the first electrode of the light emitting device 12, and the control end is electrically connected with the second scan line S2. The second reset module 116 is used for transmitting the second reset voltage Vref2 on the second reset voltage signal line SL2 to the first electrode of the light emitting device 12, so as to reset the first electrode of the light emitting device 12.

[0048] In one working cycle of the pixel circuit 11, the data writing stage t2 is performed after the reset stage t1, and the light emitting stage t3 is performed after the data writing stage t2.

[0049] The first reset module 113 is started in the reset stage t1, and the second reset module 116, the data writing module 114 and the threshold value grabbing module 115 are started in the data writing stage t2.

[0050] As shown in the figure, Figure 2 The first reset module 113 comprises a third transistor M3. The first electrode of the third transistor M3 is electrically connected with the first reset voltage signal line SL1, the second electrode is electrically connected with the gate of the driving transistor Md, and the gate is electrically connected with the first scan line S1. The data writing module 114 comprises a fourth transistor M4. The first electrode of the fourth transistor M4 is electrically connected with the data signal line DL2, the second electrode is electrically connected with the first electrode of the driving transistor Md, and the gate is electrically connected with the second scan line S2.

[0051] The threshold value grabbing module 115 includes a fifth transistor M5, a first electrode of the fifth transistor M5 is electrically connected with the second electrode of the driving transistor Md, a second electrode is electrically connected with the gate of the driving transistor Md, and a gate is electrically connected with the second scan line S2. The second reset module 116 includes a sixth transistor M6, a first electrode of the sixth transistor M6 is electrically connected with the second reset voltage signal line SL2, a second electrode is electrically connected with the first electrode of the light emitting device 12, and a gate is electrically connected with the second scan line S2.

[0052] Wherein, the same first scan line S1 and the same second scan line S2 are connected with the same sub-pixel row. The sub-pixels in the same row can enter the reset stage t1 and the data writing stage t2 at the same time.

[0053] In combination Figure 3 As shown in the reset stage t1, the first scan line S1 transmits an enable signal (such as a low level signal), the third transistor M3 is turned on, the first reset voltage VREF1 is transmitted to the gate of the driving transistor Md through the turned-on third transistor M3, and the reset of the gate of the driving transistor Md is completed.

[0054] In the data writing stage t2, the first scan line S1 transmits a non-enable signal (such as a high level signal), the second scan line S2 transmits an enable signal (such as a low level signal), the third transistor M3 is turned off, the fourth transistor M4, the fifth transistor M5 and the sixth transistor M6 are turned on, the data voltage Vdata is transmitted to the first electrode of the driving transistor Md through the turned-on fourth transistor M4, at this time, since the gate potential of the driving transistor Md is Vref1, the driving transistor Md is turned on, the data voltage Vdata is transmitted to the gate of the driving transistor Md through the turned-on driving transistor Md and the fifth transistor M5, until the gate potential of the driving transistor Md is Vdata-|Vth|, the driving transistor Md is turned off, wherein Vth is the threshold voltage of the driving transistor Md.

[0055] At the same time, the second reset voltage VREF2 is transmitted to the first electrode of the light emitting device 12 through the turned-on sixth transistor M6, and the reset of the first electrode of the light emitting device 12 is completed.

[0056] Figure 9 A driving sequence diagram of a display panel is provided in the embodiment of the present application.

[0057] In an embodiment of the present application, as Figure 9 shown, a plurality of sub-pixel rows in the display panel 01 form at least one driving group 100, the same driving group 100 includes a first group of sub-pixel rows 100A and a second group of sub-pixel rows 100B, and in one frame of the display panel 01, the first group of sub-pixel rows 100A and the second group of sub-pixel rows 100B are driven in turn.

[0058] The multiple rows of sub-pixels 10 in the first group of sub-pixel rows 100A are arranged alternately with the multiple rows of sub-pixels 10 in the second group of sub-pixel rows 100B in the second direction Y.

[0059] That is, in one frame of the display panel 01, the rows of sub-pixels 10 in the first group of sub-pixel rows 100A in one driving group 100 can be sequentially driven into the working process, and then the rows of sub-pixels 10 in the second group of sub-pixel rows 100B in the driving group 100 are sequentially driven into the working process. In the second direction Y, the rows of sub-pixels belonging to the first group of sub-pixel rows 100A are arranged alternately with the rows of sub-pixels belonging to the second group of sub-pixel rows 100B in the driving group 100.

[0060] In the embodiment of the present application, the first group of sub-pixel rows 100A and the second group of sub-pixel rows 100B in the same driving group 100 are sequentially driven, and the rows of sub-pixels in the first group of sub-pixel rows 100A are arranged alternately with the rows of sub-pixels in the second group of sub-pixel rows 100B, so that the multiple rows of sub-pixels in the same driving group 100 can be staggered driven, which is beneficial to driving the i+1th row of sub-pixels 10_i+1 into the reset stage t1 or the data writing stage t2 after the i th row of sub-pixels 10_i and the i+2th row of sub-pixels 10_i+2 sequentially enter the light-emitting stage t3, so as to facilitate the two rows of sub-pixels adjacent to the i+1th row of sub-pixels 10_i+1 and located on the opposite sides thereof to be in the light-emitting state when the i+1th row of sub-pixels 10_i+1 is in the dark state, and further facilitate reducing the dark state obviousness of the i+1th row of sub-pixels 10_i+1.

[0061] For example, as shown in FIG. 2, in the same driving group 100, the number of rows of sub-pixels included in the first group of sub-pixel rows 100A is the same as the number of rows of sub-pixels included in the second group of sub-pixel rows 100B. Figure 9

[0062] For example, as shown in FIG. 2, in the same driving group 100, the number of rows of sub-pixels included in the first group of sub-pixel rows 100A is the same as the number of rows of sub-pixels included in the second group of sub-pixel rows 100B.

[0063] For example, as shown in FIG. 2, in the same driving group 100, the number of rows of sub-pixels included in the first group of sub-pixel rows 100A is the same as the number of rows of sub-pixels included in the second group of sub-pixel rows 100B. Figure 9 For example, as shown in FIG. 2, in the display panel 01, 14 rows of sub-pixels arranged in sequence along the second direction Y form a driving group 100, of which 7 odd rows of sub-pixels 10 belong to the first group of sub-pixel rows 100A, and 7 even rows of sub-pixels 10 belong to the second group of sub-pixel rows 100B. In the process of displaying one frame of image, after the odd rows of sub-pixels 10 in the driving group 100 sequentially enter the working process, the even rows of sub-pixels 10 sequentially enter the working process.

[0064] ​The odd rows of sub-pixels in the driving group 100 form a first group of sub-pixel rows 100A, and the even rows of sub-pixels in the driving group 100 form a second group of sub-pixel rows 100B, which is beneficial to reduce the grouping complexity of each sub-pixel row in the driving group 100, improve the distribution regularity of the first group of sub-pixel rows 100A and the second group of sub-pixel rows 100B, and thus is beneficial to reduce the complexity of interlaced driving the sub-pixel rows in the driving group 100.

[0065] Please continue to refer to Figure 9 In an embodiment of the present application, the display panel 01 includes a plurality of driving groups 100, and the plurality of driving groups 100 are sequentially driven.

[0066] For example, as shown in Figure 9 The plurality of driving groups 100 include a first driving group 101, a second driving group 102, and the like, and in the process of displaying a frame of picture by the display panel 01, the first driving group 101, the second driving group 102, and the like are sequentially driven.

[0067] Since the number of sub-pixel rows in the display panel 01 is large, the display panel 01 includes a plurality of driving groups 100 in the embodiment of the present application, which is beneficial to make the number of sub-pixel rows in each driving group 100 not too large, is beneficial to reduce the driving difficulty of the display panel 01, and is convenient to realize that the plurality of sub-pixel rows arranged adjacent to each other will not be darkened at the same time.

[0068] Figure 10 Another driving sequence diagram of a display panel provided in the embodiment of the present application is shown.

[0069] In an embodiment of the present application, in combination with Figure 1 and Figure 10 As shown in

[0070] For example Figure 10 The 16 rows of sub-pixels arranged along the second direction Y form a driving group 100, and the same driving group 100 includes a first group of sub-pixel rows 100A, a second group of sub-pixel rows 100B, a third group of sub-pixel rows 100C, and a fourth group of sub-pixel rows 100D. In the same driving group 100, the first group of sub-pixel rows 100A includes the 1st row of sub-pixels, the 5th row of sub-pixels, the 9th row of sub-pixels, and the 13th row of sub-pixels, the second group of sub-pixel rows 100B includes the 3rd row of sub-pixels, the 7th row of sub-pixels, the 11th row of sub-pixels, and the 15th row of sub-pixels, the third group of sub-pixel rows 100C includes the 2nd row of sub-pixels, the 6th row of sub-pixels, the 10th row of sub-pixels, and the 14th row of sub-pixels, and the fourth group of sub-pixel rows 100D includes the 4th row of sub-pixels, the 8th row of sub-pixels, the 12th row of sub-pixels, and the 16th row of sub-pixels.

[0071] In combination withFigure 1 and Figure 10 It can be seen that, within any two adjacent rows of subpixels in the first group of subpixel rows 100A, there are three rows of subpixels that do not belong to the first group of subpixel rows 100A. For example, between the first and fifth rows of subpixels in the first group of subpixel rows 100A, there are subpixels in the second, third, and fourth rows that do not belong to the first group of subpixel rows 100A. Similarly, within any two adjacent rows of subpixels in the second group of subpixel rows 100B, there are three rows of subpixels that do not belong to the second group of subpixel rows 100B. Within any two adjacent rows of subpixels in the third group of subpixel rows 100C, there are three rows of subpixels that do not belong to the third group of subpixel rows 103. Within any two adjacent rows of subpixels in the fourth group of subpixel rows 100D, there are three rows of subpixels that do not belong to the fourth group of subpixel rows 100D.

[0072] In this embodiment, if at least two rows of subpixels between two adjacent rows of subpixels in the same group of subpixels do not belong to that group of subpixels, then after driving two adjacent rows of subpixels in the same group of subpixels to enter the light-emitting stage t3 in sequence, the subpixel row between the two adjacent rows of subpixels can be driven to enter the reset stage t1. This is beneficial to ensure that when one subpixel row in the group of subpixels is in a dark state, at least two rows of subpixels on one side and adjacent to it are in a light-emitting state, and at least two rows of subpixels on the other side and adjacent to it are in a light-emitting state, thereby further weakening the visual effect of the dark subpixel row.

[0073] For example, in combination Figure 10 and Figure 11 As shown, Figure 11 for Figure 10 A timing diagram for a driving group shows that in the same driving group 100, the first group of sub-pixel rows 100A, the second group of sub-pixel rows 100B, the third group of sub-pixel rows 100C, and the fourth group of sub-pixel rows 100D are driven sequentially. It can be seen that when one row of sub-pixels in the first group of sub-pixel rows 100A is in a dark state (EM high level), the three rows of sub-pixels above and below that row (excluding the first row of sub-pixels) are all in an illuminated state.

[0074] For example, when the 5th row of subpixels in the first group of subpixel rows 100A is in a dark state, the 2nd, 3rd and 4th row subpixels on one side of it are in a light-emitting state (EM low level), and the 6th, 7th and 8th row subpixels on the other side are also in a light-emitting state.

[0075] In one embodiment of this application, combined with Figure 4 and Figure 9As shown, in the same driving group 100, the first group of sub-pixel rows 100A and the second group of sub-pixel rows 100B each include n rows of sub-pixels.

[0076] In one frame of the display panel 01, in the same group of sub-pixel rows, the time periods in which the emission control signal lines EM in m rows of sub-pixels transmit non-enabling signals (such as high-level signals) overlap.

[0077] Wherein, n>m, n and m are positive integers.

[0078] For example, in combination with Figure 4 and Figure 9 As shown, Figure 4 i in the above formula can be 12, in combination with Figure 4 and Figure 9 It can be reasonably inferred that the first group of sub-pixel rows 100A includes 7 rows of sub-pixels, in which the time periods in which the emission control signal lines EM in the 1st, 3rd, 5th, 7th, 9th and 11th rows of sub-pixels transmit non-enabling signals (such as high-level signals) overlap. That is, n=7 and m=6.

[0079] For example, in combination with Figure 10 and Figure 11 As shown, it can be seen that the first group of sub-pixel rows 100A includes 4 rows of sub-pixels, in which the time periods in which the emission control signal lines EM in the 1st, 5th and 9th rows of sub-pixels transmit non-enabling signals (such as high-level signals) overlap. That is, n=4 and m=3.

[0080] In the embodiments of the present application, n>m, then after driving each row of sub-pixels in the first group of sub-pixel rows 100A into the working process in turn, when driving the second group of sub-pixel rows 100B, the first row of sub-pixels in the second group of sub-pixel rows 100B can start entering the reset phase t1 after the adjacent “upper” row of sub-pixels (such as belonging to the first group of sub-pixel rows 100A) and “lower” row of sub-pixels (such as belonging to the first group of sub-pixel rows 100A) in the first row of sub-pixels enter the emission phase t3 in turn, thereby facilitating the “upper” row of sub-pixels (such as belonging to the first group of sub-pixel rows 100A) and “lower” row of sub-pixels (such as belonging to the first group of sub-pixel rows 100A) of the sub-pixel row in the second group of sub-pixel rows 100B to be in the dark state, so as to realize the reduction of the visual effect of the dark state sub-pixel row in the second group of sub-pixel rows 100B.

[0081] Further, when the sub-pixel row in the first group of sub-pixel rows 100A is in the dark state, the "upper" sub-pixel row (for example, belonging to the second group of sub-pixel rows 100B) and the "lower" sub-pixel row (for example, belonging to the second group of sub-pixel rows 100B) of the sub-pixel row are in the light-emitting state of the previous frame of picture, thereby realizing the visual effect of reducing the visual effect of the dark state sub-pixel row in the first group of sub-pixel rows 100A.

[0082] Optionally, n-m≥2.

[0083] The inventors of the present application have found through research that when the first group of sub-pixel rows 100A and the second group of sub-pixel rows 100B are sequentially driven, the difference between n and m will affect the interval between the reset phase t1 of the sub-pixel row in the second group of sub-pixel rows 100B and the start time of the light-emitting phase t3 of the sub-pixel row adjacent thereto (for example, belonging to the first group of sub-pixel rows 100A). The larger the difference between n and m, the larger the interval.

[0084] For example Figure 12 As shown, Figure 12 Another driving timing diagram of a display panel provided by an embodiment of the present application is shown, taking n=7 and m=5 as an example. The driving sequence of the display panel can be as shown Figure 9 In the first driving group 101, the first group of sub-pixel rows 100A includes odd-numbered rows of sub-pixels, and the second group of sub-pixel rows 100B includes even-numbered rows of sub-pixels. The second row of sub-pixels is the first row of sub-pixels in the second group of sub-pixel rows 100B, Figure 12 The interval Z1 between the reset phase t1 of the second row of sub-pixels and the start time of the light-emitting phase t3 of the third row of sub-pixels is relatively Figure 3 The interval between the reset phase t1 of the second row of sub-pixels and the start time of the light-emitting phase t3 of the third row of sub-pixels is significantly larger. Figure 3 The start time of the reset phase t1 of the second row of sub-pixels overlaps with the start time of the light-emitting phase t3 of the third row of sub-pixels. The embodiment of the present application makes n-m≥2, which can increase the interval between the dark state period of a sub-pixel row and the dark state period of the sub-pixel row adjacent thereto, which is beneficial to improving the reliability of the adjacent rows of the dark state sub-pixel row being in the light-emitting state, thereby being beneficial to improving the visual effect of weakening the distinctiveness of the dark state sub-pixel row.

[0085] Please continue to refer to Figure 1 In an embodiment of the present application, the display panel 01 includes a plurality of data signal lines DL, and the data signal lines DL extend along the second direction Y. The plurality of data signal lines DL are arranged along the first direction X.

[0086] In the same driving group 100, the data signal lines DL sequentially transmit data voltages to the first group of sub-pixel rows 100A and the second group of sub-pixel rows 100B.

[0087] For example, in the same driving group 100, the first group of subpixel rows 100A includes odd-numbered rows of subpixels, and the second group of subpixel rows 100B includes even-numbered rows of subpixels. The first group of subpixel rows 100A is driven before the second group of subpixel rows 100B. The same data signal line DL transmits data voltage to the odd-numbered rows of subpixels first, and then transmits data voltage to the even-numbered rows of subpixels.

[0088] In this embodiment, the data voltage transmitted by the data signal line DL can be matched with the driving mode of the sub-pixel row to ensure that each sub-pixel receives the correct data voltage, thereby ensuring the display effect of the display panel 01.

[0089] Figure 13 This is a schematic diagram of yet another display panel provided in an embodiment of this application. Figure 14 for Figure 13 A cascaded sequence diagram of a mid-shift register unit.

[0090] In one embodiment of this application, combined with Figure 13 and Figure 14 As shown, the display panel 01 includes a scanning circuit 20, which includes multiple cascaded shift register units 21. The multiple cascaded shift register units 21 form at least one scanning group 200, and the scanning group 200 is electrically connected to the driving group 100.

[0091] For example, such as Figure 13 As shown, the display panel 01 includes a display area AA and a non-display area NA surrounding the display area AA. Sub-pixels 10 are located in the display area AA, and the scanning circuit 20 is located in the non-display area NA on one side of the display area AA. The scanning circuit 20 is electrically connected to the sub-pixel row through the gate line SC, and the same sub-pixel row is electrically connected to the same gate line SC.

[0092] In this embodiment, the gate line SC can refer to any one of the first scan line S1, the second scan line S2, and the light emission control signal line EM.

[0093] The same scanning group 200 includes a first group of shift register units 200A and a second group of shift register units 200B. The first group of shift register units 200A is electrically connected to the first group of sub-pixel rows 100A, and the second group of shift register units 200B is electrically connected to the second group of sub-pixel rows 100B. The first group of shift register units 200A and the second group of shift register units 200B output scanning signals sequentially.

[0094] In the embodiment of the present application, the scan group 200 can transmit a scan signal to the corresponding driving group 100, so as to drive the sub-pixel row into the working process. In the same scan group 200, the first group of shift register units 200A are electrically connected to the first group of sub-pixel rows 100A, and the second group of shift register units 200B are electrically connected to the second group of sub-pixel rows 100B. Then, the first group of shift register units 200A can drive the first group of sub-pixel rows 100A, and the second group of shift register units 200B can drive the second group of sub-pixel rows 100B. The first group of shift register units 200A and the second group of shift register units 200B can output the scan signal in turn, so as to realize the driving of the first group of sub-pixel rows 100A and the second group of sub-pixel rows 100B in the same driving group 100 in turn.

[0095] As shown in Figure 14 , the scan circuit 20 includes a plurality of scan groups 200, and the number of the scan groups 200 can be the same as the number of the driving groups 100. The plurality of scan groups 200 can output the scan signal in turn.

[0096] In this way, the plurality of scan groups 200 can drive the corresponding driving group 100 in turn, so as to realize the driving of the plurality of driving groups 100 in the display panel 01 in turn.

[0097] Further, in the corresponding scan group 200 and driving group 100, the number of the group of shift register units in the scan group 200 can be the same as the number of the group of sub-pixel rows. The plurality of groups of shift register units can output the scan signal in turn, so as to realize the driving of the group of sub-pixel rows in the corresponding driving group 100 in turn.

[0098] For example Figure 14 , the first scan group 201 is electrically connected to the first driving group 101, the first driving group 101 includes two groups of sub-pixel rows, and the first scan group 201 includes two groups of shift register units.

[0099] In an embodiment of the present application, as shown in Figure 13 , the plurality of shift register units 21 are arranged in the second direction Y in stages, and the number of the stages of the shift register units 21 is the same as the number of the rows of the sub-pixel rows electrically connected thereto. For example, the shift register unit 21 electrically connected to the i-th row of sub-pixels 10_i is the i-th stage shift register unit 21_i.

[0100] In combination with Figure 14 , in the same scan group 200, the plurality of shift register units 21 in the first group of shift register units 200A are arranged alternately with the plurality of shift register units 21 in the second group of shift register units 200B in the second direction Y.

[0101] In the embodiment of the present application, the shift register units 21 in different groups of shift register units are arranged alternately, which is beneficial to make the shift register units 21 have the same number of stages as the sub-pixel rows to which the shift register units 21 are electrically connected, thereby reducing the difficulty of connection between the shift register units 21 and the corresponding sub-pixel rows.

[0102] As shown in Figure 14 The first scanning group 201 is electrically connected with the first driving group 101, and in the first driving group 101, the first group of sub-pixel rows 100A includes odd-numbered rows of sub-pixels, and the second group of sub-pixel rows 100B includes even-numbered rows of sub-pixels.

[0103] In the first scanning group 201, the shift register units 21 in the first group of shift register units 200A are odd-numbered stage shift register units, and the shift register units 21 in the second group of shift register units 200B are even-numbered stage shift register units.

[0104] In this way, the odd-numbered stage shift register units can be electrically connected with the odd-numbered rows of sub-pixels, and the even-numbered stage shift register units can be electrically connected with the even-numbered rows of sub-pixels, which is beneficial to reduce the difficulty of wiring between the shift register units 21 and the sub-pixel rows to which the shift register units 21 are electrically connected, and facilitates the implementation of the first group of shift register units 200A driving the first group of sub-pixel rows 100A composed of odd-numbered rows of sub-pixels, and the second group of shift register units 200B driving the second group of sub-pixel rows 100B composed of even-numbered rows of sub-pixels. Please continue to refer to Figure 14 In an embodiment of the present application, the first group of shift register units 200A and the second group of shift register units 200B each include a plurality of shift register units 21, and in the same group of shift register units, the plurality of shift register units 21 are sequentially cascaded.

[0105] That is, in the first group of shift register units 200A, the shift register units 21 are sequentially cascaded, and in the second group of shift register units 200B, the shift register units 21 are sequentially cascaded.

[0106] The embodiment of the present application is beneficial to make the cascade order of the shift register units 21 the same as the driving order of the corresponding sub-pixel rows, and to realize the sequential driving of the groups of sub-pixel rows.

[0107] Further, in the same scanning group 200, the last shift register unit in the first group of shift register units 200A is cascaded with the first shift register unit in the second group of shift register units 200B.

[0108] For example Figure 14As shown, the scan circuit 20 includes a plurality of scan groups 200, and the plurality of scan groups 200 includes a first scan group 201 which can be used to drive the first driving group 101. The first scan group 201 includes 14 cascaded shift register units. The odd-numbered shift register units form a first group of shift register units 200A, and the even-numbered shift register units form a second group of shift register units 200B. The 13th shift register unit is the last shift register unit in the first group of shift register units 200A, and the 2nd shift register unit is the first shift register unit in the second group of shift register units 200B.

[0109] In the first group of shift register units 200A, the odd-numbered shift register units are sequentially cascaded, and the even-numbered shift register units are sequentially cascaded. The last shift register unit in the first group of shift register units 200A (i.e., the 13th shift register unit) is cascaded with the first shift register unit in the second group of shift register units 200B (i.e., the 2nd shift register unit).

[0110] In the same scan group 200, the last shift register unit in the first group of shift register units 200A is cascaded with the first shift register unit in the second group of shift register units 200B. Thus, the first group of shift register units 200A can be cascaded with the second group of shift register units 200B. After the shift register units 21 in the first group of shift register units 200A sequentially output the scan signals, the last shift register unit in the first group of shift register units 200A can provide a trigger signal to the second group of shift register units 200B, so that the shift register units in the second group of shift register units 200B can sequentially output the scan signals without the need of providing an additional trigger signal to the second group of shift register units 200B.

[0111] The display panel 01 provided by the embodiment of the present application can be driven by a driving method of a display panel 01. The structure of the display panel 01 can be as shown in Figure 1 、 Figure 13 As shown, the display panel 01 includes a plurality of sub-pixels 10. The ith row of sub-pixels 10_i includes a plurality of sub-pixels 10 arranged along a first direction X. A plurality of rows of sub-pixels 10 are arranged along a second direction Y. The second direction Y intersects the first direction X. i is any positive integer.

[0112] For example, the first direction X is the row direction in the display panel 01, and the second direction Y is the column direction in the display panel 01.

[0113] The driving method includes: in a frame of the display panel 01, driving the ith row of sub-pixels 10_i to emit light and driving the (i+2)th row of sub-pixels 10_i+2 to emit light in a period in which the (i+1)th row of sub-pixels 10_i+1 does not emit light.

[0114] For example, as shown in combination with Figure 1 , Figure 2 , Figure 3 and Figure 4 , in the reset stage t1 and / or the data writing stage t2 of the (i+1)th row of sub-pixels 10_i+1, the ith row of sub-pixels 10_i is in the light-emitting stage t3, and the (i+2)th row of sub-pixels 10_i+2 is in the light-emitting stage t3.

[0115] In the driving method provided by the embodiments of the present application, in at least part of the time period when the (i+1)th row of sub-pixels 10_i+1 is in the dark state, the two rows of sub-pixels adjacent to and located on the opposite sides of the (i+1)th row of sub-pixels are driven to be in the light-emitting state, which is beneficial to making the multiple rows of sub-pixels in the same area not to be darkened at the same time, thereby being beneficial to reducing the obviousness of the dark state of the (i+1)th row of sub-pixels 10_i+1, weakening the light-dark difference recognized by the human eye, and further being beneficial to reducing the harm of the picture to the human eye, and realizing the eye protection function of the display panel.

[0116] In an embodiment of the present application, the driving method further comprises: in the time period when the (i+1)th row of sub-pixels 10_i+1 does not emit light in one frame of the display panel 01, driving at least two rows of sub-pixels on one side of and adjacent to the (i+1)th row of sub-pixels 10_i+1 to emit light, and driving at least two rows of sub-pixels on the other side of and adjacent to the (i+1)th row of sub-pixels 10_i+1 to emit light.

[0117] For example, as shown in combination with Figure 1 , Figure 2 , Figure 3 and Figure 8 , in the reset stage t1 and / or the data writing stage t2 of the (i+1)th row of sub-pixels 10_i+1, the ith row of sub-pixels 10_i and the (i-1)th row of sub-pixels 10_i-1 are in the light-emitting stage t3, and the (i+2)th row of sub-pixels 10_i+2 and the (i+3)th row of sub-pixels 10_i+3 are in the light-emitting stage t3.

[0118] In the embodiments of the present application, in at least part of the time period when the (i+1)th row of sub-pixels 10_i+1 is in the dark state, at least the "upper" two rows of sub-pixels and at least the "lower" two rows of sub-pixels of the (i+1)th row of sub-pixels 10_i+1 are driven to be in the light-emitting state, which is beneficial to further reducing the obviousness of the dark state of the (i+1)th row of sub-pixels 10_i+1, thereby being beneficial to further weakening the light-dark difference recognized by the human eye, and improving the eye protection function of the display panel 01.

[0119] In combination with Figure 1 and Figure 9As shown, in an embodiment of the present application, a plurality of sub-pixel rows in the display panel 01 form at least one driving group 100, the same driving group 100 includes a first group of sub-pixel rows 100A and a second group of sub-pixel rows 100B, and the plurality of sub-pixel rows in the first group of sub-pixel rows 100A are arranged alternately with the plurality of sub-pixel rows in the second group of sub-pixel rows 100B in the second direction Y.

[0120] For example, the first group of sub-pixel rows 100A includes odd-numbered rows of sub-pixels, and the second group of sub-pixel rows 100B includes even-numbered rows of sub-pixels.

[0121] The driving method further includes: sequentially driving the first group of sub-pixel rows 100A and the second group of sub-pixel rows 100B in one frame of the display panel 01.

[0122] In an embodiment of the present application, the sub-pixel rows in the first group of sub-pixel rows 100A are arranged alternately with the sub-pixel rows in the second group of sub-pixel rows 100B, and the first group of sub-pixel rows 100A and the second group of sub-pixel rows 100B are sequentially driven, so that the plurality of sub-pixel rows in the same driving group 100 can be driven in an interleaved manner, which is conducive to driving the (i+1)th row of sub-pixels 10_i+1 into the reset phase t1 or the data writing phase t2 after the ith row of sub-pixels 10_i and the (i+2)th row of sub-pixels 10_i+2 sequentially enter the light-emitting phase t3, thereby facilitating the two rows of sub-pixels adjacent to the (i+1)th row of sub-pixels 10_i+1 and located on the opposite sides thereof to be in the light-emitting state when the (i+1)th row of sub-pixels 10_i+1 is in the dark state, and further facilitating the reduction of the visual effect of the (i+1)th row of sub-pixels 10_i+1 in the dark state.

[0123] Figure 15 A schematic diagram of a display device provided in an embodiment of the present application.

[0124] An embodiment of the present application provides a display device 02, as shown in the figure. Figure 15 As shown, the display device 02 includes the display panel 01 provided in the above embodiment. For example, the display device 02 can be an electronic device such as a mobile phone, a computer, a television, a vehicle-mounted display, a wearable display, etc., which is not limited in the present application.

[0125] In the display device 02, in the reset stage t1 and / or the data writing stage t2 of the (i+1)th row of sub-pixels 10_i+1, the ith row of sub-pixels 10_i is set to be in the light-emitting stage t3, and the (i+2)th row of sub-pixels 10_i+2 is set to be in the light-emitting stage t3. When the (i+1)th row of sub-pixels 10_i+1 is in the dark state for at least part of the period, the two rows of sub-pixels adjacent to the (i+1)th row of sub-pixels 10_i+1 and located on the opposite sides thereof can be in the light-emitting state, thereby facilitating the same area of multiple rows of sub-pixels not to be darkened at the same time, reducing the obviousness of the dark state of the (i+1)th row of sub-pixels 10_i+1, weakening the light-dark difference recognized by the human eye, thereby reducing the harm of the picture to the human eye, and realizing the eye protection function of the display panel.

[0126] The above only describes the preferred embodiments of the present application and is not used to limit the present application. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present application shall be included in the protection scope of the present application.

Claims

1. A display panel, characterized in that, It includes multiple sub-pixels, each sub-pixel including an electrically connected pixel circuit and a light-emitting device. The i-th row of sub-pixels includes multiple sub-pixels arranged along a first direction. Multiple rows of sub-pixels are arranged along a second direction, which intersects with the first direction. Here, i is any positive integer. One working cycle of the pixel circuit includes a reset phase, a data writing phase, and a light emission phase. During the reset phase and / or the data writing phase of the (i+1)th row sub-pixel, the (i)th row sub-pixel is in the light emission phase, and the (i+2)th row sub-pixel is in the light emission phase.

2. The display panel according to claim 1, characterized in that, During the reset phase and / or data writing phase of the (i+1)th row of sub-pixels, at least two rows of sub-pixels located on one side of the (i+1)th row of sub-pixels and adjacent to it are in the light-emitting phase, and at least two rows of sub-pixels located on the other side of the (i+1)th row of sub-pixels and adjacent to it are in the light-emitting phase.

3. The display panel according to claim 1, characterized in that, In the display panel, multiple sub-pixel rows form at least one driving group. The same driving group includes a first group of sub-pixel rows and a second group of sub-pixel rows. In one frame of the display panel, the first group of sub-pixel rows and the second group of sub-pixel rows are driven sequentially. In this configuration, multiple rows of sub-pixels in the first group of sub-pixel rows are alternately arranged with multiple rows of sub-pixels in the second group of sub-pixel rows in the second direction.

4. The display panel according to claim 3, characterized in that, The display panel includes multiple drive groups, which are driven sequentially.

5. The display panel according to claim 3, characterized in that, In the same driving group, the number of sub-pixel rows included in the first group of sub-pixel rows is the same as the number of sub-pixel rows included in the second group of sub-pixel rows; In this group, the sub-pixels in the first group of sub-pixel rows are odd-numbered rows, and the sub-pixels in the second group of sub-pixel rows are even-numbered rows.

6. The display panel according to claim 3, characterized in that, In the same group of subpixel rows (first group or second group), between two adjacent rows of subpixels in the second direction, there are at least two rows of subpixels that do not belong to that group of subpixel rows.

7. The display panel according to claim 3, characterized in that, The pixel circuit includes: Drive transistors; A power supply voltage writing module, wherein the input terminal of the power supply voltage writing module is electrically connected to the first power signal line, the output terminal is electrically connected to the first electrode of the driving transistor, and the control terminal is electrically connected to the light emission control signal line; The light-emitting control module has an input terminal electrically connected to the second electrode of the driving transistor, an output terminal electrically connected to the first electrode of the light-emitting device, and a control terminal electrically connected to the light-emitting control signal line. During the light-emitting stage, the light-emitting control signal line transmits an enable signal, and both the power supply voltage writing module and the light-emitting control module are in the on state. During the reset phase and the data writing phase, the light emission control signal line transmits an enable signal, and both the power supply voltage writing module and the light emission control module are in a turned-off state.

8. The display panel according to claim 7, characterized in that, In the same driving group, both the first group of sub-pixel rows and the second group of sub-pixel rows include n rows of sub-pixels; In a frame of the display panel, the time periods during which the light emission control signal lines in m rows of sub-pixels in the same group of sub-pixels transmit non-enabled signals overlap. Where n > m, and n and m are both positive integers.

9. The display panel according to claim 8, characterized in that, nm≥2.

10. The display panel according to claim 3, characterized in that, The display panel includes multiple data signal lines, which extend along the second direction and are arranged along the first direction. Within the same drive group, the data signal line sequentially transmits data voltage to the first group of sub-pixel rows and the second group of sub-pixel rows.

11. The display panel according to claim 3, characterized in that, The display panel includes a scanning circuit, which includes multiple cascaded shift register units. The multiple cascaded shift register units form at least one scanning group, and the scanning group is electrically connected to the driving group. The same scanning group includes a first group of shift register units and a second group of shift register units. The first group of shift register units is electrically connected to the first group of sub-pixels, and the second group of shift register units is electrically connected to the second group of sub-pixels. The first group of shift register units and the second group of shift register units output scanning signals sequentially.

12. The display panel according to claim 11, characterized in that, The scanning circuit includes multiple scanning groups, and the multiple scanning groups output scanning signals sequentially.

13. The display panel according to claim 11, characterized in that, Multiple shift register units are arranged along the second direction. In the same scanning group, multiple shift register units in the first group of shift register units are alternately arranged with multiple shift register units in the second group of shift register units in the second direction.

14. The display panel according to claim 13, characterized in that, The shift registers in the first group of shift registers are odd-level shift registers, while the shift registers in the second group of shift registers are even-level shift registers.

15. The display panel according to claim 11, characterized in that, In the same scan group, the last shift register in the first group of shift registers is cascaded with the first shift register in the second group of shift registers.

16. The display panel according to claim 11, characterized in that, Both the first group of shift register units and the second group of shift register units include multiple shift register units, and in the same group of shift register units, the multiple shift register units are cascaded in sequence.

17. The display panel according to claim 7, characterized in that, The pixel circuit also includes: The first reset module has an input terminal electrically connected to the first reset voltage signal line, an output terminal electrically connected to the gate of the driving transistor, and a control terminal electrically connected to the first scan line. The data writing module has an input terminal electrically connected to the data signal line, an output terminal electrically connected to the first electrode of the driving transistor, and a control terminal electrically connected to the second scan line. A threshold grasping module, wherein the input terminal of the threshold grasping module is electrically connected to the second electrode of the driving transistor, the output terminal is electrically connected to the gate of the driving transistor, and the control terminal is electrically connected to the second scan line; The second reset module has an input terminal electrically connected to the second reset voltage signal line, an output terminal electrically connected to the first electrode of the light-emitting device, and a control terminal electrically connected to the second scan line; in one working cycle of the pixel circuit, the data writing stage is performed after the reset stage; Specifically, the first reset module is activated during the reset phase, and the second reset module, the data writing module, and the threshold capture module are activated during the data writing phase.

18. A driving method for a display panel, characterized in that, The display panel includes multiple sub-pixels, the i-th row of sub-pixels includes multiple sub-pixels arranged along a first direction, and multiple rows of sub-pixels are arranged along a second direction, which intersects with the first direction, where i is any positive integer; the method includes: In a frame of the display panel, during the period when the (i+1)th row of sub-pixels is not emitting light, the (i)th row of sub-pixels is driven to emit light, and the (i+2)th row of sub-pixels is driven to emit light.

19. The driving method according to claim 18, characterized in that, The method further includes: In a frame of the display panel, during the period when the (i+1)th row of sub-pixels is not emitting light, at least two rows of sub-pixels on one side of the (i+1)th row of sub-pixels and adjacent to it are driven to emit light, and at least two rows of sub-pixels on the other side of the (i+1)th row of sub-pixels and adjacent to it are driven to emit light.

20. The driving method according to claim 18, characterized in that, In the display panel, multiple sub-pixel rows form at least one driving group. The same driving group includes a first group of sub-pixel rows and a second group of sub-pixel rows. Multiple rows of sub-pixels in the first group of sub-pixel rows and multiple rows of sub-pixels in the second group of sub-pixel rows are alternately arranged in the second direction. The method further includes: In one frame of the display panel, the first group of sub-pixel rows and the second group of sub-pixel rows are driven sequentially.

21. A display device, characterized in that, Includes the display panel as described in any one of claims 1-17.

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