Method and device for testing word line physical address of dram and storage medium

Abstract

The application discloses a DRAM word line physical address testing method and device and a storage medium, relates to the technical field of testing, and comprises the following steps: determining same-area WLS in each memory area of the DRAM respectively and neighbor-area WLS corresponding to the same-area WLS; determining the region mutual relationship between each memory area based on the neighbor-area WLS corresponding to each same-area WL; determining the adjacent same-area WLS corresponding to each same-area WL based on the same-area WLS in each memory area, and determining a boundary memory area in each memory area; and determining the physical address of each WL. The application can accurately determine the physical address of each WL in the DRAM, realizes accurate testing of the word line physical address of the DRAM, and facilitates corresponding testing of the DRAM according to the physical address of the WL, thereby improving the accuracy and efficiency of DRAM testing.

Description

Technical Field

[0001] This application relates to the field of testing technology, and in particular to a method, apparatus and storage medium for testing the word line physical address of DRAM. Background Technology

[0002] In current memory products such as DRAM (Dynamic Random Access Memory), apart from the chip designer, others usually do not know the physical addresses of each WL (Word Line) in the memory. This makes it impossible to accurately evaluate the testing effectiveness of memory testing algorithms. For example, memory testing algorithms that test the coupling effect between different rows need to write opposite data to adjacent WLs for testing. Without knowing the physical address of the WL, it is difficult to accurately determine adjacent WLs. In some memory testing processes, if a WL is continuously switched on and off too many times, it will cause the data of its adjacent WLs to become invalid, resulting in the row hammer effect. Without knowing the physical address of the WL, it is difficult to effectively reduce the probability of the row hammer effect.

[0003] Therefore, how to accurately test the physical address of DRAM word lines is a problem that urgently needs to be solved.

[0004] The above content is only used to help understand the technical solution of this application and does not represent an admission that the above content is prior art. Summary of the Invention

[0005] The main objective of this application is to provide a method, apparatus, and storage medium for testing the word line physical address of DRAM, aiming to solve the technical problem of how to accurately test the word line physical address of DRAM.

[0006] To achieve the above objectives, this application proposes a method for testing the physical address of a DRAM word line, the method comprising:

[0007] Based on each word line WL of the DRAM, the same region WL and the neighboring region WL corresponding to the same region WL in each memory region of the DRAM are determined respectively.

[0008] Based on the neighboring regions WL corresponding to each region WL, determine the inter-regional relationships between each memory region.

[0009] Based on the same region WL in each memory region, determine the adjacent same region WL corresponding to each same region WL, and determine the boundary memory region in each memory region.

[0010] Based on the WL of the same region, WL of neighboring regions, the relationship between regions, the adjacent WL of the same region corresponding to each WL of the same region, and the boundary memory region, the physical address of each WL is determined.

[0011] In one embodiment, the step of determining the same region WL and the corresponding neighboring region WL in each memory region of the DRAM based on each word line WL of the DRAM includes:

[0012] In the DRAM, the first WL is determined, and the WLs other than the first WL are taken as the WLs to be processed.

[0013] Sequentially determine the second WL in the WL to be processed, write the first data in the second WL, and write the second data in the first WL, wherein the first data and the second data are different;

[0014] Within a preset time period following the precharge PRE instruction corresponding to the first WL, a read operation is performed on the second WL to obtain the first read data, wherein the preset time period is less than the row precharge time tRP corresponding to the DRAM;

[0015] First data is written into the second WL and the first WL in sequence. Within a preset time after the PRE instruction corresponding to the first WL, a read operation is performed on the second WL to obtain the second read data. Then, the process of determining the second WL in the pending WL in sequence is returned until the pending WL is processed.

[0016] Based on the first read data in the WL to be processed, determine the same region WL corresponding to the first WL, and based on the second read data in the WL to be processed, determine the neighboring region WL corresponding to the first WL.

[0017] In one embodiment, the steps of determining the same region WL corresponding to the first WL in the WL to be processed based on the first read data, and determining the neighboring region WL corresponding to the first WL in the WL to be processed based on the second read data, include:

[0018] Based on the first data, the first failed data in the first read data is determined, and the first failed WL corresponding to the first failed data in the WL to be processed is taken as the same region WL corresponding to the first WL.

[0019] Based on the first data, the second failed data in the second read data is determined, and the second failed WL corresponding to the second failed data in the WL to be processed is taken as the neighboring region WL corresponding to the first WL.

[0020] In one embodiment, after the step of determining the neighboring region WL corresponding to the first WL in the WL to be processed based on the second read data, the method further includes:

[0021] If there is a first target memory region that determines one of the two adjacent memory regions to which the neighboring region WL to the first WL belongs, then delete the first WL and the same region WL corresponding to the first WL from the WL to be processed.

[0022] A first WL is determined in the first target memory region, the first WL is deleted in the WL to be processed, and the process returns to perform the step of determining a second WL in the WL to be processed in turn.

[0023] In one embodiment, after the step of determining the neighboring region WL corresponding to the first WL in the WL to be processed based on the second read data, the method further includes:

[0024] If there is a first target memory region that determines one of the two adjacent memory regions to which the neighboring region WL to the first WL belongs, then delete the first WL, the same region WL to which the first WL belongs, and the neighboring region WL from the WL to be processed.

[0025] In the first target memory region, a first WL is determined, and in the WL to be processed, a second WL is determined sequentially. Then, the first data is written into the second WL and the first WL in sequence.

[0026] Within a preset time period after the PRE instruction when writing the first data in the first WL, a read operation is performed on the second WL to obtain the third read data, and then the process of determining the second WL in the pending WL is returned to continue until the pending WL is processed.

[0027] Based on the third read data in the WL to be processed, determine the neighboring region WL corresponding to the first WL, and determine the same region WL among the two adjacent memory regions corresponding to the memory region to which the first WL belongs, and return to execute the step of deleting the first WL, the same region WL corresponding to the first WL, and the neighboring region WL in the WL to be processed if there is a first target memory region that determines an adjacent memory region among the two adjacent memory regions to which the neighboring region WL corresponding to the first WL belongs.

[0028] In one embodiment, the step of determining the same region WL among two adjacent memory regions corresponding to the memory region to which the first WL belongs includes:

[0029] Based on the first data, the third invalid data in the third read data is determined;

[0030] The third failure data is divided into first same-region failure data and second same-region failure data;

[0031] The WL corresponding to the first same-region failure data is taken as the same-region WL in one of the two adjacent memory regions to which the first WL belongs, and the WL corresponding to the second same-region failure data is taken as the same-region WL in the other memory region.

[0032] In one embodiment, the step of determining the adjacent same-region WL corresponding to each same-region WL based on the same-region WL in each memory region includes:

[0033] Sequentially determine the second target memory region in each memory region, write the third data into each WL in the second target memory region, and reverse the data in the third WL in each WL.

[0034] Perform continuous switching operations on the third WL, and when the number of switching operations of the third WL reaches a preset number, read the fourth read data of each WL in the target memory area;

[0035] The WL corresponding to the failed data in the fourth read data is taken as the adjacent WL corresponding to the third WL;

[0036] One of the adjacent WLs corresponding to the third WL is taken as the third WL, and the process of writing the third data into each WL in the second target memory area is returned, and the third WL in each WL is reversed, until each WL in the second target memory area is processed.

[0037] In one embodiment, the step of determining the boundary memory regions in each memory region includes:

[0038] Perform switching operations on the WL in each memory region and obtain the power consumption data of each memory region during the switching operation;

[0039] The memory region corresponding to the highest power consumption data is used as the boundary memory region.

[0040] Furthermore, to achieve the above objectives, this application also proposes a DRAM word line physical address testing apparatus, the apparatus comprising: a memory, a processor, and a computer program stored on the memory and executable on the processor, the computer program being configured to implement the steps of the aforementioned DRAM word line physical address testing method.

[0041] In addition, to achieve the above objectives, this application also proposes a storage medium, which is a computer-readable storage medium, on which a computer program is stored, and when the computer program is executed by a processor, it implements the steps of the aforementioned DRAM word line physical address testing method.

[0042] One or more technical solutions proposed in this application have at least the following technical effects:

[0043] By detecting the WL (word line address) of each memory region in the DRAM and the corresponding neighboring WL, and determining the region relationships between memory regions, the adjacent WLs of each WL, and the boundary memory regions, the physical address of each WL in the DRAM can be accurately determined. This enables accurate testing of the physical address of the DRAM word line, facilitating the corresponding testing of the DRAM based on the physical address of the WL, thus improving the accuracy and efficiency of DRAM testing. Attached Figure Description

[0044] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this application and, together with the description, serve to explain the principles of this application.

[0045] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, for those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0046] Figure 1 A flowchart illustrating the word line physical address testing method for DRAM in this application (Example 1).

[0047] Figure 2 This is a schematic diagram of the DRAM memory structure in related technologies;

[0048] Figure 3 This is a schematic diagram of the memory structure of various memory regions in DRAM in related technologies;

[0049] Figure 4 This is a schematic diagram of a WL reading operation in one embodiment of this application;

[0050] Figure 5 This is a schematic diagram of a WL reading operation in another embodiment of this application;

[0051] Figure 6 This is a simplified flowchart illustrating the process of determining the WL on both sides of WL in one embodiment of this application;

[0052] Figure 7 This is a schematic diagram of the hardware operating environment involved in the DRAM word line physical address testing method in this application embodiment.

[0053] The purpose, features, and advantages of this application will be further explained in conjunction with the embodiments and with reference to the accompanying drawings. Detailed Implementation

[0054] It should be understood that the specific embodiments described herein are merely illustrative of the technical solutions of this application and are not intended to limit this application.

[0055] To better understand the technical solution of this application, a detailed description will be provided below in conjunction with the accompanying drawings and specific implementation methods.

[0056] The main solution of this application embodiment is as follows: Based on each word line WL of the DRAM, determine the same region WL and the neighboring region WL corresponding to each memory region of the DRAM; based on the neighboring region WL corresponding to each same region WL, determine the region relationship between each memory region; based on the same region WL in each memory region, determine the adjacent same region WL corresponding to each same region WL, and determine the boundary memory region in each memory region; based on the same region WL, neighboring region WL, region relationship, adjacent same region WL, and boundary memory region, determine the physical address of each WL.

[0057] In this embodiment, for ease of description, the following description will focus on the physical address testing device for identifying word lines.

[0058] In current memory products such as DRAM (Dynamic Random Access Memory), aside from the chip designer, others typically do not know the physical addresses of each Word Line (WL) in the memory. This makes it difficult to accurately evaluate the effectiveness of memory testing algorithms. For example, memory testing algorithms that test the coupling effect between different rows require writing opposite data to adjacent WLs for testing. Without knowing the physical addresses of the WLs, it is difficult to accurately determine which WLs are adjacent. During some memory tests, repeatedly switching a WL on and off too many times can cause data corruption in its adjacent WLs, resulting in the row hammer effect. Without knowing the physical addresses of the WLs, it is difficult to effectively reduce the probability of the row hammer effect. Furthermore, during the testing or use of critical timing parameters, the lack of knowledge of the physical addresses of the WLs, and the fact that the relative distance or proximity of WLs affects certain critical timing parameters, leads to low efficiency in the testing or use process.

[0059] Therefore, how to accurately test the physical address of DRAM word lines is a problem that urgently needs to be solved.

[0060] This application provides a solution that detects the same memory region (WL) and its corresponding neighboring memory regions (WL) in each memory region of DRAM, and determines the inter-regional relationships between memory regions, the adjacent memory regions (WL) corresponding to each same memory region (WL), and the boundary memory regions. This allows for the accurate determination of the physical address of each WL in the DRAM, enabling accurate testing of the word line physical address of the DRAM. This facilitates the corresponding testing of the DRAM based on the physical address of the WL, improving the accuracy and efficiency of DRAM testing.

[0061] It should be noted that the executing entity in this embodiment can be a computing service device with data processing, network communication, and program execution functions, such as a tablet computer, personal computer, or mobile phone, or an electronic device capable of performing the above functions, such as a DRAM word line physical address testing device. The following description uses a DRAM word line physical address testing device as an example to illustrate this embodiment and the subsequent embodiments.

[0062] Based on this, embodiments of this application provide a method for testing the word line physical address of DRAM, referring to... Figure 1 , Figure 1 This is a flowchart illustrating the first embodiment of the DRAM word line physical address testing method of this application.

[0063] In this embodiment, the DRAM word line physical address testing method includes steps S110~S140:

[0064] Step S110: Based on each word line WL of the DRAM, determine the same region WL and the neighboring region WL corresponding to the same region WL in each memory region of the DRAM.

[0065] In related technologies, such as Figure 2As shown, region 1 and region 2 share a common inductive amplifier SA. The column of region 1 is BL, which is a bit line. The column of region 2 is / BL. When no WL is turned on in region 1 or region 2, BL and / BL are both in a pre-charge state and both have a potential of VREF. The principle of memory read access is as follows: When an ACT (Activate) instruction is issued to a specified row WL in region 1, the DRAM will open the WL internally. The potential stored in the capacitors of all BL on the WL will be transferred to BL. Due to the change in the potential on BL, SA will amplify BL and / BL to opposite potentials respectively. For example, if the data stored in the capacitor of BL is 1, the SA circuit will amplify the potential of BL by induction, pulling it up above VREF and the potential of / BL down below VREF. At this time, when a READ instruction is issued to any specified column address on the WL, the potentials of BL and / BL will be sent to the next stage circuit until finally output at the chip data pin. When the WL is no longer needed, a PRE (Precharge) instruction is issued to the WL. The DRAM internally will pull the potential of the WL low, and then pull the potentials of BL and / BL back to VREF through the precharge circuit.

[0066] like Figure 3 and Figure 4 As shown, Figure 3 WL1 and WL2 are located in the same memory area, meaning that WL1 and WL2 share the SA circuit and are both at BL or both at the / BL terminal.

[0067] like Figure 4 As shown, when data 0 is written to WL1 and data 1 is written to WL2, within a preset time period after the PRE instruction when writing data 1 to WL2, data is read from WL1. Since WL2 is turned off when the PRE instruction to WL2 is executed, the BL on WL2 is slowly pulled low to VREF by the pre-charge circuit. When the ACT instruction is issued to WL1 within the preset time period after the PRE instruction when writing data 1 to WL2, the BL will be transmitted from the potential of data 0 stored in the capacitor on WL1. Since the potential of the capacitor cannot cancel the current potential of BL, the corresponding SA pulls the potential of BL back to 1. This causes the capacitor on WL1 and the data sent out by BL after the READ instruction of WL1 to be amplified to the potential of data 1 by the SA. As a result, the data read by WL1 is opposite to the last written data, resulting in WL1 failure. At this time, the data of all columns of WL1 is invalid.

[0068] The preset duration is less than the tRP (RAS Precharge Time) of the chip under test. tRP is the time interval between PRE and ACT instructions in the same bank, regardless of whether the two instructions are sent to the same or different WLs in the same bank.

[0069] like Figure 3 and Figure 5 As shown, Figure 3 In the memory, WL1 is located in adjacent memory regions with WL3 and WL4 respectively. The relationship between WL1 and WL3 is that WL1 is at the BL end and WL3 is at the / BL end. The relationship between WL1 and WL4 is that WL1 is at the / BL end and WL4 is at the BL end. That is, some columns of WL1 share one SA with WL4, and the remaining columns of WL1 share another SA with WL3.

[0070] like Figure 5 As shown, when data 0 is written to WL1 and data 0 is written to WL3, within a preset time after the PRE instruction when data 0 is written to WL3, data is read from WL1. Since WL3 is turned off when the PRE instruction is executed, / BL on WL3 is slowly pulled high to VREF by the precharge circuit, and BL is slowly pulled low to VREF by the precharge circuit. When the ACT instruction is issued to WL1 within the preset time after the PRE instruction when data 0 is written to WL3, BL will be transmitted from the potential of data 0 stored on the capacitor of WL1 again. Since the potential of the capacitor cannot cancel the current potential of BL, SA pulls the potential of BL back to 1. As a result, the potential of the capacitor on WL1 and the data sent out by BL after the READ instruction are amplified to the potential of data 1 by SA. As a result, half of the column data in the read data is opposite to the last written data, and WL1 becomes invalid.

[0071] Similarly, if data 0 is written to WL1, and data 0 is written to WL4, and within a preset time after the PRE instruction when data 0 is written to WL4, the data in WL1 is read. At this time, half of the column data in the read data is the opposite of the data written last time, and WL1 becomes invalid.

[0072] Furthermore, WL3 causes half of the column data in WL1 to become invalid, and WL4 causes the other half of the column data in WL1 to become invalid. That is, WL3 will cause half of the columns in WL1 that share the SA with WL3 to become invalid, and WL4 will cause half of the columns in WL1 that share the SA with WL4 to become invalid.

[0073] In this embodiment, based on the above principle, the same-region WL and adjacent-region WL of each WL in the DRAM are determined. Then, the same-region WL and the corresponding adjacent-region WL in each memory region of the DRAM are determined. Specifically, any WL is selected as the first WL from each word line of the DRAM, and all word lines of the DRAM excluding the word lines are selected as WLs to be processed. A WL is then selected sequentially from the WLs to be processed as the second WL. For example, the second WL can be selected sequentially according to the numbering order of the WLs. The above operations are performed on the first WL and the second WL to determine the relationship between the second WL and the first WL, and the relationship between the other WLs and the first WL is determined sequentially. Then, the first WL is replaced until the relationship between all WLs is determined.

[0074] In one feasible implementation, step S110 may include steps S210~S250:

[0075] Step S210: Determine the first WL among the WLs in the DRAM, and take the WLs other than the first WL as the WLs to be processed.

[0076] Step S220: Sequentially determine the second WL in the WL to be processed, write the first data in the second WL, and write the second data in the first WL, wherein the first data and the second data are different;

[0077] Step S230: Within a preset time period after the precharge PRE instruction corresponding to the first WL, a read operation is performed on the second WL to obtain the first read data, wherein the preset time period is less than the row precharge time tRP corresponding to the DRAM.

[0078] Step S240: Write the first data into the second WL and the first WL in sequence, and within a preset time after the PRE instruction corresponding to the first WL, perform a read operation on the second WL to obtain the second read data, and return to execute the step of determining the second WL in the WL to be processed in sequence until the WL to be processed is processed.

[0079] Step S250: Based on the first read data in the WL to be processed, determine the same region WL corresponding to the first WL, and based on the second read data in the WL to be processed, determine the neighboring region WL corresponding to the first WL.

[0080] In this embodiment, any word line (WL) of the DRAM is selected as the first WL, and all word lines of the DRAM excluding the word lines of the DRAM are selected as WLs to be processed. Then, one WL is selected from the WLs to be processed as the second WL in sequence. For example, the second WL can be selected in sequence according to the numbering order of the WLs.

[0081] After determining the second write space (WL), the first data is written into the second WL. After the second WL is written, the second data is written into the first WL. This involves sequentially applying the ACT instruction to the second WL, the Write instruction to the first data, and the PRE instruction to the first WL. The second data differs from the first data; specifically, the second data can be the opposite of the first data. For example, if the first data is all 0s, the second data can be all 1s.

[0082] Within a preset time period following the PRE command corresponding to the first WL, that is, within a preset time period after the PRE command is issued to the first WL, a read operation is performed on the second WL to obtain the first read data. Specifically, within a preset time period after the PRE command is issued to the first WL, the ACT command, Read command and PRE command are issued to the second WL in sequence to read the data in the current second WL and obtain the first read data.

[0083] After obtaining the first read data, the first data is written into the second write lock (WL). This is done by sequentially issuing the ACT command, the Write command for the first data, and the PRE command to the second write lock. Then, within a preset time period following the PRE command for the first write lock, a read operation is performed on the second write lock to obtain the second read data. This involves sequentially issuing the ACT command, the Read command, and the PRE command to the second write lock to read the data currently in the second write lock.

[0084] After obtaining the second read data, determine whether each WL in the pending WL has been processed. Processing completion means that all WLs in the pending WL have undergone the above process. If there are unprocessed WLs in the pending WL, return to execute the step of determining the second WL in the pending WL in turn, until the pending WL is processed.

[0085] In this embodiment of the application, after the processing of the WL to be processed is completed, the same region WL corresponding to the first WL is determined in the WL to be processed based on the first read data, and the neighboring region WL corresponding to the first WL is determined in the WL to be processed based on the second read data. Specifically, the same region WL and the neighboring region WL are determined based on the invalid data in the first read data and the second read data, respectively. In a feasible implementation, step S250 may include steps S251~S252:

[0086] Step S251: Based on the first data, determine the first failed data in the first read data, and take the first failed WL corresponding to the first failed data in the WL to be processed as the same region WL corresponding to the first WL;

[0087] Step S252: Based on the first data, determine the second failed data in the second read data, and take the second failed WL corresponding to the second failed data in the WL to be processed as the neighboring region WL corresponding to the first WL.

[0088] In this embodiment of the application, after the processing of the WL to be processed is completed, for the first read data, data that is different from the first data is selected as the first invalid data. In each WL to be processed, the WL corresponding to each first invalid data is regarded as the same region WL in the same memory area as the first WL. Thus, the same region WL of the first WL can be accurately determined based on the first read data.

[0089] Meanwhile, for the second read data, data that is different from the first data is filtered out as second invalid data. In each unprocessed WL, the WL corresponding to each second invalid data is taken as the neighboring region WL corresponding to the first WL. The neighboring region WL is the WL in the two memory regions adjacent to the memory region to which the first WL belongs. Thus, the neighboring region WL of the first WL can be accurately determined based on the second read data.

[0090] In one feasible implementation, after step S250, the DRAM word line physical address testing method further includes steps S260-S270:

[0091] Step S260: If there is a first target memory region that determines an adjacent memory region among the two adjacent memory regions to which the neighboring region WL to be processed belongs, then delete the first WL and the same region WL to which the first WL belongs from the WL to be processed.

[0092] Step S270: Determine a first WL in the first target memory region, delete the first WL in the WL to be processed, and return to execute the step of determining a second WL in the WL to be processed in turn.

[0093] In this embodiment, after determining the same region WL and neighboring regions WL corresponding to the first WL, it is determined whether all memory regions in the DRAM have been discovered. Specifically, it is determined whether each discovered memory region has two adjacent memory regions. That is, if the two adjacent memory regions to which the neighboring region WL corresponds to the first WL belongs have both identified as having two adjacent memory regions, i.e., whether two adjacent memory regions exist. That is, if the two adjacent memory regions of WL are A and B, it is determined whether A and B are also adjacent. If they are, it indicates that the loop has been completed and all memory regions have been operated on. If so, it is determined that all memory regions in the DRAM have been discovered. If, among the two adjacent memory regions to which the neighboring region WL corresponds to the first WL belongs, there exists a first target memory region with one identified adjacent memory region, it is determined that not all memory regions in the DRAM have been discovered. In this case, the first WL and its corresponding same region WL are deleted from the WL to be processed, thereby updating the WL to be processed.

[0094] Next, arbitrarily select one WL from the WLs of the first target memory region as the first WL. After redetermining the first WL, delete the first WL from the WLs to be processed, and return to execute the step of determining the second WL in the WLs to be processed in turn. Based on the redetermined first WL, detect the WLs in the same region and the WLs in the adjacent region of the first WL, until all memory regions in the DRAM are found, thus realizing the detection of the WLs in the same region and the WLs in the adjacent region of all WLs in the DRAM.

[0095] In one feasible implementation, after step S250, the DRAM word line physical address testing method may further include steps S310 to S340:

[0096] Step S310: If there is a first target memory region that determines an adjacent memory region among the two adjacent memory regions to which the neighboring region WL to which the first WL belongs, then delete the first WL, the same region WL to which the first WL belongs, and the neighboring region WL from the WL to be processed.

[0097] Step S320: Determine a first WL in the first target memory region, determine a second WL in the WL to be processed in sequence, and write the first data into the second WL and the first WL in sequence.

[0098] Step S330: Within a preset time period after the PRE instruction when writing the first data in the first WL, perform a read operation on the second WL to obtain the third read data, and return to execute the step of determining the second WL in the WL to be processed in sequence until the WL to be processed is processed.

[0099] Step S340: Based on the third read data in the WL to be processed, determine the neighboring region WL corresponding to the first WL, and determine the same region WL among the two adjacent memory regions corresponding to the memory region to which the first WL belongs, and return to execute the step of deleting the first WL, the same region WL corresponding to the first WL, and the neighboring region WL in the WL to be processed if there is a first target memory region that determines an adjacent memory region among the two adjacent memory regions to which the neighboring region WL corresponding to the first WL belongs.

[0100] In this embodiment of the application, after step S250, the neighboring regions WL corresponding to the first WL can be divided based on the second read data to obtain the same region WL in the two adjacent memory regions of the memory region to which the first WL belongs. Thus, in the subsequent processing, it is not necessary to identify the same region WL among the WLs to be processed again.

[0101] Next, if there exists a first target memory region that determines an adjacent memory region among the two adjacent memory regions to which the first WL corresponds, then the first WL and the corresponding region WL are deleted from the WL to be processed, so as to update the WL to be processed.

[0102] Arbitrarily select a memory location (WL) in the first target memory region as the first WL. After re-determining the first WL, delete the first WL from the WL to be processed, and then determine the second WL in turn. Write the first data into the second WL and the first WL in turn, that is, apply the ACT instruction, the Write instruction for the first data, and the PRE instruction to the second WL in turn. Then write the first data into the first WL in turn, that is, apply the ACT instruction, the Write instruction for the first data, and the PRE instruction to the first WL in turn.

[0103] Within a preset time period following the PRE instruction when writing the first data to the first WL (i.e., within a preset time period after issuing the PRE instruction to the first WL), the ACT instruction, Read instruction, and PRE instruction are sequentially issued to the second WL to read the data in the current second WL and obtain the second read data. Afterwards, it is determined whether each WL in the pending WL has been processed. Processing completion means that all WLs in the pending word line have undergone the above process. If there are any unprocessed WLs in the pending WL, the process returns to the previous steps of sequentially determining the second WL in the pending WL until the pending WL is processed.

[0104] When the third read data corresponding to the first WL is obtained, the neighboring region WL corresponding to the first WL is determined based on the third read data in the WL to be processed. Specifically, the neighboring region WL corresponding to the first WL is determined based on the invalid data in the third read data, and the same region WL in the two adjacent memory regions corresponding to the memory region to which the first WL belongs is determined based on the neighboring region WL.

[0105] In one feasible implementation, step S340 may include steps S341 to S343:

[0106] Step S341: Determine the third invalid data in the third read data based on the first data;

[0107] Step S342: Divide the third failure data into first same-region failure data and second same-region failure data;

[0108] Step S343: Take the WL corresponding to the first same-region failure data as the same-region WL in one of the two adjacent memory regions to which the first WL belongs, and take the WL corresponding to the second same-region failure data as the same-region WL in the other memory region.

[0109] In this embodiment of the application, when determining the same region WL in two adjacent memory regions, the third invalid data in the third read data is determined based on the first data. Specifically, data that is different from the first data is selected from the third read data as the third invalid data.

[0110] After obtaining the third failure data, the third failure data is divided into first same-region failure data and second same-region failure data. Specifically, one failure data in the third failure data can be selected as the first same-region failure data. The other failure data in the third failure data are compared with the selected failure data. The data in the third failure data that is the same as the selected failure data is selected as the first same-region failure data, and the data in the third failure data that is different from the selected failure data is selected as the second same-region failure data.

[0111] After obtaining the first and second same-region failure data, the WL corresponding to the first same-region failure data in the WL to be processed is taken as the same-region WL in one of the two adjacent memory regions corresponding to the memory region to which the first WL belongs. The WL corresponding to the second same-region failure data in the WL to be processed is taken as the same-region WL in the other memory region. Thus, the same-region WL in the two adjacent memory regions corresponding to the memory region to which the first WL belongs can be accurately determined based on the third read data.

[0112] After determining the same region WL in two adjacent memory regions corresponding to the memory region to which the first WL belongs, return to step S310 to ensure that the same region WL and adjacent region WL in all memory regions of the DRAM are detected.

[0113] Step S120: Determine the inter-regional relationships between memory regions based on the neighboring regions WL corresponding to each region WL.

[0114] After determining the same region WL and the neighboring region WL corresponding to each memory region WL, the region interrelationship between each memory region is determined based on the neighboring region WL corresponding to each same region WL. Specifically, the neighboring region WL corresponding to any WL in each memory region can be used to determine the memory regions (adjacent memory regions) at two adjacent positions in each memory region. The region interrelationship includes the adjacent position relationship between each memory region and the adjacent memory region.

[0115] Step S130: Based on the same region WL in each memory region, determine the adjacent same region WL corresponding to each same region WL, and determine the boundary memory region in each memory region.

[0116] In this embodiment of the application, the same region WL in each memory region is first determined, and the adjacent same region WLs of each same region WL in the memory region are determined, that is, the WLs on both sides of each WL are determined. In a feasible implementation, step S130 may include steps S131 to S134:

[0117] Step S131: Sequentially determine the second target memory region in each memory region, write the third data into each WL in the second target memory region, and reverse the data of the third WL in each WL.

[0118] Step S132: Perform continuous switching operation on the third WL, and when the number of switching of the third WL reaches a preset number, read the fourth read data of each WL in the target memory area;

[0119] Step S133: Take the WL corresponding to the failed data in the fourth read data as the adjacent WL corresponding to the third WL;

[0120] Step S134: Take one of the adjacent WLs corresponding to the third WL as the third WL, and return to execute the steps of writing the third data into each WL in the second target memory area and rewriting the third WL in each WL until there are two adjacent WLs in each WL in the second target memory area.

[0121] In this embodiment of the application, a second target memory region is determined sequentially in each memory region. For example, one memory region is selected sequentially as the second target memory region according to its number, or any memory region is selected as the second target memory region. Third data is written into each WL in the second target memory region. Then, any WL in the second target memory region is selected as the third WL, and the data in the third WL is reversed.

[0122] After writing the data back to the third memory level (WL), a continuous switching operation is performed on the third WL, that is, ACT and PRE instructions are continuously issued to the third WL, and the number of switching operations is counted. When the number of switching operations of the third WL reaches a preset number, the fourth read data of each WL in the target memory area is read. The preset number of times can be reasonably set, such as 1000, 5000, etc.

[0123] After obtaining the fourth read data, invalid data is determined in the fourth read data. Specifically, each fourth read data is compared with the third data. Data in the fourth read data that is different from the third data is taken as invalid data in the third read data. The WL corresponding to the invalid data in the third read data is taken as the adjacent WL corresponding to the third WL. That is, the WL corresponding to the invalid data in the third read data is the WL on both sides of the third WL.

[0124] After determining the adjacent WLs corresponding to the third WL, one of the adjacent WLs in the same region corresponding to the third WL is taken as the third WL, and the process of writing the third data into each WL in the second target memory region is returned to execute the steps of writing the third WL in each WL and reversing the third WL in each WL until each WL in the second target memory region is processed, that is, each WL has completed the process of determining the adjacent WLs.

[0125] like Figure 6 As shown, in Figure 6 The memory area includes WL0, WL1, WL2, WL3, WL4, WL5, and WL6. Data 0 is written to all WL, and data 1 is written to WL2. Then, WL2 is continuously switched on and off a preset number of times. By reading the data of each WL in the memory area, it can be determined that the data of WL1 and WL3 is invalid (F), and thus it is determined that WL1 and WL3 are located on both sides of WL2.

[0126] Write data 0 into all WLs and data 1 into WL1. Then, continuously switch WL1 on and off a preset number of times. By reading the data of each WL in the memory area, it can be seen that the data of WL0 and WL2 is invalid (F), and thus it can be determined that WL0 and WL2 are on both sides of WL1.

[0127] Write data 0 to all WLs and data 1 to WL3. Then, continuously switch WL3 on and off a preset number of times. By reading the data of each WL in the memory area, it can be seen that the data of WL2 and WL4 is invalid (F), and thus it can be determined that WL2 and WL4 are located on both sides of WL3.

[0128] The above operations accurately determine the relative positions of WL0, WL1, WL2, WL3, and WL4. Then, continue to perform related operations on other WLs, and finally, the relative positions of WL0, WL1, WL2, WL3, WL4, WL5, and WL6 can be accurately obtained.

[0129] Simultaneously, boundary memory regions can be defined in each memory region. Half of the bounding loops (BLs) in each boundary memory region are virtual bounding loops (BLs), and the potential of these virtual BLs is connected to a fixed potential. The left and right memory regions of the DRAM electrically form a single memory region. That is, when a bounding loop (WL) is opened in the left memory region, a WL is simultaneously opened in the right memory region. The sum of the BL counts of the two WLs equals the BL count of a complete WL. Specifically, in one feasible implementation, step S130 may include steps S135-S136:

[0130] Step S135: Perform a switching operation on WL in each memory region and obtain the power consumption data of each memory region during the switching operation.

[0131] Step S136: The memory region corresponding to the maximum power consumption data in the power consumption data is taken as the boundary memory region.

[0132] In this embodiment of the application, switching operations are performed on WL in each memory region, and power consumption data of each memory region is obtained during the switching operation. Specifically, the number of WLs to be switched is not limited, that is, multiple WLs in a certain memory region can be switched.

[0133] After obtaining the power consumption data, the maximum power consumption data is obtained, and the memory region corresponding to the maximum power consumption data is determined. When switching the WL in the boundary memory region, a WL will be opened in the memory regions on both the left and right sides at the same time. That is to say, the power consumption data of the boundary memory region is the largest. Therefore, the memory region corresponding to the maximum power consumption data is taken as the boundary memory region, and thus the boundary memory region in DRAM can be accurately determined.

[0134] Step S140: Based on the same region WL, neighboring region WL, the relationship between regions, adjacent same region WL, and boundary memory region, determine the physical address of each WL.

[0135] In this embodiment of the application, the physical address of each WL in the DRAM can be accurately determined by the same region WL, neighboring regions WL, the relationship between regions, adjacent same region WL, and boundary memory regions. For each WL, the physical address of the WL may include the memory region to which the WL belongs, the WLs on both sides, the memory regions adjacent to the memory region to which the WL belongs, the relationship between the memory region to which the WL belongs and other memory regions, the boundary memory regions in the DRAM, etc.

[0136] In this embodiment, based on each word line (WL) of the DRAM, the WL of the same region and the WL of the corresponding neighboring region in each memory region of the DRAM are determined respectively. Then, based on the neighboring region WL corresponding to each same region WL, the region relationship between each memory region is determined. Then, based on the same region WL in each memory region, the adjacent same region WL corresponding to each same region WL is determined, and the boundary memory region is determined in each memory region. Then, based on the same region WL, neighboring region WL, region relationship, adjacent same region WL corresponding to each same region WL, and boundary memory region, the physical address of each WL is determined. By detecting the same region WL and the neighboring region WL corresponding to each same region WL in each memory region of the DRAM, and determining the region relationship between each memory region, the adjacent same region WL corresponding to each same region WL, and boundary memory region, the physical address of each WL in the DRAM can be accurately determined, realizing accurate testing of the physical address of the word line of the DRAM. This facilitates the corresponding testing of the DRAM based on the physical address of the WL, improving the accuracy and efficiency of DRAM testing.

[0137] It should be noted that the above examples are only for understanding this application and do not constitute a limitation on the word line physical address testing method of the DRAM of this application. Any simple modifications based on this technical concept are within the protection scope of this application.

[0138] This application also provides a word line physical address testing device for DRAM, the word line physical address testing device for DRAM comprising:

[0139] The first determining module is used to determine the same region WL and the neighboring region WL corresponding to the same region WL in each memory region of the DRAM based on each word line WL of the DRAM.

[0140] The second determining module is used to determine the inter-regional relationship between memory regions based on the neighboring regions WL corresponding to each same region WL.

[0141] The third determination module is used to determine the adjacent WL corresponding to each WL based on the WL of the same region in each memory region, and to determine the boundary memory region in each memory region.

[0142] The fourth determination module is used to determine the physical address of each WL based on the same region WL, neighboring regions WL, the relationship between regions, the adjacent same region WL corresponding to each same region WL, and the boundary memory region.

[0143] The DRAM word line physical address testing apparatus provided in this application employs the DRAM word line physical address testing method described in the above embodiments, and can solve the technical problem of how to accurately test the word line physical address of DRAM. Compared with the prior art, the beneficial effects of the DRAM word line physical address testing apparatus provided in this application are the same as those of the DRAM word line physical address testing method provided in the above embodiments, and other technical features in the DRAM word line physical address testing apparatus are the same as those disclosed in the methods of the above embodiments, and will not be repeated here.

[0144] This application provides a DRAM word line physical address testing device, which includes: at least one processor; and a memory communicatively connected to the at least one processor; wherein the memory stores instructions executable by the at least one processor, and the instructions are executed by the at least one processor to enable the at least one processor to perform the DRAM word line physical address testing method in the above embodiment 1.

[0145] The following is for reference. Figure 7 This document illustrates a schematic diagram of a word line physical address testing apparatus suitable for implementing DRAM in the embodiments of this application. The DRAM word line physical address testing apparatus in the embodiments of this application may include, but is not limited to, mobile terminals such as mobile phones, laptops, digital broadcast receivers, PDAs (Personal Digital Assistants), PADs (Portable Application Description), PMPs (Portable Media Players), in-vehicle terminals (e.g., in-vehicle navigation terminals), and fixed terminals such as digital TVs and desktop computers. Figure 7 The illustrated DRAM word line physical address testing device is merely an example and should not impose any limitations on the functionality and scope of use of the embodiments of this application.

[0146] like Figure 7As shown, the DRAM word line physical address testing device may include a processing device 1001 (e.g., a central processing unit, a graphics processing unit, etc.), which can perform various appropriate actions and processes according to a program stored in read-only memory (ROM) 1002 or a program loaded from storage device 1003 into random access memory (RAM) 1004. The RAM 1004 also stores various programs and data required for the operation of the DRAM word line physical address testing device. The processing device 1001, ROM 1002, and RAM 1004 are interconnected via a bus 1005. An input / output (I / O) interface 1006 is also connected to the bus. Typically, the following systems can be connected to I / O interface 1006: input devices 1007 including, for example, touchscreens, touchpads, keyboards, mice, image sensors, microphones, accelerometers, gyroscopes, etc.; output devices 1008 including, for example, liquid crystal displays (LCDs), speakers, vibrators, etc.; storage devices 1003 including, for example, magnetic tapes, hard disks, etc.; and communication devices 1009. Communication device 1009 allows the DRAM word line physical address test device to communicate wirelessly or wiredly with other devices to exchange data. Although the figure shows DRAM word line physical address test devices with various systems, it should be understood that it is not required to implement or have all the systems shown. More or fewer systems can be implemented or have alternatively.

[0147] Specifically, according to the embodiments disclosed in this application, the processes described above with reference to the flowcharts can be implemented as computer software programs. For example, embodiments disclosed in this application include a computer program product comprising a computer program carried on a computer-readable medium, the computer program containing program code for performing the methods shown in the flowcharts. In such embodiments, the computer program can be downloaded and installed from a network via a communication device, or installed from storage device 1003, or installed from ROM 1002. When the computer program is executed by processing device 1001, it performs the functions defined in the methods of the embodiments disclosed in this application.

[0148] The DRAM word line physical address testing apparatus provided in this application employs the DRAM word line physical address testing method described in the above embodiments, and can solve the technical problem of how to accurately test the word line physical address of DRAM. Compared with the prior art, the beneficial effects of the DRAM word line physical address testing apparatus provided in this application are the same as those of the DRAM word line physical address testing method provided in the above embodiments, and other technical features in this DRAM word line physical address testing apparatus are the same as those disclosed in the previous embodiment method, and will not be repeated here.

[0149] It should be understood that the various parts disclosed in this application can be implemented using hardware, software, firmware, or a combination thereof. In the description of the above embodiments, specific features, structures, materials, or characteristics can be combined in any suitable manner in one or more embodiments or examples.

[0150] The above description is merely a specific embodiment of this application, but the scope of protection of this application is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this application should be included within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.

[0151] This application provides a computer-readable storage medium having computer-readable program instructions (i.e., a computer program) stored thereon, the computer-readable program instructions being used to execute the DRAM word line physical address testing method in the above embodiments.

[0152] The computer-readable storage medium provided in this application may be, for example, a USB flash drive, but is not limited to, electrical, magnetic, optical, electromagnetic, infrared, or semiconductor systems, devices, or any combination thereof. More specific examples of computer-readable storage media may include, but are not limited to: electrical connections having one or more wires, portable computer disks, hard disks, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), optical fiber, portable compact disk read-only memory (CD-ROM), optical storage devices, magnetic storage devices, or any suitable combination thereof. In this embodiment, the computer-readable storage medium may be any tangible medium containing or storing a program that can be used by or in conjunction with an instruction execution system, system, or device. The program code contained on the computer-readable storage medium may be transmitted using any suitable medium, including but not limited to: wires, optical cables, RF (Radio Frequency), etc., or any suitable combination thereof.

[0153] The aforementioned computer-readable storage medium may be included in a word line physical address testing device for DRAM; or it may exist independently and not be assembled into a word line physical address testing device for DRAM.

[0154] The aforementioned computer-readable storage medium carries one or more programs. When the one or more programs are executed by the DRAM word line physical address testing device, the DRAM word line physical address testing device: based on each word line (WL) of the DRAM, determines the same region (WL) and the neighboring region (WL) corresponding to each same region (WL) in each memory region of the DRAM; based on the neighboring region (WL) corresponding to each same region (WL), determines the region interrelationship between each memory region; based on the same region (WL) in each memory region, determines the adjacent same region (WL) corresponding to each same region (WL), and determines the boundary memory region in each memory region; based on the same region (WL), neighboring region (WL), region interrelationship, adjacent same region (WL) corresponding to each same region (WL), and boundary memory region, determines the physical address of each WL.

[0155] Computer program code for performing the operations of this application can be written in one or more programming languages ​​or a combination thereof, including object-oriented programming languages ​​such as Java, Smalltalk, and C++, and conventional procedural programming languages ​​such as the "C" language or similar programming languages. The program code can be executed entirely on the user's computer, partially on the user's computer, as a standalone software package, partially on the user's computer and partially on a remote computer, or entirely on a remote computer or server. In cases involving remote computers, the remote computer can be connected to the user's computer via any type of network—including a Local Area Network (LAN) or a Wide Area Network (WAN)—or can be connected to an external computer (e.g., via the Internet using an Internet service provider).

[0156] The flowcharts and block diagrams in the accompanying drawings illustrate the architecture, functionality, and operation of possible implementations of systems, methods, and computer program products according to various embodiments of this application. In this regard, each block in a flowchart or block diagram may represent a module, segment, or portion of code containing one or more executable instructions for implementing a specified logical function. It should also be noted that in some alternative implementations, the functions indicated in the blocks may occur in a different order than those indicated in the drawings. For example, two consecutively indicated blocks may actually be executed substantially in parallel, and they may sometimes be executed in reverse order, depending on the functions involved. It should also be noted that each block in the block diagrams and / or flowcharts, and combinations of blocks in the block diagrams and / or flowcharts, can be implemented using a dedicated hardware-based system that performs the specified function or operation, or using a combination of dedicated hardware and computer instructions.

[0157] The modules described in the embodiments of this application can be implemented in software or hardware. The names of the modules do not necessarily limit the functionality of the unit itself.

[0158] The readable storage medium provided in this application is a computer-readable storage medium that stores computer-readable program instructions (i.e., a computer program) for executing the above-described DRAM word line physical address testing method, thereby solving the technical problem of how to accurately test the word line physical address of DRAM. Compared with the prior art, the beneficial effects of the computer-readable storage medium provided in this application are the same as those of the DRAM word line physical address testing method provided in the above embodiments, and will not be repeated here.

[0159] This application also provides a computer program product, including a computer program that, when executed by a processor, implements the steps of the DRAM word line physical address testing method described above.

[0160] The computer program product provided in this application solves the technical problem of how to accurately test the word line physical address of DRAM. Compared with the prior art, the beneficial effects of the computer program product provided in this application are the same as those of the DRAM word line physical address testing method provided in the above embodiments, and will not be repeated here.

[0161] The above description is only a part of the embodiments of this application and does not limit the patent scope of this application. All equivalent structural transformations made under the technical concept of this application and using the contents of the specification and drawings of this application, or direct / indirect applications in other related technical fields, are included in the patent protection scope of this application.

Claims

1. A method for testing the word line physical address of DRAM, characterized in that, The DRAM word line physical address testing method includes: Based on each word line WL of the DRAM, the same region WL and the neighboring region WL corresponding to the same region WL in each memory region of the DRAM are determined respectively. Based on the neighboring regions WL corresponding to each region WL, determine the inter-regional relationships between each memory region. Based on the same region WL in each memory region, determine the adjacent same region WL corresponding to each same region WL, and determine the boundary memory region in each memory region. Based on the same region WL, neighboring region WL, the relationship between regions, the adjacent same region WL corresponding to each same region WL and the boundary memory region, the physical address of each WL is determined. For each WL, the physical address of the WL includes the memory region to which the WL belongs, the WLs on both sides, the memory regions adjacent to the memory region to which the WL belongs, the relationship between the memory region to which the WL belongs and other memory regions, and the boundary memory region in DRAM. The step of determining the adjacent WL corresponding to each WL based on the same region WL in each memory region includes: Sequentially determine the second target memory region in each memory region, write the third data into each WL in the second target memory region, and reverse the data in the third WL in each WL. Perform continuous switching operations on the third WL, and when the number of switching operations of the third WL reaches a preset number, read the fourth read data of each WL in the target memory area; The WL corresponding to the failed data in the fourth read data is taken as the adjacent WL corresponding to the third WL; One of the adjacent WLs corresponding to the third WL is taken as the third WL, and the process of writing the third data into each WL in the second target memory area is returned, and the third WL in each WL is reversed, until each WL in the second target memory area is processed.

2. The DRAM word line physical address testing method as described in claim 1, characterized in that, The steps of determining the same region WL and the corresponding neighboring region WL in each memory region of the DRAM based on each word line WL of the DRAM include: In the DRAM, the first WL is determined, and the WLs other than the first WL are taken as the WLs to be processed. Sequentially determine the second WL in the WL to be processed, write the first data in the second WL, and write the second data in the first WL, wherein the first data and the second data are different; Within a preset time period following the precharge PRE instruction corresponding to the first WL, a read operation is performed on the second WL to obtain the first read data, wherein the preset time period is less than the row precharge time tRP corresponding to the DRAM; First data is written into the second WL and the first WL in sequence. Within a preset time after the PRE instruction corresponding to the first WL, a read operation is performed on the second WL to obtain the second read data. Then, the process of determining the second WL in the pending WL in sequence is returned until the pending WL is processed. Based on the first read data in the WL to be processed, determine the same region WL corresponding to the first WL, and based on the second read data in the WL to be processed, determine the neighboring region WL corresponding to the first WL.

3. The DRAM word line physical address testing method as described in claim 2, characterized in that, The steps of determining the same region WL corresponding to the first WL in the WL to be processed based on the first read data, and determining the neighboring region WL corresponding to the first WL in the WL to be processed based on the second read data, include: Based on the first data, the first failed data in the first read data is determined, and the first failed WL corresponding to the first failed data in the WL to be processed is taken as the same region WL corresponding to the first WL. Based on the first data, the second failed data in the second read data is determined, and the second failed WL corresponding to the second failed data in the WL to be processed is taken as the neighboring region WL corresponding to the first WL.

4. The DRAM word line physical address testing method as described in claim 2, characterized in that, After the step of determining the neighboring region WL corresponding to the first WL in the WL to be processed based on the second read data, the method further includes: If there is a first target memory region that determines one of the two adjacent memory regions to which the neighboring region WL to the first WL belongs, then delete the first WL and the same region WL corresponding to the first WL from the WL to be processed. A first WL is determined in the first target memory region, the first WL is deleted in the WL to be processed, and the process returns to perform the step of determining a second WL in the WL to be processed in turn.

5. The DRAM word line physical address testing method as described in claim 2, characterized in that, After the step of determining the neighboring region WL corresponding to the first WL in the WL to be processed based on the second read data, the method further includes: If there is a first target memory region that determines one of the two adjacent memory regions to which the neighboring region WL to the first WL belongs, then delete the first WL, the same region WL to which the first WL belongs, and the neighboring region WL from the WL to be processed. In the first target memory region, a first WL is determined, and in the WL to be processed, a second WL is determined sequentially. Then, the first data is written into the second WL and the first WL in sequence. Within a preset time period after the PRE instruction when writing the first data in the first WL, a read operation is performed on the second WL to obtain the third read data, and then the process of determining the second WL in the pending WL is returned to continue until the pending WL is processed. Based on the third read data in the WL to be processed, determine the neighboring region WL corresponding to the first WL, and determine the same region WL among the two adjacent memory regions corresponding to the memory region to which the first WL belongs, and return to execute the step of deleting the first WL, the same region WL corresponding to the first WL, and the neighboring region WL in the WL to be processed if there is a first target memory region that determines an adjacent memory region among the two adjacent memory regions to which the neighboring region WL corresponding to the first WL belongs.

6. The DRAM word line physical address testing method as described in claim 5, characterized in that, The step of determining the same region WL among two adjacent memory regions corresponding to the memory region to which the first WL belongs includes: Based on the first data, the third invalid data in the third read data is determined; The third failure data is divided into first same-region failure data and second same-region failure data; The WL corresponding to the first same-region failure data is taken as the same-region WL in one of the two adjacent memory regions to which the first WL belongs, and the WL corresponding to the second same-region failure data is taken as the same-region WL in the other memory region.

7. The DRAM word line physical address testing method according to any one of claims 1 to 6, characterized in that, The step of determining the boundary memory regions in each memory region includes: Perform switching operations on the WL in each memory region and obtain the power consumption data of each memory region during the switching operation; The memory region corresponding to the highest power consumption data is used as the boundary memory region.

8. A DRAM word line physical address testing device, characterized in that, The apparatus includes: a memory, a processor, and a computer program stored on the memory and executable on the processor, the computer program being configured to implement the steps of the word line physical address testing method for DRAM as claimed in any one of claims 1 to 7.

9. A storage medium, characterized in that, The storage medium is a computer-readable storage medium, and a computer program is stored on the storage medium. When the computer program is executed by a processor, it implements the steps of the DRAM word line physical address testing method as described in any one of claims 1 to 7.

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