Method for improving stress fragment of wafer
By employing a dual-layer CESL structure with tensile stress layer and compressive stress layer in semiconductor manufacturing, and controlling the film thickness ratio, the warping and breakage problems caused by wafer stress accumulation are solved, thereby improving product yield and production stability.
Patent Information
- Application Number
- CN202511200839.4
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-08-26
- Publication Date
- 2025-12-12
AI Technical Summary
In existing semiconductor manufacturing processes, contact etch stop layers with single tensile stress lead to wafer stress accumulation during subsequent thermal cycling processes, which can easily cause warpage and breakage, affecting product yield and production stability.
A dual-layer CESL structure combining a tensile stress layer and a compressive stress layer is adopted. By adjusting the thickness ratio of the two films, the net tensile stress is neutralized, the initial warpage value is reduced, and a lower stress substrate is provided for subsequent thermal cycling processes.
It significantly reduces the risk of wafer breakage, improves product yield and production stability, reduces the stress variation range throughout the process, and maintains the electrical performance of the device.
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Abstract
Description
TECHNICAL FIELD
[0001] The present application relates to the field of semiconductor technology, and in particular, to a method for improving wafer stress cracking. BACKGROUND
[0002] In the manufacturing process of semiconductor integrated circuits, there are usually front-end-of-line (FEOL) and back-end-of-line (BEOL) processes. The FEOL process mainly forms active devices such as transistors on a semiconductor substrate, including forming gate structures, sidewalls, source / drain regions, and metal silicides, etc. The BEOL process is to build a multi-layer metal interconnection structure on the wafer with formed devices to realize the electrical connection between different devices inside the chip.
[0003] In many semiconductor products, aluminum (Al) and its alloys are still widely used as metal interconnection materials in the BEOL process due to their cost-effectiveness and mature process. However, aluminum has a relatively high coefficient of thermal expansion. In the BEOL process, the wafer needs to undergo multiple thin film deposition, annealing and other heat treatment processes. The dramatic change in temperature causes significant thermal mismatch stress between the aluminum metal layer and the surrounding dielectric material. This stress will continue to accumulate in the multi-layer metal stack, causing the wafer to warp. When the accumulated stress exceeds the mechanical strength of the wafer, wafer cracking is easily triggered. Wafer cracking not only causes the complete scrap of the current wafer, resulting in huge economic losses, but also may contaminate the process equipment, affecting subsequent production, and causing serious threats to productivity and equipment.
[0004] In order to improve the performance of transistors, a contact etch stop layer (CESL) is usually deposited at the last stage of the FEOL process, i.e., after the formation of active devices. The CESL can use its own stress (tensile stress or compressive stress) to modulate the stress of the underlying transistor channel region, thereby improving the carrier mobility. In the prior art, silicon nitride (SiN) thin film with single tensile stress is often used as CESL to achieve specific performance goals.
[0005] However, this thin film with high tensile stress itself, although beneficial to device performance, also contributes to the overall stress state of the wafer as the initial stress layer. When entering the subsequent aluminum process BEOL process containing multiple thermal cycles, the initial tensile stress of this layer will be superimposed with the stress of each subsequently deposited thin film layer, which may cause the overall stress value and stress variation range in the BEOL process cycle to be too large, thereby increasing the risk of wafer cracking due to total stress accumulation.
[0006] Therefore, how to effectively regulate and reduce the initial stress of the wafer before entering the subsequent aluminum process without sacrificing the electrical performance of the device, and reduce the stress variation range in the subsequent process, has become a technical problem to be solved in the semiconductor manufacturing industry. SUMMARY
[0007] The technical problem to be solved by this invention is that in existing semiconductor manufacturing processes, especially in the back-end of aluminum processes, the use of a single tensile stress contact etch stop layer (CESL) results in high initial stress on the wafer. After undergoing multiple thermal cycling processes, the stress continues to accumulate, which can eventually lead to wafer warping or even breakage, thereby affecting product yield and production stability.
[0008] To achieve the above and other related objectives, the present invention provides a method for improving wafer stress breakage, comprising:
[0009] Step 1: On a semiconductor substrate with a device structure, a first contact etch stop layer is deposited, the first contact etch stop layer having tensile stress;
[0010] Step 2: Deposit a second contact etch stop layer on the first contact etch stop layer. The second contact etch stop layer has compressive stress.
[0011] Preferably, in step one, the first contact etch stop layer and / or in step two, the second contact etch stop layer is a silicon nitride layer.
[0012] Preferably, the ratio of the thickness of the first contact etch stop layer to the thickness of the second contact etch stop layer is in the range of 0.6 to 1.5.
[0013] Preferably, the ratio of the thickness of the first contact etch stop layer to the thickness of the second contact etch stop layer is 1.5.
[0014] Preferably, the thickness of the first contact etch stop layer is 300 angstroms, and the thickness of the second contact etch stop layer is 200 angstroms.
[0015] Preferably, prior to step one, the device structure includes a gate structure, a source region, and a drain region.
[0016] Preferably, the device structure further includes a sidewall formed on the sidewall of the gate structure.
[0017] Preferably, the device structure further includes a metal silicide layer formed on the upper surface of the source and drain regions.
[0018] Preferably, a metal silicide layer is also formed on the upper surface of the gate structure.
[0019] Preferably, after step two, the method further includes depositing an interlayer dielectric layer on the second contact etch stop layer.
[0020] Preferably, the interlayer dielectric layer comprises a silicon oxide layer formed using high-density plasma chemical vapor deposition.
[0021] Preferably, the interlayer dielectric layer comprises a silicon oxide layer formed using tetraethoxysilane as a precursor.
[0022] Preferably, the method further includes etching an interlayer dielectric layer, a second contact etch stop layer, and a first contact etch stop layer to form a contact hole, the contact hole exposing a portion of the device structure.
[0023] Preferably, the method further includes forming an aluminum metal interconnect layer on the interlayer dielectric layer and within the contact hole.
[0024] As described above, the method for improving wafer stress breakage according to the present invention has the following beneficial effects:
[0025] This invention employs a dual-layer CESL structure combining a tensile stress layer and a compressive stress layer. By stacking two thin films with opposite stresses, the net tensile stress of the CESL film can be effectively neutralized and reduced while maintaining a constant total thickness. This significantly reduces the initial warpage of the wafer before entering subsequent processing steps. This provides a lower-stress substrate for subsequent thermal cycling processes, reduces the overall stress variation, and ultimately fundamentally reduces the risk of wafer breakage due to stress accumulation from aluminum processes, thereby improving product yield. Attached Figure Description
[0026] Figure 1 The diagram shown is a flowchart illustrating a method for improving wafer stress breakage according to an embodiment of the present invention.
[0027] Figure 2 The diagram shows a cross-sectional view of a semiconductor substrate with a device structure formed in an embodiment of the present invention.
[0028] Figure 3 This is shown as an embodiment of the present invention. Figure 2 A schematic cross-section of the structure after the first contact etch stop layer has been deposited.
[0029] Figure 4 This is shown as an embodiment of the present invention. Figure 3 A schematic cross-section of the structure after the deposition of the second contact etch stop layer;
[0030] Figure 5 This is shown as an embodiment of the present invention. Figure 4 A schematic diagram of the cross-section after the deposition of the interlayer dielectric layer in the structure. Detailed Implementation
[0031] The following specific examples illustrate the implementation of the present invention. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention.
[0032] This invention provides a method for improving wafer stress breakage, applicable to semiconductor integrated circuit manufacturing processes, particularly those using aluminum as the back-end interconnect metal. By optimizing the structure of the contact etch stop layer (CESL) at the end of the front-end process, the accumulated stress throughout the entire back-end process is effectively reduced, thereby significantly reducing the risk of wafer breakage.
[0033] See Figure 1 The method includes:
[0034] Step 1: On the semiconductor substrate 101 where the device structure is formed (e.g., Figure 2 As shown), a first contact etch stop layer 107 is deposited, which has tensile stress, forming as shown. Figure 3 The structure shown;
[0035] Step 2: On the first contact etch stop layer 107, a second contact etch stop layer 108 is deposited. The second contact etch stop layer 108 has compressive stress, forming as shown in the figure. Figure 4 The structure shown.
[0036] By replacing the traditional single tensile stress CESL layer with a stacked structure of tensile and compressive stress layers, the net tensile stress of the CESL film can be effectively neutralized and reduced while maintaining the total thickness of the CESL. This significantly reduces the initial warpage of the wafer before entering the back-end aluminum processing, providing a flatter, lower-stress substrate for subsequent multi-stage thermal cycling processes. This effectively reduces the overall warpage caused by the stress accumulation of each film layer in the back-end processes, ultimately reducing the risk of wafer breakage due to excessive accumulated stress by approximately 20%, while ensuring that the final electrical performance of the product remains unaffected.
[0037] In a specific implementation, the semiconductor substrate 101 is typically a single-crystal silicon substrate. Before forming the device structure, the method further includes forming a shallow trench isolation (STI) structure 102 in the semiconductor substrate 101. The STI structure 102 is formed by etching trenches of a predetermined depth in the substrate, filling the trenches with a dielectric material (e.g., silicon oxide formed by high-density plasma chemical vapor deposition), and then planarizing the surface using a chemical mechanical polishing (CMP) process. The main function of the STI structure 102 is to define multiple electrically isolated active areas on the substrate surface. Subsequent device structures, such as transistors, are built upon these active areas surrounded and defined by the STI structures 102.
[0038] In some embodiments, prior to step one, the device structure includes a gate structure, a source region, and a drain region. These structures collectively constitute the most basic switching unit in a semiconductor chip, such as a metal-oxide-semiconductor field-effect transistor (MOSFET). The gate structure may include a dielectric layer 102 and a polysilicon gate 104 formed on the dielectric layer 102. The method of the present invention improves the stability of the entire wafer without affecting the structure of the device itself by controlling the thin film stress covering these devices.
[0039] In some embodiments, the device structure further includes a sidewall 105 formed on the sidewall of the polysilicon gate 104. The sidewall 105 structure plays a key role in defining the source / drain region implantation range, protecting the gate structure, and forming a lightly doped drain (LDD) structure. The double-layer CESL structure proposed in this invention can uniformly cover the complex device morphology including the sidewall 105.
[0040] In some embodiments, the device structure further includes a metal silicide layer 106 formed on the upper surfaces of the source and drain regions. Preferably, the metal silicide layer 106 is also formed on the upper surface of the polysilicon gate 104. The metal silicide layer 106, such as nickel-platinum silicide (NiPtSi), can significantly reduce the contact resistance and sheet resistance of the source, drain, and gate regions, and is a key process for improving device performance. The method of this invention is fully compatible with standard metal silicide processes.
[0041] In some embodiments, in step one, the first contact etch stop layer 107 and / or in step two, the second contact etch stop layer 108 is a silicon nitride layer. Silicon nitride is a material widely used in semiconductor manufacturing processes. Its film stress can be precisely controlled within a wide range by adjusting deposition process parameters (such as gas flow ratio, pressure, temperature, etc.), thereby stably preparing films with the required tensile or compressive stress, and exhibiting good process compatibility.
[0042] In a more specific implementation, the first contact etch stop layer 107 and the second contact etch stop layer 108 with different stresses can both be precisely formed by adjusting the parameters of the plasma-enhanced chemical vapor deposition (PECVD) process. PECVD is the industry standard technology for depositing silicon nitride thin films, and its film stress can be controlled by modulating the chemical reaction pathways and physical bombardment effects in the plasma.
[0043] For example, to obtain a first contact etch stop layer 107 with tensile stress, the PECVD process can be configured as a chemical reaction-driven deposition mode. This is typically achieved using a high-frequency radio frequency (HF-RF) plasma source. In HF plasma, the ion energy is low, resulting in a weak physical bombardment effect on the surface of the growing film. The formation of the film is primarily determined by the surface chemical reactions of the precursor gases (such as silane SiH4 and ammonia NH3). By employing a high ammonia / silane flow ratio and a suitable deposition temperature, silicon nitride films rich in NH bonds can be formed. This chemical bond structure naturally generates tensile stress upon film cooling.
[0044] Conversely, to form the second contact etch stop layer 108 with compressive stress, the PECVD process requires the introduction of a significant physical bombardment effect. The most efficient way to achieve this is to use a low-frequency radio frequency (LF-RF) plasma source, either superimposed or independently, during the deposition process. The low-frequency plasma can deplete ions (such as Ar) in the chamber. + or N2 + Accelerated to higher energies, these high-energy ions continuously bombard the surface of the growing thin film, producing an "atomic bombardment effect." This continuous physical impact forces atoms into the interstitial spaces of the film's lattice, thereby generating and accumulating compressive stress within the film. Simultaneously, by appropriately increasing the relative flow rate of silane, a silicon-rich silicon nitride layer can be formed, which itself tends to exhibit compressive stress. Precise control of the compressive stress value can be achieved through precise proportioning of high and low frequency power and regulation of gas flow rate.
[0045] In some embodiments, the ratio of the thickness of the first contact etch stop layer 107 to the thickness of the second contact etch stop layer 108 ranges from 0.6 to 1.5. This ratio range provides a wide process window, allowing for flexible adjustment of the thickness ratio of the two stress films according to the initial stress state and device performance requirements of a specific product, in order to achieve the best stress compensation effect.
[0046] In one specific embodiment, the thickness ratio of the first contact etch stop layer 107 to the second contact etch stop layer 108 is 1.5. For example, the thickness of the first contact etch stop layer 107 can be 300 angstroms, and the thickness of the second contact etch stop layer 108 can be 200 angstroms. By adjusting the thickness ratio of the two thin films, stress compensation can be achieved while ensuring that the total thickness of the CESL remains consistent with the original single-layer CESL process, for example, a total thickness of 500 angstroms. This avoids introducing new process variables due to changes in the total thickness, simplifies process integration, and ensures the stability of the process window for subsequent steps such as contact hole etching.
[0047] In some embodiments, after step two, the method further includes: depositing an interlayer dielectric layer 109 on the second contact etch stop layer 108 to form such a layer as shown in the figure. Figure 5 The structure shown.
[0048] In some embodiments, the interlayer dielectric layer 109 includes a silicon oxide layer formed using high-density plasma chemical vapor deposition (HDP-CVD). The silicon oxide layer formed by HDP-CVD has good density and strong step coverage, making it suitable for filling complex morphologies between device structures.
[0049] In some embodiments, the interlayer dielectric layer 109 further includes a silicon oxide layer formed using tetraethoxysilane (TEOS) as a precursor. TEOS-derived silicon oxide layers typically have good planarization characteristics and can be used in conjunction with HDP silicon oxide layers to obtain a dielectric layer with better global flatness, laying a good foundation for subsequent metal interconnect wiring.
[0050] In some embodiments, the method further includes etching an interlayer dielectric layer 109, a second contact etch stop layer 108, and a first contact etch stop layer 107 to form a contact hole that exposes a portion of the device structure. The purpose of this step is to establish a pathway for subsequent metal interconnects and electrical connections to the underlying device. The dual-layer CESL design here serves as an etch stop to precisely control the etching depth and prevent over-etching damage to the underlying metal silicide layer 106 or the active region.
[0051] In some embodiments, the method further includes forming an aluminum interconnect layer on the interlayer dielectric layer 109 and within the contact holes. The final formed aluminum interconnect layer is electrically connected to the device through the contact holes. Since the entire preceding process has effectively reduced the overall stress of the wafer, the stress accumulation during aluminum layer deposition and subsequent heat treatment is controlled within a safe range, thereby fundamentally solving the wafer breakage problem caused by aluminum process stress and significantly improving product yield and production stability.
[0052] It should be noted that the illustrations provided in this embodiment are only schematic representations of the basic concept of the present invention. Therefore, the drawings only show the components related to the present invention and are not drawn according to the actual number, shape and size of the components in the actual implementation. In the actual implementation, the form, quantity and proportion of each component can be arbitrarily changed, and the layout of the components may also be more complex.
[0053] The above embodiments are merely illustrative of the principles and effects of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by those skilled in the art without departing from the spirit and technical concept disclosed in the present invention should still be covered by the claims of the present invention.
Claims
1. A method for improving wafer stress breakage, characterized in that, At least including: Step 1: On a semiconductor substrate with a device structure, a first contact etch stop layer is deposited, wherein the first contact etch stop layer has tensile stress; Step 2: Deposit a second contact etch stop layer on the first contact etch stop layer, the second contact etch stop layer having compressive stress.
2. The method for improving wafer stress breakage according to claim 1, characterized in that: In step one, the first contact etch stop layer is a silicon nitride layer, and / or in step two, the second contact etch stop layer is a silicon nitride layer.
3. The method for improving wafer stress breakage according to claim 1 or 2, characterized in that: The ratio of the thickness of the first contact etch stop layer to the thickness of the second contact etch stop layer ranges from 0.6 to 1.
5.
4. The method for improving wafer stress breakage according to claim 1, characterized in that: The ratio of the thickness of the first contact etch stop layer to the thickness of the second contact etch stop layer is 1.
5.
5. The method for improving wafer stress breakage according to claim 4, characterized in that: The thickness of the first contact etch stop layer is 300 angstroms, and the thickness of the second contact etch stop layer is 200 angstroms.
6. The method for improving wafer stress breakage according to claim 1, characterized in that: Prior to step one, the device structure includes a gate structure, a source region, and a drain region.
7. The method for improving wafer stress breakage according to claim 6, characterized in that: The device structure also includes a sidewall formed on the sidewall of the gate structure.
8. The method for improving wafer stress breakage according to claim 7, characterized in that: The device structure also includes a metal silicide layer formed on the upper surface of the source region and the drain region.
9. The method for improving wafer stress breakage according to claim 8, characterized in that: The metal silicide layer is also formed on the upper surface of the gate structure.
10. The method for improving wafer stress breakage according to claim 1, characterized in that: After step two, the method further includes depositing an interlayer dielectric layer on the second contact etch stop layer.
11. The method for improving wafer stress breakage according to claim 10, characterized in that: The interlayer dielectric layer includes a silicon oxide layer formed using high-density plasma chemical vapor deposition.
12. The method for improving wafer stress breakage according to claim 10 or 11, characterized in that: The interlayer dielectric layer includes a silicon oxide layer formed using tetraethoxysilane as a precursor.
13. The method for improving wafer stress breakage according to claim 10, characterized in that: The method further includes etching the interlayer dielectric layer, the second contact etch stop layer and the first contact etch stop layer to form a contact hole, the contact hole exposing a portion of the device structure.
14. The method for improving wafer stress breakage according to claim 13, characterized in that: The method further includes forming an aluminum metal interconnect layer on the interlayer dielectric layer and within the contact hole.