Semiconductor package and manufacturing method thereof

Abstract

A semiconductor package includes: a substrate; a semiconductor die mounted on the substrate; an antenna block mounted on the substrate and on a first side of the semiconductor die, where the antenna block has a height greater than a height of the semiconductor die; an interconnect structure mounted on the substrate and on a second side of the semiconductor die, where the first side is different from the second side; and an encapsulant layer formed on the substrate and configured to encapsulate the semiconductor die but expose the antenna block and the interconnect structure.

Description

TECHNICAL FIELD

[0001] The present application relates generally to semiconductor devices, and more particularly to semiconductor packages and methods of manufacturing the same. BACKGROUND

[0002] The semiconductor industry has been facing complex integration challenges as consumers want their electronic devices to be smaller in size, faster in speed, and higher in performance, and pack more and more functionalities into a single device. One solution is Antenna-in-Package (AiP). AiP is a functional electronic system or subsystem that integrates a semiconductor system and an antenna into one package. However, the manufacturing efficiency of conventional AiP structures can be unsatisfactory.

[0003] The present application provides a new AiP structure with improved manufacturing efficiency. SUMMARY

[0004] It is an object of the present application to provide an AiP semiconductor package with improved manufacturing efficiency.

[0005] According to an aspect of the present application, a semiconductor package is provided. The semiconductor package includes a substrate, a semiconductor die mounted on the substrate, an antenna block mounted on the substrate and on a first side of the semiconductor die, the antenna block having a height greater than a height of the semiconductor die, an interconnect structure mounted on the substrate and on a second side of the semiconductor die, wherein the first side is different from the second side, and an encapsulant layer formed on the substrate and configured to encapsulate the semiconductor die but expose the antenna block and the interconnect structure.

[0006] According to another aspect of the present application, a method for forming a semiconductor package is provided. The method includes providing a substrate, mounting a semiconductor die, an antenna block, and an interconnect structure on the substrate, wherein the antenna block and the interconnect structure are located on a first side and a second side of the semiconductor die, respectively, and the antenna block has a height greater than a height of the semiconductor die, and forming an encapsulant layer on the substrate to encapsulate the semiconductor die but expose the antenna block and the interconnect structure.

[0007] It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the application, as claimed. Furthermore, the accompanying drawings illustrate one embodiment of the application and together with the description, serve to explain the principles of the application. BRIEF DESCRIPTION OF DRAWINGS

[0008] The drawings referred to in this disclosure constitute part of the specification. Features shown in the drawings are only illustrative of some embodiments of the present application and are not all embodiments of the present application, unless the detailed description explicitly states otherwise, and the reader of the specification should not infer the opposite.

[0009] Figure 1A A cross-sectional view of a semiconductor package is shown, according to one embodiment of the present application.

[0010] Figure 1B A cross-sectional view of a semiconductor package is shown, according to one embodiment of the present application. Figure 1A A top view of a semiconductor package is shown, according to one embodiment of the present application, without the encapsulant layer.

[0011] Figures 2A to 2G A cross-sectional view of steps for forming a semiconductor package is shown, according to one embodiment of the present application.

[0012] Figure 2H and 2I A cross-sectional view of a compression step is shown, according to one embodiment of the present application.

[0013] Figures 3A to 3C A cross-sectional view of steps for forming a semiconductor package is shown, according to another embodiment of the present application.

[0014] Figure 3D A cross-sectional view of a semiconductor package is shown, according to one embodiment of the present application. Figures 3A to 3C A cross-sectional view of a semiconductor package formed by the steps shown in FIG. 6 is shown, according to one embodiment of the present application.

[0015] Throughout the drawings, the same drawing reference numerals will be used to depict the same or similar components. DETAILED DESCRIPTION

[0016] The following detailed description of the exemplary embodiments of the present application refers to the accompanying drawings that form a part of this description. The drawings show, among other things, specific exemplary embodiments of the present application. These embodiments, presented in sufficient detail to enable one skilled in the art to make and use the application, are not meant to be exhaustive or limiting as to the scope of the application. Other embodiments of the present application can be utilized and logical, mechanical, and electrical changes can be made without departing from the spirit or scope of the present application. The reader should therefore not place undue reliance on the detailed description of the exemplary embodiments contained herein. Rather, the reader should understand that the detailed description is merely illustrative of the present application and that changes can be made to the embodiments described without departing from the spirit or scope of the present application as defined by the appended claims.

[0017] In this application, the use of the singular includes the plural, unless specifically stated otherwise. In this application, the use of "or" means "and / or" unless stated otherwise. Furthermore, the use of the term "including", as well as other forms such as "include" and "includes", is not limiting. Also, terms such as "element" or "component" encompass both elements and components comprising one unit and elements and components that comprise more than one subunit unless specifically stated otherwise. Further, the section headings used herein are for organizational purposes only and are not meant to be used to limit the scope of the described subject matter.

[0018] As used herein, the spatially relative terms, such as "under", "below", "lower", "on", "above", "upper", "side", "right", "left", "vertical", "horizontal", "top", "bottom", and the like, can be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientations depicted in the figures. The devices can be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly. It will be understood that, when an element is referred to as being "connected to" or "coupled to" another element, it can be directly connected or coupled to the other element or intervening elements can be present.

[0019] In a conventional antenna-in-package (AiP) structure, a cavity substrate can be used to implement an antenna block. For such conventional AiP structure, a 3D stencil is typically needed to print solder on the cavity substrate due to the height difference between the antenna block and the substrate. At the intersection between the antenna block and the substrate, the 3D stencil can include a slope, and the area under the slope of the substrate can not be able to form solder. It can be seen that the stencil and printing process for the conventional AiP structure can be complex and space inefficient. To this end, a new AiP structure with improved manufacturing efficiency is proposed in this application.

[0020] Figure 1A and 1B A semiconductor package 100 according to one embodiment of the present application is shown. Figure 1A is a cross-sectional view of the semiconductor package 100 along the cross-sectional line AA' shown in Figure 1B is a cross-sectional view of the semiconductor package 100 along the cross-sectional line AA' shown in Figure 1B is a top view of the semiconductor package 100.

[0021] As Figure 1AAs shown, the semiconductor package 100 includes a substrate 110 and various elements mounted on the substrate 110, such as a semiconductor die 120, an antenna block 130, and an interconnect structure 140. The antenna block 130 and the interconnect structure 140 are mounted on two different sides of the semiconductor die 120. Further, a sealant layer 150 is formed on the substrate 110 to seal the semiconductor die 120 but at least partially exposes the antenna block 130 and the interconnect structure 140. In some embodiments, more than one antenna block may be mounted on the substrate 110, such as... Figure 1B As shown.

[0022] In some embodiments, such as Figure 1A and 1B As shown, substrate 110 can be divided into three regions 101, 102, and 103. In region 101, at least one (e.g., three) antenna blocks 130a-130c are mounted. In region 102, semiconductor die 120 is preferably mounted at the center of region 102. In some embodiments, individual electronic components 160 may also be positioned adjacent to semiconductor die 120 in region 102. For example, electronic components 160 may surround semiconductor die 120, or may be positioned on one or both sides of semiconductor die 120. In region 103, at least one interconnect structure 140 is mounted to provide electrical connections from package 100 to other electronic components. Preferably, regions 101 and 103 are located on opposite sides of region 102. That is, antenna blocks 130a-130c and interconnect structure 140 are located on opposite sides of semiconductor die 120. In some other embodiments, the layout of antenna blocks, semiconductor die, and interconnect structure may vary as needed. It is understood that the division between regions is for illustrative purposes only. Different regions may or may not have boundary lines. The following describes exemplary forms and materials of the electronic components mentioned above.

[0023] The substrate 110 can be a multilayer structure, and the multilayer structure can include multiple insulating or passivation layers and multiple conductive layers formed above or between the insulating layers. The substrate 110 can include one or more pre-impregnated polytetrafluoroethylene, FR-4, FR-1, CEM-1, or CEM-3 laminated layers with phenolic cotton paper, epoxy, resin, woven glass, ground glass, polyester, and other reinforcing fibers or fabrics. The insulating layers can include one or more layers of silicon dioxide (Si02), silicon nitride (Si3N4), silicon oxynitride (SiON), tantalum pentoxide (Ta205), aluminum oxide (AI2O3), or other materials with similar insulating and structural properties. The substrate 110 can also be a multilayer flexible laminate, ceramic, copper-clad laminate, glass, or semiconductor wafer that includes an active surface containing one or more transistors, diodes, and other circuit elements to implement analog or digital circuits. The substrate 110 can include one or more conductive layers or redistribution layers (RDL) formed using sputtering, electrolytic plating, electroless plating, or other suitable deposition processes.

[0024] The semiconductor die 120 is mounted on the substrate 110 via, for example, solder bumps 121. In some embodiments, the semiconductor die 120 can include one or more digital chips, analog chips, or mixed-signal chips, such as an application-specific integrated circuit (“ASIC”) chip, a sensor chip, a wireless and radio frequency (RF) chip, a memory chip, a logic chip, or a voltage regulator chip. In some embodiments, the semiconductor die 120 can include an integrated circuit chip for wireless communication and / or signal processing that can require an antenna for transmitting and receiving wireless signals. In some embodiments, the semiconductor die 120 can also include output and / or input circuitry for an antenna structure for wireless communication.

[0025] Antenna blocks 130a-130c are mounted on one side of semiconductor die 120 on substrate 110 via, for example, solder bumps 131. Antenna blocks 130a-130c are used to transmit and receive electromagnetic signals from the external environment. The height of antenna blocks 130a-130c can be greater than the height of semiconductor die 120. In some embodiments, each antenna block can have an antenna body 132 made of insulating or passive material in which an antenna conductive pattern 133 can be formed for antenna functionality. Antenna conductive pattern 133 can be one or more layers of Al, Cu, Sn, Ni, Au, Ag, Ti, W, or other suitable conductive material. Antenna conductive pattern 133 can be formed by sputtering, electrolytic plating, electroless plating, or other suitable deposition process. It can be appreciated that antenna blocks 130a-130c can be pre-formed into any desired discrete antenna structure using any suitable technique. Antenna blocks 130a-130c can have the same or various configurations, such as the same or various frequencies. Preferably, the height difference between antenna blocks 130a-130c can be 15-20% of the height of the shortest antenna block. Preferably, the respective top surfaces of antenna blocks 130a-130c can be flush with each other. In some other embodiments, as explained below, a high dielectric molding block can be formed on each of antenna blocks 130a-130c. The high dielectric molding block can be preferably made of epoxy mold compound. The high dielectric molding block can have similar material as encapsulant layer 150. The high dielectric molding block can have a trapezoidal shape, a semi-spherical shape, a semi-elliptical shape, or a lens shape cross-section. The high dielectric molding block can improve the transmission and reception rate or gain of the respective antenna block. Preferably, the dielectric constant of the high dielectric molding block is 15 to 25.

[0026] Interconnect structures 140 are mounted on the other side of semiconductor die 120 compared to antenna blocks 130a-130c. That is, interconnect structures 140 and antenna blocks 130a-130c can be located on adjacent or opposite sides of semiconductor die 120. Interconnect structures 140 can be used to provide interconnects from substrate 110 to other electronic components, such as to provide board level attachment. In some embodiments, interconnect structures 140 can be pre-solder, e-bar, Cu pillar, board-to-board connector, signal I / O gate with flexible cable, etc. In some embodiments, interconnect structures 140 can be formed in the same stencil printing process as solder bumps 121, 131. It can be appreciated that various interconnect structures 140 in various forms can be mounted on the same substrate 110.

[0027] A sealant layer 150 is further formed on the substrate 120 for sealing the semiconductor die 120 but at least partially exposing the antenna blocks 130a-130c and the interconnect structure 140. The sealant layer 150 can be formed with a top surface 151 and a side surface 152 extending between the top surface 151 and the interconnect structure 140. In some embodiments, the top surface 151 can be flush with the top surfaces of the antenna blocks 130a-130c, such that the top surfaces of the antenna blocks 130a-130c can be exposed for signal transmission with the external environment. In some embodiments, the side surface 152 can be inclined, such that the sealant layer 152 can be conveniently removed from a mold. Preferably, the sealant layer 150 is formed using a film assisted molding process.

[0028] The electronic elements 160 can be any discrete active or passive electronic elements, such as resistors, capacitors, inductors, and power metal oxide semiconductor field effect transistors (MOSFETs).

[0029] Figures 2A to 2G A cross-sectional view of the steps for forming the semiconductor package 200 according to one embodiment of the present application is shown along the cross-sectional line AA' shown in Figure 1B . Figure 2H and 2I A cross-sectional view of the compression step is shown along the cross-sectional line BB' shown in Figure 1B .

[0030] Referring to Figure 2A , a substrate 210 is provided. Subsequently, electrical connection structures, such as solder bumps, can be formed on the substrate 210. Referring to Figure 2B and 2C , in a screen-printing process, a stencil 211 can be placed on the substrate 210, and a conductive bump material can be printed at the openings of the stencil 211, thereby forming a patterned solder layer 212. The material of the patterned solder layer 212 can be Al, Sn, Ni, Au, Ag, Pb, Bi, Cu, solder, and combinations thereof, and optionally a flux solution. Preferably, the patterned solder layer 212 can include a plurality of solder bumps 213. In contrast to conventional AiP structures in which the antennas are integrated in the cavity substrate, in embodiments of the present application, the antenna blocks are discrete antenna blocks. Thus, the antenna blocks can be mounted on the substrate 210 in a similar manner as other electronic components, such as via solder bumps. The solder bumps for mounting the antenna blocks are in the same plane as the solder bumps for mounting other electronic components. Thus, only a 2D stencil is required, instead of a 3D stencil. In contrast to conventional AiP structures, in embodiments of the present application, the complexity of the stencil 211 is reduced, and the efficiency of the screen-printing process can be improved.

[0031] Referring to Figure 2D The semiconductor die 220, the antenna block 230, and the electronic components 260 can be attached on the substrate 210 via a portion 212-1 of the patterned solder layer. With a reflow process, the portion 212-1 of the patterned solder layer can secure the semiconductor die 220, the antenna block 230, and the electronic components 260 onto the substrate 210, and the remaining portion 212-2 of the patterned solder layer can also be transformed into the interconnect structure 240. The interconnect structure 240 can be in the form of solder bumps. In some other embodiments, additional steps can be used to install other interconnect structures 240, such as board-to-board connectors, Cu pillars, etc. In some embodiments, other processes such as evaporation, electrolytic plating, electroless plating, ball drop, etc. can be used to form the interconnect structure 240.

[0032] After the steps shown above, the semiconductor die 220, the antenna block 230, and the interconnect structure 240 are installed on the substrate 210. Subsequently, a sealant layer can be formed, as explained below.

[0033] Referring to Figure 2E A bottom mold 271 and a top mold 272 are provided, which are mated to each other. The bottom mold 271 can provide support for the substrate 210 thereon. The top mold 272 can have an inner surface that is generally consistent with the shape of the sealant layer to be formed on the substrate 210. Specifically, the top mold 272 can include a first mold portion 272a and a second mold portion 272b, which has a lower molding surface than the first mold portion 272a. As can be seen, the shape of the top mold 272 can be configured such that the interconnect structure 240 and the antenna block 230 are at least partially exposed from the sealant layer 250 to be formed, while the semiconductor die 220 is completely sealed. It can be appreciated that in other embodiments, the shape of the mold can be adjusted, and thus, the sealant layer formed within the mold can change, and a laser ablation process can be performed after the molding process to achieve the desired shape of the sealant layer to be formed.

[0034] In some embodiments, a mold release film 280, such as a polytetrafluoroethylene (PTFE) film, is placed underneath the top mold 272 for performing a film assisted molding process. The film assisted molding process helps the sealant layer to be more easily demolded from the top mold 272, especially in cases where the shape of the sealant layer is irregular. It can be appreciated that the mold release film 280 can use other suitable materials.

[0035] After providing the top mold 271 and the bottom mold 272, the substrate 210 can be disposed therebetween. Specifically, the first mold portion 272a is disposed over the antenna blocks 230 and the semiconductor die 220, while the second mold portion 272b is disposed over the interconnect structure 240.

[0036] In some embodiments, a sealant layer on the top surface of the antenna blocks 230 is not needed, in which case the top mold 272 and the film 280 can be configured to be in close contact with the top surface of the antenna blocks 230 such that no gap is formed therebetween. Thus, in the subsequent molding process, the sealant material will not leak to the top surface of the antenna blocks 230. In some embodiments, in order to achieve the close contact between the top mold 272 and the antenna blocks 230, the top mold 272 and the bottom mold 271 can be clamped with respect to each other. In this case, the release film 280 placed underneath the top mold 272 will slightly offload the clamping force, thereby protecting the top surface of the antenna blocks 230 during the clamping step.

[0037] Referring to Figure 2H and Figure 2I In some embodiments, the height of the top surface of each antenna block on the substrate can be different. For example, referring to Figure 2H , the height of the top surface of the antenna blocks 230a-230c on the substrate 210 can be slightly different, differing by a distance D1. This height difference can be caused by the height difference of the antenna blocks themselves or the height difference of the solder bumps 231a-231c. In order to align the top surfaces of the antenna blocks 230a-230c such that the top surfaces of all the antenna blocks can be exposed together to the sealant layer to be formed, in some embodiments of the present application, a clamping step can be introduced before the molding process.

[0038] Specifically, the top mold 272 and the bottom mold 271 can be clamped with respect to each other, thus the antenna blocks 230a-230c underneath the top mold 272 are clamped on the substrate 210 and the antenna blocks 230a-230c are aligned with each other at the same level. In this case, the release film 280 placed underneath the top mold 272 will slightly offload the clamping force, thereby protecting the top surfaces of the antenna blocks 230a-230c during the clamping step.

[0039] Referring to Figure 2E and 2F After the clamping step, a molding process is performed in which a sealant material can be injected between the bottom mold 271 and the top mold 272 to form the sealant layer 250. After the molding process, the bottom mold 271 and the top mold 272 can be removed from the substrate 220 to obtain the semiconductor package 200. As Figure 2FAs shown in FIG. 2, in semiconductor package 200, the top surface of antenna block 230 is exposed, interconnect structure 240 is partially exposed, and semiconductor die 220 is completely encapsulated by encapsulant layer 250.

[0040] Referring to Figure 2G In some embodiments, a high dielectric molding block 290 can be disposed on antenna block 230. High dielectric molding block 290 can increase the slant angle transmission and reception area of the underlying antenna block 230. The transmission and reception rate or gain of antenna block 230 can be improved. In some embodiments, the formation of high dielectric molding block 290 can be after the formation of encapsulant layer 250. In some other embodiments, as explained below, the high dielectric molding block and the encapsulant layer can be formed in a single molding process such that the high dielectric molding block is integrated with the encapsulant layer.

[0041] In some embodiments, multiple antenna blocks are formed in the same semiconductor package. Embodiments of the present application provide a method for forming semiconductor package 300 that includes a pressing step and a lifting step prior to the molding process. Figures 3A to 3C A cross-sectional view of the steps for forming semiconductor package 300 is shown, where the perspective is along Figure 1B the cross-sectional line AA' shown in FIG. 2. Figure 3D A cross-sectional view of semiconductor package 300 is shown from the perspective along Figure 1B the cross-sectional line BB' shown in FIG. 2.

[0042] Referring to Figure 3A In contrast to Figure 2E , top mold 372 also includes a cavity 373 in first mold portion 372a at a location above antenna block 330. The shape of second mold portion 372b can remain the same as second mold portion 272b shown in FIG. 2. Cavity 373 reserves space for forming high dielectric molding block 390 in a subsequent molding process. Figure 2E

[0043] Still referring to Figure 3A , similar to previous embodiments, a pressing step can be performed where top mold 372 and bottom mold 371 can be pressed relative to each other such that the height of antenna block 330 can be aligned with each other. In some embodiments, release film 380 is placed underneath top mold 372 and as a result, the top surface of antenna block 330 is protected by release film 380 during the pressing step.

[0044] Referring to Figure 3B ​A lifting step is performed to create a gap of height D2 between the antenna block 330 and the closest surface of the top mold 372 (or release film 380, if applicable). By creating this gap, molding material can flow into the cavity 373 through the gap in a subsequent molding process, and thus, the sealant layer 350 and the high-dielectric molding block 390 can be formed together in a single molding step. In some embodiments, the height D2 may be relatively small so that the molding material is not unnecessarily thick enough to affect the transmission function of the antenna block 330. Exemplary materials used to form the high-dielectric molding block 390 and the sealant layer 350 include epoxy molding compounds, etc.

[0045] refer to Figure 3C In the semiconductor package 300, a high-dielectric molding block 390 is connected to a sealant layer 350, such that the high-dielectric molding block 390 and the sealant layer 350 are both formed in a single molding process. Figure 3D The semiconductor package 300 is shown from along Figure 1B The cross-sectional view is shown from the perspective of section line BB'. It is understood that the lamination step helps to ensure that the corresponding top surfaces of antenna blocks 330a-330c have the same height, and the lifting step helps to allow the high-dielectric molding block 390 and the sealant layer 350 to be formed together in a single process. Therefore, compared to conventional AiP structures and manufacturing processes, the semiconductor package and method for forming the package according to embodiments of this application improve space efficiency, reduce manufacturing complexity, and increase manufacturing efficiency.

[0046] This document includes numerous illustrative figures illustrating the various parts of a semiconductor package and their formation methods. For clarity, these figures do not show all aspects of each example component. Any example component and / or method provided herein may share any or all features with any or all other components and / or methods provided herein.

[0047] Various embodiments have been described herein with reference to the accompanying drawings. However, it will be apparent that various modifications and changes can be made thereto, and other embodiments can be implemented without departing from the broader scope of the invention as set forth in the appended claims. Furthermore, other embodiments will be apparent to those skilled in the art upon consideration of the practice of one or more embodiments of the invention disclosed herein. Therefore, the embodiments in this application and herein are intended to be considered exemplary only, and the true scope and spirit of the invention are indicated by the list of exemplary claims appended.

Claims

1. A semiconductor package, characterized by, The semiconductor package includes: a substrate; a semiconductor die mounted on the substrate; an antenna block mounted on the substrate and on a first side of the semiconductor die, the antenna block having a height greater than a height of the semiconductor die; an interconnect structure mounted on the substrate and on a second side of the semiconductor die, wherein the first side is different from the second side; and a sealant layer formed on the substrate and configured to seal the semiconductor die but expose the antenna block and the interconnect structure.

2. The semiconductor package of claim 1, wherein, The semiconductor package further includes a high dielectric molding block formed on the antenna block.

3. The semiconductor package of claim 2, wherein, The high dielectric molding block is formed with the sealant layer in a single molding process.

4. The semiconductor package of claim 1, wherein, The sealant layer includes a top surface and a sloped side surface extending between the top surface and the interconnect structure.

5. The semiconductor package of claim 4, wherein, The top surface of the sealant layer is flush with a top surface of the antenna block.

6. The semiconductor package of claim 1, wherein, The semiconductor package further includes: one or more additional antenna blocks mounted on the substrate and on the first side of the semiconductor die, wherein the antenna block and the one or more additional antenna blocks have respective top surfaces that are flush with each other.

7. The semiconductor package of claim 1, wherein, At least a portion of the semiconductor die, the interconnect structure, and the antenna block are mounted on the substrate using a stencil printing process via solder bumps.

8. The semiconductor package of claim 1, wherein, The sealant layer is formed using a film assisted molding process.

9. The semiconductor package of claim 1, wherein, The first side and the second side are opposite each other with respect to the semiconductor die.

10. A method for forming a semiconductor package, comprising: The method includes: providing a substrate; mounting a semiconductor die, an antenna block, and an interconnect structure on the substrate, wherein the antenna block and the interconnect structure are on first and second sides of the semiconductor die, respectively, and the antenna block has a height greater than a height of the semiconductor die; and forming a sealant layer on the substrate to seal the semiconductor die but expose the antenna block and the interconnect structure.

11. The method of claim 10, wherein, Mounting a semiconductor die, an antenna block, and an interconnect structure includes: screen printing a solder material on the substrate to form a patterned solder layer; attaching the semiconductor die and the antenna block to the substrate via a portion of the patterned solder layer; and reflowing the patterned solder layer to secure the semiconductor die and the antenna block to the substrate via the portion of the patterned solder layer and to transform a remaining portion of the patterned solder layer into the interconnect structure.

12. The method of claim 10, wherein, Forming a sealant layer includes: providing a top mold and a bottom mold, wherein the top mold includes a first mold portion and a second mold portion having a lower molding surface than the first mold portion; positioning the substrate between the bottom mold and the top mold, wherein the first mold portion is over the antenna block and the semiconductor die, and the second mold portion is over the interconnect structure; clamping the top mold and the bottom mold relative to each other; molding between the top mold and the bottom mold to form the sealant layer; and removing the top mold and the bottom mold from the substrate.

13. The method of claim 10, wherein, The method further includes: forming a high dielectric molding block on the antenna block.

14. The method of claim 13, wherein, forming the encapsulant layer and forming the high dielectric molding block are performed in a single molding process.

15. The method of claim 10, wherein, forming the encapsulant layer includes forming the encapsulant layer using a film assisted molding process.

16. The method of claim 10, wherein, The method further includes: mounting one or more additional antenna blocks on the substrate and on the first side of the semiconductor die; and bonding the antenna block and the one or more additional antenna blocks on the substrate such that top surfaces of the antenna block and the one or more additional antenna blocks are aligned with each other at a same level.

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