Supercomputing chip heterogeneous packaging structure and packaging method based on 2.5 D packaging

Abstract

The invention discloses a super-computing chip heterogeneous packaging structure and packaging method based on 2.5 D packaging, the super-computing chip heterogeneous packaging structure comprises a substrate and a silicon intermediate layer, the silicon intermediate layer comprises an upper RDL wiring layer I, a lower RDL wiring layer I and an intermediate layer located between the upper RDL wiring layer I and the lower RDL wiring layer I, an ASIC chip is welded on the upper surface of the silicon intermediate layer, and the lower surface of the silicon intermediate layer is welded on the lower surface of the silicon intermediate layer. The ASIC chip is in contact with the upper RDL wiring layer I, a chip I and a chip II are welded on the lower surface of the silicon intermediary layer, the chip I and the chip II are an EIC chip and a PIC chip respectively, and the upper surfaces of the chip I and the chip II are in contact with the lower RDL wiring layer I; a first optical device and a second optical device are welded between the upper surface of the substrate and the lower surface of the silicon interposer, and the first chip and the second chip are embedded in the space between the first optical device and the second optical device. Plastic package materials are arranged between the first optical device and the first chip, between the first chip and the second chip and between the second chip and the second optical device in a plastic package mode.

Description

TECHNICAL FIELD

[0001] The application relates to an ultra-computing chip packaging structure and a packaging method, in particular to an ultra-computing chip heterogeneous packaging structure and a packaging method based on 2.5D packaging, and belongs to the technical field of chip packaging. BACKGROUND

[0002] An ultra-computing center is a facility focusing on high-performance computing (HPC), and the core is to solve large-scale, high-precision and high-complexity scientific or engineering problems. The computing power is the core index. Through a large-scale computing cluster (composed of thousands to tens of thousands of high-performance computing nodes), complex tasks that cannot be completed by a single node or a general data center, such as numerical simulation and massive data parallel processing, can be processed.

[0003] Some ultra-computing center processor chips use application-specific integrated circuit chips (ASIC chips), which are chips customized for specific applications and have the characteristics of high efficiency and low energy consumption. For example, Google's TPU (Tensor Processing Unit) is an ASIC chip designed for machine learning, suitable for large-scale data centers and cloud computing scenarios, and can efficiently process deep learning tasks.

[0004] An existing ultra-computing chip packaging structure mainly includes an ASIC chip, a photonic integrated circuit chip (PIC chip), an electronic integrated circuit chip (EIC chip), and an optical device, etc. The existing packaging structure has the problem of low packaging integration, resulting in a large packaging structure size and a large data transmission path between components, which slows down data transmission and affects the computing power of the chip.

[0005] After searching, no patent documents identical or similar to the present application have been found.

[0006] In summary, how to design an ultra-computing chip packaging structure and a packaging method to improve the integration of the chip, reduce the size of the chip and shorten the data transmission path in the chip, improve the data transmission rate, and thus improve the computing power of the chip is a technical problem that needs to be solved. SUMMARY

[0007] The technical problem to be solved by the application is to provide an ultra-computing chip heterogeneous packaging structure and a packaging method based on 2.5D packaging, which improves the integration of the chip, reduces the size of the chip and shortens the data transmission path in the chip, improves the data transmission rate, and thus improves the computing power of the chip.

[0008] In order to solve the above technical problems, the technical scheme adopted by the present application is: a heterogeneous packaging structure of supercomputing chips based on 2.5D packaging, comprising a substrate and a silicon interposer, the silicon interposer comprises an upper RDL wiring layer one located on the upper surface, a lower RDL wiring layer one located on the lower surface, and an intermediate layer located between the upper RDL wiring layer one and the lower RDL wiring layer one, an ASIC chip is welded on the upper surface of the silicon interposer, the ASIC chip is in contact with the upper RDL wiring layer one, a chip one and a chip two are welded on the lower surface of the silicon interposer, the chip one and the chip two are EIC chips and PIC chips respectively, the upper surfaces of the chip one and the chip two are in contact with the lower RDL wiring layer one; optical devices one and two are also welded between the upper surface of the substrate and the lower surface of the silicon interposer, the chip one and the chip two are embedded in the space between the optical devices one and two; plastic sealing material is plastic sealed between the optical device one and the chip one, between the chip one and the chip two, and between the chip two and the optical device two.

[0009] Preferably, micro-vias are arranged on the substrate, and the micro-vias are used for heat dissipation of the EIC chips and the PIC chips.

[0010] Preferably, a recess is arranged on the upper surface of the substrate, the EIC chips and the PIC chips are located above the recess, the micro-vias are arranged on the side edges of the recess, the port of the micro-via close to the side of the recess is an inner port, the port of the micro-via away from the side of the recess is an outer port, and the inner cavity of the recess is in communication with the outside through the micro-via.

[0011] Preferably, heat-conducting indium sheets are arranged on the lower surfaces of the EIC chips and the PIC chips, and the heat-conducting indium sheets are used for radiating the heat generated by the EIC chips and the PIC chips into the recess.

[0012] Preferably, the recess is arranged in an inverted trapezoidal shape, the small end of the inverted trapezoidal recess is located at a lower position, the large end of the inverted trapezoidal recess is located at an upper position, and the micro-via is arranged on the side edge of the inverted trapezoidal recess close to the large end.

[0013] Preferably, the periphery of the heat-conducting indium sheet is flush with the periphery of the EIC chips and the PIC chips.

[0014] Preferably, the periphery of the heat-conducting indium sheet is exposed outside the periphery of the EIC chips and the PIC chips, a notch is opened on the substrate and located above the inner port of the micro-via, and the periphery of the heat-conducting indium sheet exposed outside the EIC chips and the PIC chips is inserted into the notch.

[0015] Preferably, the shape of the micro-via is arranged as a straight-through hole, a branch shape, or a scale shape.

[0016] Preferably, the substrate comprises an upper organic substrate layer one, a lower organic substrate layer two and an intermediate inorganic substrate layer between the organic substrate layer one and the organic substrate layer two, the thickness of the intermediate inorganic substrate layer is set to 400-800um; wiring is arranged on the organic substrate layer one and the organic substrate layer two.

[0017] The application also discloses a packaging method of the heterogeneous packaging structure of the supercomputer chip based on the 2.5D packaging. 1) substrate preparation: a three-layer composite substrate is adopted, the three-layer composite substrate comprises an upper organic substrate layer one, a lower organic substrate layer two and an intermediate inorganic substrate layer between the organic substrate layer one and the organic substrate layer two, a groove is etched on the organic substrate layer one, and a microchannel is etched on the side of the groove, so that the inner cavity of the groove is communicated with the outside through the microchannel; then a through hole is formed on the three-layer composite substrate, a conductive metal is arranged in the through hole, and RDL wiring is arranged on the organic substrate layer one and the organic substrate layer two, so that the circuit arranged on the organic substrate layer one and the circuit arranged on the organic substrate layer two can be electrically connected through the through hole; 2) silicon interlayer preparation: a silicon through hole is formed by performing a through hole on the silicon interlayer, a conductive metal is arranged in the silicon through hole, and RDL wiring is arranged on the upper surface and the lower surface of the silicon interlayer, so that the circuit of the upper RDL wiring layer and the circuit of the lower RDL wiring layer can be electrically connected through the silicon through hole; 3) the silicon interlayer is turned over by 180 degrees, the chip one and the chip two are flip-chip mounted, so that the chip one and the chip two are attached and welded to the lower RDL wiring layer of the silicon interlayer, then the bottom filling glue is filled at the attachment and welding position of the chip one and the chip two; the optical device one and the optical device two are also attached and welded to the lower RDL wiring layer of the silicon interlayer; then the plastic sealing material is injected in the form of open molding between the optical device one and the chip one, between the chip one and the chip two and between the chip two and the optical device two to protect the circuit; finally, the heat-conducting indium sheet is attached and welded on the chip one and the chip two; 4) the silicon interlayer is turned over by 180 degrees again, the ASIC chip is attached and welded to the upper RDL wiring layer one of the silicon interlayer, and the bottom filling glue is filled at the attachment and welding position; 5) the optical device one and the optical device two at the lower position of the silicon interlayer are attached and welded to the organic substrate layer one of the substrate, so that the chip one and the chip two are located at the upper position of the groove; The sequence of steps 1) and 2) is not limited.

[0018] The beneficial effects of this invention are as follows: The supercomputing chip packaging structure of this invention utilizes a silicon interposer to double-sidedly weld chips to form a stacked state between chips and arranges the space between optical device one and optical device two. The EIC chip and PIC chip located below are embedded in the space between optical device one and optical device two. This greatly improves the chip integration, reduces the chip size, shortens the data transmission path within the chip, and increases the data transmission rate, thereby improving the chip's computing power. By setting a groove with microvias, heat dissipation of the lower EIC chip and PIC chip is achieved, thus ensuring the stable operation of the chip. Through the design of the shape of the groove and the position of the microvias in the groove, this setting can: firstly, reduce the volume of the lower space in the groove cavity, allowing heat to rise more quickly and be transferred to the microvias for heat dissipation; secondly, allow heat to rise along the inclined side of the inverted trapezoidal groove, facilitating heat transfer; ultimately, ensure that the heat radiated into the groove can be transferred more quickly to the microvias for heat dissipation, further improving the overall heat dissipation efficiency. By setting a thermally conductive indium sheet on the lower surface of the EIC chip and PIC chip, it can efficiently conduct heat, thereby further improving the overall heat dissipation efficiency. By exposing the periphery of the thermally conductive indium sheet to the periphery of the EIC chip and PIC chip, and extending the periphery of the exposed thermally conductive indium sheet into the notch of the substrate, heat can be transferred to the microvias for dissipation more quickly, further improving the overall heat dissipation efficiency. The substrate is configured as a composite structure of organic layer-inorganic layer-organic layer, with the inorganic layer thickness set between 400µm and 800µm. This configuration ensures that the substrate does not warp during packaging and minimizes cracks that occur when drilling holes in the inorganic layer, thereby improving the chip packaging quality. Through the design of a packaging method, the heterogeneous packaging structure of the supercomputing chip based on 2.5D packaging, as described above, was realized. Attached Figure Description

[0019] Figure 1 This is a schematic diagram of the vertical cross-sectional structure of Embodiment 1 of the present invention; Figure 2 for Figure 1 A schematic diagram of the vertical cross-sectional structure of the silicon interposer in the image; Figure 3 This is a top view of the substrate structure in Embodiment 1 of the present invention; Figure 4 for Figure 1 A schematic diagram of the vertical cross-sectional structure of the substrate in the middle; Figure 5 This is a schematic diagram illustrating the packaging steps in Embodiment 1 of the present invention. Figure 1 ; Figure 6 This is a schematic diagram illustrating the packaging steps in Embodiment 1 of the present invention. Figure 2; Figure 7 Packaging step principle diagram for packaging embodiment one of the present application Figure 3 ; Figure 8 Vertical section structure diagram for embodiment two of the present application Figure 9 Enlarged structure diagram of B part in Figure 8 Figure 10 Top view structure diagram of the substrate in embodiment three of the present application In the figure: 1. substrate; 111. organic substrate layer one; 112. organic substrate layer two; 113. intermediate inorganic substrate layer; 114. through hole; 2. silicon interposer; 211. upper RDL wiring layer one; 212. lower RDL wiring layer one; 213. intermediate layer; 214. through silicon via; 3. ASIC chip; 4. chip one; 5. chip two; 6. optical device one; 7. optical device two; 8. plastic packaging material; 9. groove; 10. micro via; 11. heat-conducting indium sheet; 12. bottom filling glue; 13. notch. DETAILED DESCRIPTION

[0020] The technical solutions of the present application are further described in detail below in combination with the drawings and specific embodiments.

[0021] Embodiment one: as Figure 1 and Figure 2 ​As shown, a super-calculating chip heterogeneous packaging structure based on 2.5D packaging includes a substrate 1 and a silicon interposer 2, the silicon interposer 2 includes an upper RDL wiring layer 211 on the upper surface, a lower RDL wiring layer 212 on the lower surface, and an intermediate layer 213 between the upper RDL wiring layer 211 and the lower RDL wiring layer 212, a through silicon via 214 is arranged in the intermediate layer 213, and a conductive metal is arranged in the through silicon via 214, so that the circuits of the upper RDL wiring layer 211 and the circuits of the lower RDL wiring layer 212 are in electrical communication through the through silicon via 214. An ASIC chip 3 is soldered on the upper surface of the silicon interposer 2, the ASIC chip 3 is in contact with the upper RDL wiring layer 211, a chip 1 and a chip 2 are soldered on the lower surface of the silicon interposer 2, the chip 1 and the chip 2 are EIC chips and PIC chips respectively, and the upper surfaces of the chip 1 and the chip 2 are in contact with the lower RDL wiring layer 212. Through the above structure, the ASIC chip 3, the EIC chip and the PIC chip are all electrically connected with the silicon interposer 2. An optical device 1 and an optical device 2 are also soldered between the upper surface of the substrate 1 and the lower surface of the silicon interposer 2, and the chip 1 and the chip 2 are embedded in the space between the optical device 1 and the optical device 2. Encapsulating material 8 is encapsulated between the optical device 1 and the chip 1, between the chip 1 and the chip 2, and between the chip 2 and the optical device 2. The lower surface of the substrate 1 is soldered with a PCB (not shown in the figure). The super-calculating chip packaging structure in this embodiment uses the silicon interposer to solder chips on both sides to form a stacked state between the chips and arrange the space between the optical device 1 and the optical device 2, and embed the EIC chip and the PIC chip located below in the space between the optical device 1 and the optical device 2, which greatly improves the integration of the chips, reduces the size of the chips, shortens the data transmission path in the chips, improves the data transmission rate, and thus improves the computing power of the chips.

[0022] In this embodiment, the ASIC chip 3 is arranged above the silicon interposer 2, and the EIC chip and the PIC chip are arranged below the silicon interposer 2, because the size of the ASIC chip 3 in the super-calculating chip is larger, and it generates more heat during work, so the ASIC chip 3 is arranged above and the upper surface of the ASIC chip 3 is not encapsulated, which is convenient for heat dissipation of the ASIC chip 3. Here, a heat sink (not shown in the figure) such as a fin heat sink can be added to the upper surface of the ASIC chip 3, so that the heat generated by the ASIC chip 3 during work is dissipated through the heat sink.

[0023] Regarding the heat dissipation of the EIC chip and the PIC chip, since the EIC chip and the PIC chip are filled between the plastic packaging materials, in order to facilitate the heat dissipation of the EIC chip and the PIC chip, the applicant sets a micro-via on the substrate 1 to dissipate the heat generated by the EIC chip and the PIC chip during operation. As shown in Figure 1 , a groove 9 is arranged on the upper surface of the substrate 1, the EIC chip and the PIC chip are located at the upper position of the groove 9, the micro-via 10 is arranged on the side of the groove 9, the port of the micro-via 10 close to one side of the groove 9 is the inner port, the port of the micro-via 10 away from one side of the groove 9 is the outer port, and the inner cavity of the groove 9 is communicated with the outside through the micro-via 10. During operation, the heat generated by the EIC chip and the PIC chip is first radiated into the inner cavity of the groove 9, and then dissipated to the outside through the micro-via 10. Through the above structure, the heat dissipation of the upper ASIC chip and the lower EIC chip and PIC chip is realized, thereby ensuring the stable operation of the chip.

[0024] In order to further improve the heat dissipation efficiency, the applicant also optimizes as follows: a heat-conducting indium sheet 11 is arranged on the lower surface of the EIC chip and the PIC chip, and the heat generated by the EIC chip and the PIC chip is radiated into the groove 9 by using the heat-conducting indium sheet 11, which can play a role in efficiently conducting heat, thereby further improving the overall heat dissipation efficiency.

[0025] The groove 9 is arranged as an inverted trapezoid, the small end of the inverted trapezoidal groove 9 is located at the lower position, the large end of the inverted trapezoidal groove 9 is located at the upper position, and the micro-via 10 is arranged on the side of the inverted trapezoidal groove 9 close to the large end position. This setting can reduce the volume of the lower space in the inner cavity of the groove 9, so that the heat can be transferred more quickly to the micro-via for heat dissipation; secondly, the heat climbs along the inclined edge of the inverted trapezoidal groove 9, which is more conducive to heat transfer; finally, it ensures that the heat radiated into the groove can be transferred more quickly to the micro-via for heat dissipation, thereby further improving the overall heat dissipation efficiency.

[0026] As shown in Figure 3 , the micro-via 10 is provided with a plurality of micro-vias, which can be arranged on the four sides of the inverted trapezoidal groove 9, or only on one side, two sides or three sides of the inverted trapezoidal groove 9. The hole diameter of the micro-via 10 ranges from 20μm to 75μm. In this embodiment, the shape of the micro-via 10 is set as a straight hole, which uses a straight channel for heat dissipation, and a large number of channels can be arranged to facilitate more direct heat dissipation.

[0027] In the packaging process, the substrate can use an organic substrate, such as an epoxy resin substrate, an ABF resin substrate, etc., or an inorganic substrate, such as a ceramic substrate, a glass substrate, etc. However, the organic substrate may have warping problems due to internal stress imbalance and other problems during packaging; the inorganic substrate may have many cracks during punching because the main components of the inorganic substrate are brittle materials, and the mechanical properties of the inorganic substrate are high hardness, high brittleness, and low toughness. In view of the above problems, the applicant designs a multi-layer composite substrate, as shown in Figure 1 and Figure 4 The substrate 1 includes an upper organic substrate layer one 111, a lower organic substrate layer two 112, and an intermediate inorganic substrate layer 113 between the organic substrate layer one 111 and the organic substrate layer two 112. The organic substrate layer one 111 and the organic substrate layer two 112 can use a resin substrate, and the intermediate inorganic substrate layer 113 can use a glass substrate. The thickness of the intermediate inorganic substrate layer 113 is set to 400um to 800um. Wiring is arranged on the organic substrate layer one 111 and the organic substrate layer two 112, and a through hole 114 is opened in the intermediate inorganic substrate layer 113. A conductive metal is arranged in the through hole 114, so that the circuit arranged on the organic substrate layer one 111 and the circuit arranged on the organic substrate layer two 112 can be electrically connected through the through hole 114. The recess 9 and the micro-via 10 are both arranged on the organic substrate layer one 111. As shown in Figure 3 When wiring is arranged on the organic substrate layer one 111, it can be arranged in the four corner positions A of Figure 3 In this embodiment, the substrate is set to a composite structure of organic layer-inorganic layer-organic layer, and the thickness of the inorganic layer is set to 400um to 800um. This setting can not only ensure that the substrate does not warp during packaging, but also can minimize the cracks that occur when the inorganic layer is punched, thereby improving the packaging quality of the chip.

[0028] This embodiment also discloses a packaging method of the above heterogeneous packaging structure of the super-calculated chip, which includes the following steps: 1) Substrate preparation: as shown in Figure 4As shown, a three-layer composite substrate is adopted, the three-layer composite substrate 1 includes an upper organic substrate layer one 111, a lower organic substrate layer two 112 and an intermediate inorganic substrate layer 113 between the organic substrate layer one 111 and the organic substrate layer two 112, a groove 9 is etched on the organic substrate layer one 111, and a micro channel 10 is etched on the side of the groove 9, so that the inner cavity of the groove 9 is communicated with the outside through the micro hole 10; then a through hole is formed on the three-layer composite substrate, and a conductive metal is arranged in the through hole 114, and then RDL wiring is performed on the organic substrate layer one 111 and the organic substrate layer two 112, so that the circuit arranged on the organic substrate layer one 111 and the circuit arranged on the organic substrate layer two 112 can be electrically connected through the through hole 114; 2) Silicon interposer preparation: as shown in Figure 2 The silicon interposer 2 is first formed with a through hole to form a silicon through hole 214, a conductive metal is arranged in the silicon through hole 214, and then RDL wiring is performed on the upper surface and the lower surface of the silicon interposer 2, so that the circuit of the upper RDL wiring layer 211 and the circuit of the lower RDL wiring layer 212 can be electrically connected through the silicon through hole 214; 3) as shown in Figure 5 And Figure 6 Then the silicon interposer 2 is turned over by 180 degrees, the chip one 4 and the chip two 5 are flip-chip mounted, so that the chip one 4 and the chip two 5 are attached and welded to the lower RDL wiring layer 212 of the silicon interposer 2, and then the bottom filling glue 12 is filled at the attachment and welding position of the chip one 4 and the chip two 5; the optical device one 6 and the optical device two 7 are also attached and welded to the lower RDL wiring layer 212 of the silicon interposer 2; then the plastic sealing material 8 is injected in the form of open molding between the optical device one 6 and the chip one 4, between the chip one 4 and the chip two 5, and between the chip two 5 and the optical device two 7 to protect the circuit; finally, the heat-conducting indium sheet 11 is attached and welded on the chip one 4 and the chip two 5; 4) as shown in Figure 7 Then the silicon interposer 2 is turned over by 180 degrees again, the ASIC chip 3 is attached and welded to the upper RDL wiring layer one 211 of the silicon interposer 2, and then the bottom filling glue 12 is filled at the attachment and welding position; 5) as shown in Figure 1 Finally, the optical device one 6 and the optical device two 7 below the silicon interposer 2 are attached and welded to the organic substrate layer one 111 of the substrate 1, so that the chip one 4 and the chip two 5 are located at the upper position of the groove 9; The order of steps 1) and 2) in the method is not limited.

[0029] Example two: in example one, as shown in Figure 1As shown, the periphery of the heat-conducting indium sheet 11 is flush with the periphery of the EIC chip and the PIC chip, and compared with Embodiment One, the difference is that, as shown, Figure 8 and Figure 9 As shown, the periphery of the heat-conducting indium sheet 11 is exposed to the periphery of the EIC chip and the PIC chip, and a notch 13 is opened on the substrate 1 and above the port of the micro-via 10, and the periphery of the heat-conducting indium sheet 11 exposed to the periphery of the EIC chip and the PIC chip extends into the notch 13. In this way, heat can be transferred to the micro-via more quickly for dissipation, further improving the overall heat dissipation efficiency.

[0030] Embodiment Three: Compared with Embodiment One, the difference is the shape of the micro-via, as shown, Figure 10 As shown, the shape of the micro-via 10 in this embodiment is set to a branch shape or a scale shape, and the micro-via is set in this way to have more branch channels for shunting and rapid heat dissipation.

[0031] In summary, the super-computing chip packaging structure in the present application uses the silicon interposer to double-sidedly weld the chips to form a stacked state between the chips and arrange the space between the optical device one and the optical device two, and the EIC chip and the PIC chip located below are buried in the space between the optical device one and the optical device two, which greatly improves the integration of the chips, reduces the volume of the chips and shortens the data transmission path in the chips, improves the data transmission rate, and thus improves the computing power of the chips. By setting the groove with the micro-via, the heat dissipation of the EIC chip and the PIC chip below is realized, thereby ensuring the stable operation of the chips. Through the design of the shape of the groove and the position of the micro-via in the groove, firstly, the volume of the lower space in the cavity of the groove is reduced, so that the heat can be transferred more quickly to the micro-via for dissipation; secondly, the heat climbs along the inclined edge of the inverted trapezoidal groove, which is more conducive to heat transfer; finally, the heat radiated into the groove can be transferred more quickly to the micro-via for dissipation, further improving the overall heat dissipation efficiency. By setting the heat-conducting indium sheet on the lower surface of the EIC chip and the PIC chip, efficient heat conduction is achieved, thereby further improving the overall heat dissipation efficiency. By exposing the periphery of the heat-conducting indium sheet to the periphery of the EIC chip and the PIC chip, and extending the periphery of the heat-conducting indium sheet exposed to the periphery of the EIC chip and the PIC chip into the notch of the substrate, heat can be transferred more quickly to the micro-via for dissipation, further improving the overall heat dissipation efficiency. The substrate is set to a composite structure of organic layer-inorganic layer-organic layer, and the thickness of the inorganic layer is set to be between 400 um and 800 um, which can not only ensure that the substrate does not warp during packaging, but also minimize the cracks that occur when punching the inorganic layer, thereby improving the packaging quality of the chips. By designing a packaging method, the super-computing chip heterogeneous packaging structure based on 2.5D packaging as described above is realized.

[0032] The "plurality" as described in the embodiments means "two or more" in number. The above embodiments are only for illustrating the present application, but not for limiting the present application. Those skilled in the art can make various changes or modifications without departing from the spirit and scope of the present application. Therefore, all equivalent technical solutions should belong to the protection scope of the present application, and the protection scope of the present application should be defined by the claims.

Claims

1. A heterogeneous packaging structure for a supercomputing chip based on 2.5D packaging, comprising a substrate and a silicon interposer, wherein the silicon interposer comprises an upper RDL wiring layer one located on the upper surface, a lower RDL wiring layer one located on the lower surface, and an intermediate layer located between the upper RDL wiring layer one and the lower RDL wiring layer one, characterized in that: An ASIC chip is soldered onto the upper surface of the silicon interposer, and the ASIC chip is in contact with the upper RDL wiring layer. Chip 1 and Chip 2 are soldered onto the lower surface of the silicon interposer, and Chip 1 and Chip 2 are respectively an EIC chip and a PIC chip. The upper surfaces of Chip 1 and Chip 2 are in contact with the lower RDL wiring layer. Optical device 1 and Optical device 2 are also soldered between the upper surface of the substrate and the lower surface of the silicon interposer, and Chip 1 and Chip 2 are embedded in the space between optical device 1 and optical device 2. Molding material is encapsulated between optical device 1 and chip 1, between chip 1 and chip 2, and between chip 2 and optical device 2.

2. The heterogeneous packaging structure of a supercomputing chip based on 2.5D packaging according to claim 1, characterized in that: Microvias are formed on the substrate to dissipate heat from the EIC chip and the PIC chip.

3. The heterogeneous packaging structure of a supercomputing chip based on 2.5D packaging according to claim 2, characterized in that: A groove is provided on the upper surface of the substrate. The EIC chip and the PIC chip are located above the groove. The micro-via is provided on the side of the groove. The port of the micro-via closer to the groove is the inner port, and the port of the micro-via farther from the groove is the outer port. The inner cavity of the groove is connected to the outside through the micro-via.

4. The heterogeneous packaging structure of a supercomputing chip based on 2.5D packaging according to claim 3, characterized in that: A thermally conductive indium sheet is disposed on the lower surface of the EIC chip and the PIC chip, and the heat generated by the EIC chip and the PIC chip is radiated into the groove using the thermally conductive indium sheet.

5. The heterogeneous packaging structure of a supercomputing chip based on 2.5D packaging according to claim 4, characterized in that: The groove is configured as an inverted trapezoid, with the smaller end of the inverted trapezoidal groove located at the bottom and the larger end of the inverted trapezoidal groove located at the top. The micro-through hole is located on the side of the inverted trapezoidal groove located near the larger end.

6. The heterogeneous packaging structure of a supercomputing chip based on 2.5D packaging according to claim 4, characterized in that: The periphery of the thermally conductive indium sheet is flush with the periphery of the EIC chip and the PIC chip.

7. The heterogeneous packaging structure of a supercomputing chip based on 2.5D packaging according to claim 4, characterized in that: The periphery of the thermally conductive indium sheet is exposed around the EIC chip and the PIC chip. A notch is opened on the substrate above the microvia port, and the periphery of the thermally conductive indium sheet exposed around the EIC chip and the PIC chip extends into the notch.

8. The heterogeneous packaging structure of a supercomputing chip based on 2.5D packaging according to any one of claims 2 to 7, characterized in that: The shape of the micro-hole is set as a straight hole, a tree branch shape, or a scale shape.

9. The heterogeneous packaging structure of a supercomputing chip based on 2.5D packaging according to claim 8, characterized in that: The substrate includes an upper organic substrate layer one, a lower organic substrate layer two, and an intermediate inorganic substrate layer between the organic substrate layer one and the organic substrate layer two, wherein the thickness of the intermediate inorganic substrate layer is set to be between 400 μm and 800 μm; wiring is configured on the organic substrate layer one and the organic substrate layer two.

10. A packaging method for a heterogeneous packaging structure of a supercomputing chip based on 2.5D packaging according to claim 9, characterized in that: Includes the following steps: 1) Substrate fabrication: A three-layer composite substrate is used, comprising an upper organic substrate layer 1, a lower organic substrate layer 2, and an intermediate inorganic substrate layer between the organic substrate layer 1 and the organic substrate layer 2. Grooves are etched into the organic substrate layer 1, and microchannels are etched into the sides of the grooves, so that the inner cavity of the grooves is connected to the outside through the micro-vias. Then, through-holes are made in the three-layer composite substrate, and conductive metal is placed in the through-holes. RDL wiring is then performed on the organic substrate layer 1 and the organic substrate layer 2, so that the circuits arranged on the organic substrate layer 1 and the circuits arranged on the organic substrate layer 2 can be electrically connected through the through-holes. 2) Silicon Intermediate Layer Preparation: First, through-holes are made in the silicon intermediate layer to form silicon vias. Conductive metal is placed in the silicon vias. Then, RDL wiring is performed on the upper and lower surfaces of the silicon intermediate layer, so that the circuits of the upper RDL wiring layer and the lower RDL wiring layer are electrically connected through the silicon vias. 3) Flip the silicon interposer 180 degrees and flip-chip Chip 1 and Chip 2 onto the silicon interposer, thereby mounting and soldering Chip 1 and Chip 2 onto the lower RDL wiring layer of the silicon interposer. Then, fill the mounting and soldering area of ​​Chip 1 and Chip 2 with underfill adhesive. Also mount and solder Optical Device 1 and Optical Device 2 onto the lower RDL wiring layer of the silicon interposer. Then, inject molding compound to protect the circuit between Optical Device 1 and Chip 1, between Chip 1 and Chip 2, and between Chip 2 and Optical Device 2 using open molding. Finally, mount and solder thermally conductive indium sheets onto Chip 1 and Chip 2. 4) Flip the silicon interposer 180 degrees again, mount and solder the ASIC chip onto the upper RDL wiring layer 1 of the silicon interposer, and then fill the mounting and soldering area with bottom filler adhesive. 5) Attach and solder optical device one and optical device two, which are located below the silicon interposer layer, to the organic substrate layer one of the substrate, so that chip one and chip two are located above the groove. The order of steps 1) and 2) is not important.

Images