Semiconductor device and manufacturing method thereof

Abstract

The invention provides a semiconductor device and a manufacturing method thereof. The semiconductor device comprises an electronic unit, an encapsulation layer, a circuit structure, a protection layer, a first heat conduction component and a second heat conduction component. The encapsulation layer surrounds the electronic unit and has a first side and a second side opposite to each other. The circuit structure is disposed on the first side of the encapsulation layer and electrically connected to the electronic unit. The protection layer is disposed on the second side of the encapsulation layer. The first heat-conducting component is disposed on the protective layer. The second heat-conducting component is disposed on the first heat-conducting component, wherein the heat conductivity coefficient of the second heat-conducting component is different from that of the first heat-conducting component.

Description

TECHNICAL FIELD

[0001] The present disclosure relates to a semiconductor device and a method of fabricating the same, and more particularly to a semiconductor device with better structural reliability and a method of fabricating the same. BACKGROUND

[0002] In a wafer-level package (WLP) process or a panel-level package (PLP) process, a surface treatment method is required to thin an electronic unit or a package structure, or to perform surface roughening to improve the bonding force between layers. Therefore, the design of the surface treatment method and the optimization of the manufacturing process can improve the structural reliability of the electronic device or the semiconductor device. SUMMARY

[0003] The present disclosure is directed to a semiconductor device with better structural reliability.

[0004] The present disclosure is also directed to a method of fabricating a semiconductor device to fabricate the semiconductor device described above.

[0005] According to embodiments of the present disclosure, a semiconductor device includes an electronic unit, a package layer, a circuit structure, a protective layer, a first heat-conductive component, and a second heat-conductive component. The package layer surrounds the electronic unit and has a first side and a second side opposite to each other. The circuit structure is disposed on the first side of the package layer and electrically connected to the electronic unit. The protective layer is disposed on the second side of the package layer. The first heat-conductive component is disposed on the protective layer. The second heat-conductive component is disposed on the first heat-conductive component, wherein the thermal conductivity of the second heat-conductive component is different from that of the first heat-conductive component.

[0006] According to embodiments of the present disclosure, a method of fabricating a semiconductor device includes the following steps. A package layer is formed on an electronic unit, and the package layer surrounds the electronic unit. The package layer is ground to expose the back surface of the electronic unit. A circuit structure is formed on the first side of the package layer, wherein the circuit structure is electrically connected to the electronic unit. A protective layer is formed on the second side of the package layer. A first heat-conductive component is formed on the protective layer. A second heat-conductive component is formed on the first heat-conductive component, wherein the thermal conductivity of the second heat-conductive component is different from that of the first heat-conductive component.

[0007] Based on the above, in embodiments of the present disclosure, the protective layer is located on the second side of the package layer, and the first heat-conductive component and the second heat-conductive component with different thermal conductivities are sequentially disposed on the protective layer, wherein the protective layer can improve and / or enhance the anti-cracking strength of the electronic unit, and the heat-conductive components can make the semiconductor device of the present disclosure have better heat dissipation effect.

[0008] To make the above-mentioned features and advantages disclosed herein more apparent and understandable, specific embodiments are described below in conjunction with the accompanying drawings. Attached Figure Description

[0009] Figure 1 This is a schematic cross-sectional view of a semiconductor device according to an embodiment of the present disclosure;

[0010] Figure 2 This is a schematic cross-sectional view of a semiconductor device according to another embodiment of this disclosure;

[0011] Figure 3 This is a schematic cross-sectional view of a semiconductor device according to another embodiment of this disclosure;

[0012] Figure 4 This is a schematic cross-sectional view of a semiconductor device according to another embodiment of this disclosure;

[0013] Figures 5A to 5C This is a partial enlarged cross-sectional schematic diagram of several semiconductor devices according to various embodiments of this disclosure;

[0014] Figure 6A This is a top view schematic diagram of a semiconductor device according to an embodiment of the present disclosure;

[0015] Figure 6B yes Figure 6A A partial cross-sectional schematic diagram of a semiconductor device;

[0016] Figures 7A to 7C This is a cross-sectional schematic diagram of a method for manufacturing a semiconductor device according to an embodiment of the present disclosure;

[0017] Figure 8 This is a cross-sectional schematic diagram of a semiconductor device according to another embodiment of the present disclosure.

[0018] Explanation of reference numerals in the attached figures

[0019] 10: Carrier board;

[0020] 20: Adhesive layer;

[0021] 100a, 100b, 100c, 100d, 100g: Semiconductor devices;

[0022] 110, 110': Electronic unit;

[0023] 111: Semiconductor substrate;

[0024] 112: Pad;

[0025] 113, 113': Back side;

[0026] 114: Passivation layer;

[0027] 116: Insulation layer;

[0028] 117: Active side;

[0029] 118: Metal column;

[0030] 120, 120': Encapsulation layer;

[0031] 130, 130': Circuit structure;

[0032] 132: Conductive layer;

[0033] 134: Insulation layer;

[0034] 140, 140', 140a, 140b, 140c, 140e, 140f, 140e, 140f, 140g: Protective layer;

[0035] 141a, 141b, 141c: Surrounding surfaces;

[0036] 142e, 142f: Microstructure;

[0037] 150, 150a, 150b, 150c, 150g: First thermally conductive component;

[0038] 153: First limiting part;

[0039] 160, 160a, 160c, 160g: Second thermal conductive components;

[0040] 161, 161g, 187, 189: Top surface;

[0041] 162a: Part One;

[0042] 163: Second limiting part;

[0043] 164: Part Two;

[0044] 165: Concave-convex structure;

[0045] 170, 170': Connecting parts;

[0046] 180: Barrier layer;

[0047] 185: Buffer layer;

[0048] 190, 190': Third thermal conductive component;

[0049] 195: Conductor layer;

[0050] 197: Base rubber;

[0051] L1: Component length;

[0052] L2: Microstructure length;

[0053] D1: Component depth;

[0054] D2: Microstructure depth;

[0055] G1: First distance;

[0056] G2: Second distance;

[0057] H: Height difference;

[0058] R: Microstructure;

[0059] RS1, RS2: Rough surfaces;

[0060] S1, S1': First side;

[0061] S2, S2': Second side;

[0062] T1: First thickness;

[0063] T2: Second thickness;

[0064] X, Z: Direction. Detailed Implementation

[0065] This disclosure can be understood by referring to the following detailed description in conjunction with the accompanying drawings. It should be noted that, for ease of understanding and for the sake of brevity, many of the drawings in this disclosure depict only a portion of the electronic device, and certain components in the drawings are not drawn to scale. Furthermore, the number and dimensions of the components in the drawings are for illustrative purposes only and are not intended to limit the scope of this disclosure.

[0066] Throughout this specification and the appended claims, certain terms are used to refer to specific elements. Those skilled in the art will understand that electronic device manufacturers may use different names to refer to the same elements. This document is not intended to distinguish between elements that function identically but have different names.

[0067] In the following description and claims, the words “containing” and “including” are open-ended terms, and therefore should be interpreted as “containing but not limited to…”.

[0068] Furthermore, relative terms such as "below" or "bottom" and "above" or "top" may be used in the embodiments to describe the relative relationship of one element of the figures to another element. It is understood that if the apparatus in the figures is flipped so that it is upside down, the element described as being on the "below" side will become the element on the "above" side.

[0069] In some embodiments disclosed herein, terms such as "connection" and "interconnection," unless specifically defined, may refer to two structures in direct contact, or to two structures not in direct (indirect) contact, wherein another structure is disposed between the two structures. Furthermore, these terms regarding engagement and connection may also include situations where both structures are movable or both structures are fixed. In addition, the term "coupling" includes the transfer of energy between two structures through direct or indirect electrical connection, or the transfer of energy between two separate structures through mutual induction.

[0070] It should be understood that when an element or membrane is referred to as being "on" or "connected" to another element or membrane, it can be directly on or directly connected to that other element or membrane, or there may be an inserted element or membrane between them (indirect cases). Conversely, when an element is referred to as being "directly" on or "directly connected" to another element or membrane, there may be no inserted element or membrane between them.

[0071] In some embodiments disclosed herein, "adjacent" may refer, for example, to two structures overlapping each other in the direction of extension of the electronic device or perpendicular to the direction of extension of the electronic device. In some embodiments, there are no other components between the two structures. In some embodiments, it may also refer to the presence of other structures disposed between the two structures.

[0072] The terms “approximately,” “equal to,” “same,” “substantially,” or “roughly” are generally interpreted as being within 20% of a given value or range, or as being within 10%, 5%, 3%, 2%, 1%, or 0.5% of a given value or range.

[0073] In this disclosure, the area, width, thickness, or height of each component, or the distance or spacing between components, can be measured using an optical microscopy (OM), a scanning electron microscope (SEM), an alpha-step thickness gauge, an ellipsometry, or other suitable methods. Specifically, according to some embodiments, a scanning electron microscope can be used to obtain a cross-sectional structural image including the component to be measured, and to measure the area, width, thickness, or height of each component, or the distance or spacing between components.

[0074] In some embodiments disclosed herein, roughness judgment is defined by SEM observation, where the peaks and valleys of surface undulations on an uneven surface have a distance difference of 0.15 micrometers (μm) to 1 μm. Roughness judgment measurement may involve using SEM, transmission electron microscope (TEM), etc., to observe the surface undulations at an appropriate magnification, and comparing the undulations by taking a sample of unit length (e.g., 10 μm) to determine its roughness range. Here, "appropriate magnification" means a surface with at least 10 undulating peaks visible at this magnification. z ) or average roughness (R) a ).

[0075] In other embodiments, the term "roughness" as used refers to the degree of unevenness or undulation on an object's surface. Specifically, the "roughness" value of a surface or sidewall can be determined based on the ten-point average roughness (R0). z The ten-point average roughness (R) was obtained. z The ten-point average roughness (R0) is defined as the sum of the absolute average of the five peak values ​​and the absolute average of the five trough values, calculated by taking five peak values ​​and five trough values ​​within an evaluation length. More specifically, the ten-point average roughness (R0) is... z The following formula is used to calculate:

[0076]

[0077] Among them, R pi and R vi These are the i-th peak value and the i-th trough value, respectively. In some embodiments, the term "roughness" as used herein refers to average roughness, which can be measured using instruments commonly found in the art to which this disclosure pertains. For example, the average roughness of a surface can be measured using a focusing ion beam (FIB) microscope with magnification of 5000 to 50000x, a scanning electron microscope (SEM), a transmission electron microscope (TEM), or an atomic force microscope (AFM) with a measurement scale of 10 μm to 100 μm.

[0078] In other embodiments, Young's coefficient can be measured using a tensile testing machine, a universal testing machine, a push-pull tester (e.g., INSTRON CORPORATION model 5565), or other suitable testing equipment. Furthermore, in another embodiment, Young's coefficient can be determined based on, but is not limited to, the ASTM (American Society for Testing and Materials) standard method (ASTM D882, Standard Test Method for Tensile Properties of Plastic Sheets) or other suitable testing standards.

[0079] As used herein, the terms “film” and / or “layer” can refer to any continuous or discontinuous structure and material (such as materials deposited by the methods disclosed herein). For example, films and / or layers can include two-dimensional materials, three-dimensional materials, nanoparticles, or even partial or complete molecular layers, or partial or complete atomic layers, or atomic and / or molecular clusters. Films or layers may contain materials or layers with pinholes and may be at least partially continuous.

[0080] Although the terms first, second, third… can be used to describe multiple components, the components are not limited to these terms. These terms are used only to distinguish a single component from other components in the specification. The same terms may not be used in the claims, but rather replaced by first, second, third… in the order of the elements declared in the claims. Therefore, in the following description, a first component may be a second component in the claims.

[0081] Unless otherwise defined, all terms used herein (including technical and scientific terms) have the same meaning as commonly understood by those skilled in the art to which this disclosure is made. It is understood that these terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning consistent with the relevant art and the context of this disclosure, and should not be interpreted in an idealized or overly formal manner, unless specifically defined herein.

[0082] It should be understood that the technical features of several different embodiments can be replaced, reorganized, or mixed to complete other embodiments without departing from the spirit of this disclosure.

[0083] The electronic devices disclosed herein may include, but are not limited to, power modules, semiconductor devices, semiconductor packaging devices, display devices, antenna devices, sensing devices, light-emitting devices, or splicing devices. Electronic devices may include bendable or flexible electronic devices. Electronic devices may include electronic components. Electronic components may include passive components, active components, or combinations thereof, such as capacitors, resistors, inductors, variable capacitors, filters, diodes, transistors, sensors, microelectromechanical systems (MEMS) components, liquid crystal chips, etc., but are not limited to these. Diodes may include light-emitting diodes (LEDs) or non-light-emitting diodes. Diodes include PN junction diodes, PIN diodes, or constant current diodes. Light-emitting diodes may include, for example, organic light-emitting diodes (OLEDs), sub-millimeter LEDs, micro LEDs, quantum dot LEDs, fluorescent, phosphorescent, or other suitable materials, or combinations thereof, but are not limited to these. Sensors may include, for example, capacitive sensors, optical sensors, electromagnetic sensors, fingerprint sensors (FPS), touch sensors, antennas, or pen sensors, but are not limited thereto. The following description uses a display device as an example of an electronic device to illustrate the contents of this disclosure, but this disclosure is not limited thereto. According to embodiments of this disclosure, the manufacturing method of the provided electronic device can be applied, for example, to wafer-level package (WLP) or panel-level package (PLP) processes, and can employ chip-first or chip-last / RDL-first processes, as will be further described below. The electronic device referred to in this disclosure may include a system-on-package (SoC), a system-in-package (SiP), an antenna-in-package (AiP), a co-packaged optical (CPO), or a combination thereof, but is not limited thereto.

[0084] Reference will now be made in detail to the exemplary embodiments disclosed herein, examples of which are illustrated in the accompanying drawings. Wherever possible, the same element symbols are used in the drawings and description to denote the same or similar parts.

[0085] Figure 1 This is a schematic cross-sectional view of a semiconductor device according to an embodiment of this disclosure. Please refer to... Figure 1 In this embodiment, the semiconductor device 100a includes an electronic unit 110, an encapsulation layer 120, a circuit structure 130, a protective layer 140a, a first thermally conductive component 150a, and a second thermally conductive component 160a. The encapsulation layer 120 surrounds the electronic unit 110 and has a first side S1 and a second side S2 opposite to each other. The circuit structure 130 is disposed on the first side S1 of the encapsulation layer 120 and is electrically connected to the electronic unit 110. The protective layer 140a is disposed on the second side S2 of the encapsulation layer 120. The first thermally conductive component 150a is disposed on the protective layer 140a. The second thermally conductive component 160a is disposed on the first thermally conductive component 150a, wherein the thermal conductivity of the second thermally conductive component 160a is different from that of the first thermally conductive component 150a. In one embodiment, the thermal conductivity of the second thermally conductive component 160a is, for example, between 100 W / mK and 2000 W / mK, or between 150 W / mK and 350 W / mK, but is not limited thereto.

[0086] In one embodiment, the electronic unit 110 may be, for example, a known good die (KGD), a diode, an antenna unit, a sensor, a semiconductor-related process structure, or a semiconductor-related process structure disposed on a substrate (e.g., polyimide, glass, silicon substrate or other suitable substrate material), but is not limited thereto.

[0087] Please refer to Figure 1In this embodiment, the electronic unit 110 may include a semiconductor substrate 111, pads 112, a passivation layer 114, an insulating layer 116, and metal pillars 118. In one embodiment, the semiconductor substrate 111 may be, for example, a silicon substrate, which includes active and passive components formed therein, but is not limited thereto. The pads 112 are disposed on the semiconductor substrate 111 and can be electrically connected to other conductive components, wherein the material of the pads 112 may be, for example, aluminum, copper, nickel, molybdenum, titanium, alloys or combinations of the above materials, or other suitable metallic materials, but is not limited thereto. The passivation layer 114 is formed on the semiconductor substrate 111 and has contact openings that expose a portion of the pads 112. The passivation layer 114 may be, for example, a silicon oxide layer, a silicon nitride layer, a silicon oxynitride layer, or a dielectric layer formed of other suitable dielectric materials, but is not limited thereto. The insulating layer 116 is formed on the passivation layer 114, and the contact openings of the insulating layer 116 partially expose the pads 112. The insulating layer 116 may be, for example, a polyimide layer or a dielectric layer formed of other suitable polymers, but is not limited thereto. A metal pillar 118 is formed on the pad 112, and the metal pillar 118 may be approximately flush with the surface of the insulating layer 116, wherein the material of the metal pillar 118 may be, for example, copper, but is not limited thereto. In one embodiment, a portion of the metal pillar 118 may be embedded within the pad 112, wherein the embedment depth is, for example, from 1 micrometer to 10 micrometers, but is not limited thereto.

[0088] After the electronic unit 110 is manufactured, it undergoes a unitization cutting process to cut it into multiple electronic units 110. Due to manufacturing processes or other factors, the sizes of the front and back sides of the cut electronic unit 110 may differ slightly. That is, the projected areas of the back side 113 and the active side 117 of the electronic unit 110 on a plane may be slightly different. In one embodiment, the active side 117 of the electronic unit 110 may be recessed in the Z direction relative to the first side S1 of the encapsulation layer 120 by a distance due to the high-pressure curing process. That is, the active side 117 of the electronic unit 110 and the first side S1 of the encapsulation layer 120 are not coplanar. The non-coplanarity means that in the X direction, the surface of the encapsulation layer 120 and the active side 117 are not on the same plane, which can improve the reliability of the electronic unit 110. In one embodiment, the active side 117 may be, for example, the surface of the electronic unit 110 where the metal pillar 118 is provided.

[0089] Furthermore, in this embodiment, the encapsulation layer 120 surrounds the electronic unit 110. In this embodiment, "one component surrounding another component" can mean that the component, in a cross-sectional view of the semiconductor device 100a, can at least partially contact the side surface of the other component. Figure 1As shown, the encapsulation layer 120 can directly contact the side surface of the electronic unit 110. The encapsulation layer 120 provides the electronic unit 110 with water and vapor protection, thereby improving the reliability of the semiconductor device 100a. In one embodiment, the material of the encapsulation layer 120 is, for example, a polymer or epoxy molding compound (EMC), wherein the encapsulation layer 120 is formed, for example, by a molding process, but is not limited thereto. In one embodiment, the back surface 113 of the electronic unit 110 may be flush with the second side S2 of the encapsulation layer 120, but is not limited thereto.

[0090] Furthermore, the circuit structure 130 of this embodiment may include any suitable structure formed by stacking a conductive layer 132 and an insulating layer 134, wherein the stacking direction of the insulating layer 134 and the conductive layer 132 may be along direction Z. In one embodiment, the circuit structure 130 may contact the first side S1 of the encapsulation layer 120, wherein the metal pillar 118 of the electronic unit 110 contacts the conductive layer 132 of the circuit structure 130 and is electrically connected to the circuit structure 130. In one embodiment, the material of the conductive layer 132 may be, for example, copper, titanium, nickel, or a combination or alloy of the above materials, but is not limited thereto. In one embodiment, the material of the insulating layer 134 may be, for example, a build-up film, polyimide, epoxy, silicon dioxide, silicon nitride, solder resist, or a combination of the above, but is not limited thereto.

[0091] In one embodiment, the circuit structure 130 may also be referred to as a redistribution layer. The redistribution layer can be electrically connected to a chip or other electronic component via solder balls or other bonding components. The redistribution layer may include at least one dielectric layer and at least one conductive layer stacked alternately along the Z direction. The at least one dielectric layer and at least one conductive layer allow for circuit redistribution and / or increase in line fan-out or fan-in area, or allow different electronic components to be electrically connected to each other via the redistribution layer. For example, the pitch of two adjacent contact pads at the end of the redistribution layer that contacts an electronic component may be less than or equal to the pitch of two adjacent contact pads at the end of the redistribution layer that is away from the electronic component. Therefore, the redistribution layer can adjust the line fan-out or electrically connect a circuit structure / electronic component with a first pitch to a circuit structure / electronic component with a second pitch, but is not limited thereto. Methods of forming the redistribution layer may include using photolithography, surface treatment, laser processing, electroplating, deposition, or other processes to form at least one dielectric layer and at least one conductive layer. Surface treatment processes include roughening or activating the surface of dielectric or conductive layers to improve their adhesion. For example, increasing surface roughness can enhance the bonding strength with subsequent film layers.

[0092] Furthermore, in this embodiment, the protective layer 140a is disposed on the second side S2 of the encapsulation layer 120. Specifically, the protective layer 140a can be directly located on the back surface 113 of the electronic unit 110. Since the electronic unit 110 will generate microstructures on its back surface 113 during the thinning process (such as a polishing process, but not limited to this), the protective layer 140a, directly disposed on the back surface 113 of the electronic unit 110, can fill in these microstructures. The microstructures can be penetrated by the protective layer 140a, thereby increasing the adhesion strength of the protective layer 140a and improving the structural reliability of the electronic unit 110. In one embodiment, the protective layer 140a can completely cover the back surface 113 of the electronic unit 110, meaning that the size of the protective layer 140a is greater than or equal to the back surface 113 of the electronic unit 110. In one embodiment, the protective layer 140a can partially cover the back surface 113 of the electronic unit 110, meaning that the size of the protective layer 140a is smaller than the back surface 113 of the electronic unit 110. In one embodiment, the protective layer 140a is rectangular in shape when viewed in cross-section, but is not limited thereto.

[0093] In one embodiment, the protective layer 140a may be made of, for example, an organic or inorganic material. In another embodiment, the protective layer 140a may be made of, for example, a composite material or a polymer, wherein the composite material may be, for example, diamond-like carbon, graphene, cuprone composite, or thermally conductive silicone; and the polymer may be, for example, polyimide (PI), resin, polyethylene terephthalate (PET), polycarbonate (PC), photoresist (PR), or Ajinomoto build-up film (ABF), but is not limited thereto. In one embodiment, the Young's coefficient of the protective layer 140a is between 55 GPa and 100 GPa. In another embodiment, the Young's coefficient of the protective layer 140a is between 70 GPa and 90 GPa. In one embodiment, the coefficient of thermal expansion of the protective layer 140a is, for example, between 2.5 ppm / C and 21 ppm / C. In another embodiment, the coefficient of thermal expansion of the protective layer 140a is, for example, between 5 ppm / C and 15 ppm / C. In one embodiment, the insulating layer 116 of the electronic unit 110 has a first thickness T1, while the protective layer 140a has a second thickness T2, wherein the second thickness T2 is greater than the first thickness T1. In one embodiment, the thickness T2 of the protective layer 140a is, for example, between 0.2 mm and 0.5 mm. In one embodiment, the coefficient of thermal expansion of the protective layer 140a is different from that of the insulating layer 116 of the electronic unit 110. In one embodiment, the coefficient of thermal expansion of the protective layer 140a is greater than that of the insulating layer 116 of the electronic unit 110. In one embodiment, an infrared spectrometer (IR), an energy-dispersive X-ray spectroscopy (EDS), or other suitable methods can be used to perform material analysis and / or elemental analysis on the component to determine its composition. Then, the corresponding coefficient of thermal expansion (CTE) of the component can be obtained by looking up a table, thus obtaining the component's coefficient of thermal expansion. The component's coefficient of thermal expansion affects its degree of expansion and contraction, such as deformation.The larger the coefficient of thermal expansion of a component, the greater its deformation with temperature; conversely, the smaller the coefficient of thermal expansion, the smaller its deformation with temperature.

[0094] Please refer to this again. Figure 1 In this embodiment, the first thermally conductive component 150a is located between the second thermally conductive component 160a and the protective layer 140a. In one embodiment, the first thermally conductive component 150a and the protective layer 140a are conformally disposed and their edges are flush, meaning that the first thermally conductive component 150a exposes the surrounding surface 141a of the protective layer 140a. In one embodiment, the first thermally conductive component 150a is, for example, a thermal interface material (TIM), and the second thermally conductive component 160a is, for example, an externally attached thermally conductive component, fixed to the protective layer 140a by the first thermally conductive component 150a. In one embodiment, the first thermally conductive component 150a is, for example, a seed layer, and the second thermally conductive component 160a is formed on the first thermally conductive component 150a through processes such as electroplating and photolithography. In one embodiment, the thermal conductivity of the second thermally conductive component 160a may be less than that of the first thermally conductive component 150a. In one embodiment, the material of the second heat-conducting component 160a may be, for example, copper or aluminum, but is not limited thereto.

[0095] Furthermore, the second heat-conducting component 160a in this embodiment may include a first portion 162a and a plurality of second portions 164, wherein the first portion 162a is located between the first heat-conducting component 150a and the second portions 164, and the plurality of second portions 164 are connected to the first portion 162a. In one embodiment, the first portion 162a may extend, for example, along the X direction, while the second portions 164 are separated from each other and may extend, for example, along the Z direction. In one embodiment, in cross-sectional view, the shape of the second portions 164 may be, for example, a square, rectangle, trapezoid, wedge, cone, triangle, or a combination of the above shapes, which can increase the heat dissipation surface area.

[0096] Additionally, the semiconductor device 100a of this embodiment also includes a connector 170 disposed on and electrically connected to the circuit structure 130. The semiconductor device 100a can be electrically connected to an external circuit via the connector 170. In one embodiment, the connector 170 may be, for example, tin, nickel, gold, silver, palladium, copper, gallium, alloys thereof, or combinations thereof, but is not limited thereto. In one embodiment, the connector 170 may be, for example, a solder ball, but is not limited thereto.

[0097] In this embodiment, the protective layer 140a is located on the second side S2 of the encapsulation layer 120, and a first thermal conductive component 150a and a second thermal conductive component 160a with different thermal conductivity are sequentially disposed on the protective layer 140a. The protective layer 140a can improve and / or enhance the fracture resistance of the electronic unit 110, while the second thermal conductive component 160a can enhance the heat dissipation performance, so that the semiconductor device 100a of this embodiment can have better structural reliability and heat dissipation effect.

[0098] It should be noted that the following embodiments use the component reference numerals and some content from the foregoing embodiments, with the same reference numerals used to represent the same or similar components, and descriptions of the same technical content omitted. For explanations of the omitted parts, please refer to the foregoing embodiments; these will not be repeated in the following embodiments.

[0099] Figure 2 This is a cross-sectional schematic diagram of a semiconductor device according to another embodiment of this disclosure. Please also refer to... Figure 1 and Figure 2 In this embodiment, the semiconductor device 100b and Figure 1 Similar to the semiconductor device 100a, the difference is that in this embodiment, the protective layer 140b extends further to cover the second side S2 of the encapsulation layer 120, while the first thermal conductive component 150b extends to cover a portion of the surrounding surface 141b of the protective layer 140b.

[0100] Figure 3 This is a cross-sectional schematic diagram of a semiconductor device according to another embodiment of this disclosure. Please also refer to... Figure 1 and Figure 3 In this embodiment, the semiconductor device 100c and Figure 1Similar to the semiconductor device 100a, the difference lies in that, in this embodiment, viewed in cross-section, the protective layer 140c has a trapezoidal shape, and the first thermally conductive component 150c conformally completely covers the surrounding surface 141c of the protective layer 140c and extends to the second side S2 of the encapsulation layer 120. A portion 162c of the second thermally conductive component 160c is also thickened and extends to the edge of the first thermally conductive component 150c. In one embodiment, the second thermally conductive component 160c may include at least one uneven structure 165 to increase the heat dissipation area. In one embodiment, the edge of the second thermally conductive component 160c may be aligned with the edge of the first thermally conductive component 150c. Furthermore, the semiconductor device 100c of this embodiment also includes a barrier layer 180 surrounding the first thermally conductive component 150c and the second thermally conductive component 160c. In one embodiment, along direction X, the first distance G1 between the barrier layer 180 and the first thermally conductive component 150c is less than or equal to the second distance G2 between the barrier layer 180 and the second thermally conductive component 160c. In other words, the barrier layer 180 surrounds the first thermally conductive component 150c and the second thermally conductive component 160c and does not contact the protective layer 140c.

[0101] Figure 4 This is a cross-sectional schematic diagram of a semiconductor device according to another embodiment of this disclosure. Please also refer to... Figure 3 and Figure 4 In this embodiment, the semiconductor device 100d and Figure 3 Similar to the semiconductor device 100c, the difference lies in that: in this embodiment, the semiconductor device 100d further includes a third thermally conductive component 190, which penetrates the encapsulation layer 120 and connects the first thermally conductive component 150c to the conductive layer 132 of the circuit structure 130. In one embodiment, the third thermally conductive component 190 may have the functions of conducting electricity, conducting heat, or conducting electricity and conducting heat.

[0102] Figures 5A to 5C This is a partial enlarged cross-sectional schematic diagram of several semiconductor devices according to various embodiments of this disclosure. Please refer to [the original text]. Figure 5A In this embodiment, a microstructure R is formed on the back surface 113 of the electronic unit 110 through grinding, and the protective layer 140e is directly disposed on the back surface 113 of the electronic unit 110 and penetrates into the microstructure R to increase the adhesion strength of the protective layer 140e, thereby improving structural reliability. Furthermore, the protective layer 140e in this embodiment is more robust than... Figure 1 The protective layer 140a also has a rough surface RS1, which is composed of a plurality of microstructures 142e. In cross-section, the microstructures 142e may be, for example, semi-circular or semi-elliptical. The protective layer 140e with microstructures 142e can increase the heat dissipation area and enhance the heat conduction effect. In one embodiment, the surface roughness of the back surface 113 of the electronic unit 110 may be less than the roughness of the rough surface RS1 of the protective layer 140e.

[0103] Next, please refer to the following: Figure 5A and Figure 5B This embodiment is similar to the embodiments described above, except that the protective layer 140f in this embodiment also has a rough surface RS2, which is composed of multiple microstructures 142f. In cross-section, the microstructures 142f can be, for example, triangular or serrated. The protective layer 140f with microstructures 142f can increase the heat dissipation area and enhance the heat conduction effect. In one embodiment, the surface roughness of the back surface 113 of the electronic unit 110 can be less than the roughness of the rough surface RS2 of the protective layer 140f.

[0104] Next, please refer to the following: Figure 5A and Figure 5C This embodiment is similar to the above embodiment, except that: in this embodiment, a conductor layer 195 is further included between the electronic unit 110 and the protective layer 140e, wherein the conductor layer 195 is disposed on the back surface 113 of the electronic unit 110 to cover the microstructure R on the back surface 113 of the electronic unit 110.

[0105] In one embodiment, the protective layer may be a single-layer structure or a multi-layer structure. In one embodiment, the protective layer is a multi-layer structure, which is formed by stacking multiple films along the Z direction. In one embodiment, the protective layer may have a flat surface. In one embodiment, the protective layer may have a rough surface, wherein the rough surface may be composed of microstructures. In short, the protective layer of this embodiment can improve and / or enhance the fracture resistance of the electronic unit 110, and can improve the heat dissipation effect by forming microstructures.

[0106] In this embodiment, after the polishing process of panel-level packaging, if the microstructure R of electronic unit 110 is to be measured, the protective layer disposed on the back surface 113 of electronic unit 110 will be removed first, and then the microstructure R will be measured. Figure 6A This is a top view schematic diagram of a semiconductor device according to an embodiment of the present disclosure. Figure 6B yes Figure 6A A partial cross-sectional schematic diagram of a semiconductor device. In some embodiments, a complete region of the wafer is provided. In some embodiments, a partial region of the wafer is provided.

[0107] Please also refer to Figure 6A and Figure 6BIn this embodiment, the electronic unit 110 with its protective layer removed and the encapsulation layer 120 surrounding the electronic unit 110 are disposed on the carrier plate 10 and fixed to the carrier plate 10 by the adhesive layer 20. At this time, the back surface 113 of the electronic unit 110 and the second side S2 of the encapsulation layer 120 are exposed, while the active surface 117 of the electronic unit 110 and the first side S1 of the encapsulation layer are attached to the adhesive layer 20. In one embodiment, the carrier plate 10 may be, for example, a glass substrate, a printed circuit board, a fiberglass (FR4) substrate, a steel substrate, or other suitable substrate, and is not limited thereto. In one embodiment, the adhesive layer 20 may include, for example, an ultraviolet (UV) release film, a heat release tape (HRT), other suitable materials, or a combination of any two of the above. By providing the adhesive layer 20 on the carrier plate 10, it can be effectively separated from the electronic unit 110 subsequently.

[0108] Next, the microstructure R features of the back surface 113 of the electronic unit 110 were measured using a microscope. Please refer to [reference needed]. Figure 6A Viewed from above, the electronic unit 110 has a component length L1 and a microstructure length L2, wherein the microstructure length L2 is less than 1 / 2 or 1 / 3 of the component length L1. Here, the component length L1 refers to the longest length of the electronic unit 110 in the top view direction. In some embodiments, the component length L1 may be, for example, the straight-line distance between two opposite sides of the electronic unit 110. In another embodiment, the component length L1 may be, for example, the straight-line distance between two vertices of the electronic unit 110. The microstructure length L2 refers to the longest scratch in a single electronic unit 110, i.e., the distance between the two endpoints. Please refer to... Figure 6B In cross-sectional view, the electronic unit 110 has a component depth D1 and a microstructure depth D2, where the microstructure depth D2 is less than 1 / 2 or 1 / 3 of the component depth D1. In one embodiment, the component depth D1 may be, for example, the length of the electronic unit 110 in the normal direction. In other embodiments, the component depth D1 may refer to the length of the semiconductor substrate 111 in the normal direction. The microstructure depth D2 refers to the deepest scratch in a single electronic unit 110, for example, the distance between the two endpoints of the electronic unit 110 in the normal direction. The microstructure depth D2 may be, for example, less than or equal to 1 micrometer, but is not limited thereto.

[0109] Figures 7A to 7C This is a cross-sectional schematic diagram of a method for fabricating a semiconductor device according to an embodiment of this disclosure. Please refer to [the previous text]. Figure 7ARegarding the method for fabricating the semiconductor device in this embodiment, firstly, an electronic unit 110 is disposed on a temporary carrier (not shown) via a temporary adhesive layer (not shown). Next, an encapsulation layer 120 is formed on the electronic unit 110, wherein the encapsulation layer 120 surrounds the electronic unit 110 to form an encapsulation structure. Immediately afterwards, another temporary carrier (not shown) is provided, and the temporary adhesive layer and the temporary carrier are removed. The encapsulation structure is temporarily fixed to the other temporary carrier, and the back surface 113 of the electronic unit 110 is moved away from the temporary carrier. The method described above, where the electronic unit 110 is encapsulated on the temporary carrier with its active surface 117 initially moving away from the temporary carrier, can be referred to as a face-up process. According to some embodiments, the electronic unit 110 can also be encapsulated on the temporary carrier with its active surface 117 facing the temporary carrier, thereby exposing the back surface 113 of the electronic unit 110; this can be referred to as a face-down process.

[0110] In one embodiment, the temporary carrier may be, for example, a glass substrate, a printed circuit board, a fiberglass (FR4) substrate, a steel substrate, or other suitable substrate, without limitation. In one embodiment, the encapsulation layer 120 may be, for example, a molding compound, epoxy resin, other suitable encapsulation materials, or a combination thereof, without limitation. According to some embodiments, the release mechanism of the adhesive layer may include photorelease, thermal release, other suitable mechanisms, or any combination of the above. For example, depending on the release mechanism, the adhesive layer may be paired with different types of temporary carriers; for example, a photorelease type adhesive layer may be paired with a transparent glass substrate, while a thermal release type adhesive layer may be paired with a steel plate. The adhesive layer may include, for example, an ultraviolet (UV) release film, a heat release tape (HRT), other suitable materials, or any combination of the above. By providing an adhesive layer on the temporary carrier, the encapsulation structure can be effectively separated.

[0111] According to some embodiments, when a chip-down process is used, after forming the package structure through a molding process, the package structure is flipped, and the opening of the insulating layer 116 of the electronic unit 110 can expose the pad 112. When a chip-up process is used, and the package layer 120 overlaps the pad 112, or the package layer 120 and the insulating layer 116 simultaneously overlap the pad 112, a patterning process must be subsequently performed to expose the pad 112 to facilitate subsequent processes. The patterning step may include photolithography, etching, development, laser, plasma cleaning, a combination of the above, or other suitable steps, and is not limited thereto.

[0112] Next, please refer to Figure 7AThe encapsulation layer 120 is ground until the back surface 113 of the electronic unit 110 is exposed, thereby forming an encapsulation layer 120 having a first side S1 and a second side S2 opposite to each other. After grinding, a plurality of microstructures R are formed on the back surface 113 of the electronic unit 110. In one embodiment, the depth of the microstructures R may be, for example, less than or equal to 1 micrometer, but is not limited thereto.

[0113] Next, please refer to Figure 7A A protective layer 140 is formed on the second side S2 of the encapsulation layer 120. In one embodiment, the protective layer 140 has a flat surface relatively distant from the second side S2 of the encapsulation layer 120. In one embodiment, the protective layer 140 may have microstructures, such as... Figure 5A Microstructure 142e or Figure 5B The microstructure 142f is described, but not limited thereto. In one embodiment, the protective layer 140 is formed by methods including taping, injection molding, slit coating, spin coating, spinless coating, electroplating, chemical plating, deposition (CVD, PVD, ALD, MOCVD, MPCVD), lamination, or dipping, or by using a laser beam, microwave, or plasma, but not limited thereto. In one embodiment, the protective layer 140 may be made of, for example, organic or inorganic materials. In one embodiment, the protective layer 140 may be made of, for example, a composite material or a polymer. The composite material may be, for example, diamond-like carbon, graphene, copper monoxide composite, or thermally conductive silicone. The polymer may be, for example, polyimide (PI), resin, polyethylene terephthalate (PET), polycarbonate (PC), photoresist (PR), or Ajinomoto build-up film (ABF), but is not limited thereto.

[0114] Next, please refer to Figure 7AA first thermally conductive component 150 is formed on the protective layer 140. In one embodiment, the size of the first thermally conductive component 150 may be greater than or equal to the size of the protective layer 140. Next, a second thermally conductive component 160 is formed on the first thermally conductive component 150, wherein the thermal conductivity of the second thermally conductive component 160 is different from that of the first thermally conductive component 150. In one embodiment, the thermal conductivity of the second thermally conductive component 160 is different from that of the first thermally conductive component 150.

[0115] In one embodiment, the first thermally conductive component 150 may, for example, have a seed material layer that is a metal layer, which may be a single layer or a composite layer of multiple sublayers composed of different materials. In one embodiment, the seed material layer may include a titanium layer and a copper layer above the titanium layer, and may be formed using, for example, PVD or similar methods. Next, a patterned photoresist layer is formed on the seed material layer, wherein the patterned photoresist layer exposes a portion of the seed material layer. Next, using the patterned photoresist layer as an electroplating mask, a metal material is electroplated onto the seed material layer exposed by the patterned photoresist layer. Immediately afterwards, the patterned photoresist layer and the seed material layer below it are removed to form the second thermally conductive component 160 and the first thermally conductive component 150 below it. It should be noted that the second thermally conductive component 160 is provided by electroplating as described above, but is not limited thereto. In other embodiments, the first thermally conductive component 150 may also be, for example, a thermal interface material (TIM), and the second thermally conductive component 160 is fixed to the protective layer 140 through the first thermally conductive component 150. That is, the second thermally conductive component 160 is an externally attached thermally conductive component.

[0116] Next, a buffer layer 185 is formed on the second side S2 of the encapsulation layer 120, wherein the buffer layer 185 covers the protective layer 140, the first thermally conductive component 150, and the second thermally conductive component 160. At this time, the top surface 187 of the buffer layer 185 and the top surface 161 of the second thermally conductive component 160 have a height difference H, wherein the top surface 187 of the buffer layer 185 is higher than the top surface 161 of the second thermally conductive component 160. In one embodiment, the material of the buffer layer 185 is, for example, an organic material or an inorganic material, but is not limited thereto.

[0117] Next, please refer to the following: Figure 7A and Figure 7B Flip Figure 7A The structure is such that the first side S1 of the encapsulation layer 120 faces upward. Next, a circuit structure 130 is formed on the first side S1 of the encapsulation layer 120, wherein the circuit structure 130 is electrically connected to the electronic unit 110.

[0118] Afterwards, please refer to the following: Figure 7B and Figure 7C FlipFigure 7B The structure is such that the second side S2 of the encapsulation layer 120 faces upward. Next, the buffer layer 185 is thinned to expose the top surface 161 of the second thermal conductive component 160. Finally, the second thermal conductive component 160 can be patterned to form fins according to usage requirements, and connectors can be selectively formed on the circuit structure 130 for electrical connection with external circuits, thereby completing the fabrication of the semiconductor device.

[0119] Figure 8 This is a cross-sectional schematic diagram of a semiconductor device according to another embodiment of this disclosure. Please also refer to... Figure 1 and Figure 8 In this embodiment, the semiconductor device 100g and Figure 1 Similar to the semiconductor device 100a, the difference lies in that: in this embodiment, the semiconductor device 100g further includes a third thermal conductive component 190, which is disposed adjacent to the electronic unit 110, and the encapsulation layer 120 surrounds the third thermal conductive component 190. In this embodiment, the third thermal conductive component 190 surrounds the electronic unit 110, and the encapsulation layer 120 covers the surrounding surfaces of the electronic unit 110 and the third thermal conductive component 190. One end of the third thermal conductive component 190 directly contacts the circuit structure 130, while the other end of the third thermal conductive component 190 extends to the second side S2 of the encapsulation layer 120. That is, the heat generated by the electronic unit 110 can be directly transferred to the outside through the first thermal conductive component 150g and the second thermal conductive component 160g disposed on its back surface 113, and can also be transferred to the outside through the circuit structure 130 disposed on its active surface 117 via the third thermal conductive component 190, thereby improving the heat dissipation effect and giving the electronic device 100g better heat dissipation efficiency.

[0120] Furthermore, in this embodiment, the size of the protective layer 140g may be slightly larger than the size of the back surface 113 of the electronic unit 110. The first thermally conductive component 150g located on the protective layer 140g may have a first limiting portion 153, and the second thermally conductive component 160g may have a second limiting portion 163, wherein the first limiting portion 153 and the second limiting portion 163 cooperate with each other to fix the second thermally conductive component 160g onto the first thermally conductive component 150g. In one embodiment, one of the first limiting portion 153 and the second limiting portion 163 is a groove, and the other of the first limiting portion 153 and the second limiting portion 163 is a protrusion. In one embodiment, the first limiting portion 153 is a protrusion, and the second limiting portion 163 is a groove. Furthermore, the semiconductor device 100g in this embodiment also includes a buffer layer 185 disposed on the second side S2 of the encapsulation layer 120, wherein the buffer layer 185 surrounds the protective layer 140, the first thermally conductive component 150g, and the second thermally conductive component 160g. At this time, the top surface 189 of the buffer layer 185 is flush with the top surface 161g of the second thermally conductive component 160g, but is not limited thereto.

[0121] Please refer to this again. Figure 8 In this embodiment, the semiconductor device 100g further includes an electronic unit 110', an encapsulation layer 120', a circuit structure 130', a protective layer 140', a connector 170', and a third conductive component 190'. The encapsulation layer 120' surrounds the electronic unit 110' and has a first side S1' and a second side S2' opposite to each other. The circuit structure 130' is disposed on the first side S1' of the encapsulation layer 120' and electrically connected to the electronic unit 110'. The protective layer 140' is disposed on the second side S2' of the encapsulation layer 120' and directly covers the back surface 113' of the electronic unit 110'. The third thermally conductive component 190' is disposed adjacent to the electronic unit 110', and the encapsulation layer 120' surrounds the third thermally conductive component 190'. The third thermally conductive component 190' surrounds the electronic unit 110', and the encapsulation layer 120' covers the surrounding surfaces of the electronic unit 110' and the third thermally conductive component 190'. One end of the third thermally conductive component 190' directly contacts the circuit structure 130', while the other end of the third thermally conductive component 190' is exposed outside the second side S2' of the encapsulation layer 120', and the connector 170 is directly connected to the other end of the third thermally conductive component 190'. The connector 170' connects to the circuit structure 130', allowing the semiconductor device 100g to be electrically connected to an external circuit via the connector 170'. Furthermore, the semiconductor device 100g of this embodiment also includes an adhesive 197 disposed between the circuit structure 130 and the encapsulation layer 120', and at least covers the connector 170 to protect the connector 170 and ensure electrical connection between the electronic unit 110 and the electronic unit 110'. In short, the semiconductor device 100g of this embodiment is constructed by vertically stacking the electronic units 110 and 110' in the Z direction.

[0122] In summary, in the embodiments disclosed herein, the protective layer is located on the second side of the encapsulation layer, and a first thermal conductive component and a second thermal conductive component with different thermal conductivity are sequentially disposed on the protective layer. The protective layer can improve and / or enhance the fracture resistance of the electronic unit, while the thermal conductive components enable the semiconductor device disclosed herein to have better heat dissipation.

[0123] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions disclosed herein, and are not intended to limit them. Although the present disclosure has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some or all of the technical features therein. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments disclosed herein.

Claims

1. A semiconductor device, characterized in that, include: Electronic unit; An encapsulation layer surrounds the electronic unit and has a first side and a second side opposite to each other; The circuit structure is disposed on the first side of the encapsulation layer and electrically connected to the electronic unit; A protective layer is disposed on the second side of the encapsulation layer; A first thermally conductive component is disposed on the protective layer; as well as A second heat-conducting component is disposed on the first heat-conducting component, wherein the thermal conductivity of the second heat-conducting component is different from that of the first heat-conducting component.

2. The semiconductor device according to claim 1, characterized in that, The thermal conductivity of the second thermally conductive component is less than that of the first thermally conductive component.

3. The semiconductor device according to claim 1, characterized in that, Also includes: A barrier layer surrounds the first thermally conductive component and the second thermally conductive component.

4. The semiconductor device according to claim 3, characterized in that, The first distance between the barrier layer and the first heat-conducting component is less than or equal to the second distance between the barrier layer and the second heat-conducting component.

5. The semiconductor device according to claim 1, characterized in that, Viewed from above, the electronic unit has a component length and a microstructure length, and the microstructure length is less than 1 / 2 or 1 / 3 of the component length.

6. The semiconductor device according to claim 1, characterized in that, In cross-section, the electronic unit has a component depth and a microstructure depth, wherein the microstructure depth is less than 1 / 2 or 1 / 3 of the component depth.

7. The semiconductor device according to claim 1, characterized in that, The electronic unit includes an insulating layer having a first thickness, and a protective layer having a second thickness, wherein the second thickness is greater than the first thickness.

8. The semiconductor device according to claim 1, characterized in that, The protective layer has a rough surface, which includes multiple microstructures.

9. A method for manufacturing a semiconductor device, characterized in that, include: An encapsulation layer is formed on the electronic unit, the encapsulation layer surrounding the electronic unit; Grind the encapsulation layer until the back side of the electronic unit is exposed; A circuit structure is formed on the first side of the encapsulation layer, wherein the circuit structure is electrically connected to the electronic unit; A protective layer is formed on the second side of the encapsulation layer; A first thermally conductive component is formed on the protective layer; as well as A second thermally conductive component is formed on the first thermally conductive component, wherein the thermal conductivity of the second thermally conductive component is different from that of the first thermally conductive component.

10. The method for manufacturing a semiconductor device according to claim 9, characterized in that, The protective layer is made of composite materials or polymers.

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