Electric meter sampling filter chip and system integrated with programmable anti-aliasing filter

Abstract

The application discloses an electric meter sampling filter chip and system integrated with a programmable anti-aliasing filter, relates to the field of electric energy metering chips, and comprises a programmable anti-aliasing filter module, a digital control and interface module and a cooperative control unit. Through binary weighting control of a switch capacitor array, the cutoff frequency can be dynamically adjusted within the range of 1 kHz-100 kHz. The switching of three modes of Bessel, Butterworth and Chebyshev is physically realized through a reconstruction feedback network. The programmable AAF, ADC, control logic and digital interface are integrated on a single chip, thereby reducing the number of external components such as RC networks and operational amplifiers. Through FFT analysis of ADC sampling data, the signal-to-noise ratio is calculated in real time, and the filter mode is automatically switched. After configuration is completed, a hardware interrupt pin is triggered to replace MCU polling. The frequency response of the switch capacitor array is accurately controllable through laser trimming.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of electric energy metering chips, in particular to an electric meter sampling filter chip and system integrated with a programmable anti-aliasing filter. BACKGROUND

[0002] As a core component of a smart meter, an electric energy metering chip needs to measure parameters such as voltage, current, and power with high precision. An anti-aliasing filter (AAF) is a key module in an analog signal chain, responsible for suppressing high-frequency noise and aliasing interference. The current traditional technology has the following bottlenecks in the context of smart grids and new energy access:

[0003] 1. Fixed filter parameters: Traditional metering chips (such as TIMSP430FE and ADIADE series) integrate fixed-parameter AAFs, with the cutoff frequency, type (Butterworth / Bessel), and order determined at the design stage, which cannot adapt to complex grid environments (such as industrial harmonics and sudden impulse noise).

[0004] 2. Defects of external filtering schemes: Some systems adjust filtering characteristics through external RC networks, increasing hardware complexity and cost, and cannot dynamically adapt to real-time noise changes.

[0005] 3. Incompatibility of cross-domain technologies: Programmable filters in the audio / communication field (such as audio codecs and LTC1569) only focus on signal fidelity, do not meet the core requirements of electric energy metering for phase accuracy (error ≤ 0.1°) and dynamic range (1000:1 current measurement), and require an external MCU, resulting in low integration.

[0006] 4. Complex grid noise: The increasing proportion of new energy grid connection (2024 data ≥ 35%) leads to a surge in grid harmonics and switching noise (typical value of 150kHZ), making it difficult for fixed filters to balance "pure grid wideband requirements" and "high-noise grid narrowband requirements".

[0007] 5. Conflict between metering accuracy and real-time performance: Traditional fixed filters have a metering error ≥ 0.5% under high-frequency interference, and parameter adjustment requires downtime and re-soldering components, which cannot meet the "online real-time optimization" requirements of smart grids. SUMMARY

[0008] The present application aims to provide an electric meter sampling filter chip and system integrated with a programmable anti-aliasing filter to solve the problems raised in the background.

[0009] To achieve the above-mentioned purpose, the present application provides the following technical solutions: an electric meter sampling filter chip and system integrated with a programmable anti-aliasing filter, comprising:

[0010] The programmable anti-aliasing filter module is preliminarily isolated from other circuit regions by a guard ring structure, and the programmable anti-aliasing filter module comprises a switched capacitor array;

[0011] The digital control and interface module comprises a digital control interface, and the digital control interface is configured as an I2C / SPI interface which communicates with an external microcontroller.

[0012] The cooperative control unit is placed in a deep N-well isolation structure to form an independent isolated island, and the cooperative control unit comprises a multi-modal operational amplifier network and a modulator.

[0013] The analog part in the programmable anti-aliasing filter module and the cooperative control unit is powered by a first power supply domain, and the digital control and interface module is independently powered by a second power supply domain.

[0014] The meter sampling and filtering chip integrated with the programmable anti-aliasing filter is implemented by using a 180 nm BCD process to realize analog-digital isolation.

[0015] Preferably, the switched capacitor array is composed of a plurality of capacitor units and a switch network, and the switched capacitor array adopts an MIM capacitor array and a laser trimming technology.

[0016] Preferably, the multi-modal operational amplifier network is a programmable feedback network, and the programmable feedback network is configured in a Bessel filter, a Butterworth filter and a Chebyshev filter mode.

[0017] The Bessel mode optimizes phase linearity, and the phase error is not greater than 0.1°.

[0018] The Butterworth mode optimizes passband flatness.

[0019] The Chebyshev mode optimizes high-frequency roll-off, and the suppression capability for 150 kHz noise reaches -30 dB.

[0020] Preferably, the digital control interface integrates a cyclic redundancy check value checking module and a state interrupt pin to set the cutoff frequency, the filter type and the order of the filter in a programmed manner.

[0021] The digital control and interface module further comprises an operational amplifier mode register which is physically connected with the multi-modal operational amplifier network.

[0022] Preferably, the synergic control unit further comprises a noise monitoring module and a non-volatile memory, the noise monitoring module calculates the signal-to-noise ratio by fast Fourier transform analysis of the modulator sampling data, and automatically switches the filter mode according to the signal-to-noise ratio threshold, and the non-volatile memory is located at the edge of the digital area and is isolated by a deep N-well isolation structure, and is used to store the trimming values of the operational amplifier and the switched capacitor array.

[0023] Preferably, the method comprises the following steps:

[0024] S1 noise monitoring: collecting original noise signals in the environment;

[0025] S2 parameter configuration: setting sampling frequency, filtering threshold and modulator precision parameters;

[0026] S3 filter processing: removing interference noise in the signal;

[0027] S4 modulator sampling: converting the filtered analog signal into a digital signal;

[0028] S5 metering output: outputting noise decibel value and frequency distribution metering result;

[0029] S6 result application storage: storing the data.

[0030] Preferably, the parameter configuration stage comprises initialization of the switched capacitor array and control code calculation:

[0031] After starting execution, the switched capacitor array is configured, the key parameters are initialized, the input cutoff frequency control code is output, the capacitor array control register is set, and the unit capacitor is defined as , corresponding to the physical value 0.5pF, using Q15 fixed-point number format, the variable of the cumulative total capacitor is initialized to 0;

[0032] Looping and adding weights to the control code, looping, index i from 0 to 3, checking each bit of the cutoff frequency control code in turn;

[0033] i is the bit of the frequency control code being checked, i=0 indicates checking the lowest bit, and i=3 indicates checking the highest bit;

[0034] In each loop, the cutoff frequency control code is used to check whether the i-th bit is 1 by bit operation;

[0035] If it is 1, an accumulation operation is performed, and the accumulated value is the unit capacitor multiplied by a weight, a binary weighted design;

[0036] The calculation formula of the total capacitor value is as follows:

[0037]

[0038] The total calculated capacitance value; The unit capacitance; , , , The value of each bit representing a 4-bit frequency control code, each bit can only be 0 or 1; , , , The weight in "binary weighting", corresponding to 1, 2, 4, 8 respectively;

[0039] If The bit is activated, calculate And add to the upper Upper;

[0040] If The bit is not activated, the accumulation is 0, then skip the bit and do not accumulate;

[0041] Check if the loop ends when i≥4, apply laser trimming compensation, and output to the register, ;

[0042] ;

[0043] The value written into the hardware capacitance array control register, The ideal capacitance value calculated by software, The error value of the individual hardware, Represents the first configuration register, Represents the second configuration register.

[0044] Preferably, the noise monitoring stage includes a signal-to-noise ratio adaptive switching mechanism:

[0045] The power grid signal is input, and the modulator inside the chip starts to work, samples the input analog signal, and converts it into a digital signal waveform. The microcontroller performs fast Fourier transform analysis on the digital signal sampled by the modulator to calculate the current noise frequency;

[0046] The system calculates the signal-to-noise ratio of the current signal and compares it with the preset threshold;

[0047] When the signal-to-noise ratio is <70 dB, it is a high-noise environment: the noise is large, the signal quality is poor, the "Bessel wideband mode" cutoff frequency is selected: 50kHZ, the filter chip is configured through the I2C / SPI interface, the modulator sampling rate is maintained to 100KHZ, at the same time the interrupt pin triggers a hardware interrupt to notify the microcontroller that the configuration is completed, and the microcontroller reads the status register to confirm the configuration, and the modulator samples the input analog signal in real time.

[0048] When the signal-to-noise ratio is ≥70 dB, it is a low-noise environment: the signal quality is high, the "Chebyshev narrowband mode" cutoff frequency is selected: 100kHZ, the filter chip is configured through the I2C / SPI interface, the modulator sampling rate is updated to 200KHZ, at the same time the interrupt pin triggers a hardware interrupt to notify the microcontroller that the configuration is completed, the microcontroller reads the status register to confirm the configuration, and the modulator samples the input analog signal in real time.

[0049] Preferably, different configuration modes are selected according to the filter type;

[0050] When the Bessel mode is selected, the input is input to the multi-modal operational amplifier network, the operational amplifier feedback resistor Rf is modified to 10kΩ, the LC network is disabled, and the operational amplifier control register value is output;

[0051] When the Butterworth mode is selected, the input is input to the multi-modal operational amplifier network, the operational amplifier feedback resistor Rf is modified to 15kΩ, and the operational amplifier control register value is output;

[0052] When the Chebyshev mode is selected, the input is input to the multi-modal operational amplifier network, the operational amplifier feedback resistor Rf is modified to 20kΩ, the LC network is enabled, and the operational amplifier control register value is output.

[0053] Preferably, data is received through the I2C / SPI interface, before sending the data, the cyclic redundancy check value of the data is calculated, the cutoff frequency code and the filter type are combined, the I2C interface is called to write the cutoff frequency code and the filter type into register 0x11, the filter type occupies the high 4 bits, and the cutoff frequency code occupies the low 4 bits, the I2C interface is called to write the order into register 0x11, and the data and the cyclic redundancy check value are sent to the filter chip together;

[0054] After receiving the filter chip, the cyclic redundancy check value is calculated and compared with the received cyclic redundancy check value, and only when the matching is successful, the chip can be truly applied to the configuration, and if the matching fails, the chip ignores this write and reports an error;

[0055] Hardware interrupts are used instead of software polling to achieve efficient synchronization between the microcontroller and the filter chip;

[0056] The microcontroller does not need to wait: after the configuration instruction is issued, the MCU can continue to perform other tasks without constantly querying whether the filter is configured.

[0057] Technical effects and advantages of the present application:

[0058] 1. Breakthrough parameter solidification bottleneck, realize dynamic adaptive filtering:

[0059] Programmable filter core: through the binary weighted control of the switched capacitor array, the cutoff frequency can be dynamically adjusted in the range of 1 kHz-100 kHz, adapting to the wideband demand from the power fundamental wave (50 Hz) to high frequency noise (150 kHz);

[0060] Multi-modal operational amplifier network: by reconstructing the feedback network (modifying the Rf resistance value, enabling the LC network), physically realizing the switching of three modes of Bessel (phase error ≤0.1°), Butterworth (passband flatness optimization), and Chebyshev (150 kHz noise suppression-30 dB);

[0061] 2. Eliminate external scheme defects, improve integration and reliability:

[0062] Monolithic integrated architecture: integrating programmable AAF, modulator core architecture, control logic, and digital interface on a single chip, reducing the number of external components such as RC networks and operational amplifiers;

[0063] Efficient digital interface configuration: through I2C / SPI interface step-by-step register writing (such as 0x11 merging filter type and cutoff frequency code), supporting CRC check and interrupt response, configuration response time ≤200 μs;

[0064] 3. Solve cross-domain compatibility problems and meet special needs of metrology:

[0065] Phase accuracy guarantee: Bessel mode optimizes phase linearity (0.1° error), ensuring power calculation accuracy;

[0066] Dynamic range expansion: SNR ≥78 dB, GBW >10 MHz, supporting 1000:1 current dynamic range measurement, better than audio filters;

[0067] 4. Respond to complex power grid noise and achieve intelligent anti-interference:

[0068] Noise monitoring and adaptation: through FFT analysis of ADC sampling data, real-time calculation of signal-to-noise ratio, and automatic switching of filter modes (such as switching to Bessel wideband mode when SNR <70 dB, and switching to Chebyshev narrowband mode when SNR ≥70 dB);

[0069] Isolation design noise suppression: Guard Ring isolation layer runs through the chip periphery, Deep N-Well forms an independent isolation island, reducing the interference of digital power supply noise on analog signals;

[0070] 5. Balance precision and real-time, support smart grid:

[0071] Fast response mechanism: hardware interrupt pin (INT_PIN) triggers notification within 200us after configuration is completed, replacing MCU polling, meeting the smart grid millisecond-level regulation and control demand;

[0072] Laser trimming ensures precision: switch capacitor array is trimmed by laser (precision ±0.1%), ensuring accurate and controllable frequency response. BRIEF DESCRIPTION OF DRAWINGS

[0073] Figure 1 The physical architecture diagram of the programmable anti-aliasing filter chip of the application is shown in the figure;

[0074] Figure 2 The physical circuit diagram of the switch capacitor array of the application is shown in the figure;

[0075] Figure 3 The physical structure diagram of the multi-modal operational amplifier network of the application is shown in the figure;

[0076] Figure 4 The design diagram of the digital control interface of the application is shown in the figure;

[0077] Figure 5 The overall flowchart of the application is shown in the figure;

[0078] Figure 6 The flowchart of the cooperative working mechanism of the application is shown in the figure;

[0079] Figure 7 The switch capacitor parameter flowchart of the application is shown in the figure;

[0080] Figure 8 The filter type setting diagram of the application is shown in the figure;

[0081] Figure 9 The filter state machine control flowchart of the application is shown in the figure. DETAILED DESCRIPTION

[0082] The technical solutions in the embodiments of the application will be described clearly and completely below with reference to the accompanying drawings in the embodiments of the application. Obviously, the described embodiments are only part of the embodiments of the application, rather than all the embodiments of the application. Based on the embodiments in the application, all other embodiments obtained by those skilled in the art without creative labor fall within the protection scope of the application.

[0083] The application provides an integrated programmable anti-aliasing filter electric meter sampling filter chip and system as shown in Figures 1-9 The application provides an integrated programmable anti-aliasing filter electric meter sampling filter chip and system as shown in

[0084] A programmable anti-aliasing filter module is preliminarily isolated from other circuit areas by a guard ring structure, resists noise from digital circuits and substrates, and realizes a basis of ≥78dB signal-to-noise ratio (SNR) and >10MHz gain-bandwidth product (GBW);

[0085] The programmable anti-aliasing filter module includes a switched capacitor array, which changes the total capacitance value of the access circuit by switching, thereby physically changing the cutoff frequency of the filter;

[0086] The digital control and interface module includes a digital control interface configured as an I2C / SPI interface, which communicates with an external microcontroller (MCU), receives external control signals through the I2C / SPI interface, and provides a convenient configuration channel;

[0087] The digital control interface integrates a cyclic redundancy check (CRC) check module and a state interrupt pin, which actively notifies the host controller when conversion is complete or an error occurs, eliminating the need for the MCU to continuously query, improving system efficiency, and the cyclic redundancy check (CRC) check module is used to verify the correctness of data transmission and improve communication reliability. The cutoff frequency, filter type and order of the filter are set in a programmed manner;

[0088] The digital control and interface module is isolated on the right side of the integrated programmable anti-aliasing filter of the meter sampling filter chip and is powered by an independent power supply, ensuring that digital switch noise does not interfere with sensitive analog signals.

[0089] The cooperative control unit is placed in a deep N-well isolation structure to form an independent isolated island, and the cooperative control unit includes a multi-modal operational amplifier network and a modulator (ADC). The multi-modal operational amplifier network uses a folded common-source common-gate design to ensure a gain-bandwidth product (GBW) >10MHz to accurately implement various complex transfer functions. By changing the connection mode or feedback network of the internal operational amplifier, it is physically reconstructed as one of the three filter types of Bessel, Butterworth or Chebyshev to adapt to different application requirements;

[0090] The multi-modal operational amplifier network is adjacent to the modulator (ADC) to shorten the wiring distance of high-sensitivity analog signals, and the modulator (ADC) is surrounded by its own guard ring structure;

[0091] The modulator (ADC) adopts The modulator core architecture converts analog signals into high-resolution digital code streams through sampling and noise shaping technology, with a signal-to-noise ratio (SNR) ≥78dB, which determines the dynamic range and measurement accuracy of the chip and is a guarantee of high-precision measurement.

[0092] The programmable anti-aliasing filter module and the analog part in the cooperative control unit are powered by a first power supply domain, and the digital control and interface module is independently powered by a second power supply domain;

[0093] The meter sampling filter chip integrating the programmable anti-aliasing filter is implemented by using a 180 nm BCD process to realize analog-digital isolation;

[0094] A guard ring isolation layer penetrates through the whole chip, surrounds the periphery of the chip, and isolates between modules. The guard ring isolation layer physically separates the noisy digital circuit power supply and the quiet sensitive analog circuit power supply, greatly reduces the interference of digital switch noise on the analog signal (especially high-precision ADC) through the power supply, and adopts differential line pairs for wiring of the key analog signals (such as the input / output of the filter) in the chip to effectively suppress common-mode noise (such as power supply noise, substrate noise) and improve signal integrity.

[0095] The programmable filter, high-precision ADC, control logic and digital interface are integrated in one chip, reducing the number of external components and the product size.

[0096] Flexible programmable: the filter type and cutoff frequency can be configured through the digital interface, so that one hardware platform can adapt to various application scenarios, greatly improving the design flexibility.

[0097] High precision and high reliability: from laser trimming capacitors, high-performance operational amplifiers and modulator cores to careful physical isolation design (deep N-well isolation structure (Deep N-Well), guard ring structure (Guard Ring)), the measurement accuracy and stable anti-interference ability are realized.

[0098] The switched capacitor array is composed of multiple capacitor units and a switch network, and the switched capacitor array adopts MIM (metal-insulator-metal) capacitor array and laser trimming technology.

[0099] MIM capacitors are common passive components in IC technology, and have the advantages of high precision, good temperature stability and small parasitic effect;

[0100] The switched capacitor array is composed of 16 (4-bit binary weighted) capacitor units (C1-C16) ) and a switch network, and the total capacitance value is configured by digital control bits to realize 16-step programmable adjustment of the cutoff frequency in the range of 1 kHz to 100 kHz. Each capacitor is laser trimmed, with a precision of ±0.1%, which is the physical basis for accurate and controllable frequency response of the filter;

[0101] By switching, the total capacitance value of the access circuit is changed, thereby physically changing the cutoff frequency of the filter.

[0102] The multi-mode operational amplifier network is a programmable feedback network, and the programmable feedback network is configured in Bessel, Butterworth and Cheby modes;

[0103] The Bessel mode optimizes phase linearity, and the phase error is not greater than 0.1°;

[0104] The Butterworth mode optimizes passband flatness;

[0105] The Cheby mode optimizes high-frequency roll-off, and the noise suppression capability for 150 kHz noise reaches -30 dB.

[0106] Capacitance control logic: receiving user instructions, decoding and physically controlling the on-off of switches in the switch capacitor array;

[0107] The digital control and interface module further includes an operational amplifier mode register, which is physically connected with the multi-mode operational amplifier network, wherein the register bit domain is used to combine the filter type and cutoff frequency control code, store the user-selected filter type, support step-by-step configuration and cyclic redundancy check (CRC) check, and ensure the reliability of instruction transmission. The response time of the digital control interface is not greater than 200 μs.

[0108] The cooperative control unit further includes a noise monitoring module and a non-volatile memory. The noise monitoring module calculates the signal-to-noise ratio by fast Fourier transform (FFT) analysis of the modulator (ADC) sampling data, and automatically switches the filter mode according to the signal-to-noise ratio threshold. The non-volatile memory is located at the edge of the digital area and is isolated by a Deep N-Well isolation layer, and is used to store the trimming values of the operational amplifier and the switch capacitor array.

[0109] Embodiment one: an electric meter sampling filter chip system integrated with a programmable anti-aliasing filter, comprising the following steps:

[0110] S1 noise monitoring: collecting original noise signals in the environment;

[0111] S2 parameter configuration: setting sampling frequency, filtering threshold, and modulator (ADC) accuracy parameters;

[0112] S3 filter processing: removing interference noise in the signal;

[0113] S4 modulator (ADC) sampling: converting the filtered analog signal into a digital signal;

[0114] S5 measurement output: outputting noise decibel value and frequency distribution measurement results;

[0115] S6 Result application storage: store data.

[0116] Parameter configuration phase includes initialization of switched capacitor array and control code calculation:

[0117] After starting execution, configure the switched capacitor array, initialize key parameters, input the cutoff frequency control code, output the capacitor array control register, and set the unit capacitor Defined as Corresponding to the physical value 0.5pF, the Q15 fixed-point number format is used, which is an efficient method for processing decimals in embedded systems. It amplifies decimals times and stores and calculates them as integers, and the variable initialized to 0, prepares for subsequent weighted accumulation;

[0118] Loop to parse and weighted accumulate the control code, loop with index i from 0 to 3, and check each bit of the cutoff frequency control code in turn;

[0119] i is the bit of the frequency control code being checked, i=0 indicates checking the lowest bit, and i=3 indicates checking the highest bit;

[0120] In each loop, use bit operation to check the i-th bit of the cutoff frequency control code to see if it is 1;

[0121] If it is 1, perform the accumulation operation, and the value accumulated is the unit capacitor multiplied by a weight, binary weighted design;

[0122] The total capacitor value is calculated as follows:

[0123]

[0124] is the calculated total capacitor value; is the unit capacitor; , , , represents the value of each bit of the 4-bit frequency control code, and each bit can only be 0 or 1; , , , is the weight in "binary weighted", corresponding to 1, 2, 4, 8 respectively;

[0125] If (the bit is activated), calculate and add it to the previous ;

[0126] If If the bit is not activated, the accumulation is 0, then skip the bit, do not accumulate;

[0127] Achieve dynamic adjustability: through 16 combinations of 4-bit control code, can produce from 0x (1+2+4+8)=15x A total of 16 different capacitance values, so as to achieve precise control of the cutoff frequency;

[0128] Check the loop ends when i≥4, apply laser tuning compensation, and output to the register, ;

[0129] ;

[0130] For the value of the hardware capacitor array control register, For the ideal capacitance value calculated by software, For the error value of the hardware individual, Represent the first configuration register, Represent the second configuration register.

[0131] Example two: noise monitoring stage includes SNR adaptive switching mechanism:

[0132] The grid signal input, the modulator (ADC) inside the chip starts to work, the input analog signal is sampled, and it is converted into digital signal waveform, the microcontroller (MCU) carries out fast Fourier transform (FFT) analysis to the digital signal sampled by the modulator (ADC), calculates the current noise frequency, converts the time domain signal into the frequency domain signal, so as to clearly show the intensity distribution of different frequency components, identifies the main noise frequency band, based on the spectrum result, the system can accurately calculate the current grid SNR (SNR).

[0133] The system calculates the SNR of the current signal, and compares it with the preset threshold (70dB).

[0134] When the signal-to-noise ratio (SNR) <70dB is a high-noise environment: the noise is large, the signal quality is poor, and the "Bessel wideband mode" cutoff frequency is selected: 50kHZ. A higher cutoff frequency is set to allow more high-frequency harmonic components in the signal to pass through, ensuring the integrity of the waveform. The filter chip is configured through the I2C / SPI interface, and the modulator (ADC) sampling rate is maintained at 100KHZ. Since the cutoff frequency is 50kHz, the original 100kHz sampling rate still satisfies the Nyquist theorem, so there is no need to change it. At the same time, the interrupt pin (INT_PIN) triggers a hardware interrupt to notify the microcontroller (MCU) that the configuration is complete. The microcontroller (MCU) reads the status register to confirm the configuration, and the modulator (ADC) samples the input analog signal in real time.

[0135] When the signal-to-noise ratio (SNR) ≥70dB is a low-noise environment: the signal quality is high, and the "Chebyshev narrowband mode" cutoff frequency is selected: 100kHZ. A relatively low cutoff frequency is set to more aggressively filter out high-frequency noise. The filter chip is configured through the I2C / SPI interface, and the modulator (ADC) sampling rate is updated to 200KHZ. According to the Nyquist sampling theorem, the sampling rate must be greater than twice the highest frequency of the signal. Since the filter cutoff frequency is set to 100kHz, updating the ADC sampling rate to 200kHz is sufficient and efficient, avoiding unnecessary high sampling that causes data burden.

[0136] At the same time, the interrupt pin (INT_PIN) triggers a hardware interrupt to notify the microcontroller (MCU) that the configuration is complete. The microcontroller (MCU) reads the status register to confirm the configuration, and the modulator (ADC) samples the input analog signal in real time.

[0137] When the filter chip completes mode switching and ADC sampling rate reconfiguration, it sends a hardware interrupt signal to the MCU through a dedicated interrupt pin (INT_PIN). The new configuration is effective, and a new acquisition cycle can begin;

[0138] According to real-time noise information, the system automatically switches from "Bessel wideband mode" to "Chebyshev narrowband mode" to cope with it, always maintaining the optimal working state.

[0139] According to the filter type, select different configuration modes;

[0140] When the Bessel mode is selected, input to the multi-modal operational amplifier network, modify the operational amplifier feedback resistance Rf=10kΩ, disable the LC network, and output the operational amplifier control register value;

[0141] When the Butterworth mode is selected, input to the multi-modal operational amplifier network, modify the operational amplifier feedback resistance Rf=15kΩ, and output the operational amplifier control register value;

[0142] When Chebyshev mode is selected, input to the multi-mode op-amp network, modify the op-amp feedback resistor Rf=20kΩ, enable LC network, output op-amp control register value.

[0143] Through the I2C / SPI interface to receive data, before sending data, calculate the cyclic redundancy check value (CRC) check, merge the cutoff frequency code and filter type, call the I2C interface to write the cutoff frequency code and filter type into register 0x11, the filter type occupies the high 4 bits, and the cutoff frequency code occupies the low 4 bits, call the I2C interface to write the order into register 0x11, send the data and the cyclic redundancy check value (CRC) check sum to the filter chip together;

[0144] After receiving, the filter chip calculates the cyclic redundancy check value (CRC) value and compares it with the received cyclic redundancy check value (CRC), and only when the match is successful, the chip will truly apply the configuration, and if the match fails, the chip will ignore this write and report an error;

[0145] Use hardware interrupts instead of software polling to achieve efficient synchronization between the microcontroller (MCU) and the filter chip;

[0146] The microcontroller (MCU) does not need to wait: after issuing the configuration instruction, the MCU can continue to perform other tasks without constantly querying whether the filter has been configured.

[0147] Event-driven: when the filter chip completes internal configuration (including register update, settling time, etc., total time ≤200μs), it is ready to receive an interrupt signal. Once the microcontroller (MCU) sends this signal, the chip will immediately generate an interrupt to the microcontroller (MCU), informing it that "the configuration has taken effect, start transmitting data";

[0148] Meet the real-time requirements of the power grid: the "configuration-interrupt response" mode delays the configuration within a very short and predictable time (200μs), ensuring deterministic response of the entire system. 200μs is the minimum and sufficient time set according to the chip data manual, ensuring that the chip has sufficient time to latch the register value and switch to the new working state, avoiding data operations when the state is unstable, thus ensuring the real-time and reliability of the system from another dimension;

[0149] Strictly follow the safety process of "parameter preparation - step-by-step writing - issuing completion signal";

[0150] High reliability: through step-by-step writing, hardware cyclic redundancy check value (CRC) check, and precise bit operation, multiple safeguards are provided to ensure the correctness of the configuration instruction;

[0151] Strong real-time: using hardware interrupt and accurate delay, fast and deterministic synchronization with microcontroller (MCU) is realized, which perfectly meets the real-time requirement of power grid.

[0152] Finally, it should be noted that: the above only for the preferred embodiments of the present application, and not for limiting the present application, although the foregoing embodiments of the present application are described in detail, for those skilled in the art, it still can be modified, or part of the technical features of the equivalent replacement, within the spirit and principles of the present application, any modification, equivalent replacement, improvement, etc., should be included in the scope of the present application.

Claims

1. An electricity meter sampling filter chip integrating a programmable anti-aliasing filter, characterized in that, include: The programmable anti-aliasing filter module provides initial isolation from other circuit regions through a guard ring structure. The programmable anti-aliasing filter module includes a switched capacitor array. The digital control and interface module includes a digital control interface configured as an I2C / SPI interface, which communicates with an external microcontroller. The collaborative control unit is placed in a deep N-well isolation structure to form an independent isolation island. The collaborative control unit includes a multi-mode operational amplifier network and a modulator. The multi-mode operational amplifier network adopts a folded common source and common gate design. The multi-mode operational amplifier network is close to the modulator to shorten the trace distance of the high-sensitivity analog signal. The modulator is surrounded by its own guard ring structure. The analog section of the programmable anti-aliasing filter module and the collaborative control unit is powered by the first power domain, while the digital control and interface module is independently powered by the second power domain. The meter sampling filter chip with integrated programmable anti-aliasing filter uses 180nm BCD process to achieve analog-to-digital isolation.

2. The meter sampling filter chip with integrated programmable anti-aliasing filter according to claim 1, characterized in that, The switched capacitor array consists of multiple capacitor units and a switching network, and the switched capacitor array adopts MIM capacitor array and laser trimming technology.

3. The meter sampling filter chip with integrated programmable anti-aliasing filter according to claim 1, characterized in that, The multimodal operational amplifier network is a programmable feedback network, which is configured as a Bessel filter, a Butterworth filter, and a Chebyshev filter mode. Among them, the Bessel mode optimizes phase linearity, with a phase error of no more than 0.1°; Butterworth mode optimizes passband flatness; Chebyshev mode optimizes high-frequency roll-off, achieving -30dB noise suppression at 150kHz.

4. The meter sampling filter chip with integrated programmable anti-aliasing filter according to claim 1, characterized in that, The digital control interface integrates a cyclic redundancy check module and a status interrupt pin, allowing the filter's cutoff frequency, filter type, and order to be set programmatically. The digital control and interface module also includes an operational amplifier mode register, which is configured to be physically connected to the multi-mode operational amplifier network.

5. The meter sampling filter chip with integrated programmable anti-aliasing filter according to claim 1, characterized in that, The collaborative control unit also includes a noise monitoring module and a non-volatile memory. The noise monitoring module calculates the signal-to-noise ratio by analyzing the modulator sampled data through fast Fourier transform and automatically switches the filter mode according to the signal-to-noise ratio threshold. The non-volatile memory is located at the edge of the digital area and is isolated by a deep N-well isolation structure layer. It is used to store the adjustment values ​​of the operational amplifier and switched capacitor array.

6. A meter sampling filter chip system with an integrated programmable anti-aliasing filter, as described in any one of claims 1-5, characterized in that, Includes the following steps: S1 noise monitoring: Collects raw noise signals from the environment; S2 parameter configuration: Set sampling frequency, filter threshold, and modulator accuracy parameters; S3 filter plate treatment: Removes interference noise from the signal; S4 modulator sampling: converts the filtered analog signal into a digital signal; S5 metering output: Outputs noise decibel value and frequency distribution measurement results; S6 Result Application Storage: Stores the data.

7. The meter sampling filter chip system with integrated programmable anti-aliasing filter according to claim 6, characterized in that, The parameter configuration phase includes the initialization of the switched capacitor array and the calculation of control codes: After execution begins, the switched capacitor array is configured, key parameters are initialized, the cutoff frequency control code is input, the capacitor array control register is output, and the unit capacitance is set. Defined as The corresponding physical value is 0.5pF. Using the Q15 fixed-point format, the variable of the accumulated total capacitance is... Initialize to 0; The process involves iterative parsing and weighted accumulation of the control code, with index i ranging from 0 to 3, checking each bit of the cutoff frequency control code sequentially. i represents the current position of the frequency control code being checked. i=0 indicates checking the least significant bit, and i=3 indicates checking the most significant bit. In each loop, the bit operation cutoff frequency control code is used to check if the i-th bit is 1; If the value is 1, an accumulation operation is performed, and the accumulated value is the unit capacitance. Multiply by a weight, binary weighted design; Total capacitance The calculation formula is as follows: This is the calculated total capacitance value; Unit capacitance; , , , Each bit represents the value of a 4-bit frequency control code; each bit can only be 0 or 1. , , , These are the weights in the "binary weighted" calculation, corresponding to 1, 2, 4, and 8 respectively; if If this bit is activated, then the calculation is performed. And accumulate to the top superior; if If the bit is not active, and the accumulated value is 0, then skip the bit and do not accumulate. The loop ends when i ≥ 4, laser trimming compensation is applied, and the result is output to a register. ; ； The value to be written to the hardware capacitor array control register. This is the ideal capacitance value calculated by the software. This refers to the error value of an individual piece of hardware. Represents the first configuration register. This represents the second configuration register.

8. The meter sampling filter chip system with integrated programmable anti-aliasing filter according to claim 6, characterized in that, The noise monitoring phase includes a signal-to-noise ratio adaptive switching mechanism: When a power grid signal is input, the modulator inside the chip starts working, sampling the input analog signal and converting it into a digital signal waveform. The microcontroller performs a fast Fourier transform analysis on the digital signal sampled by the modulator to calculate the current noise frequency harmonics. The system calculates the signal-to-noise ratio of the current signal and compares it with a preset threshold; When the signal-to-noise ratio is <70dB, it is a high-noise environment: the noise is very large and the signal quality is poor. Select the "Bessel wideband mode" cutoff frequency: 50kHz, configure the filter chip through the I2C / SPI interface, keep the modulator sampling rate at 100kHz, and at the same time, the interrupt pin triggers a hardware interrupt to notify the microcontroller that the configuration is complete. The microcontroller reads the status register to confirm the configuration and samples the input analog signal in real time through the modulator. When the signal-to-noise ratio is ≥70dB, it is a low-noise environment with high signal quality. Select "Chebyshev Narrowband Mode" with a cutoff frequency of 100kHz. Configure the filter chip through the I2C / SPI interface, update the modulator sampling rate to 200kHz, and trigger a hardware interrupt on the interrupt pin to notify the microcontroller that the configuration is complete. The microcontroller reads the status register to confirm the configuration and samples the input analog signal in real time through the modulator.

9. The meter sampling filter chip system with integrated programmable anti-aliasing filter according to claim 6, characterized in that, Select different configuration modes based on the filter type; When Bessel mode is selected, the input is fed into the multimode op-amp network, the op-amp feedback resistor Rf is modified to 10kΩ, the LC network is disabled, and the op-amp control register value is output. When Butterworth mode is selected, the input is fed into the multimode op-amp network, and the op-amp feedback resistor Rf=15kΩ is modified to output the op-amp control register value. When Chebyshev mode is selected, the input is fed into the multimode op-amp network. The op-amp feedback resistor Rf is modified to 20kΩ to enable the LC network and output the op-amp control register value.

10. The meter sampling filter chip system with integrated programmable anti-aliasing filter according to claim 6, characterized in that, Data is received via the I2C / SPI interface. Before sending the data, the cyclic redundancy check value of the data is calculated. The cutoff frequency code and filter type are merged. The I2C interface is called to write the cutoff frequency code and filter type into register 0x11. The filter type occupies the high 4 bits and the cutoff frequency code occupies the low 4 bits. The I2C interface is called to write the order into register 0x11. The data and the cyclic redundancy check value are sent together to the filter chip. After receiving the data, the filter chip calculates the cyclic redundancy check value and compares it with the received cyclic redundancy check value. If the match is successful, the chip actually applies the configuration; if the match fails, the chip ignores the write and reports an error. Hardware interrupts are used instead of software polling to achieve efficient synchronization between the microcontroller and the filter chip; The microcontroller does not need to wait: After the configuration command is issued, the microcontroller can continue to perform other tasks without constantly checking whether the filter configuration is complete.

Images