Turbo code log domain decoding method and device based on memory-computing integrated device

Abstract

The application relates to the technical field of communication, and discloses a Turbo code log domain decoding method and device based on a memory-computing integrated device, which can create a unified driving vector, an external confidence updating column vector corresponding to each undirected edge and an external log-likelihood ratio updating column vector corresponding to each variable node according to a probability graph model corresponding to Turbo code to be decoded, and configure an external confidence updating array and an external log-likelihood ratio updating array in the memory-computing integrated device according to each external confidence updating column vector and the external log-likelihood ratio updating column vector, drive the external confidence updating array and the external log-likelihood ratio updating array to respectively perform external confidence and external log-likelihood ratio operation and updating based on the unified driving vector until Turbo decoding is completed, so that original bit information corresponding to the Turbo code to be decoded is obtained. The application can significantly reduce hardware resource consumption and power consumption while retaining excellent error correction capability of the Turbo code.

Description

Technical Field

[0001] This invention relates to the field of communication technology, and in particular to a Turbo code logarithmic field decoding method and apparatus based on a memory computing device. Background Technology

[0002] In communication systems, Turbo codes are widely adopted as one of the core channel coding schemes in many wireless communication standards due to their performance, which approaches the Shannon limit.

[0003] Turbo decoding, a related technology, improves decoding accuracy by repeatedly exchanging external information between two component decoders and performing multiple iterative operations. However, this method also consumes significant power. Summary of the Invention

[0004] This invention provides a Turbo code logarithmic field decoding method and apparatus based on an in-memory computing device to solve the problem of high power consumption in related technologies and reduce the power consumption of Turbo decoding.

[0005] In a first aspect, the present invention provides a Turbo code logarithmic field decoding method based on an in-memory compute unit, applied at the decoding end, the method comprising:

[0006] Obtain the probabilistic graphical model corresponding to the Turbo code to be decoded, and the initial log-likelihood ratio of each variable node in the probabilistic graphical model; wherein, the initial log-likelihood ratio of the variable node is determined according to the logarithmic field operation method;

[0007] The initial log-likelihood ratio of each variable node is used as the confidence level that the variable node transmits to each verification node connected to the variable node through an undirected edge.

[0008] The confidence level transmitted by each of the variable nodes to each of the verification nodes is determined based on the confidence level transmitted by each of the variable nodes to each of the verification nodes.

[0009] Based on the confidence level passed from each verification node to each variable node and the probabilistic graphical model, a unified driving vector, an external confidence level update column vector corresponding to each undirected edge, and an external log-likelihood ratio update column vector corresponding to each variable node are created.

[0010] Configure the node states in the in-memory compute unit based on each of the external confidence update column vectors and each of the external log-likelihood ratio update column vectors to obtain the external confidence update array and the external log-likelihood ratio update array.

[0011] Based on the unified driving vector, the external confidence update array, and the external log-likelihood ratio update array, the confidence level and the log-likelihood ratio of each variable node transmitted to each check node are iteratively updated until the iteration stopping condition is met, so as to decode the original bit information corresponding to the Turbo code to be decoded.

[0012] Secondly, the present invention provides a Turbo code logarithmic field decoding device based on an in-memory compute unit, applied at a decoding end, the device comprising:

[0013] The acquisition unit is used to acquire the probabilistic graphical model corresponding to the Turbo code to be decoded, and the initial log-likelihood ratio of each variable node in the probabilistic graphical model; wherein the initial log-likelihood ratio of the variable node is determined according to the logarithmic field operation method;

[0014] As a unit, it is used to take the initial log-likelihood ratio of each variable node as the confidence level that the variable node transmits to each verification node connected to the variable node through an undirected edge;

[0015] A determining unit is configured to determine the confidence level transmitted by each of the variable nodes to each of the verification nodes based on the confidence level transmitted by each of the variable nodes to each of the verification nodes.

[0016] A creation unit is used to create a unified driving vector, an external confidence update column vector corresponding to each undirected edge, and an external log-likelihood ratio update column vector corresponding to each variable node based on the confidence level passed from each verification node to each variable node and the probabilistic graphical model.

[0017] A configuration unit is used to configure the node state in the in-memory compute unit according to each of the external confidence update column vectors and each of the external log-likelihood ratio update column vectors, so as to obtain the external confidence update array and the external log-likelihood ratio update array.

[0018] The iterative unit, based on the unified driving vector, the external confidence update array, and the external log-likelihood ratio update array, iteratively updates the confidence level and the log-likelihood ratio of each variable node transmitted to each verification node until the iteration stopping condition is met, so as to decode the original bit information corresponding to the Turbo code to be decoded.

[0019] Thirdly, the present invention provides a computer device, comprising: a memory and a processor, wherein the memory and the processor are communicatively connected to each other, the memory stores computer instructions, and the processor executes the computer instructions to perform the Turbo code logarithmic field decoding method based on the in-memory computing unit described in the first aspect or any corresponding embodiment thereof.

[0020] Fourthly, the present invention provides a computer-readable storage medium storing computer instructions for causing a computer to execute the Turbo code logarithmic field decoding method based on the first aspect or any corresponding embodiment thereof.

[0021] The present invention provides a method and apparatus for Turbo code logarithmic field decoding based on an in-memory computing unit. It creates a unified driving vector, an external confidence update column vector corresponding to each undirected edge, and an external log-likelihood ratio update column vector corresponding to each variable node, based on the probabilistic graphical model corresponding to the Turbo code to be decoded. Based on each external confidence update column vector and external log-likelihood ratio update column vector, an external confidence update array and an external log-likelihood ratio update array are configured in the in-memory computing unit. Using the unified driving vector, the external confidence update array and the external log-likelihood ratio update array are driven to perform external confidence and external log-likelihood ratio calculations and updates respectively until Turbo decoding is completed, obtaining the original bit information corresponding to the Turbo code to be decoded. This invention stores some static variables involved in Turbo decoding in the in-memory computing unit and transfers some digital operations to the in-memory computing unit, utilizing the storage and computing performance of the in-memory computing unit for computation, thus overcoming the power consumption bottleneck. While retaining the excellent error correction capability of Turbo codes, it significantly reduces hardware resource consumption and power consumption. Attached Figure Description

[0022] To more clearly illustrate the technical solutions in this invention or related technologies, the accompanying drawings used in the description of the embodiments or related technologies will be briefly introduced below. Obviously, the accompanying drawings described below are some embodiments of this invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0023] Figure 1 A flowchart of a Turbo code logarithmic field decoding method based on an in-memory computing device is provided for an embodiment of the present invention;

[0024] Figure 2 This is a schematic diagram illustrating the connection relationship between the verification node and each variable node in a probabilistic graphical model provided by an embodiment of the present invention.

[0025] Figure 3 A flowchart illustrating another Turbo code logarithmic field decoding method based on an in-memory compute unit provided in this embodiment of the invention;

[0026] Figure 4 A schematic diagram of a Turbo code logarithmic field decoding device based on an in-memory computing unit is provided in an embodiment of the present invention;

[0027] Figure 5 This is a schematic diagram of the structure of a computer device provided in an embodiment of the present invention. Detailed Implementation

[0028] To make the objectives, technical solutions, and advantages of this invention clearer, the technical solutions of this invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this invention. All other embodiments obtained by those skilled in the art based on the embodiments of this invention without creative effort are within the scope of protection of this invention.

[0029] The following is combined with Figures 1-3 The present invention describes a Turbo code logarithmic field decoding method based on an in-memory compute unit.

[0030] like Figure 1 As shown, this embodiment proposes a first Turbo code logarithmic field decoding method based on a memory-based computing device, applied to the decoding end. This method may include the following steps:

[0031] S101. Obtain the probabilistic graphical model corresponding to the Turbo code to be decoded, and the initial log-likelihood ratio of each variable node in the probabilistic graphical model. The Turbo code to be decoded is obtained by digitally modulating the original Turbo code at the encoding end; the original Turbo code is obtained by Turbo encoding the original bit information at the encoding end; and the initial log-likelihood ratio of the variable nodes is determined according to the logarithmic field operation method.

[0032] It should be noted that this embodiment can be applied to the decoding end to decode the Turbo code to be decoded obtained by the encoding end using Turbo encoding and digital modulation to obtain the original bit information.

[0033] Taking Binary Phase Shift Keying (BPSK) as an example, this paper introduces the communication between the encoder and decoder, and the decoding objective of this embodiment. Specifically, the encoder can encode the original bit information K codewords into N codewords using a Turbo encoder. x Then, based on BPSK modulation, N symbols s are generated and sent to the decoding end. Due to noise interference during transmission, the decoding end in this embodiment receives N symbols. y The decoding task at the decoding end is to... y The original K codewords, or raw bit information, are restored.

[0034] In-memory computing devices are integrated devices that combine storage and computing capabilities, such as resistive random access memory (RRAM), phase-change memory (PCM), magnetic memory (MRAM), and flash memory.

[0035] The Turbo code to be decoded can be the received Turbo code sent by the encoder that needs to be decoded. The Turbo code to be decoded can include N codewords, where N is an integer greater than 1.

[0036] Specifically, in this embodiment, an extended parity-check matrix and a corresponding probabilistic graphical model can be created based on the Turbo code to be decoded.

[0037] Specifically, a probabilistic graphical model can include multiple variable nodes, multiple check nodes, and multiple undirected edges. Undirected edges are used to connect variable nodes and check nodes that have a connection relationship. Each variable node uniquely corresponds to a column vector in the extended check matrix, and each check node uniquely corresponds to a row vector in the extended check matrix. If the row order in the extended check matrix is ​​equal to... i Column order equals j If the element is 1, then the first node index is equal to j The variable node and the second node index are equal to i The check nodes have a connection relationship. If the row order in the extended check matrix is ​​equal to... i Column order equals j If the element is 0, then the first node index is equal to j The variable node and the second node index are equal to i There are no connections between the verification nodes. The first node number is the sequence number of the variable node among all variable nodes, and the second node number is the sequence number of the verification node among all verification nodes.

[0038] To better illustrate the relationship between the extended parity-check matrix and the probabilistic graphical model, as well as the relationship between variable nodes, parity nodes, and undirected edges, the following Example 1 is presented and combined with... Figure 2 Let me introduce it.

[0039] Example 1: When the extended parity-check matrix H Given a matrix of I rows and J columns, where the row vector of the third row is [0, 1, 1, 1, 0, 0], the probabilistic graphical model includes I check nodes and J variable nodes (in this case, J is 6). The third check node in the probabilistic graphical model... i (at this time, i 3) The connection relationships between the variables and the nodes are as follows: Figure 2As shown in the diagram, the 2nd, 3rd, and 4th elements of this row vector are 1, and the 1st, 5th, and 6th elements are 0. Therefore, the 3rd check node is connected to the 2nd, 3rd, and 4th variable nodes via undirected edges, while the 3rd check node is not connected to the 1st, 5th, and 6th variable nodes. It should be noted that... Figure 2 Apart from the third verification node, the connection relationships between other verification nodes and variable nodes are not shown. The connection relationships between other verification nodes and variable nodes can be understood by referring to the connection relationship between the third verification node and variable nodes mentioned above.

[0040] Optionally, step S101 includes:

[0041] Receive the Turbo code to be decoded sent by the encoder and obtain the noise power corresponding to the Turbo code to be decoded;

[0042] Based on the Turbo code to be decoded, create an initial parity check matrix and a corresponding initial probabilistic graphical model;

[0043] Eliminate short loop structures in the initial parity check matrix and the initial probabilistic graphical model to obtain the extended parity check matrix and the corresponding probabilistic graphical model;

[0044] The initial log-likelihood ratio for each variable node is determined based on the noise power, the Turbo code to be decoded, and the logarithmic field operation method.

[0045] Specifically, this embodiment can establish algebraic constraints based on the two recursive systematic convolutional (RSC) components of the Turbo encoder. Let the input information sequence be... System bits and check bits The check bits are determined by two generator polynomials, which are the feedback polynomial and the feedforward polynomial set internally by the RSC encoder.

[0046] Specifically, in this embodiment, the generator polynomial described above can be used to map the Galois field GF(2) to binary coefficient vectors [1,0,1,1] and [1,1,0,1]. Based on the number of encoded information bits K, a cyclic shift is performed (the first row is padded with 0s to length K, the second row is obtained by cyclically shifting one bit to the right of the first row padded with 0s to length K, the third row is obtained by cyclically shifting one bit to the right of the second row again, and so on) to obtain a K×K cyclic shift matrix. and For example, when K equals 8, and the generator polynomial is mapped to a binary coefficient vector [1,0,1,1], an 8×8 cyclic shift matrix can be constructed:

[0047] .

[0048] This embodiment can be used for the construction. and By performing horizontal concatenation, the component verification matrix is ​​obtained. .

[0049] Wherein, the component parity check matrix satisfies . Indicated by system bits and check bits The concatenated vector. The dot product symbol represents the dot product of two row vectors.

[0050] Subsequently, according to the interleaving rules, the interleaving effect of the second RSC component encoder is written as a permutation matrix. The corresponding check relation is right-multiplied. ,get:

[0051] .

[0052] Similarly, satisfying Based on the above component parity-check matrices, the overall parity-check matrix of the Turbo code (code rate 1 / 3, unchanged), i.e., the initial parity-check matrix, is as follows:

[0053] .

[0054] The initial check matrix has a size of 2K×3K (K is the number of encoded information bits) and satisfies the check relationship.

[0055] Subsequently, this embodiment can create a corresponding initial probabilistic graphical model based on the initial parity check matrix, identify and eliminate short loop structures in the initial parity check matrix and the initial probabilistic graphical model, and obtain an extended parity check matrix and a probabilistic graphical model.

[0056] Optional. In this embodiment, after creating the initial parity-check matrix and the initial probabilistic graphical model, the approach of expanding the parity-check matrix is ​​used to systematically eliminate the 4-rings in the initial parity-check matrix and the initial probabilistic graphical model.

[0057] It should be noted that a 4-ring corresponds to a pattern in the check matrix: the elements at the four intersections of two rows (e.g., c_i and c_j) and two columns (e.g., v_p and v_q) are all 1. This indicates that two check equations simultaneously constrain the same pair of variable nodes. Therefore, these 4-rings are eliminated and replaced. First, all four 1s constituting the 4-ring are cleared to zero. Then, a new variable node v_pq is introduced into the initial probabilistic graphical model, and a new check equation (i.e., adding a row to the initial check matrix) is added to define it: v_pq ⊕ v_p ⊕ v_q = 0. The original check equations c_i and c_j are modified so that they are associated through the newly introduced v_pq node, instead of directly connecting v_p and v_q simultaneously. All 4-rings in the initial check matrix are traversed, and the above operation is repeated for all detected 4-rings. The initial check matrix and initial probabilistic graphical model after eliminating all 4-rings are determined as the extended check matrix and probabilistic graphical model, respectively.

[0058] It should be noted that this embodiment fundamentally eliminates the short-ring structure that is most detrimental to decoding performance by replacing each 4-ring in the initial parity-check matrix and the initial probabilistic graphical model with a larger 6-ring. Due to the structural characteristics of Turbo codes, the short rings in their initial parity-check matrix and initial probabilistic graphical model are mainly such 4-rings. Therefore, after this round of expansion optimization, no further processing is usually required. The final result is an expanded parity-check matrix without 4-rings, which is more suitable for high-performance iterative decoding.

[0059] Understandably, the number of variable nodes will increase in the extended parity-check matrix and probabilistic graphical model obtained after the extended optimization, compared to the initial parity-check matrix and probabilistic graphical model.

[0060] Specifically, if the encoding end encodes K codewords into N codewords... x Then, based on BPSK modulation, N symbols s are generated and transmitted. Due to noise interference during transmission, this embodiment receives N symbols. y Each y Restore to the corresponding x Thus, based on each x The initial K codewords are obtained. At this point, the Turbo code to be decoded received in this embodiment includes N codewords. .

[0061] In this embodiment, the initial log-likelihood ratio of each variable node can be calculated. For the unexpanded first... j Variable nodes The calculation method is as follows:

[0062] .

[0063] in, For the first j The initial log-likelihood ratio of each variable node. and For the first The set of sub-constellation symbols with bits 0 / 1. It is the first one received by the decoding end. j Each code character s The codewords sent by the encoding end. This represents noise power.

[0064] For the variable nodes introduced by the extension, since they are obtained by the receiver itself and there is no prior channel information, their initial log-likelihood ratio is considered to be 0.

[0065] S102. The initial log-likelihood ratio of each variable node is used as the confidence level that the variable node transmits to each verification node connected to the variable node through an undirected edge.

[0066] Specifically, for any variable node, this embodiment can use the initial log-likelihood ratio of the variable node as the confidence level that the variable node transmits to each verification node connected to the variable node.

[0067] It is understandable that for a verification node that is not connected to any variable node and is not connected by an undirected edge, the variable node cannot pass a message to the verification node, and therefore there is no confidence level passed from the variable node to the verification node. If there is a verification node that is not connected to any variable node, this embodiment can disregard the verification node from beginning to end.

[0068] S103. Determine the confidence level that each verification node transmits to each variable node based on the confidence level transmitted by each variable node to each verification node.

[0069] Specifically, in this embodiment, when it is determined that the verification node is directed to a certain variable node... j When transmitting confidence levels, it can be based on the variable node. j The confidence level passed from each variable node to the verification node is used to determine the confidence level of the verification node to the variable node. j The confidence level of the transmission.

[0070] Optionally, step S103 includes:

[0071] For any verification node, determine the minimum confidence level from the target confidence levels passed from each first variable node to the verification node. If the target confidence level is greater than 1, define the target value corresponding to the target confidence level as 1; if the target confidence level is less than 0, define the target value corresponding to the target confidence level as -1; if the target confidence level is equal to 0, define the target value corresponding to the target confidence level as 0. Multiply the target value corresponding to each target confidence level, the minimum confidence level, and the set normalization coefficient to obtain the corresponding product, which is used as the confidence level passed from the verification node to the second variable node. Here, the second variable node is a variable node connected to the verification node, and the first variable node is a variable node other than the second variable node among all the variable nodes connected to the verification node.

[0072] Specifically, this embodiment can use sign The function is used to determine the target value corresponding to each target confidence level.

[0073] The normalization coefficient can be used to scale or weight the messages updated by the check node. The introduction of the normalization coefficient aims to improve the performance of the minimum-sum decoding algorithm, making the minimum-sum approximation closer to the accurate signal processing algorithm.

[0074] S104. Based on the confidence and probabilistic graphical model passed from each verification node to each variable node, create a unified driving vector, an external confidence update column vector corresponding to each undirected edge, and an external log-likelihood ratio update column vector corresponding to each variable node.

[0075] It should be noted that the relevant technology can calculate the external confidence level from each variable node to each check node, as well as the external log-likelihood ratio of each variable node, based on the confidence level passed from each check node to each variable node. The confidence level passed from each variable node to the check node and the log-likelihood ratio of each variable node are updated based on the external confidence level and the external log-likelihood ratio. Then, the updated confidence level and log-likelihood ratio are used to update the confidence level passed from each check node to each variable node, iterating until Turbo decoding is complete.

[0076] To reduce Turbo decoding power consumption, this embodiment configures the calculation and update process of external confidence and external log-likelihood ratio to be performed in the in-memory compute unit, thereby realizing the simulation calculation of external confidence and external log-likelihood ratio based on the in-memory compute unit and reducing Turbo decoding power consumption.

[0077] The external confidence update column vector corresponding to the undirected edge is used to configure the corresponding external confidence update array in the in-memory compute unit to determine and update the external confidence passed from the variable node corresponding to the undirected edge to the verification node corresponding to the undirected edge.

[0078] The external log-likelihood ratio update column vector corresponding to the variable node is used to configure the corresponding external log-likelihood ratio update array in the in-memory compute unit in order to determine and update the external log-likelihood ratio of the variable node.

[0079] The unified driving vector can be used to drive the configured external confidence update array and external log-likelihood ratio update array in the in-memory computing unit to perform external confidence and external log-likelihood ratio calculations and updates.

[0080] Specifically, in this embodiment, based on the confidence level passed from each verification node to each variable node, and based on each variable node, verification node, and undirected edge in the probabilistic graphical model, a unified driving vector, an external confidence level update column vector corresponding to each undirected edge, and an external log-likelihood ratio update column vector corresponding to each variable node are created.

[0081] S105. Configure the node states in the in-memory compute unit according to each external confidence update column vector and each external log-likelihood ratio update column vector to obtain the external confidence update array and the external log-likelihood ratio update array.

[0082] Specifically, in this embodiment, the column vector can be updated according to the external confidence score corresponding to each undirected edge, and the corresponding node column can be configured in the in-memory compute unit to obtain the external confidence score update array. Then, in this embodiment, the column vector can be updated according to the external log-likelihood ratio of each variable node, and the corresponding node column can be configured in the in-memory compute unit to obtain the external log-likelihood ratio update array.

[0083] S106. Based on the unified driving vector, external confidence update array and external log-likelihood ratio update array, iteratively update the confidence level and log-likelihood ratio of each variable node to each check node until the iteration stopping condition is met, so as to interpret the original bit information.

[0084] Specifically, this embodiment can iteratively update the confidence level and the log-likelihood ratio of each variable node to each verification node based on a unified driving vector, an external confidence update array, and an external log-likelihood ratio update array. This enables the storage of some static variables involved in Turbo decoding in an in-memory computing unit, and the transfer of some digital operations to the in-memory computing unit. By utilizing the storage and computing performance of the in-memory computing unit, the power consumption bottleneck can be overcome, and while retaining the excellent error correction capability of Turbo codes, the hardware resource consumption and power consumption can be significantly reduced.

[0085] The Turbo code logarithmic field decoding method based on an in-memory compute unit (IMCU) proposed in this embodiment creates a unified driving vector, an external confidence update column vector for each undirected edge, and an external log-likelihood ratio update column vector for each variable node, based on the probabilistic graphical model corresponding to the Turbo code to be decoded. Based on each external confidence update column vector and external log-likelihood ratio update column vector, an external confidence update array and an external log-likelihood ratio update array are configured in the ICU. Using the unified driving vector, the external confidence update array and the external log-likelihood ratio update array are driven to perform external confidence and external log-likelihood ratio calculations and updates respectively until Turbo decoding is completed, thus obtaining the original bit information. This embodiment stores some static variables involved in Turbo decoding in the ICU and transfers some digital operations to the ICU, utilizing the storage and computing performance of the ICU for computation, overcoming the power consumption bottleneck, and significantly reducing hardware resource consumption and power consumption while retaining the excellent error correction capability of Turbo codes.

[0086] based on Figure 1 This embodiment proposes a second method for Turbo code logarithmic field decoding based on in-memory computing. In this method, step S104 includes:

[0087] Starting from 1, number each variable node sequentially to obtain the first node number of each variable node; and starting from 1, number each verification node sequentially to obtain the second node number of each verification node.

[0088] For any undirected edge, combine the first node index of the variable node connected by the undirected edge and the second node index of the check node connected by the undirected edge to obtain the edge index of the undirected edge.

[0089] Arrange the edge indices of each undirected edge to obtain an edge index vector;

[0090] Arrange the first node number in each edge number of the edge number vector in turn to obtain the variable number vector; and arrange the second node number in each edge number vector in turn to obtain the verification number vector.

[0091] A unified driving vector is created based on the verification sequence vector, the variable sequence vector, and the confidence level passed from each verification node to each variable node.

[0092] Based on the verification index vector and the variable index vector, create an external confidence update column vector for each undirected edge; and based on the variable index vector, create an external log-likelihood ratio update column vector for each variable node.

[0093] Optionally, the edge indices of each undirected edge are arranged to obtain an edge index vector, including:

[0094] In each undirected edge, select the first edge number with the first node number 1 from the edge numbers, and sort each first edge number in ascending order of the second node number to obtain the corresponding first edge number subvector; in each undirected edge, select the second edge number with the first node number 2 from the edge numbers, and sort each second edge number in ascending order of the second node number to obtain the corresponding second edge number subvector; in each undirected edge, select the third edge number with the first node number 3 from the edge numbers, and so on until each edge number subvector is obtained;

[0095] Sort each edge number subvector in the order in which they were obtained to obtain the edge number vector.

[0096] Specifically, the variable index vector created in this embodiment is represented as follows: The verification sequence number vector is represented as . The first node number of the variable node in each edge number vector is included. This includes the first node index of the check node in each edge index vector. For example, when the 5th edge index in the edge index vector is... hour, The 5th element is 1. The fifth element is 6.

[0097] Optionally, the number of elements in both the verification index vector and the variable index vector is equal to the total number of undirected edges M;

[0098] The above-mentioned unified driving vector is created based on the verification sequence vector, the variable sequence vector, and the confidence level passed from each verification node to each variable node, including:

[0099] Arrange the first confidence level, the second confidence level, up to the Mth confidence level in sequence to obtain the unified driving vector;

[0100] Wherein, the k-th confidence level is any confidence level from the first confidence level to the M-th confidence level, and the k-th confidence level is specifically the confidence level passed from the verification node corresponding to the k-th second node in the verification sequence number vector to the variable node corresponding to the k-th first node in the variable sequence number vector.

[0101] Specifically, the unified driving vector created in this embodiment includes M confidence levels. For the k-th confidence level, this embodiment can determine the confidence level passed from the verification node corresponding to the k-th second node in the verification sequence vector to the variable node corresponding to the k-th first node in the variable sequence vector as the k-th confidence level.

[0102] Optionally, the above-mentioned creation of an external confidence update column vector for each undirected edge based on the verification index vector and the variable index vector includes:

[0103] Traverse each edge number in the edge number vector in the order of the elements;

[0104] For the traversal of the first m The edge sequence number is used to create the edge with the first edge. m The first null column vector with M elements corresponding to each edge index;

[0105] For any position of the first element in the first null column vector, determine the order 'a' of the first element position. If 'a' satisfies a first predefined condition, assign the value 1 to the element corresponding to the first element position; otherwise, assign the value 0 to the element corresponding to the first element position. The first predefined condition is that the order 'a' of the variable index vector and the order 'a' of the variable index vector are... m All elements are of equal size, and the a-th element in the verification sequence vector is equal to the a-th element in the verification sequence vector. m The elements are of different sizes;

[0106] The column vector obtained by assigning values ​​to each element at the first element position in the first null value column vector is determined as the external confidence update column vector corresponding to the target undirected edge; where the target undirected edge is the first... m Each edge number corresponds to an undirected edge.

[0107] Optionally, the above-mentioned creation of an external log-likelihood ratio update column vector for each variable node based on the variable index vector includes:

[0108] Traverse each variable node in ascending order of its first node number;

[0109] For the traversed number... j The first variable node, created in relation to the first... j A second null value column vector with M elements corresponding to each variable node;

[0110] For any position of the second element in the second null value column vector, determine the order b of the second element positions. If b satisfies a second predefined condition, assign the value 1 to the element corresponding to the second element position; otherwise, assign the value 0 to the element corresponding to the second element position. The second predefined condition is that the b-th element in the variable index vector is... j They are the same size;

[0111] The column vector obtained by assigning values ​​to the elements at the second element position in the second null column vector is determined as the first null column vector. jThe external log-likelihood ratio of each variable node updates the column vector.

[0112] Specifically, in this embodiment, the following formula is used to assign a value to each element in the first null column vector.

[0113] ;

[0114] Specifically, Indicates the first m The first null value column vector corresponding to each edge index. In m Used as an edge number identifier. e This indicates the first null value in the column vector. e Each element. Representing vectors The Middle e One element, Representing vectors The Middle m One element, and Representing vectors The Middle e The element and the first m Each element.

[0115] Specifically, in this embodiment, the following formula is used to assign a value to each element in the second null value column vector.

[0116] ;

[0117] Specifically, Indicates the first m The second null value column vector corresponding to each edge index. In m Used as an edge number identifier. e This indicates the second null value column vector. e Each element. Representing vectors The Middle e Each element.

[0118] Optionally, step S105 above includes:

[0119] Arrange each external confidence update column vector in the order they were obtained to obtain the external confidence update matrix; and arrange each external log-likelihood ratio update column vector in the order they were obtained to obtain the external likelihood ratio update matrix.

[0120] In the in-memory computing unit, a first node array to be configured is determined, whose number of node rows and columns corresponds to the number of element rows and columns of the external confidence update matrix, and a second node array to be configured is determined, which is horizontally adjacent to the first node array to be configured and whose number of node rows and columns corresponds to the number of element rows and columns of the external likelihood ratio update matrix.

[0121] The node state at each position of the first node array to be configured is configured according to the element value at each position in the external confidence update matrix, thus obtaining the external confidence update array; the node state at each position of the second node array to be configured is configured according to the element value at each position in the external likelihood ratio update matrix, thus obtaining the external log-likelihood ratio update array.

[0122] Specifically, in this embodiment, the external log-likelihood ratio update column vectors corresponding to each undirected edge can be arranged first to obtain the external confidence update matrix.

[0123] Optionally, in this embodiment, the external confidence update matrix can be configured directly according to the following formula.

[0124] ;

[0125] at this time, This represents the first element in the external confidence update matrix to be configured. e Line number m Column elements, and Representing vectors respectively The Middle e The element and the first m One element, and Representing vectors respectively The Middle e The element and the first m Each element.

[0126] Specifically, in this embodiment, the external log-likelihood ratio update column vectors corresponding to each variable node can be arranged to obtain the external log-likelihood ratio update matrix.

[0127] Optionally, in this embodiment, the external confidence update matrix can be configured directly according to the following formula.

[0128] ;

[0129] at this time, This represents the th element in the external log-likelihood ratio update matrix to be configured. e Line number m Column elements, Representing vectors The first in e Each element.

[0130] Specifically, in this embodiment, the state of the node corresponding to any position in the external confidence update matrix can be configured based on any element in the in-memory computing unit. For example, when the in-memory computing unit is a memristor, if the element is 1, the node's resistance state is configured as low resistance; if the element is 0, the node's resistance state is configured as high resistance. After configuring the node state according to each element in the external confidence update matrix, the external confidence update array can be obtained.

[0131] Specifically, in this embodiment, at a horizontally adjacent position of the external confidence update array in the in-memory computing unit, the node state at the corresponding position in the in-memory computing unit can be configured according to each element in the external likelihood ratio update matrix to obtain the external log-likelihood ratio update array.

[0132] It is understandable that the external log-likelihood ratio update array and the external confidence update array in the in-memory compute unit are adjacent and have aligned rows.

[0133] Optionally, when the in-memory computing unit is a memristor, the unified drive vector is a unified voltage vector. Step S106 includes:

[0134] The voltage corresponding to each element in the unified voltage vector is input into each row of the external confidence update array and the external log-likelihood ratio update array, respectively. The first current output of each node column in the external confidence update array and the second current output of each node column in the external log-likelihood ratio update array are read.

[0135] Each first current is used as the external confidence level transmitted from each variable node to each verification node, and each second current is used as the external log-likelihood ratio of each variable node.

[0136] Add the initial log-likelihood ratio of each variable node to its external log-likelihood ratio to obtain the new log-likelihood ratio for each variable node.

[0137] Hard decision is made on the new log-likelihood ratio of each variable node to obtain the codeword vector;

[0138] If the remainder of the extended parity-check matrix and the codeword vector corresponding to the probabilistic graphical model is not equal to 0, then the external confidence level passed from each variable node to each parity-check node is added to the initial log-likelihood ratio of the variable node to obtain the new confidence level passed from each variable node to each parity-check node, and these new confidence levels are used as the current confidence levels passed from each variable node to each parity-check node. The process then returns to the step of determining the confidence level passed from each parity-check node to each variable node based on the confidence level passed from the variable node to each parity-check node, until the latest remainder result is equal to 0, at which point the iteration stops.

[0139] Determine the total number of characters K in the original bit information, and select the first K elements from the latest codeword vector as the original bit information.

[0140] Specifically, in this embodiment, the voltage corresponding to each element in the unified voltage vector can be determined separately, and the voltage corresponding to each element can be input into each row of the external confidence update array and the external log-likelihood ratio update array. For example, in this embodiment, the voltage corresponding to the first element and the second element in the unified voltage vector can be determined separately, the voltage corresponding to the first element can be input into the first row of the external confidence update array and the external log-likelihood ratio update array, and the voltage corresponding to the second element can be input into the second row of the external confidence update array and the external log-likelihood ratio update array.

[0141] Specifically, in this embodiment, after inputting voltage to each row of nodes in the external confidence update array and the external log-likelihood ratio update array, the current value of each column of nodes in the external confidence update array and the external log-likelihood ratio update array can be read respectively.

[0142] Specifically, this embodiment can determine the unique undirected edge corresponding to the current value of each column node in the external confidence update array, and use the current value uniquely corresponding to the undirected edge as the external confidence value passed from the corresponding variable node to the corresponding verification node. For example, when the state of the first column node in the external confidence update array is configured according to the external confidence update column vector corresponding to the first undirected edge, the current value of the first column node uniquely corresponds to the first undirected edge. In this embodiment, the current value of the first column node in the external confidence update array can be used as the external confidence value passed from the variable node connected to the first undirected edge to the verification node connected to the first undirected edge.

[0143] Specifically, the current values ​​uniquely corresponding to each undirected edge obtained in this embodiment are arranged as follows:

[0144]

[0145] Understandable, Each element in the array represents the current value corresponding to the undirected edge between the variable node with the first node number 1 and each verification node that has a connection relationship. For example, The variable node with the first node index 1 and the variable node with the second node index 1 The current value corresponding to the undirected edge between the verification nodes. Each element in the table represents the current value of the undirected edge between the variable node with the first node number 2 and each verification node that has a connection relationship. The elements in the first node are numbered as follows: JThe variable nodes are respectively connected to the undirected edges between each verification node and the nodes that have a connection relationship.

[0146] Specifically, in this embodiment, the variable node that uniquely corresponds to the current value of each column of nodes in the external log-likelihood ratio update array can be determined, and the current value uniquely corresponding to the variable node can be used as the external log-likelihood ratio of the variable node.

[0147] Specifically, in this embodiment, after determining the external log-likelihood ratio of each variable node, for any variable node, the external log-likelihood ratio of the variable node is added to the initial log-likelihood ratio of the variable node to obtain the new log-likelihood ratio of the variable node.

[0148] like Figure 3 As shown, RRAM core represents the in-memory compute unit. Node state configuration is performed in the in-memory compute unit to obtain the external confidence update array and the external log-likelihood ratio update array. Figure 3 In this context, DAC stands for Digital-to-Analog Converter, used to convert digital signals into analog signals, while ADC stands for Analog-to-Digital Converter, used to convert analog signals into digital signals. Figure 3 In Variable node j To the verification node i The confidence level of the transmitted external message is called the external confidence level. Refers to the verification node To variable node j Confidence level of message delivery Variable node j The external log-likelihood ratio. N ( j ) indicates the relationship with the first j This is represented by a set of check nodes connected to each variable node. This embodiment uses... Figure 3 The in-memory computing unit configures node states to obtain external confidence update arrays and external log-likelihood ratio update arrays. These external confidence update arrays and external log-likelihood ratio update arrays are then used to implement [the following]. and The operation.

[0149] Figure 3 middle, The new log-likelihood ratio represents the variable node. This represents the initial log-likelihood ratio of the variable node. The initial LLR input refers to the initial log-likelihood ratio input.

[0150] Next, in this embodiment, a hard decision is made on the new log-likelihood ratio of each variable node to obtain the codeword corresponding to each variable node. When the new log-likelihood ratio of a variable node is less than 0, the codeword corresponding to the variable node is determined to be 1; when the new log-likelihood ratio of a variable node is greater than 0, the codeword corresponding to the variable node is determined to be 0. The codewords corresponding to each variable node are arranged sequentially to obtain the codeword vector. c If the remainder function of the extended parity-check matrix and the codeword vector c is... The result of the operation is calculated. If the result is equal to 0, the iteration stopping condition is met, the decoding is successful, and the first K codewords in the codeword vector are selected as the decoding result, i.e., the original bit information. If the result is not equal to 0, the iteration stopping condition is not met, and the decoding is not yet successful.

[0151] Specifically, when decoding has not yet succeeded, this embodiment can add the initial log-likelihood ratio of the variable node to the external confidence level passed from the variable node to the verification node to obtain a new confidence level passed from the variable node to the verification node. For example... Figure 3 As shown, Represents variable nodes j To the verification node i The new confidence level is transmitted. The variable node represents the variable node. The calculation formula is a minimum and approximate algorithm. The normalization coefficient is... express sign The function is min, which is the function to find the minimum value.

[0152] At this point, this embodiment can determine the new confidence level passed by each variable node to each check node. Then, this embodiment can use the new confidence level passed by each variable node to each check node as the current confidence level, return to step S103, and continue until the remainder of the extended parity-check matrix and the latest codeword vector equals 0, confirming successful decoding and obtaining the corresponding decoding result, i.e., the original bit information.

[0153] It should be noted that the Turbo decoding method used in related technologies involves a large number of discrete fixed-point number operations. The energy efficiency of communication baseband based on traditional digital circuits is severely limited by the power consumption and cost of random access memory, as well as the energy overhead brought by discrete fixed-point number operations in the digital domain. The digital circuit processing paradigm in related technologies cannot fundamentally achieve a breakthrough in energy efficiency. In particular, a standard Turbo decoder requires a large number of on-chip memory units to cache intermediate operation data and powerful processing units to perform multiple iterative operations, which directly leads to a large chip area and significant power consumption.

[0154] The Turbo code logarithmic field decoding method based on in-memory computing proposed in this embodiment can store some static variables in devices with in-memory computing characteristics such as memristors, thereby transferring some digital operations to the analog domain and using Kirchhoff's circuit laws for computation. This method breaks through the power consumption bottleneck of digital circuits, realizes innovation in decoding mode and efficient reuse of computing resources, and provides a high-efficiency decoding solution with significantly reduced hardware overhead for low-power edge devices.

[0155] like Figure 4 As shown, this embodiment proposes a Turbo code logarithmic field decoding device based on a memory computing unit, applied at the decoding end. The device may include:

[0156] The acquisition unit 101 is used to acquire the probabilistic graphical model corresponding to the Turbo code to be decoded, and the initial log-likelihood ratio of each variable node in the probabilistic graphical model; wherein, the Turbo code to be decoded is obtained by digitally modulating the original Turbo code at the encoding end, the original Turbo code is obtained by Turbo encoding the original bit information at the encoding end, and the initial log-likelihood ratio of the variable node is determined according to the logarithmic field operation method;

[0157] Unit 102 is used to take the initial log-likelihood ratio of each variable node as the confidence level that the variable node transmits to each verification node connected to the variable node through an undirected edge.

[0158] The determining unit 103 is used to determine the confidence level that each verification node transmits to each variable node based on the confidence level that each variable node transmits to each verification node.

[0159] Create unit 104 to create a unified driving vector, an external confidence update column vector corresponding to each undirected edge, and an external log-likelihood ratio update column vector corresponding to each variable node based on the confidence and probabilistic graphical model passed from each verification node to each variable node.

[0160] Configuration unit 105 is used to configure the node state in the in-memory computing unit according to each external confidence update column vector and each external log-likelihood ratio update column vector to obtain the external confidence update array and the external log-likelihood ratio update array.

[0161] Iteration unit 106, based on a unified driving vector, an external confidence update array, and an external log-likelihood ratio update array, iteratively updates the confidence level and log-likelihood ratio of each variable node to each verification node until the iteration stopping condition is met, so as to decode the original bit information.

[0162] It should be noted that the processing steps of acquiring unit 101, designating unit 102, determining unit 103, creating unit 104, configuring unit 105, and iterating unit 106, and their beneficial effects, can be referred to respectively. Figure 1 Steps S101 to S105 are not described in detail here.

[0163] Optionally, the acquisition unit 101 is also used for:

[0164] Receive the Turbo code to be decoded sent by the encoder and obtain the noise power corresponding to the Turbo code to be decoded;

[0165] Based on the Turbo code to be decoded, create an initial parity check matrix and a corresponding initial probabilistic graphical model;

[0166] Eliminate short loop structures in the initial parity check matrix and the initial probabilistic graphical model to obtain the extended parity check matrix and the corresponding probabilistic graphical model;

[0167] The initial log-likelihood ratio for each variable node is determined based on the noise power, the Turbo code to be decoded, and the logarithmic field operation method.

[0168] Optionally, the determining unit 103 is also used for:

[0169] For any verification node, determine the minimum confidence level from the target confidence levels passed from each first variable node to the verification node. If the target confidence level is greater than 1, define the target value corresponding to the target confidence level as 1; if the target confidence level is less than 0, define the target value corresponding to the target confidence level as -1; if the target confidence level is equal to 0, define the target value corresponding to the target confidence level as 0. Multiply the target value corresponding to each target confidence level, the minimum confidence level, and the set normalization coefficient to obtain the corresponding product, which is used as the confidence level passed from the verification node to the second variable node. Here, the second variable node is a variable node connected to the verification node, and the first variable node is a variable node other than the second variable node among all the variable nodes connected to the verification node.

[0170] Optionally, creating unit 104 is also used for:

[0171] Starting from 1, number each variable node sequentially to obtain the first node number of each variable node; and starting from 1, number each verification node sequentially to obtain the second node number of each verification node.

[0172] For any undirected edge, combine the first node index of the variable node connected by the undirected edge and the second node index of the check node connected by the undirected edge to obtain the edge index of the undirected edge.

[0173] Arrange the edge indices of each undirected edge to obtain an edge index vector;

[0174] Arrange the first node number in each edge number of the edge number vector in turn to obtain the variable number vector; and arrange the second node number in each edge number vector in turn to obtain the verification number vector.

[0175] A unified driving vector is created based on the verification sequence vector, the variable sequence vector, and the confidence level passed from each verification node to each variable node.

[0176] Based on the verification index vector and the variable index vector, create an external confidence update column vector for each undirected edge; and based on the variable index vector, create an external log-likelihood ratio update column vector for each variable node.

[0177] Optionally, creating unit 104 is also used for:

[0178] In each undirected edge, select the first edge number with the first node number 1 from the edge numbers, and sort each first edge number in ascending order of the second node number to obtain the corresponding first edge number subvector; in each undirected edge, select the second edge number with the first node number 2 from the edge numbers, and sort each second edge number in ascending order of the second node number to obtain the corresponding second edge number subvector; in each undirected edge, select the third edge number with the first node number 3 from the edge numbers, and so on until each edge number subvector is obtained;

[0179] Sort each edge number subvector in the order in which they were obtained to obtain the edge number vector.

[0180] Optionally, the number of elements in both the verification index vector and the variable index vector is equal to the total number of undirected edges M; creating cell 104 is also used for:

[0181] Arrange the first confidence level, the second confidence level, up to the Mth confidence level in sequence to obtain the unified driving vector;

[0182] Wherein, the k-th confidence level is any confidence level from the first confidence level to the M-th confidence level, and the k-th confidence level is specifically the confidence level passed from the verification node corresponding to the k-th second node in the verification sequence number vector to the variable node corresponding to the k-th first node in the variable sequence number vector.

[0183] Optionally, creating unit 104 is also used for:

[0184] Traverse each edge number in the edge number vector in the order of the elements;

[0185] For the traversal of the first m The edge sequence number is used to create the edge with the first edge. mThe first null column vector with M elements corresponding to each edge index;

[0186] For any position of the first element in the first null column vector, determine the order 'a' of the first element position. If 'a' satisfies a first predefined condition, assign the value 1 to the element corresponding to the first element position; otherwise, assign the value 0 to the element corresponding to the first element position. The first predefined condition is that the order 'a' of the variable index vector and the order 'a' of the variable index vector are... m All elements are of equal size, and the a-th element in the verification sequence vector is equal to the a-th element in the verification sequence vector. m The elements are of different sizes;

[0187] The column vector obtained by assigning values ​​to each element at the first element position in the first null value column vector is determined as the external confidence update column vector corresponding to the target undirected edge; where the target undirected edge is the first... m The undirected edges corresponding to the edge indices;

[0188] Optionally, creating unit 104 is also used for:

[0189] Traverse each variable node in ascending order of its first node number;

[0190] For the traversed number... j The first variable node, created in relation to the first... j A second null value column vector with M elements corresponding to each variable node;

[0191] For any position of the second element in the second null value column vector, determine the order b of the second element positions. If b satisfies a second predefined condition, assign the value 1 to the element corresponding to the second element position; otherwise, assign the value 0 to the element corresponding to the second element position. The second predefined condition is that the b-th element in the variable index vector is... j They are the same size;

[0192] The column vector obtained by assigning values ​​to the elements at the second element position in the second null column vector is determined as the first null column vector. j The external log-likelihood ratio of each variable node updates the column vector.

[0193] Optionally, configuration unit 105 is also used for:

[0194] Arrange each external confidence update column vector in the order they were obtained to obtain the external confidence update matrix; and arrange each external log-likelihood ratio update column vector in the order they were obtained to obtain the external likelihood ratio update matrix.

[0195] In the in-memory computing unit, a first node array to be configured is determined, whose number of node rows and columns corresponds to the number of element rows and columns of the external confidence update matrix, and a second node array to be configured is determined, which is horizontally adjacent to the first node array to be configured and whose number of node rows and columns corresponds to the number of element rows and columns of the external likelihood ratio update matrix.

[0196] The node state at each position of the first node array to be configured is configured according to the element value at each position in the external confidence update matrix, thus obtaining the external confidence update array; the node state at each position of the second node array to be configured is configured according to the element value at each position in the external likelihood ratio update matrix, thus obtaining the external log-likelihood ratio update array.

[0197] Optionally, when the in-memory computing unit is a memristor, the unified drive vector is a unified voltage vector;

[0198] Iteration unit 106 is also used for:

[0199] The voltage corresponding to each element in the unified voltage vector is input into each row of the external confidence update array and the external log-likelihood ratio update array, respectively. The first current output of each node column in the external confidence update array and the second current output of each node column in the external log-likelihood ratio update array are read.

[0200] Each first current is used as the external confidence level transmitted from each variable node to each verification node, and each second current is used as the external log-likelihood ratio of each variable node.

[0201] Add the initial log-likelihood ratio of each variable node to its external log-likelihood ratio to obtain the new log-likelihood ratio for each variable node.

[0202] Hard decision is made on the new log-likelihood ratio of each variable node to obtain the codeword vector;

[0203] If the remainder of the extended parity-check matrix and the codeword vector corresponding to the probabilistic graphical model is not equal to 0, then the external confidence level passed from each variable node to each parity-check node is added to the initial log-likelihood ratio of the variable node to obtain the new confidence level passed from each variable node to each parity-check node, and these new confidence levels are used as the current confidence levels passed from each variable node to each parity-check node. The process then returns to the step of determining the confidence level passed from each parity-check node to each variable node based on the confidence level passed from the variable node to each parity-check node, until the latest remainder result is equal to 0, at which point the iteration stops.

[0204] Determine the total number of characters K in the original bit information, and select the first K elements from the latest codeword vector as the original bit information.

[0205] The Turbo code logarithmic field decoding device based on an in-memory computing unit proposed in this embodiment can create a unified driving vector, an external confidence update column vector corresponding to each undirected edge, and an external log-likelihood ratio update column vector corresponding to each variable node according to the probabilistic graphical model corresponding to the Turbo code to be decoded. Based on each external confidence update column vector and external log-likelihood ratio update column vector, an external confidence update array and an external log-likelihood ratio update array are configured in the in-memory computing unit. Based on the unified driving vector, the external confidence update array and the external log-likelihood ratio update array are driven to perform external confidence and external log-likelihood ratio calculations and updates respectively until Turbo decoding is completed, obtaining the original bit information. This invention stores some static variables involved in Turbo decoding in the in-memory computing unit and transfers some digital operations to the in-memory computing unit, utilizing the storage and computing performance of the in-memory computing unit for computation, overcoming the power consumption bottleneck, and significantly reducing its hardware resource consumption and power consumption while retaining the excellent error correction capability of Turbo codes.

[0206] In this embodiment, the Turbo code logarithmic field decoding device based on in-memory computing is presented in the form of a functional unit. Here, a unit refers to an ASIC (Application Specific Integrated Circuit) circuit, a processor and memory that execute one or more software or fixed programs, and / or other devices that can provide the above functions.

[0207] This invention also provides a computer device having the above-described features. Figure 4 The Turbo code logarithmic field decoding device based on in-memory computing is shown.

[0208] Please see Figure 5 The present invention provides a schematic diagram of the structure of a computer device according to an optional embodiment. The computer device includes one or more processors 10, a memory 20, and interfaces for connecting the various components, including high-speed interfaces and low-speed interfaces. The various components are interconnected via different buses and can be mounted on a common motherboard or otherwise installed as needed. The processors can process instructions executed within the computer device, including instructions stored in or on memory to display graphical information of a GUI on an external input / output device (such as a display device coupled to the interface). In some optional embodiments, multiple processors and / or multiple buses can be used with multiple memories, if desired. Similarly, multiple computer devices can be connected, each providing some of the necessary operations (e.g., as a server array, a group of blade servers, or a multiprocessor system). Figure 5 Take a processor 10 as an example.

[0209] Processor 10 may be a central processing unit, a network processor, or a combination thereof. Processor 10 may further include a hardware chip. The hardware chip may be an application-specific integrated circuit (ASIC), a programmable logic device (PLD), or a combination thereof. The programmable logic device may be a complex programmable logic device (CAMP), a field-programmable gate array (FPGA), a general-purpose array logic (GPA), or any combination thereof.

[0210] The memory 20 stores instructions executable by at least one processor 10 to cause at least one processor 10 to perform the method shown in the above embodiments.

[0211] The memory 20 may include a program storage area and a data storage area. The program storage area may store the operating system and applications required for at least one function. The data storage area may store data created based on the use of the computer device. Furthermore, the memory 20 may include high-speed random access memory and may also include non-transitory memory, such as at least one disk storage device, flash memory device, or other non-transitory solid-state storage device. In some alternative embodiments, the memory 20 may optionally include memory remotely located relative to the processor 10, which can be connected to the computer device via a network. Examples of such networks include, but are not limited to, the Internet, intranets, local area networks, mobile communication networks, and combinations thereof.

[0212] Memory 20 may include volatile memory, such as random access memory. Memory may also include non-volatile memory, such as flash memory, hard disk, or solid-state drive. Memory 20 may also include combinations of the above types of memory.

[0213] The computer device also includes a communication interface 30 for communicating with other devices or communication networks.

[0214] This invention also provides a computer-readable storage medium. The methods described above according to embodiments of the invention can be implemented in hardware or firmware, or implemented as computer code that can be recorded on a storage medium, or implemented as computer code downloaded over a network and originally stored on a remote storage medium or a non-transitory machine-readable storage medium and then stored on a local storage medium. Thus, the methods described herein can be processed by software stored on a storage medium using a general-purpose computer, a dedicated processor, or programmable or dedicated hardware. The storage medium can be a magnetic disk, optical disk, read-only memory, random access memory, flash memory, hard disk, or solid-state drive, etc.; further, the storage medium can also include combinations of the above types of memory. It is understood that computers, processors, microprocessor controllers, or programmable hardware include storage components capable of storing or receiving software or computer code, which, when accessed and executed by the computer, processor, or hardware, implements the methods shown in the above embodiments.

[0215] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, and not to limit them; although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features; and these modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of the present invention.

Claims

1. A Turbo code logarithmic field decoding method based on a memory-based computing device, characterized in that, Applied to the decoding end, the method includes: Obtain the probabilistic graphical model corresponding to the Turbo code to be decoded, and the initial log-likelihood ratio of each variable node in the probabilistic graphical model; wherein, the initial log-likelihood ratio of the variable node is determined according to the logarithmic field operation method; The initial log-likelihood ratio of each variable node is used as the confidence level that the variable node transmits to each verification node connected to the variable node through an undirected edge. The confidence level transmitted by each of the variable nodes to each of the verification nodes is determined based on the confidence level transmitted by each of the variable nodes to each of the verification nodes. Based on the confidence level passed from each verification node to each variable node and the probabilistic graphical model, a unified driving vector, an external confidence level update column vector corresponding to each undirected edge, and an external log-likelihood ratio update column vector corresponding to each variable node are created. Configure the node states in the in-memory compute unit based on each of the external confidence update column vectors and each of the external log-likelihood ratio update column vectors to obtain the external confidence update array and the external log-likelihood ratio update array. Based on the unified driving vector, the external confidence update array, and the external log-likelihood ratio update array, the confidence level and the log-likelihood ratio of each variable node transmitted to each check node are iteratively updated until the iteration stopping condition is met, so as to decode the original bit information corresponding to the Turbo code to be decoded.

2. The method according to claim 1, characterized in that, The Turbo code to be decoded is obtained by digital modulation of the original Turbo code by the encoding end, and the original Turbo code is obtained by Turbo encoding of the original bit information by the encoding end; The process of obtaining the probabilistic graphical model corresponding to the Turbo code to be decoded, and the initial log-likelihood ratio of each variable node in the probabilistic graphical model, includes: Receive the Turbo code to be decoded sent by the encoding end, and obtain the noise power corresponding to the Turbo code to be decoded; Based on the Turbo code to be decoded, create an initial parity-check matrix and a corresponding initial probability graphical model; Eliminate the short loop structures in the initial parity-check matrix and the initial probabilistic graphical model to obtain the extended parity-check matrix and the corresponding probabilistic graphical model; The initial log-likelihood ratio of each variable node is determined based on the noise power, the Turbo code to be decoded, and the logarithmic field operation method.

3. The method according to claim 1, characterized in that, The step of determining the confidence level transmitted by each verification node to each variable node based on the confidence level transmitted by each variable node to each verification node includes: For any of the verification nodes, a minimum confidence level is determined from the target confidence levels transmitted from each first variable node to the verification node. If the target confidence level is greater than 1, the target value corresponding to the target confidence level is defined as 1; if the target confidence level is less than 0, the target value corresponding to the target confidence level is defined as -1; if the target confidence level is equal to 0, the target value corresponding to the target confidence level is defined as 0. The target value corresponding to each target confidence level, the minimum confidence level, and the set normalization coefficient are multiplied to obtain the corresponding product, which is used as the confidence level transmitted from the verification node to the second variable node. The second variable node is a variable node connected to the verification node, and the first variable node is a variable node other than the second variable node among all the variable nodes connected to the verification node.

4. The method according to claim 1, characterized in that, The process of creating a unified driving vector, an external confidence update column vector corresponding to each undirected edge, and an external log-likelihood ratio update column vector corresponding to each variable node based on the confidence level transmitted from each verification node to each variable node and the probabilistic graphical model includes: Starting from 1, each variable node is numbered sequentially to obtain the first node number of each variable node; and starting from 1, each verification node is numbered sequentially to obtain the second node number of each verification node. For any of the undirected edges, the first node index of the variable node connected to the undirected edge and the second node index of the check node connected to the undirected edge are combined to obtain the edge index of the undirected edge. Arrange the edge indices of each undirected edge to obtain an edge index vector; Arrange the first node number in each edge number of the edge number vector in sequence to obtain the variable number vector; and arrange the second node number in each edge number of the edge number vector in sequence to obtain the verification number vector. The unified driving vector is created based on the verification sequence vector, the variable sequence vector, and the confidence level passed from each verification node to each variable node. Based on the verification index vector and the variable index vector, create an external confidence update column vector corresponding to each undirected edge; and based on the variable index vector, create an external log-likelihood ratio update column vector corresponding to each variable node.

5. The method according to claim 4, characterized in that, The step of arranging the edge indices of each undirected edge to obtain an edge index vector includes: In each of the undirected edges, select each first edge number with the first node number 1 from the edge numbers, and sort each first edge number in ascending order of the second node number to obtain the corresponding first edge number subvector; in each of the undirected edges, select each second edge number with the first node number 2 from the edge numbers, and sort each second edge number in ascending order of the second node number to obtain the corresponding second edge number subvector; in each of the undirected edges, select each third edge number with the first node number 3 from the edge numbers, until each edge number subvector is obtained; The edge number subvectors are sorted sequentially according to the order in which they are obtained to obtain the edge number vector.

6. The method according to claim 5, characterized in that, The number of elements in both the verification sequence vector and the variable sequence vector is equal to the total number of undirected edges M. The step of creating the unified driving vector based on the verification sequence vector, the variable sequence vector, and the confidence level passed from each verification node to each variable node includes: The unified driving vector is obtained by sequentially arranging the first confidence level, the second confidence level, up to the Mth confidence level; Wherein, the k-th confidence level is any confidence level from the first confidence level to the M-th confidence level, and the k-th confidence level is specifically the confidence level passed from the verification node corresponding to the k-th second node number in the verification sequence number vector to the variable node corresponding to the k-th first node number in the variable sequence number vector.

7. The method according to claim 6, characterized in that, The step of creating an external confidence update column vector corresponding to each undirected edge based on the verification index vector and the variable index vector includes: According to the order of the elements, traverse each edge number in the edge number vector in sequence; For the traversal of the first The edge number is used to create a sequence with the first edge. A first null column vector with M elements corresponding to the edge indices; For any first element position in the first null value column vector, determine the order 'a' of the first element position. If 'a' satisfies a first set condition, assign the value 1 to the element corresponding to the first element position; otherwise, assign the value 0 to the element corresponding to the first element position. The first set condition is that the order 'a' of the variable index vector and the order 'a' of the variable index vector are... All elements are of equal size, and the a-th element in the verification sequence vector is equal to the a-th element in the verification sequence vector. The elements are of different sizes; The column vector obtained by assigning values ​​to each element at the first element position in the first null value column vector is determined as the external confidence update column vector corresponding to the target undirected edge; wherein, the target undirected edge is the first... The undirected edges corresponding to the edge indices; The step of creating an external log-likelihood ratio update column vector for each variable node based on the variable index vector includes: In ascending order of the first node number, each variable node is traversed sequentially. For the traversed number... The variable node mentioned above is created in relation to the first... A second null value column vector corresponding to each variable node and having M elements; For any position of the second element in the second null value column vector, determine the order b of the second element positions. If b satisfies a second set condition, assign the value 1 to the element corresponding to the second element position; if b does not satisfy the second set condition, assign the value 0 to the element corresponding to the second element position. The second set condition is that the b-th element in the variable index vector is... They are the same size; The column vector obtained by assigning values ​​to each element at the second element position in the second null value column vector is determined as the first column vector. The external log-likelihood ratio of each variable node updates the column vector.

8. The method according to claim 7, characterized in that, The step of configuring the node states in the in-memory compute unit based on each of the external confidence update column vectors and each of the external log-likelihood ratio update column vectors to obtain the external confidence update array and the external log-likelihood ratio update array includes: The external confidence update column vectors are arranged sequentially according to the order in which they are obtained to obtain the external confidence update matrix; and the external log-likelihood ratio update column vectors are arranged sequentially according to the order in which they are obtained to obtain the external likelihood ratio update matrix. In the in-memory computing unit, a first node array to be configured is determined, whose number of node rows and columns corresponds to the number of element rows and columns of the external confidence update matrix; and a second node array to be configured is determined, which is horizontally adjacent to the first node array to be configured, and whose number of node rows and columns corresponds to the number of element rows and columns of the external likelihood ratio update matrix. The node state at each position of the first node array to be configured is configured according to the element value at each position in the external confidence update matrix to obtain the external confidence update array; the node state at each position of the second node array to be configured is configured according to the element value at each position in the external likelihood ratio update matrix to obtain the external log-likelihood ratio update array.

9. The method according to claim 8, characterized in that, When the in-memory computing unit is a memristor, the unified drive vector is a unified voltage vector; The process involves iteratively updating the confidence level and log-likelihood ratio of each variable node transmitted to each check node based on the unified driving vector, the external confidence update array, and the external log-likelihood ratio update array, until the iteration stopping condition is met, in order to decode the original bit information corresponding to the Turbo code to be decoded, including: The voltage corresponding to each element in the unified voltage vector is input to each row node of the external confidence update array and the external log-likelihood ratio update array, respectively. The first current output by each node column in the external confidence update array and the second current output by each node column in the external log-likelihood ratio update array are read. Each of the first currents is used as the external confidence level transmitted from each of the variable nodes to each of the verification nodes, and each of the second currents is used as the external log-likelihood ratio of each of the variable nodes. Add the external log-likelihood ratio of each variable node to the initial log-likelihood ratio of the variable node to obtain the new log-likelihood ratio of each variable node; Hard decision is made on the new log-likelihood ratio of each variable node to obtain the codeword vector; If the remainder of the extended parity-check matrix corresponding to the probabilistic graphical model and the codeword vector is not equal to 0, then the external confidence level passed by each variable node to each parity-check node is added to the initial log-likelihood ratio of the variable node to obtain the new confidence level passed by each variable node to each parity-check node, and these new confidence levels are used as the current confidence levels passed by each variable node to each parity-check node. Then, the step of determining the confidence level passed by each parity-check node to each variable node based on the confidence level passed by each variable node to each parity-check node is returned to be executed until the latest remainder result is equal to 0. If the result of the modulo operation is equal to 0, then the total number of characters K of the original bit information is determined, and the first K elements in the latest codeword vector are selected as the original bit information.

10. A Turbo code logarithmic field decoding device based on a memory computing unit, characterized in that, Applied to a decoding end, the device includes: The acquisition unit is used to acquire the probabilistic graphical model corresponding to the Turbo code to be decoded, and the initial log-likelihood ratio of each variable node in the probabilistic graphical model; wherein the initial log-likelihood ratio of the variable node is determined according to the logarithmic field operation method; As a unit, it is used to take the initial log-likelihood ratio of each variable node as the confidence level that the variable node transmits to each verification node connected to the variable node through an undirected edge; A determining unit is configured to determine the confidence level transmitted by each of the variable nodes to each of the verification nodes based on the confidence level transmitted by each of the variable nodes to each of the verification nodes. A creation unit is used to create a unified driving vector, an external confidence update column vector corresponding to each undirected edge, and an external log-likelihood ratio update column vector corresponding to each variable node based on the confidence level passed from each verification node to each variable node and the probabilistic graphical model. A configuration unit is used to configure the node state in the in-memory compute unit according to each of the external confidence update column vectors and each of the external log-likelihood ratio update column vectors, so as to obtain the external confidence update array and the external log-likelihood ratio update array. The iterative unit, based on the unified driving vector, the external confidence update array, and the external log-likelihood ratio update array, iteratively updates the confidence level transmitted by each variable node to each check node and the log-likelihood ratio of each variable node until the iteration stopping condition is met, so as to decode the original bit information.

Images