Turbo code probability domain decoding method and device based on storage and calculation all-in-one device

Abstract

The invention relates to the technical field of communication, and discloses a Turbo code probability domain decoding method and device based on a storage and calculation all-in-one device, which are applied to a decoding end. According to the method, an expansion check matrix and a probability graph model can be constructed, and a storage and calculation all-in-one device sub-array and a driving vector corresponding to each undirected edge are configured according to the expansion check matrix, the probability graph model and a probability domain operation mode; and interpreting the Turbo code to be interpreted based on the storage and calculation integrator sub-array corresponding to each undirected edge, the driving vector and the confidence coefficient of each variable node transmitting the own state value to each check node connected through the undirected edge to obtain corresponding original bit information. According to the invention, part of static variables involved in Turbo decoding can be stored in the storage and calculation all-in-one device based on the probability field, part of digital operation is transferred to the storage and calculation all-in-one device, operation is carried out by using the storage and calculation performance of the storage and calculation all-in-one device, and the hardware resource consumption and power consumption of the Turbo code are remarkably reduced while the excellent error correction capability of the Turbo code is reserved.

Description

Technical Field

[0001] This invention relates to the field of communication technology, and in particular to a Turbo code probability domain decoding method and apparatus based on a memory computing device. Background Technology

[0002] In modern digital communication systems, Turbo codes, as a revolutionary channel coding scheme, have been widely used in the field of communication due to their excellent error correction performance, which approaches the Shannon limit.

[0003] Turbo decoding in related technologies relies on complex iterative algorithms, which involve repeatedly exchanging external information between two or more component soft-input soft-output decoders. This iterative mechanism is the source of its high performance. However, Turbo decoding in related technologies has relatively high power consumption. Summary of the Invention

[0004] This invention provides a Turbo code probability domain decoding method and apparatus based on a memory computing device to solve the problem of high power consumption in related technologies and reduce the power consumption of Turbo decoding.

[0005] In a first aspect, the present invention provides a Turbo code probability domain decoding method based on an in-memory computing device, applied at the decoding end, the method comprising: Obtain the extended parity-check matrix and probabilistic graphical model corresponding to the Turbo code to be decoded, as well as the initial probability of the state value of each variable node in the probabilistic graphical model; wherein, the initial probability of the state value of the variable node is determined based on the probability domain operation method; The initial probability of the state value of each variable node is used as the confidence level by which the variable node passes its own state value to each verification node connected by undirected edges; For any of the verification nodes, based on each target undirected edge between the verification node and each connected target variable node, and based on the extended verification matrix, a node state matrix corresponding to each target undirected edge is constructed. Based on each target undirected edge and the confidence that each target variable node transmits its own state value to the verification node, a driving vector corresponding to each target undirected edge is constructed. The in-memory compute unit is configured based on the node state matrix corresponding to each undirected edge to obtain the in-memory compute unit subarray corresponding to each undirected edge; Based on the driving vector corresponding to each undirected edge, the in-memory compute subarray, and each confidence level, the confidence level transmitted by each variable node to each verification node and the new probability of the state value of each variable node are iteratively updated until the set iteration stopping condition is met, so as to decode the original bit information.

[0006] Secondly, the present invention provides a Turbo code probability domain decoding device based on a memory-based computing unit, applied at a decoding end, the device comprising: The acquisition unit is used to acquire the extended parity-check matrix and probabilistic graphical model corresponding to the Turbo code to be decoded, as well as the initial probability of the state value of each variable node in the probabilistic graphical model; wherein, the initial probability of the state value of the variable node is determined based on the probability domain operation method; As a unit, it is used to set the initial probability of the state value of each variable node as the confidence level of the variable node to pass its own state value to each verification node connected by undirected edges. The first construction unit is used to construct, for any verification node, a node state matrix corresponding to each target undirected edge based on each target undirected edge between the verification node and each target variable node connected to it, and based on the extended verification matrix. The second construction unit is used to construct the driving vector corresponding to each of the target undirected edges based on the confidence of each target variable node in passing its own state value to the verification node. The configuration unit is used to configure the in-memory compute unit based on the node state matrix corresponding to each undirected edge, so as to obtain the in-memory compute unit subarray corresponding to each undirected edge. The decoding unit is used to iteratively update the confidence level transmitted by each variable node to each verification node and the new probability of the state value of each variable node according to the driving vector corresponding to each undirected edge, the in-memory compute subarray and each confidence level, until the set iteration stop condition is met, so as to decode the original bit information.

[0007] Thirdly, the present invention provides a computer device, including: a memory and a processor, the memory and the processor being communicatively connected to each other, the memory storing computer instructions, and the processor executing the computer instructions to perform the Turbo code probability domain decoding method based on the in-memory computing unit described in the first aspect or any corresponding embodiment.

[0008] Fourthly, the present invention provides a computer-readable storage medium storing computer instructions for causing a computer to execute the Turbo code probability domain decoding method based on the first aspect or any corresponding embodiment described above.

[0009] This invention provides a Turbo code probabilistic domain decoding method and apparatus based on an in-memory computing unit (IMU). Applied to the decoding end, it constructs an extended parity-check matrix (EPC) matrix and a probabilistic graphical model. Based on the EPC matrix, probabilistic graphical model, and probabilistic domain operation method, it configures the IMU subarray and voltage vector corresponding to each undirected edge. Based on the IMU subarray, driving vector, and the confidence level of each variable node transmitting its own state value to each parity-check node connected by the undirected edge, it iteratively updates the confidence level transmitted by each variable node to each parity-check node and the new probability of each variable node's state value until a set iteration stopping condition is met. This process decodes the Turbo code to be decoded, obtaining the original bit information. This invention can store some static variables involved in Turbo decoding in the IMU and transfer some digital operations to the IMU, utilizing the storage and computing performance of the IMU for computation. This overcomes the power consumption bottleneck, significantly reducing hardware resource consumption and power consumption while retaining the excellent error correction capability of Turbo codes. Attached Figure Description

[0010] To more clearly illustrate the technical solutions in this invention or related technologies, the accompanying drawings used in the description of the embodiments or related technologies will be briefly introduced below. Obviously, the accompanying drawings described below are some embodiments of this invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0011] Figure 1 A flowchart of a Turbo code probability domain decoding method based on a memory computing device is provided in an embodiment of the present invention; Figure 2 A verification node in a probabilistic graphical model provided in an embodiment of the present invention. i A diagram illustrating the connection relationships between various variable nodes; Figure 3 A parallel decoding processing architecture provided in this embodiment of the invention; Figure 4 A schematic diagram of the structure of a Turbo code probability domain decoding device based on a memory computing unit provided in an embodiment of the present invention; Figure 5 This is a schematic diagram of the structure of a computer device provided in an embodiment of the present invention. Detailed Implementation

[0012] To make the objectives, technical solutions, and advantages of this invention clearer, the technical solutions of this invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this invention. All other embodiments obtained by those skilled in the art based on the embodiments of this invention without creative effort are within the scope of protection of this invention.

[0013] The following is combined Figures 1-3 The present invention describes the Turbo code probability domain decoding method based on an in-memory computing device.

[0014] like Figure 1 As shown, this embodiment proposes a first Turbo code probabilistic domain decoding method based on a memory-based computing device, applied to the decoding end. This method may include the following steps: S101. Obtain the extended parity-check matrix and probabilistic graphical model corresponding to the Turbo code to be decoded, as well as the initial probability of the state value of each variable node in the probabilistic graphical model. The Turbo code to be decoded is obtained by digitally modulating the original Turbo code at the encoding end and sending it to the decoding end. The original Turbo code is obtained by Turbo encoding the original bit information at the encoding end. The initial probability of the state value of the variable node is determined based on probability domain operations.

[0015] It should be noted that this embodiment can be applied to the decoding end to decode the Turbo code to be decoded obtained by the encoding end using Turbo encoding and digital modulation to obtain the original bit information.

[0016] Taking Binary Phase Shift Keying (BPSK) as an example, this paper introduces the communication between the encoder and decoder, and the decoding objective of this embodiment. Specifically, the encoder can encode the original bit information K codewords into N codewords using a Turbo encoder. x Then, based on BPSK modulation, N symbols s are generated and sent to the decoding end. Due to noise interference during transmission, the decoding end in this embodiment receives N symbols. y The decoding task at the decoding end is to... y The original K codewords, or raw bit information, are restored.

[0017] In-memory computing devices are integrated devices that combine storage and computing capabilities, such as resistive random access memory (RRAM), phase-change memory (PCM), magnetic memory (MRAM), and flash memory.

[0018] The Turbo code to be decoded can be the received Turbo code sent by the encoder that needs to be decoded. The Turbo code to be decoded can include N codewords, where N is an integer greater than 1.

[0019] The extended parity-check matrix is ​​a parity-check matrix created based on the Turbo code to be decoded, used for decoding the Turbo code.

[0020] Specifically, the probabilistic graphical model is a unified probabilistic graphical model corresponding to the extended parity-check matrix, used for decoding the Turbo code to be decoded.

[0021] Specifically, a probabilistic graphical model can include multiple variable nodes, multiple check nodes, and multiple undirected edges. Undirected edges are used to connect variable nodes and check nodes that have a connection relationship. Each variable node uniquely corresponds to a column vector in the extended check matrix, and each check node uniquely corresponds to a row vector in the extended check matrix. If the row order in the extended check matrix is ​​equal to... i Column order equals j If the element is 1, then the order of the first node is equal to... i The order of the verification node and the second node is equal to j The variable nodes have a connection relationship. If the row order in the extended parity matrix is ​​equal to... i Column order equals j If the element is 0, then the order of the first node is equal to... i The order of the verification node and the second node is equal to j The variable nodes have no connection relationship. The first node's order is the sequence number of the check node among all check nodes, and the second node's order is the sequence number of the variable node among all variable nodes.

[0022] To better illustrate the relationship between the extended parity-check matrix and the probabilistic graphical model, as well as the relationship between variable nodes, parity nodes, and undirected edges, the following Example 1 is presented and combined with... Figure 2 Let me introduce it.

[0023] Example 1: When the extended parity-check matrix H Given a matrix of I rows and J columns, where the row vector of the third row is [0, 1, 1, 1, 0, 0], the probabilistic graphical model includes I check nodes and J variable nodes (in this case, J is 6). The third check node in the probabilistic graphical model... i (at this time, i 3) The connection relationships between the variables and the nodes are as follows: Figure 2 As shown in the diagram, the 2nd, 3rd, and 4th elements of this row vector are 1, and the 1st, 5th, and 6th elements are 0. Therefore, the 3rd check node is connected to the 2nd, 3rd, and 4th variable nodes via undirected edges, while the 3rd check node is not connected to the 1st, 5th, and 6th variable nodes. It should be noted that... Figure 2Apart from the third verification node, the connection relationships between other verification nodes and variable nodes are not shown. The connection relationships between other verification nodes and variable nodes can be understood by referring to the connection relationship between the third verification node and variable nodes mentioned above.

[0024] Each variable node's initial probability state value can include the first and second initial probabilities, given that the original Turbo codewords corresponding to the variable node are 1 and 0, respectively.

[0025] Optionally, step S101 includes: Receive the Turbo code to be decoded sent by the encoder and determine the noise variance corresponding to the Turbo code to be decoded; Based on the Turbo code to be decoded, create an initial parity-check matrix and a corresponding initial probabilistic graphical model; Eliminate short loop structures in the initial parity check matrix and the initial probabilistic graphical model to obtain the extended parity check matrix and the probabilistic graphical model; The initial probability of the state value of each variable node is determined based on the noise variance and the probability domain operation method. The initial probability of the state value of each variable node includes the first initial probability and the second initial probability, given that the original Turbo codeword of the variable node is 1 and 0 respectively, under the condition that the extended codeword of the variable node is known.

[0026] Specifically, this embodiment can establish algebraic constraints based on the two recursive systematic convolutional (RSC) components of the Turbo encoder. Let the input information sequence be... System bits and check bits The check bits are determined by two generator polynomials set internally by the RSC encoder. These two generator polynomials include a feedback polynomial and a feedforward polynomial.

[0027] Specifically, in this embodiment, the generator polynomial described above can be used to map the Galois field GF(2) to binary coefficient vectors [1,0,1,1] and [1,1,0,1]. Based on the number of encoded information bits K, a cyclic shift is performed (the first row is padded with 0s to length K, the second row is obtained by cyclically shifting one bit to the right of the first row padded with 0s to length K, the third row is obtained by cyclically shifting one bit to the right of the second row again, and so on) to obtain a K×K cyclic shift matrix. and For example, when K equals 8, and the generator polynomial is mapped to a binary coefficient vector [1,0,1,1], an 8×8 cyclic shift matrix can be constructed: .

[0028] This embodiment can be used to construct a cyclic shift matrix. and By performing horizontal concatenation, the component verification matrix is ​​obtained. .

[0029] Wherein, the component parity check matrix satisfies . Indicated by system bits and check bits The concatenated vector. The dot product symbol represents the dot product of two row vectors.

[0030] Subsequently, according to the interleaving rules, the interleaving effect of the second RSC component encoder is written as a permutation matrix. The corresponding check relation is right-multiplied. ,get: .

[0031] Similarly, satisfying Based on the above component parity-check matrices, the overall parity-check matrix of the Turbo code (code rate 1 / 3, unchanged), i.e., the initial parity-check matrix, is as follows: .

[0032] The initial check matrix has a size of 2K×3K (K is the number of encoded information bits) and satisfies the check relationship.

[0033] Subsequently, this embodiment can create a corresponding initial probabilistic graphical model based on the initial parity check matrix, identify and eliminate short loop structures in the initial parity check matrix and the initial probabilistic graphical model, and obtain an extended parity check matrix and a probabilistic graphical model.

[0034] Optional. In this embodiment, after creating the initial parity-check matrix and the initial probabilistic graphical model, the approach of expanding the parity-check matrix is ​​used to systematically eliminate the 4-rings in the initial parity-check matrix and the initial probabilistic graphical model.

[0035] It should be noted that a 4-ring corresponds to a pattern in the check matrix: the elements at the four intersections of two rows (e.g., c_i and c_j) and two columns (e.g., v_p and v_q) are all 1. This indicates that two check equations simultaneously constrain the same pair of variable nodes. Therefore, these 4-rings are eliminated and replaced. First, all four 1s constituting the 4-ring are cleared to zero. Then, a new variable node v_pq is introduced into the initial probabilistic graphical model, and a new check equation (i.e., adding a row to the initial check matrix) is added to define it: v_pq ⊕ v_p ⊕ v_q = 0. The original check equations c_i and c_j are modified so that they are associated through the newly introduced v_pq node, instead of directly connecting v_p and v_q simultaneously. All 4-rings in the initial check matrix are traversed, and the above operation is repeated for all detected 4-rings. The initial check matrix and initial probabilistic graphical model after eliminating all 4-rings are determined as the extended check matrix and probabilistic graphical model, respectively.

[0036] It should be noted that this embodiment fundamentally eliminates the short-ring structure that is most detrimental to decoding performance by replacing each 4-ring in the initial parity-check matrix and the initial probabilistic graphical model with a larger 6-ring. Due to the structural characteristics of Turbo codes, the short rings in their initial parity-check matrix and initial probabilistic graphical model are mainly such 4-rings. Therefore, after this round of expansion optimization, no further processing is usually required. The final result is an expanded parity-check matrix without 4-rings, which is more suitable for high-performance iterative decoding.

[0037] Understandably, the number of variable nodes will increase in the extended parity-check matrix and probabilistic graphical model obtained after the extended optimization, compared to the initial parity-check matrix and probabilistic graphical model.

[0038] Specifically, if the encoding end encodes K codewords into N codewords... x Then, based on BPSK modulation, N symbols s are generated and transmitted. Due to noise interference during transmission, this embodiment receives N symbols. y Each y The original K codewords are restored, which are the original bit information. At this point, the Turbo code to be decoded received in this embodiment includes N codewords. .

[0039] In this embodiment, it is necessary to determine the initial probability of the state value of each variable node in the probabilistic graphical model. Specifically, the total number of variable nodes in the probabilistic graphical model will increase compared to the initial probabilistic graphical model. Each variable node in the probabilistic graphical model uniquely corresponds to an extended codeword. For the variable nodes in the probabilistic graphical model... j ( The initial probabilities of its state values ​​include the first and second initial probabilities, given that the original Turbo codewords corresponding to the variable nodes are 1 and 0 respectively. and Taking BPSK modulated signals as an example, the calculation formula is as follows: , This represents the noise variance.

[0040] For variable nodes ( ), J This represents the total number of variable nodes in the probabilistic graphical model, and the number of variable nodes at this point. j Since this was obtained by the decoder itself in this embodiment and does not contain prior channel information, it is considered that... .

[0041] S102. Take the initial probability of the state value of each variable node as the confidence level of the variable node to pass its own state value to each verification node connected by undirected edges.

[0042] Specifically, for any variable node, this embodiment can use the initial probability of the variable node's state value as the confidence level for the variable node to transmit its own state value to different verification nodes. It is understood that the variable node will only transmit messages to verification nodes with which it has a connection, and will not transmit messages to verification nodes with which it does not have a connection.

[0043] S103. For any verification node, construct the node state matrix corresponding to each target undirected edge based on each target undirected edge between the verification node and each target variable node connected to it, and based on the extended verification matrix.

[0044] Here, the target variable node is a variable node that is connected to a certain verification node through an undirected edge. The target undirected edge is the undirected edge connecting the verification node and the target variable node.

[0045] Specifically, in this embodiment, for any verification node in the probabilistic graphical model, each target variable node connected to the verification node through undirected edges can be determined, as well as the target undirected edges between the verification node and each target variable node can be determined. Based on each target undirected edge and the extended verification matrix, the node state matrix corresponding to each target undirected edge is constructed.

[0046] Specifically, the node state matrix is ​​a matrix used to configure the state of nodes in the in-memory computing unit.

[0047] It is understood that this embodiment can construct a node state matrix corresponding to each target undirected edge connected to a certain verification node. Therefore, this embodiment can construct a node state matrix corresponding to each undirected edge based on each undirected edge in the probabilistic graphical model. The total number of node state matrices corresponds to the total number of undirected edges.

[0048] S104. Based on the confidence level of each target undirected edge and each target variable node in passing its own state value to the verification node, construct the driving vector corresponding to each target undirected edge.

[0049] Specifically, in this embodiment, for any verification node in the probabilistic graphical model, the driving vector corresponding to each target undirected edge can be constructed based on each target undirected edge connected to the verification node and the confidence level of each target variable node in passing its own state value to the verification node.

[0050] It should be noted that the driving vector is used to input a driving physical quantity of the corresponding size into the in-memory computing unit, which drives the in-memory computing unit to store and compute based on its in-memory computing characteristics, thereby realizing Turbo decoding.

[0051] It is understood that this embodiment can construct a driving vector for each target undirected edge connected to a certain verification node. Therefore, this embodiment can construct a driving vector for each undirected edge based on each undirected edge in the probabilistic graphical model. The total number of driving vectors corresponds to the total number of undirected edges.

[0052] S105. Configure the in-memory compute unit based on the node state matrix corresponding to each undirected edge to obtain the in-memory compute unit subarray corresponding to each undirected edge.

[0053] Specifically, in this embodiment, for any node state matrix corresponding to an undirected edge, the state of each node in the initial state in-memory compute unit can be configured according to the node state matrix corresponding to the undirected edge to obtain the in-memory compute unit subarray corresponding to the undirected edge.

[0054] The initial state in-memory compute unit can be an in-memory compute unit whose node state has not been set.

[0055] It is understood that, in this embodiment, for any undirected edge in the probabilistic graphical model, a corresponding in-memory compute subarray can be configured.

[0056] S106. Based on the driving vector corresponding to each undirected edge, the in-memory compute subarray, and each of the above confidence levels, iteratively update the confidence level transmitted by each variable node to each verification node and the new probability of the state value of each variable node until the set iteration stopping condition is met, so as to decode the original bit information.

[0057] The iteration stopping condition can be set by technical personnel according to the actual situation, such as a specific number of iterations or a specific iteration duration.

[0058] Specifically, this embodiment can iteratively update the confidence level of each variable node to each verification node and the new probability of the state value of each variable node according to the driving vector and in-memory compute subarray corresponding to each undirected edge in the probabilistic graphical model, as well as the confidence level of each variable node to pass its own state value to each verification node connected through the undirected edge, until the iteration stopping condition is met, and determine the original bit information (such as the K codewords mentioned above) according to the final iteration result.

[0059] The Turbo code probabilistic domain decoding method based on in-memory computing proposed in this embodiment can construct an extended parity-check matrix and a probabilistic graphical model. Based on the extended parity-check matrix, the probabilistic graphical model, and the probabilistic domain operation method, it configures the in-memory computing subarray and voltage vector corresponding to each undirected edge. Based on the in-memory computing subarray, driving vector, and the confidence level of each variable node in transmitting its own state value to each parity-check node connected by the undirected edge, it iteratively updates the confidence level transmitted by each variable node to each parity-check node and the new probability of each variable node's state value. This allows for the decoding of the Turbo code to obtain the original bit information. This invention can store some static variables involved in Turbo decoding in the in-memory computing unit and transfer some digital operations to the in-memory computing unit, utilizing its storage and computing performance to overcome power consumption bottlenecks. While retaining the excellent error correction capability of Turbo codes, it significantly reduces hardware resource consumption and power consumption.

[0060] based on Figure 1 This embodiment proposes a second Turbo code probabilistic domain decoding method based on in-memory computing. In this method, when the in-memory computing device is a memristor, the node state matrix is ​​a node resistance state matrix. In this case, the above-mentioned construction of the node state matrix corresponding to each target undirected edge based on each target undirected edge between the verification node and each connected target variable node, and based on the extended parity-check matrix, includes: Obtain the number t of the target undirected edges, and determine the internal order of each target undirected edge among all target undirected edges; Construct multiple candidate vectors obtained by arranging and combining t target binary characters. For any candidate vector, if the element order of the target binary characters in the candidate vector is equal to the internal order of the target undirected edge, then establish an association between the target binary characters in the candidate vector and the target variable nodes connected by the target undirected edge. Iterate through each target undirected edge in turn; For the a-th target undirected edge encountered during traversal, the multiple candidate vectors are divided into multiple first candidate vectors and multiple second candidate vectors to be processed. Based on each first candidate vector, second candidate vector, association relationship and extended verification matrix, the node resistance state matrix corresponding to the target undirected edge is constructed; where the a-th element in the first candidate vector is 1 and the a-th element in the second candidate vector is 0.

[0061] Optionally, based on each first candidate vector, second candidate vector, association relationship, and extended verification matrix, the node resistance matrix corresponding to the target undirected edge is constructed, including: For any candidate vector to be processed, construct a zero vector with the total number of elements equal to the total number of variable nodes. Determine the node order of the target variable nodes associated with each target binary character in the candidate vector to be processed as the unique order to be arranged for each target binary character. Replace each zero element in the zero vector whose position order is equal to the order to be arranged with the target binary character that uniquely corresponds to the order to be arranged to obtain the processed candidate vector. Wherein, the candidate vector to be processed is either the first candidate vector or the second candidate vector. When the candidate vector to be processed is the first candidate vector, the processed candidate vector is the first processed candidate vector; when the candidate vector to be processed is the second candidate vector, the processed candidate vector is the second processed candidate vector. In the extended check matrix, determine the unique target row vector corresponding to the check node; For any first-processed candidate vector, perform a modulo operation between the target row vector and the first-processed candidate vector to obtain the corresponding first value, invert the first value to obtain the first inverted value; arrange each first inverted value to obtain the first node resistive state column vector. For any second-processed candidate vector, perform a modulo operation between the target row vector and the second-processed candidate vector to obtain the corresponding second value. Invert the second value to obtain the second inverted value. Arrange each second inverted value to obtain the second node resistive column vector. By horizontally concatenating the first node resistance column vector and the second node resistance column vector, we obtain the node resistance matrix corresponding to the target undirected edge.

[0062] To better illustrate the above execution process, this embodiment continues to combine Example 1 and... Figure 2 Let me introduce it.

[0063] Example 1: In this embodiment, for any verification node... i The verification node can be determined in the probabilistic graphical model. i Connecting the target variable nodes and the target undirected edges. For example... Figure 2 As shown, when iWhen the value is 3, the target variable nodes connected to the 3rd verification node are the 2nd, 3rd, and 4th variable nodes, respectively. At this time, the number of target undirected edges t is equal to 3, and each target undirected edge is an undirected edge connecting the 3rd verification node to the 2nd, 3rd, and 4th variable nodes, respectively. The internal order of each target undirected edge among all target undirected edges is 1, 2, and 3, respectively.

[0064] The target binary characters include 0 and 1. At this point, t equals 3. Multiple candidate vectors are constructed by permuting and combining the three target binary characters. The number of candidate vectors is 2^3, or 8 candidate vectors: (0,0,0), (0,0,1), (0,1,0), (0,1,1), (1,0,0), (1,0,1), (1,1,0), and (1,1,1). It can be understood that the number of elements in the candidate vectors is the same as the number of target undirected edges. The first, second, and third target binary characters in the candidate vectors are associated with the target variable nodes connected by the target undirected edges of order 1, 2, and 3, respectively. In other words, the first, second, and third target binary characters in the candidate vectors are associated with the second, third, and fourth variable nodes, respectively.

[0065] 'a' represents the internal order of the target undirected edges. The first, second, and third target undirected edges are traversed sequentially. Upon reaching each target undirected edge, the eight candidate vectors are divided into first and second candidate vectors. For example, when traversing the third target undirected edge, 'a' equals 3. If the third element of a candidate vector is 1, it is determined as the first candidate vector; if the third element is 0, it is determined as the second candidate vector. The first candidate vectors at this point include (0,0,1), (0,1,1), (1,0,1), and (1,1,1), while the second candidate vectors include (0,0,0), (0,1,0), (1,0,0), and (1,1,0).

[0066] Each of the first and second candidate vectors mentioned above is taken as a candidate vector to be processed. For example, when the first candidate vector (0, 1, 1) is taken as a candidate vector to be processed, a zero vector (0, 0, 0, 0, 0, 0) with a total number of elements equal to the total number of variable nodes (6) is first constructed. The first, second, and third target binary characters in the first candidate vector are associated with the second, third, and fourth variable nodes, respectively. Therefore, in this embodiment, the second, third, and fourth zero elements in the zero vector can be replaced with the first, second, and third target binary characters in the first candidate vector, respectively, to obtain the corresponding first processed candidate vector (0, 0, 1, 1, 0, 0).

[0067] At this point, when this embodiment traverses to the third target undirected edge, it can obtain four first-processed candidate vectors and four second-processed candidate vectors based on this target undirected edge. Then, this embodiment can determine the unique target row vector corresponding to the third verification node in the extended verification matrix, i.e., the third row vector in the extended verification matrix. For any first-processed candidate vector, the target row vector and the first-processed candidate vector are moduloed to obtain the corresponding first value. This first value is then inverted to obtain the first inverted value. At this point, four corresponding first inverted values ​​are obtained. These four first inverted values ​​are arranged vertically to obtain the first node's resistive column vector. For any second-processed candidate vector, the target row vector and the second-processed candidate vector are moduloed to obtain the corresponding second value. This second value is then inverted to obtain the second inverted value. At this point, four corresponding second inverted values ​​are obtained. These four second inverted values ​​are arranged vertically to obtain the second node's resistive column vector. By horizontally concatenating the first node resistance column vector and the second node resistance column vector, we obtain the node resistance matrix corresponding to the third target undirected edge.

[0068] Optionally, when the in-memory processor is a memristor, the driving vector is a voltage vector. In this case, step S104 includes: When traversing to the a-th undirected edge of the target, delete the a-th element in each candidate vector to obtain multiple first vectors. Remove duplicates from the multiple first vectors to obtain multiple second vectors. For any second vector, determine the target confidence corresponding to each target binary character in the second vector, and multiply the target confidence corresponding to each target binary character in the second vector to obtain the product corresponding to the second vector. Arrange the products corresponding to each second vector to obtain the voltage vector corresponding to the target undirected edge. The target confidence corresponding to the target binary character in the second vector is: the confidence of the target variable node associated with the target binary character that passes its own state value equal to the target binary character to the verification node.

[0069] To better illustrate the above execution process, this embodiment continues to combine Example 1 and... Figure 2 Let me introduce it.

[0070] Example 1: Let 'a' be the internal order of the undirected edges connecting each target to the third verification node. When 'a' is 3, the eight candidate vectors created in this embodiment are (0, 0, 0), (0, 0, 1), (0, 1, 0), (0, 1, 1), (1, 0, 0), (1, 0, 1), (1, 1, 0), and (1, 1, 1). In this case, the third element of each candidate vector can be deleted to obtain eight first vectors (0, 0), (0, 0), (0, 1), (0, 1), (1, 0), (1, 0), (1, 1), and (1, 1). After deduplication, the remaining four second vectors (0, 0), (0, 1), (1, 0), and (1, 1) are obtained. For any of the second vectors, such as the second vector (0, 1), this embodiment can determine the target confidence level corresponding to each target binary character in the second vector. The confidence level corresponding to the first target binary character in the second vector is: the confidence level of the target variable node (i.e., the second variable node) associated with the target binary character transmitting the message with its own state value equal to 0 to the third verification node. The confidence level corresponding to the second target binary character in the second vector is: the confidence level of the target variable node (i.e., the third variable node) associated with the target binary character transmitting the message with its own state value equal to 1 to the third verification node. Multiplying the two determined confidence levels yields one product corresponding to the second vector. Four products are calculated for the four second vectors. Arranging these four products vertically yields the voltage vector corresponding to the third target undirected edge.

[0071] The voltage vector corresponding to the target undirected edge constructed in this embodiment can be represented as: .

[0072] by Let's take an example to explain the meaning of each character. Among them, Indicates the first i The verification node and the first j An undirected edge between variable nodes, where the subscript 2 of x represents the second element in the voltage vector. Indicates the first i The verification node and the first j The second element in the voltage vector corresponding to the undirected edge of each variable node.

[0073] Optionally, when the in-memory compute unit is a memristor, the in-memory compute unit subarray is a memristor subarray. In this case, step S105 includes: For any undirected edge, the corresponding node resistance state matrix is ​​obtained based on the number of rows and columns of the elements in the node resistance state matrix. The number of rows and columns of the nodes in the initial memristor subarray corresponds to the number of rows and columns of the elements. For any target element in the node resistance matrix, the target node corresponding to the position is determined in the initial memristor subarray according to the position of the target element in the node resistance matrix. If the target element is 1, the resistance state of the target node is set to low resistance state; if the target element is 0, the resistance state of the target node is set to high resistance state. The initial state memristor subarray that completes the node resistance state configuration based on each target element in the node resistance state matrix is ​​determined as the memristor subarray corresponding to the undirected edge.

[0074] To better illustrate the above execution process, this embodiment continues to combine Example 1 and... Figure 2 Let me introduce it.

[0075] Example 1: In this embodiment, when introducing the construction of the above-mentioned node resistance matrix, the first node resistance column vector and the second node resistance column vector are horizontally concatenated to obtain the node resistance matrix corresponding to the third target undirected edge. Specifically, in Figure 2 In the memristor subarray corresponding to the third target undirected edge, the resistance state of each node in the first node column is configured according to each element in the first node resistance state column vector, and the resistance state of each node in the second node column is configured according to each element in the second node resistance state column vector.

[0076] The memristor subarray corresponding to the target undirected edge constructed in this embodiment can be represented as a matrix: .

[0077] Among them, with Let's take an example to explain the meaning of each character. Indicates the first i The verification node and the first j Undirected edges between nodes, where 1 and 2 in the x index represent... It is the second element in the first row of the memristor subarray. Indicates the first i The verification node and the first j The undirected edge between the variable nodes corresponds to the second element in the first row of the memristor subarray. Specifically, and Each represents a candidate vector after the first processing described above. and Each of these represents a candidate vector after the second processing described above. The first column on the left of this matrix is ​​configured based on the first node's resistance state column vector, and the second column on the right of this matrix is ​​configured based on the second node's resistance state column vector.

[0078] Among them, the memristor subarray This is obtained by configuring the resistance states based on the elements in the node resistance state matrix, and the elements of the node resistance state matrix can be configured as follows: , The negation operator is 'NOT', and mod is the modulo operator. For the extended parity check matrix, the first i row vectors. Indicates according to the first i The verification node and the first j The above-mentioned processed candidate vector is constructed from the undirected edges between the variable nodes.

[0079] Optionally, the memristor subarray corresponding to the undirected edge includes a first node column and a second node column. The first node column corresponds to the case where the variable node connected to the undirected edge has a state value of 1, and the second node column corresponds to the case where the variable node connected to the undirected edge has a state value of 0.

[0080] At this point, step S106 above includes: For any undirected edge, according to each voltage element in the voltage vector corresponding to the undirected edge, input a voltage equal to the magnitude of the voltage element to each row node in the memristor subarray corresponding to the undirected edge, and read the first current value of the first node column and the second current value of the second node column in the memristor subarray respectively. Based on the first and second current values ​​in each memristor subarray, update the new confidence level of each variable node in passing its own state value to each check node, and update the new probability of the state value of each variable node. Determine whether the new probability of the state value of each variable node satisfies the iteration stopping condition; If the new probability of the state value of each variable node does not meet the iteration stopping condition, then the new confidence of each variable node passing its own state value to each verification node is taken as the current confidence, and the process returns to step S104 until the iteration stopping condition is met. If the iteration stopping condition is met, the original bit information is determined based on the new probability of the state value of each variable node.

[0081] Optionally, the initial probability of the state value of each variable node includes the first initial probability and the second initial probability, given that the original Turbo codewords corresponding to the variable node are 1 and 0 respectively, under the condition that the extended codewords corresponding to the variable node are known.

[0082] The above update, based on the first and second current values ​​in each memristor subarray, yields a new confidence level for each variable node to pass its own state value to each verification node, including: For the first one with a connection relationship i The verification node and the first jBased on the node order of the check node and the variable node, determine the group of undirected edges connected to the variable node, and determine the first undirected edge between the check node and the variable node. Then, determine any undirected edge in the undirected edge group other than the first undirected edge as the second undirected edge. Multiply the first current value in the memristor subarray corresponding to each second undirected edge with the first initial probability in the initial probability of the state value of the variable node to obtain the new confidence that the variable node will pass its own state value of 1 to the verification node. Multiply the second current value in the memristor subarray corresponding to each second undirected edge by the second initial probability in the initial probability of the variable node's state value to obtain the new confidence that the variable node will pass its own state value, which is equal to 0, to the check node.

[0083] Optionally, update the new probability of the state value of each variable node, including: For any variable node, determine each undirected edge connected to the variable node, multiply the first current value in the memristor subarray corresponding to each undirected edge connected to the variable node by the square of the first initial probability in the initial probability of the variable node's state value to obtain a new probability that the variable node's own state value is equal to 1, and multiply the second current value in the memristor subarray corresponding to each undirected edge connected to the variable node by the square of the second initial probability in the initial probability of the variable node's state value to obtain a new probability that the variable node's own state value is equal to 0. Determine whether the new probability of the state value of each variable node satisfies the iteration stopping condition, including: Hard-determine the new probability of the state value of each variable node to obtain the codeword vector; Perform a modulo operation on the extended parity-check matrix and the codeword vector to obtain the result; If the result of the operation is equal to 0, then the iteration stopping condition is satisfied. If the result of the operation is not equal to 0, then the iteration stopping condition is not met. The original bit information is determined based on the new probability of the state value of each variable node, including: Determine the total number of characters K in the original bit information, select the first K elements from the latest codeword vector, and use them as the whole to determine the original bit information.

[0084] To better illustrate the above execution process, this embodiment continues to combine it with Example 1 above. Figure 2 and Figure 3 Let me introduce it.

[0085] Example 1, such as Figure 3 As shown, the node resistance matrix constructed in this embodiment has The voltage vector has The current read is . Figure 3 The DAC is an exponential-to-analog converter, and the ADC is an exponential-to-digital converter.

[0086] in, This represents the memristor subarray corresponding to the undirected edge between the first verification node and the first target variable node with a connection relationship. Indicates the first I The verifiable node and the first node with a connection relationship The undirected edges between the target variable nodes correspond to the memristor subarrays. It should be noted that... and It does not refer to the second node order of the variable node, but rather to the order of the target variable node connected to the verification node among all target variable nodes connected to that verification node.

[0087] This represents the voltage vector corresponding to the undirected edge between the first verification node and the first target variable node with a connection relationship. Indicates the first I The verifiable node and the first node with a connection relationship The voltage vector corresponding to the undirected edge between the target variable nodes. This includes the first and second current values ​​in the memristor subarray corresponding to the undirected edge between the first verification node and the first target variable node with which it is connected. Including the first I The verifiable node and the first node with a connection relationship The first and second current values ​​in the memristor subarray corresponding to the undirected edges between the target variable nodes.

[0088] Corresponding to the same undirected edge and For example, in this embodiment, the undirected edge can be used as a reference. Each voltage element in the array is transmitted via a digital-to-analog converter (DAC) to the memristor subarray corresponding to the undirected edge. Each row of nodes in the array receives a voltage equal to the size of the voltage element; for example, this voltage is input to the memristor subarray. The first row of nodes in the input and... A voltage equal to the magnitude of the first voltage element is applied to the memristor subarray. The second row of nodes in the input is the same as the input. A voltage equal to the second voltage element is applied until the last row of nodes in the memristor subarray is input. The voltage is equal in magnitude to the last voltage element. Then, in this embodiment, the first and second current values ​​in the memristor subarray can be read via an analog-to-digital converter (ADC). For the node resistance matrix, voltage vector, and current vector corresponding to other undirected edges, this embodiment can refer to the above process for parallel processing, and will not be repeated here.

[0089] The operation process performed in the memristor subarray is represented in matrix multiplication form as follows: .

[0090] in, T This is the matrix transpose symbol. and middle, ij Indicates the first i The verification node and the first j Undirected edges between nodes of variable type. (The text in parentheses is incomplete and likely refers to a separate topic.) , indicating the first column. (The text in parentheses is incomplete and cannot be translated.) , indicating the second column. Indicates the first i The verification node and the first j The first current value in the memristor subarray corresponding to the undirected edge between each variable node. Indicates the first i The verification node and the first j The second current value in the memristor subarray corresponding to the undirected edge between each variable node.

[0091] Continuing with Example 1 above and Figure 2 This section describes the process of updating the confidence level of a variable node as it passes its own state value to the verification node.

[0092] For example, in this embodiment, during the process of updating the new confidence level obtained by the second variable node transmitting its own state value to the third verification node, all undirected edges connected to the second variable node, i.e., the undirected edge group (this undirected edge group includes the undirected edges between the second variable node and each verification node with a connection relationship), can be determined first, and the second variable node can be determined first. j The undirected edge between the first variable node and the third check node is called the first undirected edge. The undirected edges in this group, excluding the first undirected edge, are called the second undirected edges. In this embodiment, the first current value in the memristor subarray corresponding to each second undirected edge is multiplied by the first initial probability in the initial probability of the state value of the second variable node to obtain the corresponding product. That is, the second variable node transmits its own state value of 1 to the third check node with a new confidence level. Similarly, the second current value in the memristor subarray corresponding to each second undirected edge is multiplied by the second initial probability in the initial probability of the state value of the second variable node to obtain the corresponding product. That is, the second variable node transmits its own state value of 0 to the third check node with a new confidence level.

[0093] The confidence update formula can be: .

[0094] in, For the first j The first variable node passes its own state value to the first variable node. i The new confidence level of each verification node For the first j The first or second initial probability in the initial probability of the state value of the variable node, when When it is 1, Let the first initial probability be, when When it is 0, This is the second initial probability. N ( j ) indicates the relationship with the first j A set of check nodes connected to each variable node. This indicates that, except for the first node in the set of verification nodes... i Other verification nodes besides the one verification node.

[0095] The confidence update formula can be implemented by cascading multipliers.

[0096] Then, this embodiment can update the new probability of the state value of each variable node. Continuing with Example 1 above and... Figure 2 This section describes the process of updating the confidence level of a variable node as it passes its own state value to the verification node.

[0097] For example, in this embodiment, for the second variable node, all undirected edges connected to the second variable node are determined. The squares of the first current values ​​in the memristor subarray corresponding to each undirected edge connected to the second variable node are multiplied together to obtain the corresponding product, which is the new probability that the state value of the second variable node is equal to 1. The squares of the second current values ​​in the memristor subarray corresponding to each undirected edge connected to the second variable node are multiplied together to obtain the corresponding product, which is the new probability that the state value of the second variable node is equal to 0.

[0098] The formula for calculating the new probability of the variable node's own state value can be expressed as: ; .

[0099] in, Indicates the first j The new probability of a variable node having a state value of 1. This represents the first initial probability in the initial probability of the state value of the variable node. Indicates the first j The new probability of a variable node having a state value of 0. This represents the second initial probability in the initial probability of the state value of the variable node.

[0100] The iteration stopping condition is a set condition used to determine whether to stop iterating or continue iterating.

[0101] Subsequently, this embodiment can determine whether decoding is successful by judging the iteration stopping condition based on the new probability of the state value of each variable node.

[0102] Specifically, in this embodiment, a hard decision can be made on the new probability of the state value of each variable node. If the new probability of a variable node's own state value being equal to 1 is greater than the new probability of its own state value being equal to 0, then the codeword corresponding to that variable node is determined to be 1. If the new probability of a variable node's own state value being equal to 1 is not greater than the new probability of its own state value being equal to 0, then the codeword corresponding to that variable node is determined to be 0.

[0103] The formula for a hard decision can be expressed as: .

[0104] in, The first one obtained by decoding j The codewords corresponding to each variable node.

[0105] At this point, after hard-determining the new probabilities of the state values ​​of each variable node in this embodiment, a codeword vector consisting of J codewords can be generated. The coefficient parity check matrix and the codeword vector are then compared. Perform the modulo operation , H To expand the parity check matrix and obtain The calculation result is used to determine the decoding success of a variable node. If the result is 0, the iteration stopping condition is met, the decoding is successful, and the first K codewords in the codeword vector are selected as the decoding result, i.e., the original bit information. If the result is not 0, the iteration stopping condition is not met, the decoding is unsuccessful. In this case, each variable node can pass its own state value to each check node with a new confidence level as the current confidence level, and the process returns to step S104 until the iteration stopping condition is met, and the first K codewords in the latest codeword vector are selected as the decoding result, i.e., the original bit information.

[0106] It should be noted that, in this embodiment, when obtaining the initial probabilities of the state values ​​of each variable node, a hard decision can be made on the initial probabilities of the state values ​​of each variable node to determine whether the iteration stopping condition is met. Based on the decision result, it is determined whether to proceed with iteration or directly obtain a successful decoding result. In this embodiment, the process of making a hard decision on the new probabilities of the state values ​​of each variable node and determining whether the iteration stopping condition is met based on the generated codeword vector can be used to determine whether the initial probabilities of the state values ​​of each variable node meet the iteration stopping condition in step S102. The specific process will not be elaborated further.

[0107] It should be noted that the Turbo decoding method used in related technologies involves a large number of discrete fixed-point number operations. The energy efficiency of communication baseband based on traditional digital circuits is severely limited by the power consumption and cost of random access memory, as well as the energy overhead brought by discrete fixed-point number operations in the digital domain. The digital circuit processing paradigm in related technologies cannot fundamentally achieve a breakthrough in energy efficiency. In particular, a standard Turbo decoder requires a large number of on-chip memory units to cache intermediate operation data and powerful processing units to perform multiple iterative operations, which directly leads to a large chip area and significant power consumption.

[0108] The Turbo code probabilistic domain decoding method based on in-memory computing proposed in this embodiment can store some static variables in devices with in-memory computing characteristics such as memristors, thereby transferring some digital operations to the analog domain and using Kirchhoff's circuit laws for computation. This breaks through the power consumption bottleneck of digital circuits, realizes the innovation of decoding mode and the efficient reuse of computing resources, and provides a high-efficiency decoding solution with significantly reduced hardware overhead for low-power edge devices.

[0109] It should be noted that, Figure 3 The architecture shown directly utilizes each memristor subarray for decoding, which is a time-parallel processing architecture. In this parallel processing architecture, each subarray is independently disconnected.

[0110] The Turbo code probability domain decoding method based on in-memory computing proposed in this embodiment can use memristor arrays with parallel or serial processing architectures for Turbo decoding, thereby achieving diversification of Turbo decoding architectures.

[0111] like Figure 4 As shown, this embodiment proposes a Turbo code probabilistic domain decoding device based on a memory computing unit, applied at the decoding end. The device includes: The acquisition unit 401 is used to acquire the extended parity-check matrix and probabilistic graphical model corresponding to the Turbo code to be decoded, as well as the initial probability of the state value of each variable node in the probabilistic graphical model; wherein, the Turbo code to be decoded is obtained by the encoder performing digital modulation on the original Turbo code and sending it to the decoder, the original Turbo code is obtained by the encoder performing Turbo encoding on the original bit information, and the initial probability of the state value of the variable node is determined based on the probability domain operation method; As unit 402, it is used to set the initial probability of the state value of each variable node as the confidence of the variable node to pass its own state value to each verification node connected by undirected edges. The first construction unit 403 is used to construct, for any verification node, a node state matrix corresponding to each target undirected edge based on each target undirected edge between the verification node and each target variable node connected to it, and based on the extended verification matrix. The second construction unit 404 is used to construct the driving vector corresponding to each target undirected edge based on the confidence of each target undirected edge and each target variable node in passing its own state value to the verification node. Configuration unit 405 is used to configure the in-memory compute unit based on the node state matrix corresponding to each undirected edge, so as to obtain the in-memory compute unit subarray corresponding to each undirected edge. The decoding unit 406 is used to iteratively update the confidence level transmitted by each variable node to each verification node and the new probability of the state value of each variable node according to the driving vector corresponding to each undirected edge, the in-memory compute subarray and each confidence level, until the set iteration stopping condition is met, so as to decode the original bit information.

[0112] It should be noted that the processing procedures and beneficial effects of the acquisition unit 401, the processing unit 402, the first construction unit 403, the second construction unit 404, the configuration unit 405, and the interpretation unit 406 can be referred to respectively. Figure 1 Steps S101 to S106 are not described in detail here.

[0113] Optionally, the acquisition unit 401 is also used for: Receive the Turbo code to be decoded sent by the encoder and determine the noise variance corresponding to the Turbo code to be decoded; Based on the Turbo code to be decoded, create an initial parity-check matrix and a corresponding initial probabilistic graphical model; Eliminate short loop structures in the initial parity check matrix and the initial probabilistic graphical model to obtain the extended parity check matrix and the probabilistic graphical model; The initial probability of the state value of each variable node is determined based on the noise variance and the probability domain operation method.

[0114] Optionally, when the in-memory computing unit is a memristor, the node state matrix is ​​the node resistance state matrix; The first building unit 403 is also used for: Obtain the number t of the target undirected edges, and determine the internal order of each target undirected edge among all target undirected edges; Construct multiple candidate vectors obtained by arranging and combining t target binary characters. For any candidate vector, if the element order of the target binary characters in the candidate vector is equal to the internal order of the target undirected edge, then establish an association between the target binary characters in the candidate vector and the target variable nodes connected by the target undirected edge. Iterate through each target undirected edge in turn; For the a-th target undirected edge encountered during traversal, the multiple candidate vectors are divided into multiple first candidate vectors and multiple second candidate vectors to be processed. Based on each first candidate vector, second candidate vector, association relationship and extended verification matrix, the node resistance state matrix corresponding to the target undirected edge is constructed; where the a-th element in the first candidate vector is 1 and the a-th element in the second candidate vector is 0.

[0115] Optionally, the first building unit 403 is also used for: For any candidate vector to be processed, construct a zero vector with the total number of elements equal to the total number of variable nodes. Determine the node order of the target variable nodes associated with each target binary character in the candidate vector to be processed as the unique order to be arranged for each target binary character. Replace each zero element in the zero vector whose position order is equal to the order to be arranged with the target binary character that uniquely corresponds to the order to be arranged to obtain the processed candidate vector. Wherein, the candidate vector to be processed is either the first candidate vector or the second candidate vector. When the candidate vector to be processed is the first candidate vector, the processed candidate vector is the first processed candidate vector; when the candidate vector to be processed is the second candidate vector, the processed candidate vector is the second processed candidate vector. In the extended check matrix, determine the unique target row vector corresponding to the check node; For any first-processed candidate vector, perform a modulo operation between the target row vector and the first-processed candidate vector to obtain the corresponding first value, invert the first value to obtain the first inverted value; arrange each first inverted value to obtain the first node resistive state column vector. For any second-processed candidate vector, perform a modulo operation between the target row vector and the second-processed candidate vector to obtain the corresponding second value. Invert the second value to obtain the second inverted value. Arrange each second inverted value to obtain the second node resistive column vector. By horizontally concatenating the first node resistance column vector and the second node resistance column vector, we obtain the node resistance matrix corresponding to the target undirected edge.

[0116] Optionally, when the in-memory processor is a memristor, the driving vector is a voltage vector; The second building unit 404 is also used for: When traversing to the a-th undirected edge of the target, delete the a-th element in each candidate vector to obtain multiple first vectors. Remove duplicates from the multiple first vectors to obtain multiple second vectors. For any second vector, determine the target confidence corresponding to each target binary character in the second vector, and multiply the target confidence corresponding to each target binary character in the second vector to obtain the product corresponding to the second vector. Arrange the products corresponding to each second vector to obtain the voltage vector corresponding to the target undirected edge. The target confidence corresponding to the target binary character in the second vector is: the confidence of the target variable node associated with the target binary character that passes its own state value equal to the target binary character to the verification node.

[0117] Optionally, when the in-memory compute unit is a memristor, the in-memory compute unit subarray is a memristor subarray; Configuration unit 405 is also used for: For any undirected edge, the corresponding node resistance state matrix is ​​obtained based on the number of rows and columns of the elements in the node resistance state matrix. The number of rows and columns of the nodes in the initial memristor subarray corresponds to the number of rows and columns of the elements. For any target element in the node resistance matrix, the target node corresponding to the position is determined in the initial memristor subarray according to the position of the target element in the node resistance matrix. If the target element is 1, the resistance state of the target node is set to low resistance state; if the target element is 0, the resistance state of the target node is set to high resistance state. The initial state memristor subarray that completes the node resistance state configuration based on each target element in the node resistance state matrix is ​​determined as the memristor subarray corresponding to the undirected edge.

[0118] Optionally, the memristor subarray corresponding to the undirected edge includes a first node column and a second node column. The first node column corresponds to the case where the variable node connected by the undirected edge has a state value of 1, and the second node column corresponds to the case where the variable node connected by the undirected edge has a state value of 0. Decoding unit 406 is also used for: For any undirected edge, according to each voltage element in the voltage vector corresponding to the undirected edge, input a voltage equal to the magnitude of the voltage element to each row node in the memristor subarray corresponding to the undirected edge, and read the first current value of the first node column and the second current value of the second node column in the memristor subarray respectively. Based on the first and second current values ​​in each memristor subarray, update the new confidence level of each variable node in passing its own state value to each check node, and update the new probability of the state value of each variable node. Determine whether the new probability of the state value of each variable node satisfies the iteration stopping condition; If the new probability of the state value of each variable node does not meet the iteration stopping condition, then the new confidence of each variable node passing its own state value to each verification node is taken as the current confidence. Then, the process of constructing the driving vector corresponding to each target undirected edge based on each target undirected edge and the confidence of each target variable node passing its own state value to the verification node is returned until the iteration stopping condition is met. If the iteration stopping condition is met, the original bit information is determined based on the new probability of the state value of each variable node.

[0119] Optionally, the initial probability of the state value of each variable node includes the first initial probability and the second initial probability, given that the original Turbo codewords corresponding to the variable node are 1 and 0 respectively, under the condition that the extended codewords corresponding to the variable node are known. Decoding unit 406 is also used for: For the first one with a connection relationship i The verification node and the first j Based on the node order of the check node and the variable node, determine the group of undirected edges connected to the variable node, and determine the first undirected edge between the check node and the variable node. Then, determine any undirected edge in the undirected edge group other than the first undirected edge as the second undirected edge. Multiply the first current value in the memristor subarray corresponding to each second undirected edge with the first initial probability in the initial probability of the state value of the variable node to obtain the new confidence that the variable node will pass its own state value of 1 to the verification node. Multiply the second current value in the memristor subarray corresponding to each second undirected edge by the second initial probability in the initial probability of the variable node's state value to obtain the new confidence that the variable node will pass its own state value, which is equal to 0, to the check node.

[0120] Optionally, the interpreter unit 406 is also used for: For any variable node, determine each undirected edge connected to the variable node, multiply the first current value in the memristor subarray corresponding to each undirected edge connected to the variable node by the square of the first initial probability in the initial probability of the variable node's state value to obtain a new probability that the variable node's own state value is equal to 1, and multiply the second current value in the memristor subarray corresponding to each undirected edge connected to the variable node by the square of the second initial probability in the initial probability of the variable node's state value to obtain a new probability that the variable node's own state value is equal to 0. Optionally, the interpreter unit 406 is also used for: Hard-determine the new probability of the state value of each variable node to obtain the codeword vector; Perform a modulo operation on the extended parity-check matrix and the codeword vector to obtain the result; If the result of the operation is equal to 0, then the iteration stopping condition is satisfied. If the result of the operation is not equal to 0, then the iteration stopping condition is not met. Optionally, the interpreter unit 406 is also used for: Determine the total number of characters K in the original bit information, select the first K elements from the latest codeword vector, and use them as the whole to determine the original bit information.

[0121] The Turbo code probabilistic domain decoding device based on an in-memory computing unit proposed in this embodiment can decode the Turbo code by constructing an extended parity-check matrix and a probabilistic graphical model, configuring an in-memory computing unit subarray and voltage vector corresponding to each undirected edge according to the extended parity-check matrix and the probabilistic graphical model, and transmitting the state value of each variable node to each parity-check node connected by the undirected edge based on the in-memory computing unit subarray, driving vector, and confidence level of each variable node. The confidence level transmitted by each variable node to each parity-check node and the new probability of the state value of each variable node are iteratively updated until a set iteration stopping condition is met, thus obtaining the original bit information. This invention can store some static variables involved in Turbo decoding in the in-memory computing unit and transfer some digital operations to the in-memory computing unit, utilizing the storage and computing performance of the in-memory computing unit for computation, overcoming the power consumption bottleneck, and significantly reducing its hardware resource consumption and power consumption while retaining the excellent error correction capability of Turbo codes.

[0122] In this embodiment, the Turbo code probability domain decoding device based on in-memory computing is presented in the form of a functional unit. Here, a unit refers to an ASIC (Application Specific Integrated Circuit) circuit, a processor and memory that execute one or more software or fixed programs, and / or other devices that can provide the above functions.

[0123] This invention also provides a computer device having the above-described features. Figure 4 The Turbo code probability domain decoding device based on a memory-in-memory processor is shown.

[0124] Please see Figure 5 The present invention provides a schematic diagram of the structure of a computer device according to an optional embodiment. The computer device includes one or more processors 10, a memory 20, and interfaces for connecting the various components, including high-speed interfaces and low-speed interfaces. The various components are interconnected via different buses and can be mounted on a common motherboard or otherwise installed as needed. The processors can process instructions executed within the computer device, including instructions stored in or on memory to display graphical information of a GUI on an external input / output device (such as a display device coupled to the interface). In some optional embodiments, multiple processors and / or multiple buses can be used with multiple memories, if desired. Similarly, multiple computer devices can be connected, each providing some of the necessary operations (e.g., as a server array, a group of blade servers, or a multiprocessor system). Figure 5 Take a processor 10 as an example.

[0125] Processor 10 may be a central processing unit, a network processor, or a combination thereof. Processor 10 may further include a hardware chip. The hardware chip may be an application-specific integrated circuit (ASIC), a programmable logic device (PLD), or a combination thereof. The programmable logic device may be a complex programmable logic device (CAMP), a field-programmable gate array (FPGA), a general-purpose array logic (GDA), or any combination thereof.

[0126] The memory 20 stores instructions executable by at least one processor 10 to cause at least one processor 10 to perform the method shown in the above embodiments.

[0127] The memory 20 may include a program storage area and a data storage area. The program storage area may store the operating system and applications required for at least one function. The data storage area may store data created based on the use of the computer device. Furthermore, the memory 20 may include high-speed random access memory and may also include non-transitory memory, such as at least one disk storage device, flash memory device, or other non-transitory solid-state storage device. In some alternative embodiments, the memory 20 may optionally include memory remotely located relative to the processor 10, which can be connected to the computer device via a network. Examples of such networks include, but are not limited to, the Internet, intranets, local area networks, mobile communication networks, and combinations thereof.

[0128] Memory 20 may include volatile memory, such as random access memory. Memory may also include non-volatile memory, such as flash memory, hard disk, or solid-state drive. Memory 20 may also include combinations of the above types of memory.

[0129] The computer device also includes a communication interface 30 for communicating with other devices or communication networks.

[0130] This invention also provides a computer-readable storage medium. The methods described above according to embodiments of the invention can be implemented in hardware or firmware, or implemented as computer code that can be recorded on a storage medium, or implemented as computer code downloaded via a network and originally stored on a remote storage medium or a non-transitory machine-readable storage medium and then stored on a local storage medium. Thus, the methods described herein can be processed by software stored on a storage medium using a general-purpose computer, a dedicated processor, or programmable or dedicated hardware. The storage medium can be a magnetic disk, optical disk, read-only memory, random access memory, flash memory, hard disk, or solid-state drive, etc.; further, the storage medium can also include combinations of the above types of memory. It is understood that computers, processors, microprocessor controllers, or programmable hardware include storage components capable of storing or receiving software or computer code, which, when accessed and executed by the computer, processor, or hardware, implements the methods shown in the above embodiments.

[0131] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, and not to limit them; although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features; and these modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of the present invention.

Claims

1. A Turbo code probabilistic domain decoding method based on a memory computing device, characterized in that, Applied to the decoding end, the method includes: Obtain the extended parity-check matrix and probabilistic graphical model corresponding to the Turbo code to be decoded, as well as the initial probability of the state value of each variable node in the probabilistic graphical model; wherein, the initial probability of the state value of the variable node is determined based on the probability domain operation method; The initial probability of the state value of each variable node is used as the confidence level by which the variable node passes its own state value to each verification node connected by undirected edges; For any of the verification nodes, based on each target undirected edge between the verification node and each connected target variable node, and based on the extended verification matrix, a node state matrix corresponding to each target undirected edge is constructed. Based on each target undirected edge and the confidence that each target variable node transmits its own state value to the verification node, a driving vector corresponding to each target undirected edge is constructed. The in-memory compute unit is configured based on the node state matrix corresponding to each undirected edge to obtain the in-memory compute unit subarray corresponding to each undirected edge; Based on the driving vector corresponding to each undirected edge, the in-memory compute subarray, and each confidence level, the confidence level transmitted by each variable node to each verification node and the new probability of the state value of each variable node are iteratively updated until the set iteration stopping condition is met, so as to decode the original bit information corresponding to the Turbo code to be decoded.

2. The method according to claim 1, characterized in that, The Turbo code to be decoded is obtained by digitally modulating the original Turbo code at the encoding end and sending it to the decoding end. The original Turbo code is obtained by the encoding end by Turbo encoding the original bit information. The process of obtaining the extended parity-check matrix and probabilistic graphical model corresponding to the Turbo code to be decoded, as well as the initial probability of the state value of each variable node in the probabilistic graphical model, includes: Receive the Turbo code to be decoded sent by the encoding end, and determine the noise variance corresponding to the Turbo code to be decoded; Based on the Turbo code to be decoded, create an initial parity-check matrix and a corresponding initial probability graphical model; Eliminate short loop structures in the initial parity-check matrix and the initial probabilistic graphical model to obtain the extended parity-check matrix and the probabilistic graphical model; Based on the noise variance and probability domain operation method, the initial probability of the state value of each variable node is determined.

3. The method according to claim 1, characterized in that, When the in-memory computing unit is a memristor, the node state matrix is ​​the node resistance state matrix; The step of constructing a node state matrix corresponding to each target undirected edge based on each target undirected edge between the verification node and each connected target variable node, and based on the extended verification matrix, includes: Obtain the number t of the target undirected edges, and determine the internal order of each target undirected edge among all target undirected edges; Construct multiple candidate vectors obtained by arranging and combining t target binary characters. For any candidate vector, if the element order of the target binary characters in the candidate vector is equal to the internal order of the target undirected edge, then establish an association between the target binary characters in the candidate vector and the target variable nodes connected by the target undirected edge. Iterate through each of the aforementioned target undirected edges in turn; For the a-th target undirected edge traversed, the multiple candidate vectors are divided into multiple first candidate vectors and multiple second candidate vectors to be processed. Based on each first candidate vector, second candidate vector, the association relationship and the extended verification matrix, the node resistance matrix corresponding to the target undirected edge is constructed; wherein, the a-th element in the first candidate vector is 1 and the a-th element in the second candidate vector is 0.

4. The method according to claim 3, characterized in that, The step of constructing the node resistance matrix corresponding to the target undirected edge based on each of the first candidate vector, the second candidate vector, the association relationship, and the extended verification matrix includes: For any candidate vector to be processed, a zero vector is constructed with the total number of elements equal to the total number of variable nodes. The node order of the target variable nodes associated with each target binary character in the candidate vector to be processed is determined as the unique order to be arranged for each target binary character. Each zero element in the zero vector whose position order is equal to the order to be arranged is replaced with the target binary character that uniquely corresponds to the order to be arranged, so as to obtain the processed candidate vector. Wherein, the candidate vector to be processed is either the first candidate vector or the second candidate vector; when the candidate vector to be processed is the first candidate vector, the processed candidate vector is the first processed candidate vector; when the candidate vector to be processed is the second candidate vector, the processed candidate vector is the second processed candidate vector. In the extended verification matrix, determine the target row vector that uniquely corresponds to the verification node; For any of the first processed candidate vectors, the target row vector is moduloed by the first processed candidate vector to obtain the corresponding first value. The first value is then inverted to obtain the first inverted value. Each of the first inverted values ​​is arranged to obtain the first node resistance column vector. For any second-processed candidate vector, perform a modulo operation between the target row vector and the second-processed candidate vector to obtain the corresponding second value, invert the second value to obtain a second inverted value; arrange each second inverted value to obtain a second node resistance column vector. By horizontally concatenating the first node resistance column vector and the second node resistance column vector, the node resistance matrix corresponding to the target undirected edge is obtained.

5. The method according to claim 4, characterized in that, When the in-memory computing unit is a memristor, the driving vector is a voltage vector; The step of constructing a driving vector corresponding to each target undirected edge based on the confidence level of each target variable node in transmitting its own state value to the verification node includes: When traversing to the a-th target undirected edge, the a-th element in each candidate vector is deleted to obtain multiple first vectors. Duplicates are then removed from these first vectors to obtain multiple second vectors. For any second vector, the target confidence level corresponding to each target binary character in the second vector is determined. The target confidence levels corresponding to each target binary character in the second vector are multiplied to obtain the product corresponding to the second vector. The products corresponding to each second vector are arranged to obtain the voltage vector corresponding to the target undirected edge. The target confidence level corresponding to the target binary character in the second vector is: the confidence level of the target variable node associated with the target binary character, which transmits its own state value equal to the target binary character to the verification node.

6. The method according to claim 5, characterized in that, When the in-memory computing unit is a memristor, the in-memory computing unit subarray is a memristor subarray; The step of configuring the in-memory compute unit based on the node state matrix corresponding to each undirected edge to obtain the in-memory compute unit subarray corresponding to each undirected edge includes: For any node resistance state matrix corresponding to any of the undirected edges, the corresponding initial memristor subarray is obtained according to the number of rows and columns of the elements in the node resistance state matrix, wherein the number of rows and columns of the nodes in the initial memristor subarray corresponds to the number of rows and columns of the elements; For any target element in the node resistance matrix, the target node corresponding to the position is determined in the initial memristor subarray according to the position of the target element in the node resistance matrix. If the target element is 1, the resistance state of the target node is set to low resistance state; if the target element is 0, the resistance state of the target node is set to high resistance state. The initial memristor subarray that completes the node resistance configuration according to each target element in the node resistance matrix is ​​determined as the memristor subarray corresponding to the undirected edge.

7. The method according to claim 6, characterized in that, The memristor subarray corresponding to the undirected edge includes a first node column and a second node column. The first node column corresponds to the case where the variable node connected by the undirected edge has a state value of 1, and the second node column corresponds to the case where the variable node connected by the undirected edge has a state value of 0. The process involves iteratively updating the confidence level transmitted from each variable node to each verification node and the new probability of the state value of each variable node based on the driving vector corresponding to each undirected edge, the in-memory compute subarray, and each confidence level, until a set iteration stopping condition is met, in order to decode the original bit information corresponding to the Turbo code to be decoded, including: For any of the undirected edges, according to each voltage element in the voltage vector corresponding to the undirected edge, input a voltage equal to the magnitude of the voltage element to each row node in the memristor subarray corresponding to the undirected edge, and read the first current value of the first node column and the second current value of the second node column in the memristor subarray respectively. Based on the first current value and the second current value in each memristor subarray, update the new confidence level of each variable node in passing its own state value to each verification node, and update the new probability of the state value of each variable node. Determine whether the new probability of the state value of each variable node satisfies the iteration stopping condition; If the new probability of the state value of each variable node does not meet the iteration stopping condition, then the new confidence of each variable node passing its own state value to each verification node is taken as the current confidence. Then, the step of constructing the driving vector corresponding to each target undirected edge based on each target undirected edge and the confidence of each target variable node passing its own state value to the verification node is returned until the iteration stopping condition is met. If the iteration stopping condition is met, the original bit information is determined based on the new probability of the state value of each variable node.

8. The method according to claim 7, characterized in that, The initial probability of the state value of each variable node includes a first initial probability and a second initial probability, given that the original Turbo codewords corresponding to the variable node are 1 and 0 respectively, under the condition that the extended codewords corresponding to the variable node are known. The step of updating the confidence level of each variable node to pass its own state value to each verification node based on the first current value and the second current value in each memristor subarray includes: For the first one with a connection relationship The verification node and the first Based on the node order of the verification node and the variable node, determine the undirected edge group connected to the variable node, and determine the first undirected edge between the verification node and the variable node. Then, determine any undirected edge in the undirected edge group other than the first undirected edge as the second undirected edge. Multiply the first current value in the memristor subarray corresponding to each second undirected edge by the first initial probability in the initial probability of the state value of the variable node to obtain the new confidence that the variable node will pass its own state value of 1 to the verification node. Multiply the second current value in the memristor subarray corresponding to each second undirected edge by the second initial probability in the initial probability of the state value of the variable node to obtain the new confidence that the variable node will pass its own state value of 0 to the verification node.

9. The method according to claim 8, characterized in that, The update obtains the new probability of the state value of each variable node, including: For any variable node, determine each undirected edge connected to the variable node, multiply the first current value in the memristor subarray corresponding to each undirected edge connected to the variable node by the square of the first initial probability in the initial probability of the variable node's state value to obtain a new probability that the variable node's own state value is equal to 1, and multiply the second current value in the memristor subarray corresponding to each undirected edge connected to the variable node by the square of the second initial probability in the initial probability of the variable node's state value to obtain a new probability that the variable node's own state value is equal to 0. The step of determining whether the new probability of the state value of each variable node satisfies the iteration stopping condition includes: Hard-determine the new probability of the state value of each variable node to obtain the codeword vector; Perform a modulo operation on the extended parity-check matrix and the codeword vector to obtain the result; If the result of the operation is equal to 0, then the iteration stopping condition is satisfied. If the result of the operation is not equal to 0, then it is determined that the iteration stopping condition has not been met; The step of determining the original bit information based on the new probability of the state value of each variable node includes: Determine the total number of characters K of the original bit information, select the first K elements from the latest codeword vector, and determine them as the original bit information.

10. A Turbo code probability domain decoding device based on a memory computing unit, characterized in that, Applied to a decoding end, the device includes: The acquisition unit is used to acquire the extended parity-check matrix and probabilistic graphical model corresponding to the Turbo code to be decoded, as well as the initial probability of the state value of each variable node in the probabilistic graphical model; wherein, the initial probability of the state value of the variable node is determined based on the probability domain operation method; As a unit, it is used to set the initial probability of the state value of each variable node as the confidence level of the variable node to pass its own state value to each verification node connected by undirected edges. The first construction unit is used to construct, for any verification node, a node state matrix corresponding to each target undirected edge based on each target undirected edge between the verification node and each target variable node connected to it, and based on the extended verification matrix. The second construction unit is used to construct the driving vector corresponding to each of the target undirected edges based on the confidence of each target variable node in passing its own state value to the verification node. The configuration unit is used to configure the in-memory compute unit based on the node state matrix corresponding to each undirected edge, so as to obtain the in-memory compute unit subarray corresponding to each undirected edge. The decoding unit is used to iteratively update the confidence level transmitted by each variable node to each verification node and the new probability of the state value of each variable node according to the driving vector corresponding to each undirected edge, the in-memory compute subarray and each confidence level, until the set iteration stop condition is met, so as to decode the original bit information corresponding to the Turbo code to be decoded.

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