Circuit structure for realizing one-step solution of linear equation set based on memristor array

Abstract

The application belongs to the technical field of integrated circuits, and discloses a circuit structure for one-step solution of linear equations based on a memristor array, wherein the linear equations are Ax=b, and in the circuit, a first memristor array matrix operation core realizes mapping of the matrix A, takes a negative value of a first operation voltage vector as a bit line voltage, performs a matrix multiplication operation, reads a word line current as a first operation current vector after the operation, a bias mapping module maps b into a bias current vector, a current superposition module superimposes the first operation current vector and the bias current vector to generate a superimposed current vector, and converts the superimposed current vector into a second operation voltage vector through a transimpedance amplifier module, a second memristor array matrix operation core realizes mapping of the matrix A, takes the second operation voltage vector as a bit line voltage, performs a matrix multiplication operation, reads a word line current, and performs an integral operation on the word line current through an integrator module to obtain an updated first operation voltage vector. T The above hardware circuit can realize solution of the linear equations.

Description

Technical Field

[0001] This invention belongs to the field of integrated circuit technology, and more specifically, relates to a circuit structure for solving a system of linear equations in one step based on a memristor array. Background Technology

[0002] Solving systems of linear equations is a core mathematical problem in many fields such as scientific computing, signal processing, machine learning, and optimal control. With the advent of the Internet of Things, artificial intelligence, and big data era, the demand for real-time, low-power solutions to small- and medium-scale linear systems is becoming increasingly urgent in scenarios such as sensor data fusion, real-time image reconstruction, and model predictive control on edge devices.

[0003] The Kaczmarz algorithm, a classic iterative projection algorithm, is widely used in fields such as computed tomography due to its simple structure, sparse matrix friendliness, and low memory consumption. Its basic iterative form is row-by-row projection, with convergence speed depending on the row order. However, this algorithm is currently only implemented in software; mature hardware deployment technology is still lacking. No publicly available circuit structure allows for hardware implementation of this algorithm, and solving it in software inevitably faces challenges related to computational power, real-time performance, and power consumption.

[0004] Therefore, how to build a hardware circuit capable of solving linear equations is a technical problem that urgently needs to be solved. Summary of the Invention

[0005] In view of the above-mentioned defects or improvement needs of the existing technology, the present invention provides a circuit structure for solving linear equations in one step based on memristor array, the purpose of which is to realize the solution of linear equations through hardware circuit.

[0006] To achieve the above objective, a circuit structure for solving a linear equation system in one step based on a memristor array is provided, wherein the linear equation system is Ax = b, where A is a coefficient matrix, b is a constant column vector, and x is the column vector to be solved.

[0007] The circuit structure includes a bias mapping module, a first memristor array matrix operation core forming a closed loop, a current superposition module, a transimpedance amplifier module, a second memristor array matrix operation core, and an integrator module;

[0008] The first memristor array matrix operation core is used to operate with a first operation voltage vector The negative value is used as its bit line voltage, and after performing matrix multiplication, its word line current is read by its internal current reading module as the first operational current vector. The memristor array in the first memristor array matrix operation core is used to implement the mapping of matrix A, and its word lines generate word line currents; r is the iteration round;

[0009] The bias mapping module is used to map the constant column vector b into a bias current vector. ;

[0010] The current superposition module is used to superimpose the first operational current vector and the bias current vector Superposition generates a superimposed current vector;

[0011] The transimpedance amplifier module is used to convert the superimposed current vector into a second operational voltage vector. ;

[0012] The second memristor array matrix operation core is used to operate on the second operation voltage vector. After the word line voltage is used as its bit line voltage and matrix multiplication is performed, its word line current is read by its internal current reading module as the second operational current vector. The memristor array in the second memristor array matrix operation core is used to implement matrix A. T Mapping;

[0013] The integrator module is used to process the second operational current vector. Perform integration to obtain the updated first operational voltage vector and provide it to the first memristor array matrix operation core to execute the next round of iteration;

[0014] The convergence of the first operational voltage vector is used as the solution to the linear equation system.

[0015] In summary, compared with the prior art, the technical solutions conceived in this invention have the following main advantages:

[0016] The circuit structure for one-step solution of linear equations based on memristor arrays constructed in this invention includes a bias mapping module, a first memristor array matrix operation core, a current superposition module, a transimpedance amplifier module, a second memristor array matrix operation core, and an integrator module. The memristor array, as the carrier of matrix mapping, is well-suited for matrix operations and exhibits high integration and low power consumption, offering advantages in computational density and energy efficiency. A transimpedance amplifier module and an integrator module are used as connections between the two memristor arrays to convert the current signal output by the memristor arrays into a signal usable as a memristor array... The input voltage signal enables signal transmission between the two memristor arrays. At the same time, all parameters in the algorithm are represented by electrical signals, realizing the deployment and operation of the algorithm on the circuit. The first memristor array matrix operation core, current superposition module, transimpedance amplifier module, second memristor array matrix operation core and integrator module form a closed loop. Only the bias current needs to be input through the bias mapping module. No other operation is required. The circuit structure automatically performs cyclic iteration based on its closed-loop design and finally obtains the converged solution. That is, the solution can be obtained by performing one operation, which is very simple. Attached Figure Description

[0017] Figure 1 This is a circuit structure based on a memristor array to solve a system of linear equations in one step, according to one embodiment of the present invention. Detailed Implementation

[0018] To make the objectives, technical solutions, and advantages of this invention clearer, the invention will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the invention. Furthermore, the technical features involved in the various embodiments of this invention described below can be combined with each other as long as they do not conflict with each other.

[0019] The conventional form of the rent of a linear equation is:

[0020] ;

[0021] Where A is an M*N dimensional coefficient matrix, M and N are positive integers, b is an N-dimensional constant column vector, and x is an M-dimensional column vector to be solved.

[0022] The system of equations can be transformed into the following form:

[0023] ;

[0024] In the formula, x * dx / dt is the exact solution to the linear system of equations Ax = b; x is the value of the system at time r after iteration; dx / dt refers to the derivative of x with respect to time, which can also be understood as Δx. Since x *Since Ax is an exact solution to the linear system of equations Ax = b, the equation Ax... * = b holds true. Substituting this equation into the above equation, we get:

[0025] ;

[0026] The present invention is based on the design of a circuit structure that can achieve the process by applying a trigger signal only once and through a closed loop.

[0027] like Figure 1 The diagram shows a circuit structure for one-step solution of a system of linear equations based on a memristor array in one embodiment of the present invention. It includes a bias mapping module, a first memristor array matrix operation core forming a closed loop, a current superposition module, a transimpedance amplifier module, a second memristor array matrix operation core, and an integrator module.

[0028] In this system, the memristor array in the first memristor array matrix operation core is used to implement the mapping of matrix A, and the memristor array in the second memristor array matrix operation core is used to implement matrix A. T The mapping is as follows. Understandingly, mapping a matrix to a memristor array essentially involves linearly mapping the elements of the matrix to the conductance values ​​of the memristors at the corresponding locations in the memristor array. The bias mapping module then linearly maps the constant column vector b to the bias current vector. .

[0029] The following provides a detailed description of each module.

[0030] The first memristor array matrix operation core is used to operate on the first operation voltage vector. The negative value is used as its bit line voltage, and after performing matrix multiplication, its word line current is read by its internal current reading module as the first operational current vector. Before performing the operation, matrix A needs to be mapped to the memristor array of the first memristor array matrix operation core.

[0031] In this invention, the first operational voltage vector is used as the solution x of the linear equation system. Through multiple iterations, the first operational voltage vector gradually converges, thereby obtaining the optimal solution. The negative value of the value is used as its bit line voltage and matrix multiplication is performed to realize the operation of -Ax. The result of the operation exists in the circuit in the form of current and participates in subsequent operations.

[0032] Specifically, the memristor array of the first memristor array matrix operation core is composed of interleaved 1T1R units. A 1T1R unit refers to a gated programmable storage unit consisting of one transistor (T) and one memristor (R), which can be used to store matrix elements or for analog domain calculations. The value of each element in matrix A is mapped to the memristor of the corresponding 1T1R unit in the array, represented by the resistance state of the memristor (high resistance, low resistance, or multiple resistance states). The size of the memristor array is M*N, where M is the number of rows and N is the number of columns, and both M and N are positive integers.

[0033] In one embodiment, the first memristor array matrix operation core further includes a peripheral control module, a word line driving and decoding module (WL driving and decoding module for short), and a bit line driving and input control module (BL driving and input control module for short). The word line is connected to the gate of the transistor, and the word line driving and decoding module controls the selection of the 1T1R unit through the word line; the bit line is connected to the electrode of the memristor, and the bit line driving and input control module writes data into the memristor through the bit line.

[0034] The bias mapping module is used to map the constant column vector b to the bias current vector. Understandably, if b is an N-dimensional constant column vector, then the bias mapping module will generate N corresponding bias current vectors, i.e., bias current vectors. In each iteration, the bias current vector remains unchanged. In other words, the role of the bias mapping module is to map the column vector b in the linear equation system Ax = b into a column of bias current vectors, and add b in the form of current to the closed-loop operation of the proposed circuit structure.

[0035] The current superposition module is used to superimpose the first operational current vector. and the bias current vector Superposition generates a superimposed current vector. Specifically, the first operational current vector in N dimensions... With N-dimensional bias current vector Superposition generates an N-dimensional superimposed current vector.

[0036] In this invention, the N-dimensional first operation current vector (representing -Ax) output by the first memristor array matrix operation core and the N-dimensional bias current vector (representing b) output by the bias mapping module are superimposed to obtain an N-dimensional superimposed current, which realizes the operation of b-Ax.

[0037] A transimpedance amplifier module is used to convert the superimposed current vector into a second operational voltage vector. .

[0038] Specifically, the transimpedance amplifier module has N parallel transimpedance amplifiers (TIAs), each corresponding to an N-dimensional superimposed current vector. Each TIA converts its corresponding superimposed current into a voltage. The N-dimensional superimposed current vector is then converted into an N-dimensional second operational voltage vector. In the specific design, each transimpedance amplifier includes a two-input, single-output operational amplifier and a resistor. The positive input terminal of the operational amplifier is grounded, and a resistor is connected between the negative input terminal and the output terminal. The negative input terminal of the operational amplifier is also used to connect a superimposed current. The negative input terminal of the nth transimpedance amplifier connects to the nth-dimensional superimposed current and converts it into a voltage. Combining all the conversion results, an N-dimensional second operational voltage vector is obtained. In other words, the transimpedance amplifier module converts the total current (N-dimensional current vector) generated by the first memristor array matrix operation core and the bias mapping module into voltage (N-dimensional voltage vector).

[0039] In this invention, the superimposed current vector is input into the transimpedance amplifier module, which amplifies the superimposed current vector by a factor of R (R is the resistance value of the resistor in the TIA), and converts the superimposed current vector into a voltage vector. Its mathematical expression is still b-Ax, because R only transforms its electrical representation, which is a linear change.

[0040] The second memristor array matrix operation core is used to operate on the second operation voltage vector. After the word line voltage is used as its bit line voltage and matrix multiplication is performed, its word line current is read by its internal current reading module as the second operational current vector. Before performing the operation, matrix A needs to be... T The memristor array mapped to the second memristor array matrix operation core.

[0041] Specifically, the memristor array matrix operation core of the second memristor array matrix operation core is composed of interlaced 1T1R units, and its 1T1R units have the same structure as those of the first memristor array matrix operation core. The function of the second memristor array matrix operation core is to process matrix A involved in matrix operations. T Mapping into its array, specifically, mapping matrix A T The value of each element is linearly mapped to the memristor of the corresponding 1T1R cell in the array, and is represented by the resistance state (high resistance, low resistance, or multiple resistance states) of the memristor; the size of the memristor array matrix is ​​N*M, where N is the number of rows and M is the number of columns, and M and N are both positive integers.

[0042] In one embodiment, the second memristor array matrix operation core further includes a peripheral control module, a word line driving and decoding module (WL driving and decoding module for short), and a bit line driving and input control module (BL driving and input control module for short). The word line is connected to the gate of the transistor, and the word line driving and decoding module controls the selection of the 1T1R unit through the word line; the bit line is connected to the electrode of the memristor, and the bit line driving and input control module writes data into the memristor through the bit line.

[0043] In this invention, the second operational voltage vector is used as the input to the second memristor array matrix operation core to obtain an M-dimensional second operational current vector. This operation is equivalent to left-multiplying the signal (b-Ax) by a matrix A. T Achieve -A T Ax+A T The operation of b. According to the formula above, -A T Ax+A T The physical meaning of b is precisely dx / dt.

[0044] Integrator module, which is used for the second operational current vector Perform integration to obtain the updated first operational voltage vector, and provide it to the first memristor array matrix operation core to execute the next round of iteration.

[0045] Specifically, the integrator module contains a column of M parallel integrators, and the M integrators are coupled to an M-dimensional second operational current vector. In a one-to-one correspondence, each integrator integrates its corresponding second operational current to obtain the corresponding voltage. The M-dimensional second operational current is then integrated to obtain an M-dimensional second operational voltage vector. In the specific design, each integrator includes a two-input, single-output operational amplifier and a capacitor; the positive input terminal of the operational amplifier is grounded, and the capacitor is connected between the negative input terminal and the output terminal of the operational amplifier. The negative input terminal of the operational amplifier is also used to connect the second operational current vector. The corresponding second operational current. That is, the function of the integrator module is to integrate the M-dimensional current column vector output by the second memristor array matrix operation core to obtain the integrated M-dimensional voltage column vector.

[0046] In this invention, an M-dimensional current vector (dx / dt) is input into an integrator module for integration. The integration result is represented by the voltage across the capacitor in the integrator, which is the new x obtained after one iteration. If this is at time t, it can be represented as x(t), and the value of x is stored on the capacitor in the integrator module. Initially, all capacitors in the integrator module discharge to a voltage difference of 0. x(t) iteratively increases from the initial value of 0, eventually approaching and converging to x. *The convergence speed depends on the amplification factor R in the TIA and the value of the integrating capacitor C in the integrator. The larger R is and the smaller C is, the faster the system converges; conversely, the convergence speed is slower. However, an excessively small C can easily lead to system instability. Therefore, while ensuring system stability, the values ​​of R and C should be appropriately adjusted to accelerate the system convergence speed.

[0047] In one embodiment, the circuit structure further includes an initialization module and a startup module; the initialization module is used to control the first memristor array matrix operation core to map matrix A to its memristor array, and to control the second memristor array matrix operation core to map matrix A to its memristor array. T The integrator module maps the integrator to its memristor array and clears the capacitor voltage in the integrator module to zero. The startup module, after the initialization module performs its initialization operation, is used to start the bias mapping module to map the constant column vector b to a bias current vector. In this invention, after the bias mapping module is started, no other operations are required. The circuit structure automatically performs iterative loops based on its closed-loop design, and finally obtains the converged solution.

[0048] In one embodiment, the circuit structure further includes an output module, which is used to obtain the first operational voltage vector output in each iteration and output the current first operational voltage vector as the solution result of the column vector to be solved when the first operational voltage vector converges to a preset degree.

[0049] Overall, the above describes the workflow of a circuit structure based on memristor arrays for one-step solution of linear equations:

[0050] Initialization settings: Discharge all capacitors in the integrator module until the voltage difference is 0; map matrix A to the first memristor array matrix operation core; set matrix A... T Map to the second memristor array matrix operation core; map column vector b to the bias mapping module;

[0051] Automatic cycling mode: Since the initial voltage across the capacitor is 0, the only external excitation of the circuit is a bias current vector of length N. Therefore, it enters the loop from the bias mapping module, and the bias current vector... First, the signal enters the transimpedance amplifier module and is converted into a second operational voltage vector of length N. Then, it passes through the second memristor array matrix operation core to obtain a second operational current vector of length M. This output current column vector is then input to the integrator module. The current continuously injects charge into the integrator capacitor, macroscopically representing the integration of the capacitor voltage, ultimately yielding a first operational voltage vector of length M. This first operational voltage vector is then automatically input into the first memristor array matrix operation core for a new round of calculation. In this new iteration, the first memristor array matrix operation core calculates a first operational current vector of length N. This first operational current vector is then compared with the bias current vector of length N. After being added together, a new superimposed current vector is formed and re-input into the transimpedance amplifier module. This process is repeated iteratively. After several iterations, when the capacitor voltage on the integrator (i.e., the first operational voltage) basically converges, the loop mode ends, the column vector x is solved, and the final voltage stored on each capacitor is each element of the column vector x in the linear equation system Ax = b.

[0052] The technical features of the embodiments described above can be combined arbitrarily. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as the combination of these technical features does not contradict each other, it should be considered within the scope of this specification. It should be noted that the terms "in one embodiment," "for example," and "again" in this invention are intended to illustrate the invention and are not intended to limit the invention.

[0053] The embodiments described above are merely examples of several implementations of the present invention, and while the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the patent application. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of the present invention, and these modifications and improvements all fall within the scope of protection of the present invention.

Claims

1. A circuit structure for one-step solution of a system of linear equations based on a memristor array, characterized in that, The linear system of equations is Ax = b, where A is the coefficient matrix, b is the constant column vector, and x is the column vector to be solved. The circuit structure includes a bias mapping module, a first memristor array matrix operation core forming a closed loop, a current superposition module, a transimpedance amplifier module, a second memristor array matrix operation core, and an integrator module; The first memristor array matrix operation core is used to operate with a first operation voltage vector The negative value is used as its bit line voltage, and after performing matrix multiplication, its word line current is read by its internal current reading module as the first operational current vector. The memristor array in the first memristor array matrix operation core is used to implement the mapping of matrix A, and its word lines generate word line currents; r is the iteration round; The bias mapping module is used to map the constant column vector b into a bias current vector. ; The current superposition module is used to superimpose the first operational current vector and the bias current vector Superposition generates a superimposed current vector; The transimpedance amplifier module is used to convert the superimposed current vector into a second operational voltage vector. ; The second memristor array matrix operation core is used to operate on the second operation voltage vector. After the word line voltage is used as its bit line voltage and matrix multiplication is performed, its word line current is read by its internal current reading module as the second operational current vector. The memristor array in the second memristor array matrix operation core is used to implement matrix A. T Mapping; The integrator module is used to process the second operational current vector. Perform integration to obtain the updated first operational voltage vector and provide it to the first memristor array matrix operation core to execute the next round of iteration; The convergence of the first operational voltage vector is used as the solution to the linear equation system.

2. The circuit structure for one-step solution of linear equations based on memristor array as described in claim 1, characterized in that, Each memristor array matrix operation core includes a peripheral control module, a word line driver and decoding module, a bit line driver and input control module, and a current readout module. The word line driver and decoding module, the bit line driver and input control module, and the current readout module are all controlled by the peripheral control module. The word line driver and decoding module controls the selection of each cell of the memristor array through word lines. The bit line driver and input control module writes data into each cell of the memristor array through bit lines.

3. The circuit structure for one-step solution of linear equations based on memristor array as described in claim 1, characterized in that, In both the first and second memristor array matrix operation cores, the memristor arrays are composed of interleaved 1T1R units. Each 1T1R unit is a selectable programmable in-memory unit consisting of one transistor and one memristor.

4. The circuit structure for one-step solution of a system of linear equations based on a memristor array as described in claim 3, characterized in that, The first memristor array matrix operation core and the second memristor array matrix operation core use the same 1T1R unit.

5. The circuit structure for one-step solution of linear equations based on memristor array as described in claim 1, characterized in that, The transimpedance amplifier module has multiple transimpedance amplifiers in parallel. Each transimpedance amplifier includes a dual-input single-output operational amplifier and a resistor. The positive input terminal of the operational amplifier is grounded, and the resistor is connected between the negative input terminal and the output terminal of the operational amplifier. The negative input terminal of the operational amplifier is also used to connect the corresponding superimposed current in the superimposed current vector.

6. The circuit structure for one-step solution of linear equations based on memristor array as described in claim 1, characterized in that, The integrator module has multiple integrators in parallel. Each integrator includes a two-input, single-output operational amplifier and a capacitor. The positive input terminal of the operational amplifier is grounded, and the capacitor is connected between the negative input terminal and the output terminal of the operational amplifier. The negative input terminal of the operational amplifier is also used to connect a second operational current vector. The corresponding second operational current.

7. The circuit structure for one-step solution of linear equations based on memristor array as described in claim 1, characterized in that, The circuit structure also includes an initialization module and a startup module; The initialization module is used to control the first memristor array matrix operation core to map matrix A to its memristor array, and to control the second memristor array matrix operation core to map matrix A to its memristor array. T Map to its memristor array and clear the capacitor voltage in the integrator module to zero; The startup module is used to start the bias mapping module to map the constant column vector b to a bias current vector after the initialization module performs the initialization operation. .

8. The circuit structure for one-step solution of linear equations based on memristor array as described in claim 1, characterized in that, The circuit structure also includes an output module, which is used to obtain the first operational voltage vector output in each iteration and output the current first operational voltage vector as the solution result of the column vector to be solved when the first operational voltage vector converges to a preset degree.

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